sys/dev/netif/sr/if_sr.c

   1 /*
   2  * Copyright (c) 1996 - 2001 John Hay.
   3  * Copyright (c) 1996 SDL Communications, Inc.
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of the author nor the names of any co-contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written permission.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/sr/if_sr.c,v 1.48.2.1 2002/06/17 15:10:58 jhay Exp $
  31  * $DragonFly: src/sys/dev/netif/sr/if_sr.c,v 1.2 2003/06/17 04:28:31 dillon Exp $
  32  */
  33
  34 /*
  35  * Programming assumptions and other issues.
  36  *
  37  * Only a 16K window will be used.
  38  *
  39  * The descriptors of a DMA channel will fit in a 16K memory window.
  40  *
  41  * The buffers of a transmit DMA channel will fit in a 16K memory window.
  42  *
  43  * When interface is going up, handshaking is set and it is only cleared
  44  * when the interface is down'ed.
  45  *
  46  * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE,
  47  * internal/external clock, etc.....
  48  *
  49  */
  50
  51 #include "opt_netgraph.h"
  52 #ifdef NETGRAPH
  53 #include <dev/sr/if_sr.h>
  54 #endif  /* NETGRAPH */
  55
  56 #include <sys/param.h>
  57 #include <sys/systm.h>
  58 #include <sys/kernel.h>
  59 #include <sys/malloc.h>
  60 #include <sys/mbuf.h>
  61 #include <sys/sockio.h>
  62 #include <sys/socket.h>
  63 #include <sys/bus.h>
  64 #include <machine/bus.h>
  65 #include <machine/resource.h>
  66 #include <machine/bus_pio.h>
  67 #include <machine/bus_memio.h>
  68 #include <sys/rman.h>
  69
  70 #include <net/if.h>
  71 #ifdef NETGRAPH
  72 #include <sys/syslog.h>
  73 #else /* NETGRAPH */
  74 #include <net/if_sppp.h>
  75
  76 #include <net/bpf.h>
  77 #endif  /* NETGRAPH */
  78
  79 #include <machine/md_var.h>
  80
  81 #include <dev/ic/hd64570.h>
  82 #include <dev/sr/if_srregs.h>
  83
  84 #ifdef NETGRAPH
  85 #include <netgraph/ng_message.h>
  86 #include <netgraph/netgraph.h>
  87 #endif /* NETGRAPH */
  88 /* #define USE_MODEMCK */
  89
  90 #ifndef BUGGY
  91 #define BUGGY           0
  92 #endif
  93
  94 #ifndef NETGRAPH
  95 #define PPP_HEADER_LEN  4
  96 #endif /* NETGRAPH */
  97
  98 static int      next_sc_unit = 0;
  99 #ifndef NETGRAPH
 100 #ifdef USE_MODEMCK
 101 static int      sr_watcher = 0;
 102 #endif
 103 #endif /* NETGRAPH */
 104
 105 /*
 106  * Define the software interface for the card... There is one for
 107  * every channel (port).
 108  */
 109 struct sr_softc {
 110 #ifndef NETGRAPH
 111         struct  sppp ifsppp;    /* PPP service w/in system */
 112 #endif /* NETGRAPH */
 113         struct  sr_hardc *hc;   /* card-level information */
 114
 115         int     unit;           /* With regard to all sr devices */
 116         int     subunit;        /* With regard to this card */
 117
 118         struct  buf_block {
 119                 u_int   txdesc; /* DPRAM offset */
 120                 u_int   txstart;/* DPRAM offset */
 121                 u_int   txend;  /* DPRAM offset */
 122                 u_int   txtail; /* # of 1st free gran */
 123                 u_int   txmax;  /* # of free grans */
 124                 u_int   txeda;  /* err descr addr */
 125         } block[SR_TX_BLOCKS];
 126
 127         char    xmit_busy;      /* Transmitter is busy */
 128         char    txb_inuse;      /* # of tx grans in use */
 129         u_int   txb_new;        /* ndx to new buffer */
 130         u_int   txb_next_tx;    /* ndx to next gran rdy tx */
 131
 132         u_int   rxdesc;         /* DPRAM offset */
 133         u_int   rxstart;        /* DPRAM offset */
 134         u_int   rxend;          /* DPRAM offset */
 135         u_int   rxhind;         /* ndx to the hd of rx bufrs */
 136         u_int   rxmax;          /* # of avail grans */
 137
 138         u_int   clk_cfg;        /* Clock configuration */
 139
 140         int     scachan;        /* channel # on card */
 141 #ifdef NETGRAPH
 142         int     running;        /* something is attached so we are running */
 143         int     dcd;            /* do we have dcd? */
 144         /* ---netgraph bits --- */
 145         char            nodename[NG_NODELEN + 1]; /* store our node name */
 146         int             datahooks;      /* number of data hooks attached */
 147         node_p          node;           /* netgraph node */
 148         hook_p          hook;           /* data hook */
 149         hook_p          debug_hook;
 150         struct ifqueue  xmitq_hipri;    /* hi-priority transmit queue */
 151         struct ifqueue  xmitq;          /* transmit queue */
 152         int             flags;          /* state */
 153 #define SCF_RUNNING     0x01            /* board is active */
 154 #define SCF_OACTIVE     0x02            /* output is active */
 155         int             out_dog;        /* watchdog cycles output count-down */
 156 #if ( __FreeBSD__ >= 3 )
 157         struct callout_handle handle;   /* timeout(9) handle */
 158 #endif
 159         u_long          inbytes, outbytes;      /* stats */
 160         u_long          lastinbytes, lastoutbytes; /* a second ago */
 161         u_long          inrate, outrate;        /* highest rate seen */
 162         u_long          inlast;         /* last input N secs ago */
 163         u_long          out_deficit;    /* output since last input */
 164         u_long          oerrors, ierrors[6];
 165         u_long          opackets, ipackets;
 166 #endif /* NETGRAPH */
 167 };
 168
 169 #ifdef NETGRAPH
 170 #define DOG_HOLDOFF     6       /* dog holds off for 6 secs */
 171 #define QUITE_A_WHILE   300     /* 5 MINUTES */
 172 #define LOTS_OF_PACKETS 100
 173 #endif /* NETGRAPH */
 174
 175 /*
 176  * Baud Rate table for Sync Mode.
 177  * Each entry consists of 3 elements:
 178  * Baud Rate (x100) , TMC, BR
 179  *
 180  * Baud Rate = FCLK / TMC / 2^BR
 181  * Baud table for Crystal freq. of 9.8304 Mhz
 182  */
 183 #ifdef N2_TEST_SPEED
 184 struct rate_line {
 185         int     target;         /* target rate/100 */
 186         int     tmc_reg;        /* TMC register value */
 187         int     br_reg;         /* BR (BaudRateClk) selector */
 188 } n2_rates[] = {
 189         /* Baudx100     TMC             BR */
 190         { 3,            128,            8 },
 191         { 6,            128,            7 },
 192         { 12,           128,            6 },
 193         { 24,           128,            5 },
 194         { 48,           128,            4 },
 195         { 96,           128,            3 },
 196         { 192,          128,            2 },
 197         { 384,          128,            1 },
 198         { 560,          88,             1 },
 199         { 640,          77,             1 },
 200         { 1280,         38,             1 },
 201         { 2560,         19,             1 },
 202         { 5120,         10,             1 },
 203         { 10000,        5,              1 },
 204         { 15000,        3,              1 },
 205         { 25000,        2,              1 },
 206         { 50000,        1,              1 },
 207         { 0,            0,              0 }
 208 };
 209
 210 int     sr_test_speed[] = {
 211         N2_TEST_SPEED,
 212         N2_TEST_SPEED
 213 };
 214
 215 int     etc0vals[] = {
 216         SR_MCR_ETC0,            /* ISA channel 0 */
 217         SR_MCR_ETC1,            /* ISA channel 1 */
 218         SR_FECR_ETC0,           /* PCI channel 0 */
 219         SR_FECR_ETC1            /* PCI channel 1 */
 220 };
 221 #endif
 222
 223 devclass_t sr_devclass;
 224 #ifndef NETGRAPH
 225 MODULE_DEPEND(if_sr, sppp, 1, 1, 1);
 226 #else
 227 MODULE_DEPEND(ng_sync_sr, netgraph, 1, 1, 1);
 228 #endif
 229
 230 static void     srintr(void *arg);
 231 static void     sr_xmit(struct sr_softc *sc);
 232 #ifndef NETGRAPH
 233 static void     srstart(struct ifnet *ifp);
 234 static int      srioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
 235 static void     srwatchdog(struct ifnet *ifp);
 236 #else
 237 static void     srstart(struct sr_softc *sc);
 238 static void     srwatchdog(struct sr_softc *sc);
 239 #endif /* NETGRAPH */
 240 static int      sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat);
 241 static void     sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len);
 242 static void     sr_eat_packet(struct sr_softc *sc, int single);
 243 static void     sr_get_packets(struct sr_softc *sc);
 244
 245 static void     sr_up(struct sr_softc *sc);
 246 static void     sr_down(struct sr_softc *sc);
 247 static void     src_init(struct sr_hardc *hc);
 248 static void     sr_init_sca(struct sr_hardc *hc);
 249 static void     sr_init_msci(struct sr_softc *sc);
 250 static void     sr_init_rx_dmac(struct sr_softc *sc);
 251 static void     sr_init_tx_dmac(struct sr_softc *sc);
 252 static void     sr_dmac_intr(struct sr_hardc *hc, u_char isr);
 253 static void     sr_msci_intr(struct sr_hardc *hc, u_char isr);
 254 static void     sr_timer_intr(struct sr_hardc *hc, u_char isr);
 255 #ifndef NETGRAPH
 256 #ifdef USE_MODEMCK
 257 static void     sr_modemck(void *x);
 258 #endif
 259 #else
 260 static void     sr_modemck(struct sr_softc *x);
 261 #endif /* NETGRAPH */
 262
 263 #ifdef NETGRAPH
 264 static  void    ngsr_watchdog_frame(void * arg);
 265 static  void    ngsr_init(void* ignored);
 266
 267 static ng_constructor_t ngsr_constructor;
 268 static ng_rcvmsg_t      ngsr_rcvmsg;
 269 static ng_shutdown_t    ngsr_rmnode;
 270 static ng_newhook_t     ngsr_newhook;
 271 /*static ng_findhook_t  ngsr_findhook; */
 272 static ng_connect_t     ngsr_connect;
 273 static ng_rcvdata_t     ngsr_rcvdata;
 274 static ng_disconnect_t  ngsr_disconnect;
 275
 276 static struct ng_type typestruct = {
 277         NG_VERSION,
 278         NG_SR_NODE_TYPE,
 279         NULL,
 280         ngsr_constructor,
 281         ngsr_rcvmsg,
 282         ngsr_rmnode,
 283         ngsr_newhook,
 284         NULL,
 285         ngsr_connect,
 286         ngsr_rcvdata,
 287         ngsr_rcvdata,
 288         ngsr_disconnect,
 289         NULL
 290 };
 291
 292 static int      ngsr_done_init = 0;
 293 #endif /* NETGRAPH */
 294
 295 /*
 296  * Register the ports on the adapter.
 297  * Fill in the info for each port.
 298 #ifndef NETGRAPH
 299  * Attach each port to sppp and bpf.
 300 #endif
 301  */
 302 int
 303 sr_attach(device_t device)
 304 {
 305         int intf_sw, pndx;
 306         u_int32_t flags;
 307         u_int fecr, *fecrp;
 308         struct sr_hardc *hc;
 309         struct sr_softc *sc;
 310 #ifndef NETGRAPH
 311         struct ifnet *ifp;
 312 #endif /* NETGRAPH */
 313         int unit;               /* index: channel w/in card */
 314
 315         hc = (struct sr_hardc *)device_get_softc(device);
 316         MALLOC(sc, struct sr_softc *,
 317                 hc->numports * sizeof(struct sr_softc),
 318                 M_DEVBUF, M_WAITOK | M_ZERO);
 319         if (sc == NULL)
 320                 goto errexit;
 321         hc->sc = sc;
 322
 323         /*
 324          * Get the TX clock direction and configuration. The default is a
 325          * single external clock which is used by RX and TX.
 326          */
 327         switch(hc->cardtype) {
 328         case SR_CRD_N2:
 329                 flags = device_get_flags(device);
 330 #ifdef N2_TEST_SPEED
 331                 if (sr_test_speed[0] > 0)
 332                         hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 333                 else
 334 #endif
 335                 if (flags & SR_FLAGS_0_CLK_MSK)
 336                         hc->sc[0].clk_cfg =
 337                             (flags & SR_FLAGS_0_CLK_MSK)
 338                             >> SR_FLAGS_CLK_SHFT;
 339
 340                 if (hc->numports == 2)
 341 #ifdef N2_TEST_SPEED
 342                         if (sr_test_speed[1] > 0)
 343                                 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK;
 344                         else
 345 #endif
 346                         if (flags & SR_FLAGS_1_CLK_MSK)
 347                                 hc->sc[1].clk_cfg = (flags & SR_FLAGS_1_CLK_MSK)
 348                                     >> (SR_FLAGS_CLK_SHFT +
 349                                     SR_FLAGS_CLK_CHAN_SHFT);
 350                 break;
 351         case SR_CRD_N2PCI:
 352                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
 353                 fecr = *fecrp;
 354                 for (pndx = 0; pndx < hc->numports; pndx++, sc++) {
 355                         switch (pndx) {
 356                         case 1:
 357                                 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT;
 358                                 break;
 359                         case 0:
 360                         default:
 361                                 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT;
 362                         }
 363
 364 #ifdef N2_TEST_SPEED
 365                         if (sr_test_speed[pndx] > 0)
 366                                 sc->clk_cfg = SR_FLAGS_INT_CLK;
 367                         else
 368 #endif
 369                                 switch (intf_sw) {
 370                                 default:
 371                                 case SR_FE_ID_RS232:
 372                                 case SR_FE_ID_HSSI:
 373                                 case SR_FE_ID_RS422:
 374                                 case SR_FE_ID_TEST:
 375                                         break;
 376
 377                                 case SR_FE_ID_V35:
 378                                         sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK;
 379                                         break;
 380
 381                                 case SR_FE_ID_X21:
 382                                         sc->clk_cfg = SR_FLAGS_EXT_CLK;
 383                                         break;
 384                                 }
 385                 }
 386                 sc = hc->sc;
 387                 break;
 388         }
 389
 390         /*
 391          * Report Card configuration information before we start configuring
 392          * each channel on the card...
 393          */
 394         printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n",
 395                hc->cunit, hc->memsize / 1024, hc->mempages,
 396                (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports);
 397
 398         src_init(hc);
 399         sr_init_sca(hc);
 400
 401         if (BUS_SETUP_INTR(device_get_parent(device), device, hc->res_irq,
 402             INTR_TYPE_NET, srintr, hc, &hc->intr_cookie) != 0)
 403                 goto errexit;
 404
 405         /*
 406          * Now configure each port on the card.
 407          */
 408         for (unit = 0; unit < hc->numports; sc++, unit++) {
 409                 sc->hc = hc;
 410                 sc->subunit = unit;
 411                 sc->unit = next_sc_unit;
 412                 next_sc_unit++;
 413                 sc->scachan = unit % NCHAN;
 414
 415                 sr_init_rx_dmac(sc);
 416                 sr_init_tx_dmac(sc);
 417                 sr_init_msci(sc);
 418
 419                 printf("sr%d: Adapter %d, port %d.\n",
 420                        sc->unit, hc->cunit, sc->subunit);
 421
 422 #ifndef NETGRAPH
 423                 ifp = &sc->ifsppp.pp_if;
 424                 ifp->if_softc = sc;
 425                 ifp->if_unit = sc->unit;
 426                 ifp->if_name = "sr";
 427                 ifp->if_mtu = PP_MTU;
 428                 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST;
 429                 ifp->if_ioctl = srioctl;
 430                 ifp->if_start = srstart;
 431                 ifp->if_watchdog = srwatchdog;
 432
 433                 sc->ifsppp.pp_flags = PP_KEEPALIVE;
 434                 sppp_attach((struct ifnet *)&sc->ifsppp);
 435                 if_attach(ifp);
 436
 437                 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN);
 438 #else   /* NETGRAPH */
 439                 /*
 440                  * we have found a node, make sure our 'type' is availabe.
 441                  */
 442                 if (ngsr_done_init == 0) ngsr_init(NULL);
 443                 if (ng_make_node_common(&typestruct, &sc->node) != 0)
 444                         goto errexit;
 445                 sc->node->private = sc;
 446                 callout_handle_init(&sc->handle);
 447                 sc->xmitq.ifq_maxlen = IFQ_MAXLEN;
 448                 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN;
 449                 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit);
 450                 if (ng_name_node(sc->node, sc->nodename)) {
 451                         ng_rmnode(sc->node);
 452                         ng_unref(sc->node);
 453                         return (0);
 454                 }
 455                 sc->running = 0;
 456 #endif  /* NETGRAPH */
 457         }
 458
 459         if (hc->mempages)
 460                 SRC_SET_OFF(hc->iobase);
 461
 462         return (0);
 463
 464 errexit:
 465         sr_deallocate_resources(device);
 466         return (ENXIO);
 467 }
 468
 469 int
 470 sr_detach(device_t device)
 471 {
 472         device_t parent = device_get_parent(device);
 473         struct sr_hardc *hc = device_get_softc(device);
 474
 475         if (hc->intr_cookie != NULL) {
 476                 if (BUS_TEARDOWN_INTR(parent, device,
 477                         hc->res_irq, hc->intr_cookie) != 0) {
 478                                 printf("intr teardown failed.. continuing\n");
 479                 }
 480                 hc->intr_cookie = NULL;
 481         }
 482
 483         /* XXX Stop the DMA. */
 484
 485         /*
 486          * deallocate any system resources we may have
 487          * allocated on behalf of this driver.
 488          */
 489         FREE(hc->sc, M_DEVBUF);
 490         hc->sc = NULL;
 491         hc->mem_start = NULL;
 492         return (sr_deallocate_resources(device));
 493 }
 494
 495 int
 496 sr_allocate_ioport(device_t device, int rid, u_long size)
 497 {
 498         struct sr_hardc *hc = device_get_softc(device);
 499
 500         hc->rid_ioport = rid;
 501         hc->res_ioport = bus_alloc_resource(device, SYS_RES_IOPORT,
 502                         &hc->rid_ioport, 0ul, ~0ul, size, RF_ACTIVE);
 503         if (hc->res_ioport == NULL) {
 504                 goto errexit;
 505         }
 506         return (0);
 507
 508 errexit:
 509         sr_deallocate_resources(device);
 510         return (ENXIO);
 511 }
 512
 513 int
 514 sr_allocate_irq(device_t device, int rid, u_long size)
 515 {
 516         struct sr_hardc *hc = device_get_softc(device);
 517
 518         hc->rid_irq = rid;
 519         hc->res_irq = bus_alloc_resource(device, SYS_RES_IRQ,
 520                         &hc->rid_irq, 0ul, ~0ul, 1, RF_SHAREABLE|RF_ACTIVE);
 521         if (hc->res_irq == NULL) {
 522                 goto errexit;
 523         }
 524         return (0);
 525
 526 errexit:
 527         sr_deallocate_resources(device);
 528         return (ENXIO);
 529 }
 530
 531 int
 532 sr_allocate_memory(device_t device, int rid, u_long size)
 533 {
 534         struct sr_hardc *hc = device_get_softc(device);
 535
 536         hc->rid_memory = rid;
 537         hc->res_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 538                         &hc->rid_memory, 0ul, ~0ul, size, RF_ACTIVE);
 539         if (hc->res_memory == NULL) {
 540                 goto errexit;
 541         }
 542         return (0);
 543
 544 errexit:
 545         sr_deallocate_resources(device);
 546         return (ENXIO);
 547 }
 548
 549 int
 550 sr_allocate_plx_memory(device_t device, int rid, u_long size)
 551 {
 552         struct sr_hardc *hc = device_get_softc(device);
 553
 554         hc->rid_plx_memory = rid;
 555         hc->res_plx_memory = bus_alloc_resource(device, SYS_RES_MEMORY,
 556                         &hc->rid_plx_memory, 0ul, ~0ul, size, RF_ACTIVE);
 557         if (hc->res_plx_memory == NULL) {
 558                 goto errexit;
 559         }
 560         return (0);
 561
 562 errexit:
 563         sr_deallocate_resources(device);
 564         return (ENXIO);
 565 }
 566
 567 int
 568 sr_deallocate_resources(device_t device)
 569 {
 570         struct sr_hardc *hc = device_get_softc(device);
 571
 572         if (hc->res_irq != 0) {
 573                 bus_deactivate_resource(device, SYS_RES_IRQ,
 574                         hc->rid_irq, hc->res_irq);
 575                 bus_release_resource(device, SYS_RES_IRQ,
 576                         hc->rid_irq, hc->res_irq);
 577                 hc->res_irq = 0;
 578         }
 579         if (hc->res_ioport != 0) {
 580                 bus_deactivate_resource(device, SYS_RES_IOPORT,
 581                         hc->rid_ioport, hc->res_ioport);
 582                 bus_release_resource(device, SYS_RES_IOPORT,
 583                         hc->rid_ioport, hc->res_ioport);
 584                 hc->res_ioport = 0;
 585         }
 586         if (hc->res_memory != 0) {
 587                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 588                         hc->rid_memory, hc->res_memory);
 589                 bus_release_resource(device, SYS_RES_MEMORY,
 590                         hc->rid_memory, hc->res_memory);
 591                 hc->res_memory = 0;
 592         }
 593         if (hc->res_plx_memory != 0) {
 594                 bus_deactivate_resource(device, SYS_RES_MEMORY,
 595                         hc->rid_plx_memory, hc->res_plx_memory);
 596                 bus_release_resource(device, SYS_RES_MEMORY,
 597                         hc->rid_plx_memory, hc->res_plx_memory);
 598                 hc->res_plx_memory = 0;
 599         }
 600         return (0);
 601 }
 602
 603 /*
 604  * N2 Interrupt Service Routine
 605  *
 606  * First figure out which SCA gave the interrupt.
 607  * Process it.
 608  * See if there is other interrupts pending.
 609  * Repeat until there no interrupts remain.
 610  */
 611 static void
 612 srintr(void *arg)
 613 {
 614         struct sr_hardc *hc = (struct sr_hardc *)arg;
 615         sca_regs *sca = hc->sca;        /* MSCI register tree */
 616         u_char  isr0, isr1, isr2;       /* interrupt statii captured */
 617
 618 #if BUGGY > 1
 619         printf("sr: srintr_hc(hc=%08x)\n", hc);
 620 #endif
 621
 622         /*
 623          * Since multiple interfaces may share this interrupt, we must loop
 624          * until no interrupts are still pending service.
 625          */
 626         while (1) {
 627                 /*
 628                  * Read all three interrupt status registers from the N2
 629                  * card...
 630                  */
 631                 isr0 = SRC_GET8(hc->sca_base, sca->isr0);
 632                 isr1 = SRC_GET8(hc->sca_base, sca->isr1);
 633                 isr2 = SRC_GET8(hc->sca_base, sca->isr2);
 634
 635                 /*
 636                  * If all three registers returned 0, we've finished
 637                  * processing interrupts from this device, so we can quit
 638                  * this loop...
 639                  */
 640                 if ((isr0 | isr1 | isr2) == 0)
 641                         break;
 642
 643 #if BUGGY > 2
 644                 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n",
 645 #ifndef NETGRAPH
 646                         unit, isr0, isr1, isr2);
 647 #else
 648                         hc->cunit, isr0, isr1, isr2);
 649 #endif /* NETGRAPH */
 650 #endif
 651
 652                 /*
 653                  * Now we can dispatch the interrupts. Since we don't expect
 654                  * either MSCI or timer interrupts, we'll test for DMA
 655                  * interrupts first...
 656                  */
 657                 if (isr1)       /* DMA-initiated interrupt */
 658                         sr_dmac_intr(hc, isr1);
 659
 660                 if (isr0)       /* serial part IRQ? */
 661                         sr_msci_intr(hc, isr0);
 662
 663                 if (isr2)       /* timer-initiated interrupt */
 664                         sr_timer_intr(hc, isr2);
 665         }
 666 }
 667
 668 /*
 669  * This will only start the transmitter. It is assumed that the data
 670  * is already there.
 671  * It is normally called from srstart() or sr_dmac_intr().
 672  */
 673 static void
 674 sr_xmit(struct sr_softc *sc)
 675 {
 676         u_short cda_value;      /* starting descriptor */
 677         u_short eda_value;      /* ending descriptor */
 678         struct sr_hardc *hc;
 679 #ifndef NETGRAPH
 680         struct ifnet *ifp;      /* O/S Network Services */
 681 #endif /* NETGRAPH */
 682         dmac_channel *dmac;     /* DMA channel registers */
 683
 684 #if BUGGY > 0
 685         printf("sr: sr_xmit( sc=%08x)\n", sc);
 686 #endif
 687
 688         hc = sc->hc;
 689 #ifndef NETGRAPH
 690         ifp = &sc->ifsppp.pp_if;
 691 #endif /* NETGRAPH */
 692         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
 693
 694         /*
 695          * Get the starting and ending addresses of the chain to be
 696          * transmitted and pass these on to the DMA engine on-chip.
 697          */
 698         cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart;
 699         cda_value &= 0x00ffff;
 700         eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart;
 701         eda_value &= 0x00ffff;
 702
 703         SRC_PUT16(hc->sca_base, dmac->cda, cda_value);
 704         SRC_PUT16(hc->sca_base, dmac->eda, eda_value);
 705
 706         /*
 707          * Now we'll let the DMA status register know about this change
 708          */
 709         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
 710
 711         sc->xmit_busy = 1;      /* mark transmitter busy */
 712
 713 #if BUGGY > 2
 714         printf("sr%d: XMIT  cda=%04x, eda=%4x, rcda=%08lx\n",
 715                sc->unit, cda_value, eda_value,
 716                sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart);
 717 #endif
 718
 719         sc->txb_next_tx++;      /* update next transmit seq# */
 720
 721         if (sc->txb_next_tx == SR_TX_BLOCKS)    /* handle wrap... */
 722                 sc->txb_next_tx = 0;
 723
 724 #ifndef NETGRAPH
 725         /*
 726          * Finally, we'll set a timout (which will start srwatchdog())
 727          * within the O/S network services layer...
 728          */
 729         ifp->if_timer = 2;      /* Value in seconds. */
 730 #else
 731         /*
 732          * Don't time out for a while.
 733          */
 734         sc->out_dog = DOG_HOLDOFF;      /* give ourself some breathing space*/
 735 #endif /* NETGRAPH */
 736 }
 737
 738 /*
 739  * This function will be called from the upper level when a user add a
 740  * packet to be send, and from the interrupt handler after a finished
 741  * transmit.
 742  *
 743  * NOTE: it should run at spl_imp().
 744  *
 745  * This function only place the data in the oncard buffers. It does not
 746  * start the transmition. sr_xmit() does that.
 747  *
 748  * Transmitter idle state is indicated by the IFF_OACTIVE flag.
 749  * The function that clears that should ensure that the transmitter
 750  * and its DMA is in a "good" idle state.
 751  */
 752 #ifndef NETGRAPH
 753 static void
 754 srstart(struct ifnet *ifp)
 755 {
 756         struct sr_softc *sc;    /* channel control structure */
 757 #else
 758 static void
 759 srstart(struct sr_softc *sc)
 760 {
 761 #endif /* NETGRAPH */
 762         struct sr_hardc *hc;    /* card control/config block */
 763         int len;                /* total length of a packet */
 764         int pkts;               /* packets placed in DPRAM */
 765         int tlen;               /* working length of pkt */
 766         u_int i;
 767         struct mbuf *mtx;       /* message buffer from O/S */
 768         u_char *txdata;         /* buffer address in DPRAM */
 769         sca_descriptor *txdesc; /* working descriptor pointr */
 770         struct buf_block *blkp;
 771
 772 #ifndef NETGRAPH
 773 #if BUGGY > 0
 774         printf("sr: srstart( ifp=%08x)\n", ifp);
 775 #endif
 776         sc = ifp->if_softc;
 777         if ((ifp->if_flags & IFF_RUNNING) == 0)
 778                 return;
 779 #endif /* NETGRAPH */
 780         hc = sc->hc;
 781         /*
 782          * It is OK to set the memory window outside the loop because all tx
 783          * buffers and descriptors are assumed to be in the same 16K window.
 784          */
 785         if (hc->mempages) {
 786                 SRC_SET_ON(hc->iobase);
 787                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
 788         }
 789
 790         /*
 791          * Loop to place packets into DPRAM.
 792          *
 793          * We stay in this loop until there is nothing in
 794          * the TX queue left or the tx buffers are full.
 795          */
 796 top_srstart:
 797
 798         /*
 799          * See if we have space for more packets.
 800          */
 801         if (sc->txb_inuse == SR_TX_BLOCKS) {    /* out of space? */
 802 #ifndef NETGRAPH
 803                 ifp->if_flags |= IFF_OACTIVE;   /* yes, mark active */
 804 #else
 805                 /*ifp->if_flags |= IFF_OACTIVE;*/       /* yes, mark active */
 806 #endif /* NETGRAPH */
 807
 808                 if (hc->mempages)
 809                         SRC_SET_OFF(hc->iobase);
 810
 811 #if BUGGY > 9
 812                 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n",
 813                        sc->unit, sc->txb_inuse);
 814 #endif
 815                 return;
 816         }
 817         /*
 818          * OK, the card can take more traffic.  Let's see if there's any
 819          * pending from the system...
 820          *
 821          * NOTE:
 822          * The architecture of the networking interface doesn't
 823          * actually call us like 'write()', providing an address.  We get
 824          * started, a lot like a disk strategy routine, and we actually call
 825          * back out to the system to get traffic to send...
 826          *
 827          * NOTE:
 828          * If we were gonna run through another layer, we would use a
 829          * dispatch table to select the service we're getting a packet
 830          * from...
 831          */
 832 #ifndef NETGRAPH
 833         mtx = sppp_dequeue(ifp);
 834 #else /* NETGRAPH */
 835         IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 836         if (mtx == NULL) {
 837                 IF_DEQUEUE(&sc->xmitq, mtx);
 838         }
 839 #endif /* NETGRAPH */
 840         if (!mtx) {
 841                 if (hc->mempages)
 842                         SRC_SET_OFF(hc->iobase);
 843                 return;
 844         }
 845         /*
 846          * OK, we got a packet from the network services of the O/S. Now we
 847          * can move it into the DPRAM (under control of the descriptors) and
 848          * fire it off...
 849          */
 850         pkts = 0;
 851         i = 0;                  /* counts # of granules used */
 852
 853         blkp = &sc->block[sc->txb_new]; /* address of free granule */
 854         txdesc = (sca_descriptor *)
 855             (hc->mem_start + (blkp->txdesc & hc->winmsk));
 856
 857         txdata = (u_char *)(hc->mem_start
 858                             + (blkp->txstart & hc->winmsk));
 859
 860         /*
 861          * Now we'll try to install as many packets as possible into the
 862          * card's DP RAM buffers.
 863          */
 864         for (;;) {              /* perform actual copy of packet */
 865                 len = mtx->m_pkthdr.len;        /* length of message */
 866
 867 #if BUGGY > 1
 868                 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n",
 869                            sc->unit, mtx, len);
 870 #endif
 871
 872 #ifndef NETGRAPH
 873                 if (ifp->if_bpf)
 874                         bpf_mtap(ifp, mtx);
 875 #else   /* NETGRAPH */
 876                 sc->outbytes += len;
 877 #endif  /* NETGRAPH */
 878
 879                 /*
 880                  * We can perform a straight copy because the tranmit
 881                  * buffers won't wrap.
 882                  */
 883                 m_copydata(mtx, 0, len, txdata);
 884
 885                 /*
 886                  * Now we know how big the message is gonna be.  We must now
 887                  * construct the descriptors to drive this message out...
 888                  */
 889                 tlen = len;
 890                 while (tlen > SR_BUF_SIZ) {     /* loop for full granules */
 891                         txdesc->stat = 0;       /* reset bits */
 892                         txdesc->len = SR_BUF_SIZ;       /* size of granule */
 893                         tlen -= SR_BUF_SIZ;
 894
 895                         txdesc++;       /* move to next dscr */
 896                         txdata += SR_BUF_SIZ;   /* adjust data addr */
 897                         i++;
 898                 }
 899
 900                 /*
 901                  * This section handles the setting of the final piece of a
 902                  * message.
 903                  */
 904                 txdesc->stat = SCA_DESC_EOM;
 905                 txdesc->len = tlen;
 906                 pkts++;
 907
 908                 /*
 909                  * prepare for subsequent packets (if any)
 910                  */
 911                 txdesc++;
 912                 txdata += SR_BUF_SIZ;   /* next mem granule */
 913                 i++;            /* count of granules */
 914
 915                 /*
 916                  * OK, we've now placed the message into the DPRAM where it
 917                  * can be transmitted.  We'll now release the message memory
 918                  * and update the statistics...
 919                  */
 920                 m_freem(mtx);
 921 #ifndef NETGRAPH
 922                 ++sc->ifsppp.pp_if.if_opackets;
 923 #else   /* NETGRAPH */
 924                 sc->opackets++;
 925 #endif /* NETGRAPH */
 926
 927                 /*
 928                  * Check if we have space for another packet. XXX This is
 929                  * hardcoded.  A packet can't be larger than 3 buffers (3 x
 930                  * 512).
 931                  */
 932                 if ((i + 3) >= blkp->txmax) {   /* enough remains? */
 933 #if BUGGY > 9
 934                         printf("sr%d.srstart: i=%d (%d pkts); card full.\n",
 935                                sc->unit, i, pkts);
 936 #endif
 937                         break;
 938                 }
 939                 /*
 940                  * We'll pull the next message to be sent (if any)
 941                  */
 942 #ifndef NETGRAPH
 943                 mtx = sppp_dequeue(ifp);
 944 #else /* NETGRAPH */
 945                 IF_DEQUEUE(&sc->xmitq_hipri, mtx);
 946                 if (mtx == NULL) {
 947                         IF_DEQUEUE(&sc->xmitq, mtx);
 948                 }
 949 #endif /* NETGRAPH */
 950                 if (!mtx) {     /* no message?  We're done! */
 951 #if BUGGY > 9
 952                         printf("sr%d.srstart: pending=0, pkts=%d\n",
 953                                sc->unit, pkts);
 954 #endif
 955                         break;
 956                 }
 957         }
 958
 959         blkp->txtail = i;       /* record next free granule */
 960
 961         /*
 962          * Mark the last descriptor, so that the SCA know where to stop.
 963          */
 964         txdesc--;               /* back up to last descriptor in list */
 965         txdesc->stat |= SCA_DESC_EOT;   /* mark as end of list */
 966
 967         /*
 968          * Now we'll reset the transmit granule's descriptor address so we
 969          * can record this in the structure and fire it off w/ the DMA
 970          * processor of the serial chip...
 971          */
 972         txdesc = (sca_descriptor *)blkp->txdesc;
 973         blkp->txeda = (u_short)((u_int)&txdesc[i]);
 974
 975         sc->txb_inuse++;        /* update inuse status */
 976         sc->txb_new++;          /* new traffic wuz added */
 977
 978         if (sc->txb_new == SR_TX_BLOCKS)
 979                 sc->txb_new = 0;
 980
 981         /*
 982          * If the tranmitter wasn't marked as "busy" we will force it to be
 983          * started...
 984          */
 985         if (sc->xmit_busy == 0) {
 986                 sr_xmit(sc);
 987 #if BUGGY > 9
 988                 printf("sr%d.srstart: called sr_xmit()\n", sc->unit);
 989 #endif
 990         }
 991         goto top_srstart;
 992 }
 993
 994 #ifndef NETGRAPH
 995 /*
 996  * Handle ioctl's at the device level, though we *will* call up
 997  * a layer...
 998  */
 999 #if BUGGY > 2
1000 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0};
1001 #endif
1002
1003 static int
1004 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1005 {
1006         int s, error, was_up, should_be_up;
1007         struct sr_softc *sc = ifp->if_softc;
1008
1009 #if BUGGY > 0
1010         printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n",
1011                ifp->if_unit, ifp, cmd, data);
1012 #endif
1013
1014         was_up = ifp->if_flags & IFF_RUNNING;
1015
1016         error = sppp_ioctl(ifp, cmd, data);
1017
1018 #if BUGGY > 1
1019         printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n",
1020               ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags);
1021 #endif
1022
1023         if (error)
1024                 return error;
1025
1026         if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) {
1027 #if BUGGY > 2
1028                 if (bug_splats[sc->unit]++ < 2) {
1029                         printf("sr(%d).if_addrlist = %08x\n",
1030                                sc->unit, ifp->if_addrlist);
1031                         printf("sr(%d).if_bpf = %08x\n",
1032                                sc->unit, ifp->if_bpf);
1033                         printf("sr(%d).if_init = %08x\n",
1034                                sc->unit, ifp->if_init);
1035                         printf("sr(%d).if_output = %08x\n",
1036                                sc->unit, ifp->if_output);
1037                         printf("sr(%d).if_start = %08x\n",
1038                                sc->unit, ifp->if_start);
1039                         printf("sr(%d).if_done = %08x\n",
1040                                sc->unit, ifp->if_done);
1041                         printf("sr(%d).if_ioctl = %08x\n",
1042                                sc->unit, ifp->if_ioctl);
1043                         printf("sr(%d).if_reset = %08x\n",
1044                                sc->unit, ifp->if_reset);
1045                         printf("sr(%d).if_watchdog = %08x\n",
1046                                sc->unit, ifp->if_watchdog);
1047                 }
1048 #endif
1049                 return 0;
1050         }
1051
1052         s = splimp();
1053         should_be_up = ifp->if_flags & IFF_RUNNING;
1054
1055         if (!was_up && should_be_up) {
1056                 /*
1057                  * Interface should be up -- start it.
1058                  */
1059                 sr_up(sc);
1060                 srstart(ifp);
1061
1062                 /*
1063                  * XXX Clear the IFF_UP flag so that the link will only go
1064                  * up after sppp lcp and ipcp negotiation.
1065                  */
1066                 /* ifp->if_flags &= ~IFF_UP; */
1067         } else if (was_up && !should_be_up) {
1068                 /*
1069                  * Interface should be down -- stop it.
1070                  */
1071                 sr_down(sc);
1072                 sppp_flush(ifp);
1073         }
1074         splx(s);
1075         return 0;
1076 }
1077 #endif /* NETGRAPH */
1078
1079 /*
1080  * This is to catch lost tx interrupts.
1081  */
1082 static void
1083 #ifndef NETGRAPH
1084 srwatchdog(struct ifnet *ifp)
1085 #else
1086 srwatchdog(struct sr_softc *sc)
1087 #endif /* NETGRAPH */
1088 {
1089         int     got_st0, got_st1, got_st3, got_dsr;
1090 #ifndef NETGRAPH
1091         struct sr_softc *sc = ifp->if_softc;
1092 #endif /* NETGRAPH */
1093         struct sr_hardc *hc = sc->hc;
1094         msci_channel *msci = &hc->sca->msci[sc->scachan];
1095         dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan];
1096
1097 #if BUGGY > 0
1098 #ifndef NETGRAPH
1099         printf("srwatchdog(unit=%d)\n", unit);
1100 #else
1101         printf("srwatchdog(unit=%d)\n", sc->unit);
1102 #endif /* NETGRAPH */
1103 #endif
1104
1105 #ifndef NETGRAPH
1106         if (!(ifp->if_flags & IFF_RUNNING))
1107                 return;
1108
1109         ifp->if_oerrors++;      /* update output error count */
1110 #else   /* NETGRAPH */
1111         sc->oerrors++;  /* update output error count */
1112 #endif /* NETGRAPH */
1113
1114         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
1115         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
1116         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
1117         got_dsr = SRC_GET8(hc->sca_base, dmac->dsr);
1118
1119 #ifndef NETGRAPH
1120 #if     0
1121         if (ifp->if_flags & IFF_DEBUG)
1122 #endif
1123                 printf("sr%d: transmit failed, "
1124 #else   /* NETGRAPH */
1125         printf("sr%d: transmit failed, "
1126 #endif /* NETGRAPH */
1127                        "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n",
1128                        sc->unit,
1129                        got_st0, got_st1, got_st3, got_dsr);
1130
1131         if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) {
1132                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT);
1133                 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1134                 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN);
1135         }
1136         sc->xmit_busy = 0;
1137 #ifndef NETGRAPH
1138         ifp->if_flags &= ~IFF_OACTIVE;
1139 #else
1140         /*ifp->if_flags &= ~IFF_OACTIVE; */
1141 #endif /* NETGRAPH */
1142
1143         if (sc->txb_inuse && --sc->txb_inuse)
1144                 sr_xmit(sc);
1145
1146 #ifndef NETGRAPH
1147         srstart(ifp);   /* restart transmitter */
1148 #else
1149         srstart(sc);    /* restart transmitter */
1150 #endif /* NETGRAPH */
1151 }
1152
1153 static void
1154 sr_up(struct sr_softc *sc)
1155 {
1156         u_int *fecrp;
1157         struct sr_hardc *hc = sc->hc;
1158         sca_regs *sca = hc->sca;
1159         msci_channel *msci = &sca->msci[sc->scachan];
1160
1161 #if BUGGY > 0
1162         printf("sr_up(sc=%08x)\n", sc);
1163 #endif
1164
1165         /*
1166          * Enable transmitter and receiver. Raise DTR and RTS. Enable
1167          * interrupts.
1168          *
1169          * XXX What about using AUTO mode in msci->md0 ???
1170          */
1171         SRC_PUT8(hc->sca_base, msci->ctl,
1172                  SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS);
1173
1174         if (sc->scachan == 0)
1175                 switch (hc->cardtype) {
1176                 case SR_CRD_N2:
1177                         outb(hc->iobase + SR_MCR,
1178                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0));
1179                         break;
1180                 case SR_CRD_N2PCI:
1181                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1182                         *fecrp &= ~SR_FECR_DTR0;
1183                         break;
1184                 }
1185         else
1186                 switch (hc->cardtype) {
1187                 case SR_CRD_N2:
1188                         outb(hc->iobase + SR_MCR,
1189                              (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1));
1190                         break;
1191                 case SR_CRD_N2PCI:
1192                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1193                         *fecrp &= ~SR_FECR_DTR1;
1194                         break;
1195                 }
1196
1197         if (sc->scachan == 0) {
1198                 SRC_PUT8(hc->sca_base, sca->ier0,
1199                          SRC_GET8(hc->sca_base, sca->ier0) | 0x000F);
1200                 SRC_PUT8(hc->sca_base, sca->ier1,
1201                          SRC_GET8(hc->sca_base, sca->ier1) | 0x000F);
1202         } else {
1203                 SRC_PUT8(hc->sca_base, sca->ier0,
1204                          SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0);
1205                 SRC_PUT8(hc->sca_base, sca->ier1,
1206                          SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0);
1207         }
1208
1209         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE);
1210         inb(hc->iobase);        /* XXX slow it down a bit. */
1211         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE);
1212
1213 #ifndef NETGRAPH
1214 #ifdef USE_MODEMCK
1215         if (sr_watcher == 0)
1216                 sr_modemck(NULL);
1217 #endif
1218 #else   /* NETGRAPH */
1219         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1220         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
1221         sc->running = 1;
1222 #endif /* NETGRAPH */
1223 }
1224
1225 static void
1226 sr_down(struct sr_softc *sc)
1227 {
1228         u_int *fecrp;
1229         struct sr_hardc *hc = sc->hc;
1230         sca_regs *sca = hc->sca;
1231         msci_channel *msci = &sca->msci[sc->scachan];
1232
1233 #if BUGGY > 0
1234         printf("sr_down(sc=%08x)\n", sc);
1235 #endif
1236 #ifdef NETGRAPH
1237         untimeout(ngsr_watchdog_frame, sc, sc->handle);
1238         sc->running = 0;
1239 #endif /* NETGRAPH */
1240
1241         /*
1242          * Disable transmitter and receiver. Lower DTR and RTS. Disable
1243          * interrupts.
1244          */
1245         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE);
1246         inb(hc->iobase);        /* XXX slow it down a bit. */
1247         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE);
1248
1249         SRC_PUT8(hc->sca_base, msci->ctl,
1250                  SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS);
1251
1252         if (sc->scachan == 0)
1253                 switch (hc->cardtype) {
1254                 case SR_CRD_N2:
1255                         outb(hc->iobase + SR_MCR,
1256                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0));
1257                         break;
1258                 case SR_CRD_N2PCI:
1259                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1260                         *fecrp |= SR_FECR_DTR0;
1261                         break;
1262                 }
1263         else
1264                 switch (hc->cardtype) {
1265                 case SR_CRD_N2:
1266                         outb(hc->iobase + SR_MCR,
1267                              (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1));
1268                         break;
1269                 case SR_CRD_N2PCI:
1270                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1271                         *fecrp |= SR_FECR_DTR1;
1272                         break;
1273                 }
1274
1275         if (sc->scachan == 0) {
1276                 SRC_PUT8(hc->sca_base, sca->ier0,
1277                          SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F);
1278                 SRC_PUT8(hc->sca_base, sca->ier1,
1279                          SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F);
1280         } else {
1281                 SRC_PUT8(hc->sca_base, sca->ier0,
1282                          SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0);
1283                 SRC_PUT8(hc->sca_base, sca->ier1,
1284                          SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0);
1285         }
1286 }
1287
1288 /*
1289  * Initialize the card, allocate memory for the sr_softc structures
1290  * and fill in the pointers.
1291  */
1292 static void
1293 src_init(struct sr_hardc *hc)
1294 {
1295         struct sr_softc *sc = hc->sc;
1296         int x;
1297         u_int chanmem;
1298         u_int bufmem;
1299         u_int next;
1300         u_int descneeded;
1301
1302 #if BUGGY > 0
1303         printf("src_init(hc=%08x)\n", hc);
1304 #endif
1305
1306         chanmem = hc->memsize / hc->numports;
1307         next = 0;
1308
1309         for (x = 0; x < hc->numports; x++, sc++) {
1310                 int blk;
1311
1312                 for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1313                         sc->block[blk].txdesc = next;
1314                         bufmem = (16 * 1024) / SR_TX_BLOCKS;
1315                         descneeded = bufmem / SR_BUF_SIZ;
1316
1317                         sc->block[blk].txstart = sc->block[blk].txdesc
1318                             + ((((descneeded * sizeof(sca_descriptor))
1319                                  / SR_BUF_SIZ) + 1)
1320                                * SR_BUF_SIZ);
1321
1322                         sc->block[blk].txend = next + bufmem;
1323                         sc->block[blk].txmax =
1324                             (sc->block[blk].txend - sc->block[blk].txstart)
1325                             / SR_BUF_SIZ;
1326                         next += bufmem;
1327
1328 #if BUGGY > 2
1329                         printf("sr%d: blk %d: txdesc %08x, txstart %08x\n",
1330                                sc->unit, blk,
1331                                sc->block[blk].txdesc, sc->block[blk].txstart);
1332 #endif
1333                 }
1334
1335                 sc->rxdesc = next;
1336                 bufmem = chanmem - (bufmem * SR_TX_BLOCKS);
1337                 descneeded = bufmem / SR_BUF_SIZ;
1338                 sc->rxstart = sc->rxdesc +
1339                     ((((descneeded * sizeof(sca_descriptor)) /
1340                        SR_BUF_SIZ) + 1) * SR_BUF_SIZ);
1341                 sc->rxend = next + bufmem;
1342                 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ;
1343                 next += bufmem;
1344         }
1345 }
1346
1347 /*
1348  * The things done here are channel independent.
1349  *
1350  * Configure the sca waitstates.
1351  * Configure the global interrupt registers.
1352  * Enable master dma enable.
1353  */
1354 static void
1355 sr_init_sca(struct sr_hardc *hc)
1356 {
1357         sca_regs *sca = hc->sca;
1358
1359 #if BUGGY > 0
1360         printf("sr_init_sca(hc=%08x)\n", hc);
1361 #endif
1362
1363         /*
1364          * Do the wait registers. Set everything to 0 wait states.
1365          */
1366         SRC_PUT8(hc->sca_base, sca->pabr0, 0);
1367         SRC_PUT8(hc->sca_base, sca->pabr1, 0);
1368         SRC_PUT8(hc->sca_base, sca->wcrl, 0);
1369         SRC_PUT8(hc->sca_base, sca->wcrm, 0);
1370         SRC_PUT8(hc->sca_base, sca->wcrh, 0);
1371
1372         /*
1373          * Configure the interrupt registers. Most are cleared until the
1374          * interface is configured.
1375          */
1376         SRC_PUT8(hc->sca_base, sca->ier0, 0x00);        /* MSCI interrupts. */
1377         SRC_PUT8(hc->sca_base, sca->ier1, 0x00);        /* DMAC interrupts */
1378         SRC_PUT8(hc->sca_base, sca->ier2, 0x00);        /* TIMER interrupts. */
1379         SRC_PUT8(hc->sca_base, sca->itcr, 0x00);        /* Use ivr and no intr
1380                                                          * ack */
1381         SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */
1382         SRC_PUT8(hc->sca_base, sca->imvr, 0x40);
1383
1384         /*
1385          * Configure the timers. XXX Later
1386          */
1387
1388         /*
1389          * Set the DMA channel priority to rotate between all four channels.
1390          *
1391          * Enable all dma channels.
1392          */
1393         SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2);
1394         SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN);
1395 }
1396
1397 /*
1398  * Configure the msci
1399  *
1400  * NOTE: The serial port configuration is hardcoded at the moment.
1401  */
1402 static void
1403 sr_init_msci(struct sr_softc *sc)
1404 {
1405         int portndx;            /* on-board port number */
1406         u_int mcr_v;            /* contents of modem control */
1407         u_int *fecrp;           /* pointer for PCI's MCR i/o */
1408         struct sr_hardc *hc = sc->hc;
1409         msci_channel *msci = &hc->sca->msci[sc->scachan];
1410 #ifdef N2_TEST_SPEED
1411         int br_v;               /* contents for BR divisor */
1412         int etcndx;             /* index into ETC table */
1413         int fifo_v, gotspeed;   /* final tabled speed found */
1414         int tmc_v;              /* timer control register */
1415         int wanted;             /* speed (bitrate) wanted... */
1416         struct rate_line *rtp;
1417 #endif
1418
1419         portndx = sc->scachan;
1420
1421 #if BUGGY > 0
1422         printf("sr: sr_init_msci( sc=%08x)\n", sc);
1423 #endif
1424
1425         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET);
1426         SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 |
1427                  SCA_MD0_CRC_CCITT |
1428                  SCA_MD0_CRC_ENABLE |
1429                  SCA_MD0_MODE_HDLC);
1430         SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK);
1431         SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ);
1432
1433         /*
1434          * According to the manual I should give a reset after changing the
1435          * mode registers.
1436          */
1437         SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET);
1438         SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT |
1439                  SCA_CTL_UDRNC |
1440                  SCA_CTL_RTS);
1441
1442         /*
1443          * XXX Later we will have to support different clock settings.
1444          */
1445         switch (sc->clk_cfg) {
1446         default:
1447 #if BUGGY > 0
1448                 printf("sr%: clk_cfg=%08x, selected default clock.\n",
1449                        portndx, sc->clk_cfg);
1450 #endif
1451                 /* FALLTHROUGH */
1452         case SR_FLAGS_EXT_CLK:
1453                 /*
1454                  * For now all interfaces are programmed to use the RX clock
1455                  * for the TX clock.
1456                  */
1457
1458 #if BUGGY > 0
1459                 printf("sr%d: External Clock Selected.\n", portndx);
1460 #endif
1461
1462                 SRC_PUT8(hc->sca_base, msci->rxs,
1463                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1464                 SRC_PUT8(hc->sca_base, msci->txs,
1465                          SCA_TXS_CLK_RX | SCA_TXS_DIV1);
1466                 break;
1467
1468         case SR_FLAGS_EXT_SEP_CLK:
1469 #if BUGGY > 0
1470                 printf("sr%d: Split Clocking Selected.\n", portndx);
1471 #endif
1472
1473                 SRC_PUT8(hc->sca_base, msci->rxs,
1474                          SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1);
1475                 SRC_PUT8(hc->sca_base, msci->txs,
1476                          SCA_TXS_CLK_TXC | SCA_TXS_DIV1);
1477                 break;
1478
1479         case SR_FLAGS_INT_CLK:
1480 #if BUGGY > 0
1481                 printf("sr%d: Internal Clocking selected.\n", portndx);
1482 #endif
1483
1484                 /*
1485                  * XXX I do need some code to set the baud rate here!
1486                  */
1487 #ifdef N2_TEST_SPEED
1488                 switch (hc->cardtype) {
1489                 case SR_CRD_N2PCI:
1490                         fecrp = (u_int *)(hc->sca_base + SR_FECR);
1491                         mcr_v = *fecrp;
1492                         etcndx = 2;
1493                         break;
1494                 case SR_CRD_N2:
1495                 default:
1496                         mcr_v = inb(hc->iobase + SR_MCR);
1497                         etcndx = 0;
1498                 }
1499
1500                 fifo_v = 0x10;  /* stolen from Linux version */
1501
1502                 /*
1503                  * search for appropriate speed in table, don't calc it:
1504                  */
1505                 wanted = sr_test_speed[portndx];
1506                 rtp = &n2_rates[0];     /* point to first table item */
1507
1508                 while ((rtp->target > 0)        /* search table for speed */
1509                        &&(rtp->target != wanted))
1510                         rtp++;
1511
1512                 /*
1513                  * We've searched the table for a matching speed.  If we've
1514                  * found the correct rate line, we'll get the pre-calc'd
1515                  * values for the TMC and baud rate divisor for subsequent
1516                  * use...
1517                  */
1518                 if (rtp->target > 0) {  /* use table-provided values */
1519                         gotspeed = wanted;
1520                         tmc_v = rtp->tmc_reg;
1521                         br_v = rtp->br_reg;
1522                 } else {        /* otherwise assume 1MBit comm rate */
1523                         gotspeed = 10000;
1524                         tmc_v = 5;
1525                         br_v = 1;
1526                 }
1527
1528                 /*
1529                  * Now we mask in the enable clock output for the MCR:
1530                  */
1531                 mcr_v |= etc0vals[etcndx + portndx];
1532
1533                 /*
1534                  * Now we'll program the registers with these speed- related
1535                  * contents...
1536                  */
1537                 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v);
1538                 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v);
1539                 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v);
1540                 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v);
1541
1542                 switch (hc->cardtype) {
1543                 case SR_CRD_N2PCI:
1544                         *fecrp = mcr_v;
1545                         break;
1546                 case SR_CRD_N2:
1547                 default:
1548                         outb(hc->iobase + SR_MCR, mcr_v);
1549                 }
1550
1551 #if BUGGY > 0
1552                 if (wanted != gotspeed)
1553                         printf("sr%d: Speed wanted=%d, found=%d\n",
1554                                wanted, gotspeed);
1555
1556                 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n",
1557                        portndx, gotspeed, tmc_v, br_v);
1558 #endif
1559 #else
1560                 SRC_PUT8(hc->sca_base, msci->rxs,
1561                          SCA_RXS_CLK_INT | SCA_RXS_DIV1);
1562                 SRC_PUT8(hc->sca_base, msci->txs,
1563                          SCA_TXS_CLK_INT | SCA_TXS_DIV1);
1564
1565                 SRC_PUT8(hc->sca_base, msci->tmc, 5);
1566
1567                 if (portndx == 0)
1568                         switch (hc->cardtype) {
1569                         case SR_CRD_N2PCI:
1570                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1571                                 *fecrp |= SR_FECR_ETC0;
1572                                 break;
1573                         case SR_CRD_N2:
1574                         default:
1575                                 mcr_v = inb(hc->iobase + SR_MCR);
1576                                 mcr_v |= SR_MCR_ETC0;
1577                                 outb(hc->iobase + SR_MCR, mcr_v);
1578                         }
1579                 else
1580                         switch (hc->cardtype) {
1581                         case SR_CRD_N2:
1582                                 mcr_v = inb(hc->iobase + SR_MCR);
1583                                 mcr_v |= SR_MCR_ETC1;
1584                                 outb(hc->iobase + SR_MCR, mcr_v);
1585                                 break;
1586                         case SR_CRD_N2PCI:
1587                                 fecrp = (u_int *)(hc->sca_base + SR_FECR);
1588                                 *fecrp |= SR_FECR_ETC1;
1589                                 break;
1590                         }
1591 #endif
1592         }
1593
1594         /*
1595          * XXX Disable all interrupts for now. I think if you are using the
1596          * dmac you don't use these interrupts.
1597          */
1598         SRC_PUT8(hc->sca_base, msci->ie0, 0);
1599         SRC_PUT8(hc->sca_base, msci->ie1, 0x0C);
1600         SRC_PUT8(hc->sca_base, msci->ie2, 0);
1601         SRC_PUT8(hc->sca_base, msci->fie, 0);
1602
1603         SRC_PUT8(hc->sca_base, msci->sa0, 0);
1604         SRC_PUT8(hc->sca_base, msci->sa1, 0);
1605
1606         SRC_PUT8(hc->sca_base, msci->idl, 0x7E);        /* set flags value */
1607
1608         SRC_PUT8(hc->sca_base, msci->rrc, 0x0E);
1609         SRC_PUT8(hc->sca_base, msci->trc0, 0x10);
1610         SRC_PUT8(hc->sca_base, msci->trc1, 0x1F);
1611 }
1612
1613 /*
1614  * Configure the rx dma controller.
1615  */
1616 static void
1617 sr_init_rx_dmac(struct sr_softc *sc)
1618 {
1619         struct sr_hardc *hc;
1620         dmac_channel *dmac;
1621         sca_descriptor *rxd;
1622         u_int cda_v, sarb_v, rxbuf, rxda, rxda_d;
1623
1624 #if BUGGY > 0
1625         printf("sr_init_rx_dmac(sc=%08x)\n", sc);
1626 #endif
1627
1628         hc = sc->hc;
1629         dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)];
1630
1631         if (hc->mempages)
1632                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1633
1634         /*
1635          * This phase initializes the contents of the descriptor table
1636          * needed to construct a circular buffer...
1637          */
1638         rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk));
1639         rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk);
1640
1641         for (rxbuf = sc->rxstart;
1642              rxbuf < sc->rxend;
1643              rxbuf += SR_BUF_SIZ, rxd++) {
1644                 /*
1645                  * construct the circular chain...
1646                  */
1647                 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart;
1648                 rxd->cp = (u_short)(rxda & 0xffff);
1649
1650                 /*
1651                  * set the on-card buffer address...
1652                  */
1653                 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff);
1654                 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff);
1655
1656                 rxd->len = 0;   /* bytes resident w/in granule */
1657                 rxd->stat = 0xff;       /* The sca write here when finished */
1658         }
1659
1660         /*
1661          * heal the chain so that the last entry points to the first...
1662          */
1663         rxd--;
1664         rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1665
1666         /*
1667          * reset the reception handler's index...
1668          */
1669         sc->rxhind = 0;
1670
1671         /*
1672          * We'll now configure the receiver's DMA logic...
1673          */
1674         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA transfer */
1675         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1676
1677         /* XXX maybe also SCA_DMR_CNTE */
1678         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1679         SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ);
1680
1681         cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff);
1682         sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff);
1683
1684         SRC_PUT16(hc->sca_base, dmac->cda, cda_v);
1685         SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v);
1686
1687         rxd = (sca_descriptor *)sc->rxstart;
1688
1689         SRC_PUT16(hc->sca_base, dmac->eda,
1690                   (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff));
1691
1692         SRC_PUT8(hc->sca_base, dmac->dir, 0xF0);
1693
1694
1695         SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);  /* Enable DMA */
1696 }
1697
1698 /*
1699  * Configure the TX DMA descriptors.
1700  * Initialize the needed values and chain the descriptors.
1701  */
1702 static void
1703 sr_init_tx_dmac(struct sr_softc *sc)
1704 {
1705         int blk;
1706         u_int txbuf, txda, txda_d;
1707         struct sr_hardc *hc;
1708         sca_descriptor *txd;
1709         dmac_channel *dmac;
1710         struct buf_block *blkp;
1711         u_int x;
1712         u_int sarb_v;
1713
1714 #if BUGGY > 0
1715         printf("sr_init_tx_dmac(sc=%08x)\n", sc);
1716 #endif
1717
1718         hc = sc->hc;
1719         dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)];
1720
1721         if (hc->mempages)
1722                 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc);
1723
1724         /*
1725          * Initialize the array of descriptors for transmission
1726          */
1727         for (blk = 0; blk < SR_TX_BLOCKS; blk++) {
1728                 blkp = &sc->block[blk];
1729                 txd = (sca_descriptor *)(hc->mem_start
1730                                          + (blkp->txdesc & hc->winmsk));
1731                 txda_d = (u_int) hc->mem_start
1732                     - (blkp->txdesc & ~hc->winmsk);
1733
1734                 x = 0;
1735                 txbuf = blkp->txstart;
1736                 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) {
1737                         txda = (u_int) & txd[1] - txda_d + hc->mem_pstart;
1738                         txd->cp = (u_short)(txda & 0xffff);
1739
1740                         txd->bp = (u_short)((txbuf + hc->mem_pstart)
1741                                             & 0xffff);
1742                         txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16)
1743                                             & 0xff);
1744                         txd->len = 0;
1745                         txd->stat = 0;
1746                         x++;
1747                 }
1748
1749                 txd--;
1750                 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart)
1751                                     & 0xffff);
1752
1753                 blkp->txtail = (u_int)txd - (u_int)hc->mem_start;
1754         }
1755
1756         SRC_PUT8(hc->sca_base, dmac->dsr, 0);   /* Disable DMA */
1757         SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT);
1758         SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF);
1759         SRC_PUT8(hc->sca_base, dmac->dir,
1760                  SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF);
1761
1762         sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16;
1763         sarb_v &= 0x00ff;
1764
1765         SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v);
1766 }
1767
1768 /*
1769  * Look through the descriptors to see if there is a complete packet
1770  * available. Stop if we get to where the sca is busy.
1771  *
1772  * Return the length and status of the packet.
1773  * Return nonzero if there is a packet available.
1774  *
1775  * NOTE:
1776  * It seems that we get the interrupt a bit early. The updateing of
1777  * descriptor values is not always completed when this is called.
1778  */
1779 static int
1780 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat)
1781 {
1782         int granules;   /* count of granules in pkt */
1783         int wki, wko;
1784         struct sr_hardc *hc;
1785         sca_descriptor *rxdesc; /* current descriptor */
1786         sca_descriptor *endp;   /* ending descriptor */
1787         sca_descriptor *cda;    /* starting descriptor */
1788
1789         hc = sc->hc;            /* get card's information */
1790
1791         /*
1792          * set up starting descriptor by pulling that info from the DMA half
1793          * of the HD chip...
1794          */
1795         wki = DMAC_RXCH(sc->scachan);
1796         wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda);
1797
1798         cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk));
1799
1800 #if BUGGY > 1
1801         printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n",
1802                wki, wko, cda);
1803 #endif
1804
1805         /*
1806          * open the appropriate memory window and set our expectations...
1807          */
1808         if (hc->mempages) {
1809                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1810                 SRC_SET_ON(hc->iobase);
1811         }
1812         rxdesc = (sca_descriptor *)
1813             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1814         endp = rxdesc;
1815         rxdesc = &rxdesc[sc->rxhind];
1816         endp = &endp[sc->rxmax];
1817
1818         *len = 0;               /* reset result total length */
1819         granules = 0;           /* reset count of granules */
1820
1821         /*
1822          * This loop will scan descriptors, but it *will* puke up if we wrap
1823          * around to our starting point...
1824          */
1825         while (rxdesc != cda) {
1826                 *len += rxdesc->len;    /* increment result length */
1827                 granules++;
1828
1829                 /*
1830                  * If we hit a valid packet's completion we'll know we've
1831                  * got a live one, and that we can deliver the packet.
1832                  * Since we're only allowed to report a packet available,
1833                  * somebody else does that...
1834                  */
1835                 if (rxdesc->stat & SCA_DESC_EOM) {      /* End Of Message */
1836                         *rxstat = rxdesc->stat; /* return closing */
1837 #if BUGGY > 0
1838                         printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n",
1839                                sc->unit, *len, *rxstat, granules);
1840 #endif
1841                         return 1;       /* indicate success */
1842                 }
1843                 /*
1844                  * OK, this packet take up multiple granules.  Move on to
1845                  * the next descriptor so we can consider it...
1846                  */
1847                 rxdesc++;
1848
1849                 if (rxdesc == endp)     /* recognize & act on wrap point */
1850                         rxdesc = (sca_descriptor *)
1851                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1852         }
1853
1854         /*
1855          * Nothing found in the DPRAM.  Let the caller know...
1856          */
1857         *len = 0;
1858         *rxstat = 0;
1859
1860         return 0;
1861 }
1862
1863 /*
1864  * Copy a packet from the on card memory into a provided mbuf.
1865  * Take into account that buffers wrap and that a packet may
1866  * be larger than a buffer.
1867  */
1868 static void
1869 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len)
1870 {
1871         struct sr_hardc *hc;
1872         sca_descriptor *rxdesc;
1873         u_int rxdata;
1874         u_int rxmax;
1875         u_int off = 0;
1876         u_int tlen;
1877
1878 #if BUGGY > 0
1879         printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n",
1880                m, sc, len);
1881 #endif
1882
1883         hc = sc->hc;
1884
1885         rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ);
1886         rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ);
1887
1888         rxdesc = (sca_descriptor *)
1889             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1890         rxdesc = &rxdesc[sc->rxhind];
1891
1892         /*
1893          * Using the count of bytes in the received packet, we decrement it
1894          * for each granule (controller by an SCA descriptor) to control the
1895          * looping...
1896          */
1897         while (len) {
1898                 /*
1899                  * tlen gets the length of *this* granule... ...which is
1900                  * then copied to the target buffer.
1901                  */
1902                 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ;
1903
1904                 if (hc->mempages)
1905                         SRC_SET_MEM(hc->iobase, rxdata);
1906
1907                 bcopy(hc->mem_start + (rxdata & hc->winmsk),
1908                       mtod(m, caddr_t) +off,
1909                       tlen);
1910
1911                 off += tlen;
1912                 len -= tlen;
1913
1914                 /*
1915                  * now, return to the descriptor's window in DPRAM and reset
1916                  * the descriptor we've just suctioned...
1917                  */
1918                 if (hc->mempages)
1919                         SRC_SET_MEM(hc->iobase, sc->rxdesc);
1920
1921                 rxdesc->len = 0;
1922                 rxdesc->stat = 0xff;
1923
1924                 /*
1925                  * Move on to the next granule.  If we've any remaining
1926                  * bytes to process we'll just continue in our loop...
1927                  */
1928                 rxdata += SR_BUF_SIZ;
1929                 rxdesc++;
1930
1931                 if (rxdata == rxmax) {  /* handle the wrap point */
1932                         rxdata = sc->rxstart;
1933                         rxdesc = (sca_descriptor *)
1934                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1935                 }
1936         }
1937 }
1938
1939 /*
1940  * If single is set, just eat a packet. Otherwise eat everything up to
1941  * where cda points. Update pointers to point to the next packet.
1942  *
1943  * This handles "flushing" of a packet as received...
1944  *
1945  * If the "single" parameter is zero, all pending reeceive traffic will
1946  * be flushed out of existence.  A non-zero value will only drop the
1947  * *next* (currently) pending packet...
1948  */
1949 static void
1950 sr_eat_packet(struct sr_softc *sc, int single)
1951 {
1952         struct sr_hardc *hc;
1953         sca_descriptor *rxdesc; /* current descriptor being eval'd */
1954         sca_descriptor *endp;   /* last descriptor in chain */
1955         sca_descriptor *cda;    /* current start point */
1956         u_int loopcnt = 0;      /* count of packets flushed ??? */
1957         u_char stat;            /* captured status byte from descr */
1958
1959         hc = sc->hc;
1960         cda = (sca_descriptor *)(hc->mem_start +
1961                                  (SRC_GET16(hc->sca_base,
1962                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) &
1963                                   hc->winmsk));
1964
1965         /*
1966          * loop until desc->stat == (0xff || EOM) Clear the status and
1967          * length in the descriptor. Increment the descriptor.
1968          */
1969         if (hc->mempages)
1970                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
1971
1972         rxdesc = (sca_descriptor *)
1973             (hc->mem_start + (sc->rxdesc & hc->winmsk));
1974         endp = rxdesc;
1975         rxdesc = &rxdesc[sc->rxhind];
1976         endp = &endp[sc->rxmax];
1977
1978         /*
1979          * allow loop, but abort it if we wrap completely...
1980          */
1981         while (rxdesc != cda) {
1982                 loopcnt++;
1983
1984                 if (loopcnt > sc->rxmax) {
1985                         printf("sr%d: eat pkt %d loop, cda %x, "
1986                                "rxdesc %x, stat %x.\n",
1987                                sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc,
1988                                rxdesc->stat);
1989                         break;
1990                 }
1991                 stat = rxdesc->stat;
1992
1993                 rxdesc->len = 0;
1994                 rxdesc->stat = 0xff;
1995
1996                 rxdesc++;
1997                 sc->rxhind++;
1998
1999                 if (rxdesc == endp) {
2000                         rxdesc = (sca_descriptor *)
2001                             (hc->mem_start + (sc->rxdesc & hc->winmsk));
2002                         sc->rxhind = 0;
2003                 }
2004                 if (single && (stat == SCA_DESC_EOM))
2005                         break;
2006         }
2007
2008         /*
2009          * Update the eda to the previous descriptor.
2010          */
2011         rxdesc = (sca_descriptor *)sc->rxdesc;
2012         rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax];
2013
2014         SRC_PUT16(hc->sca_base,
2015                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2016                   (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff));
2017 }
2018
2019 /*
2020  * While there is packets available in the rx buffer, read them out
2021  * into mbufs and ship them off.
2022  */
2023 static void
2024 sr_get_packets(struct sr_softc *sc)
2025 {
2026         u_char rxstat;          /* acquired status byte */
2027         int i;
2028         int pkts;               /* count of packets found */
2029         int rxndx;              /* rcv buffer index */
2030         int tries;              /* settling time counter */
2031         u_int len;              /* length of pending packet */
2032         struct sr_hardc *hc;    /* card-level information */
2033         sca_descriptor *rxdesc; /* descriptor in memory */
2034 #ifndef NETGRAPH
2035         struct ifnet *ifp;      /* network intf ctl table */
2036 #endif /* NETGRAPH */
2037         struct mbuf *m = NULL;  /* message buffer */
2038
2039 #if BUGGY > 0
2040         printf("sr_get_packets(sc=%08x)\n", sc);
2041 #endif
2042
2043         hc = sc->hc;
2044 #ifndef NETGRAPH
2045         ifp = &sc->ifsppp.pp_if;
2046 #endif /* NETGRAPH */
2047
2048         if (hc->mempages) {
2049                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2050                 SRC_SET_ON(hc->iobase); /* enable shared memory */
2051         }
2052         pkts = 0;               /* reset count of found packets */
2053
2054         /*
2055          * for each complete packet in the receiving pool, process each
2056          * packet...
2057          */
2058         while (sr_packet_avail(sc, &len, &rxstat)) {    /* packet pending? */
2059                 /*
2060                  * I have seen situations where we got the interrupt but the
2061                  * status value wasn't deposited.  This code should allow
2062                  * the status byte's value to settle...
2063                  */
2064
2065                 tries = 5;
2066
2067                 while ((rxstat == 0x00ff)
2068                        && --tries)
2069                         sr_packet_avail(sc, &len, &rxstat);
2070
2071 #if BUGGY > 1
2072                 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n",
2073                        len, rxstat);
2074 #endif
2075
2076                 pkts++;
2077 #ifdef NETGRAPH
2078                 sc->inbytes += len;
2079                 sc->inlast = 0;
2080 #endif /* NETGRAPH */
2081
2082                 /*
2083                  * OK, we've settled the incoming message status. We can now
2084                  * process it...
2085                  */
2086                 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) {
2087 #if BUGGY > 1
2088                         printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n",
2089                                sc->unit, rxstat, len);
2090 #endif
2091
2092                         MGETHDR(m, M_DONTWAIT, MT_DATA);
2093                         if (m == NULL) {
2094                                 /*
2095                                  * eat (flush) packet if get mbuf fail!!
2096                                  */
2097                                 sr_eat_packet(sc, 1);
2098                                 continue;
2099                         }
2100                         /*
2101                          * construct control information for pass-off
2102                          */
2103 #ifndef NETGRAPH
2104                         m->m_pkthdr.rcvif = ifp;
2105 #else
2106                         m->m_pkthdr.rcvif = NULL;
2107 #endif /* NETGRAPH */
2108                         m->m_pkthdr.len = m->m_len = len;
2109                         if (len > MHLEN) {
2110                                 MCLGET(m, M_DONTWAIT);
2111                                 if ((m->m_flags & M_EXT) == 0) {
2112                                         /*
2113                                          * We couldn't get a big enough
2114                                          * message packet, so we'll send the
2115                                          * packet to /dev/null...
2116                                          */
2117                                         m_freem(m);
2118                                         sr_eat_packet(sc, 1);
2119                                         continue;
2120                                 }
2121                         }
2122                         /*
2123                          * OK, we've got a good message buffer.  Now we can
2124                          * copy the received message into it
2125                          */
2126                         sr_copy_rxbuf(m, sc, len);      /* copy from DPRAM */
2127
2128 #ifndef NETGRAPH
2129                         if (ifp->if_bpf)
2130                                 bpf_mtap(ifp, m);
2131
2132 #if BUGGY > 3
2133                         {
2134                                 u_char *bp;
2135
2136                                 bp = (u_char *)m;
2137                                 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n",
2138                                        sc->unit,
2139                                        bp[0], bp[1], bp[2],
2140                                        bp[4], bp[5], bp[6]);
2141                         }
2142 #endif
2143                         sppp_input(ifp, m);
2144                         ifp->if_ipackets++;
2145
2146 #else   /* NETGRAPH */
2147 #if BUGGY > 3
2148                         {
2149                                 u_char *bp;
2150
2151                                 bp = mtod(m,u_char *);
2152                                 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x",
2153                                        sc->unit,
2154                                        bp[0], bp[1], bp[2],
2155                                        bp[4], bp[5], bp[6]);
2156                                 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n",
2157                                        bp[6], bp[7], bp[8],
2158                                        bp[9], bp[10], bp[11]);
2159                         }
2160 #endif
2161                         ng_queue_data(sc->hook, m, NULL);
2162                         sc->ipackets++;
2163 #endif /* NETGRAPH */
2164                         /*
2165                          * Update the eda to the previous descriptor.
2166                          */
2167                         i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ;
2168                         sc->rxhind = (sc->rxhind + i) % sc->rxmax;
2169
2170                         rxdesc = (sca_descriptor *)sc->rxdesc;
2171                         rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax;
2172                         rxdesc = &rxdesc[rxndx];
2173
2174                         SRC_PUT16(hc->sca_base,
2175                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda,
2176                                   (u_short)((u_int)(rxdesc + hc->mem_pstart)
2177                                              & 0xffff));
2178
2179                 } else {
2180                         int got_st3, got_cda, got_eda;
2181                         int tries = 5;
2182
2183                         while ((rxstat == 0xff) && --tries)
2184                                 sr_packet_avail(sc, &len, &rxstat);
2185
2186                         /*
2187                          * It look like we get an interrupt early
2188                          * sometimes and then the status is not
2189                          * filled in yet.
2190                          */
2191                         if (tries && (tries != 5))
2192                                 continue;
2193
2194                         /*
2195                          * This chunk of code handles the error packets.
2196                          * We'll log them for posterity...
2197                          */
2198                         sr_eat_packet(sc, 1);
2199
2200 #ifndef NETGRAPH
2201                         ifp->if_ierrors++;
2202 #else
2203                         sc->ierrors[0]++;
2204 #endif /* NETGRAPH */
2205
2206                         got_st3 = SRC_GET8(hc->sca_base,
2207                                   hc->sca->msci[sc->scachan].st3);
2208                         got_cda = SRC_GET16(hc->sca_base,
2209                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda);
2210                         got_eda = SRC_GET16(hc->sca_base,
2211                                   hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda);
2212
2213 #if BUGGY > 0
2214                         printf("sr%d: Receive error chan %d, "
2215                                "stat %02x, msci st3 %02x,"
2216                                "rxhind %d, cda %04x, eda %04x.\n",
2217                                sc->unit, sc->scachan, rxstat,
2218                                got_st3, sc->rxhind, got_cda, got_eda);
2219 #endif
2220                 }
2221         }
2222
2223 #if BUGGY > 0
2224         printf("sr%d: sr_get_packets() found %d packet(s)\n",
2225                sc->unit, pkts);
2226 #endif
2227
2228         if (hc->mempages)
2229                 SRC_SET_OFF(hc->iobase);
2230 }
2231
2232 /*
2233  * All DMA interrupts come here.
2234  *
2235  * Each channel has two interrupts.
2236  * Interrupt A for errors and Interrupt B for normal stuff like end
2237  * of transmit or receive dmas.
2238  */
2239 static void
2240 sr_dmac_intr(struct sr_hardc *hc, u_char isr1)
2241 {
2242         u_char dsr;             /* contents of DMA Stat Reg */
2243         u_char dotxstart;       /* enables for tranmit part */
2244         int mch;                /* channel being processed */
2245         struct sr_softc *sc;    /* channel's softc structure */
2246         sca_regs *sca = hc->sca;
2247         dmac_channel *dmac;     /* dma structure of chip */
2248
2249 #if BUGGY > 0
2250         printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1);
2251 #endif
2252
2253         mch = 0;                /* assume chan0 on card */
2254         dotxstart = isr1;       /* copy for xmitter starts */
2255
2256         /*
2257          * Shortcut if there is no interrupts for dma channel 0 or 1.
2258          * Skip processing for channel 0 if no incoming hit
2259          */
2260         if ((isr1 & 0x0F) == 0) {
2261                 mch = 1;
2262                 isr1 >>= 4;
2263         }
2264         do {
2265                 sc = &hc->sc[mch];
2266
2267                 /*
2268                  * Transmit channel - DMA Status Register Evaluation
2269                  */
2270                 if (isr1 & 0x0C) {
2271                         dmac = &sca->dmac[DMAC_TXCH(mch)];
2272
2273                         /*
2274                          * get the DMA Status Register contents and write
2275                          * back to reset interrupt...
2276                          */
2277                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2278                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2279
2280                         /*
2281                          * Check for (& process) a Counter overflow
2282                          */
2283                         if (dsr & SCA_DSR_COF) {
2284                                 printf("sr%d: TX DMA Counter overflow, "
2285                                        "txpacket no %lu.\n",
2286 #ifndef NETGRAPH
2287                                        sc->unit, sc->ifsppp.pp_if.if_opackets);
2288                                 sc->ifsppp.pp_if.if_oerrors++;
2289 #else
2290                                        sc->unit, sc->opackets);
2291                                 sc->oerrors++;
2292 #endif /* NETGRAPH */
2293                         }
2294                         /*
2295                          * Check for (& process) a Buffer overflow
2296                          */
2297                         if (dsr & SCA_DSR_BOF) {
2298                                 printf("sr%d: TX DMA Buffer overflow, "
2299                                        "txpacket no %lu, dsr %02x, "
2300                                        "cda %04x, eda %04x.\n",
2301 #ifndef NETGRAPH
2302                                        sc->unit, sc->ifsppp.pp_if.if_opackets,
2303 #else
2304                                        sc->unit, sc->opackets,
2305 #endif /* NETGRAPH */
2306                                        dsr,
2307                                        SRC_GET16(hc->sca_base, dmac->cda),
2308                                        SRC_GET16(hc->sca_base, dmac->eda));
2309 #ifndef NETGRAPH
2310                                 sc->ifsppp.pp_if.if_oerrors++;
2311 #else
2312                                 sc->oerrors++;
2313 #endif /* NETGRAPH */
2314                         }
2315                         /*
2316                          * Check for (& process) an End of Transfer (OK)
2317                          */
2318                         if (dsr & SCA_DSR_EOT) {
2319                                 /*
2320                                  * This should be the most common case.
2321                                  *
2322                                  * Clear the IFF_OACTIVE flag.
2323                                  *
2324                                  * Call srstart to start a new transmit if
2325                                  * there is data to transmit.
2326                                  */
2327 #if BUGGY > 0
2328                                 printf("sr%d: TX Completed OK\n", sc->unit);
2329 #endif
2330                                 sc->xmit_busy = 0;
2331 #ifndef NETGRAPH
2332                                 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE;
2333                                 sc->ifsppp.pp_if.if_timer = 0;
2334 #else
2335                                 /* XXX may need to mark tx inactive? */
2336                                 sc->out_deficit++;
2337                                 sc->out_dog = DOG_HOLDOFF;
2338 #endif /* NETGRAPH */
2339
2340                                 if (sc->txb_inuse && --sc->txb_inuse)
2341                                         sr_xmit(sc);
2342                         }
2343                 }
2344                 /*
2345                  * Receive channel processing of DMA Status Register
2346                  */
2347                 if (isr1 & 0x03) {
2348                         dmac = &sca->dmac[DMAC_RXCH(mch)];
2349
2350                         dsr = SRC_GET8(hc->sca_base, dmac->dsr);
2351                         SRC_PUT8(hc->sca_base, dmac->dsr, dsr);
2352
2353                         /*
2354                          * End of frame processing (MSG OK?)
2355                          */
2356                         if (dsr & SCA_DSR_EOM) {
2357 #if BUGGY > 0
2358                                 int tt, ind;
2359
2360 #ifndef NETGRAPH
2361                                 tt = sc->ifsppp.pp_if.if_ipackets;
2362 #else   /* NETGRAPH */
2363                                 tt = sc->ipackets;
2364 #endif /* NETGRAPH */
2365                                 ind = sc->rxhind;
2366 #endif
2367
2368                                 sr_get_packets(sc);
2369 #if BUGGY > 0
2370 #ifndef NETGRAPH
2371                                 if (tt == sc->ifsppp.pp_if.if_ipackets)
2372 #else   /* NETGRAPH */
2373                                 if (tt == sc->ipackets)
2374 #endif /* NETGRAPH */
2375                                 {
2376                                         sca_descriptor *rxdesc;
2377                                         int i;
2378
2379                                         printf("SR: RXINTR isr1 %x, dsr %x, "
2380                                                "no data %d pkts, orxind %d.\n",
2381                                                dotxstart, dsr, tt, ind);
2382                                         printf("SR: rxdesc %x, rxstart %x, "
2383                                                "rxend %x, rxhind %d, "
2384                                                "rxmax %d.\n",
2385                                                sc->rxdesc, sc->rxstart,
2386                                                sc->rxend, sc->rxhind,
2387                                                sc->rxmax);
2388                                         printf("SR: cda %x, eda %x.\n",
2389                                             SRC_GET16(hc->sca_base, dmac->cda),
2390                                             SRC_GET16(hc->sca_base, dmac->eda));
2391
2392                                         if (hc->mempages) {
2393                                                 SRC_SET_ON(hc->iobase);
2394                                                 SRC_SET_MEM(hc->iobase, sc->rxdesc);
2395                                         }
2396                                         rxdesc = (sca_descriptor *)
2397                                                  (hc->mem_start +
2398                                                   (sc->rxdesc & hc->winmsk));
2399                                         rxdesc = &rxdesc[sc->rxhind];
2400
2401                                         for (i = 0; i < 3; i++, rxdesc++)
2402                                                 printf("SR: rxdesc->stat %x, "
2403                                                        "len %d.\n",
2404                                                        rxdesc->stat,
2405                                                        rxdesc->len);
2406
2407                                         if (hc->mempages)
2408                                                 SRC_SET_OFF(hc->iobase);
2409                                 }
2410 #endif /* BUGGY */
2411                         }
2412                         /*
2413                          * Check for Counter overflow
2414                          */
2415                         if (dsr & SCA_DSR_COF) {
2416                                 printf("sr%d: RX DMA Counter overflow, "
2417                                        "rxpkts %lu.\n",
2418 #ifndef NETGRAPH
2419                                        sc->unit, sc->ifsppp.pp_if.if_ipackets);
2420                                 sc->ifsppp.pp_if.if_ierrors++;
2421 #else   /* NETGRAPH */
2422                                        sc->unit, sc->ipackets);
2423                                 sc->ierrors[1]++;
2424 #endif /* NETGRAPH */
2425                         }
2426                         /*
2427                          * Check for Buffer overflow
2428                          */
2429                         if (dsr & SCA_DSR_BOF) {
2430                                 printf("sr%d: RX DMA Buffer overflow, "
2431                                        "rxpkts %lu, rxind %d, "
2432                                        "cda %x, eda %x, dsr %x.\n",
2433 #ifndef NETGRAPH
2434                                        sc->unit, sc->ifsppp.pp_if.if_ipackets,
2435 #else   /* NETGRAPH */
2436                                        sc->unit, sc->ipackets,
2437 #endif /* NETGRAPH */
2438                                        sc->rxhind,
2439                                        SRC_GET16(hc->sca_base, dmac->cda),
2440                                        SRC_GET16(hc->sca_base, dmac->eda),
2441                                        dsr);
2442
2443                                 /*
2444                                  * Make sure we eat as many as possible.
2445                                  * Then get the system running again.
2446                                  */
2447                                 if (hc->mempages)
2448                                         SRC_SET_ON(hc->iobase);
2449
2450                                 sr_eat_packet(sc, 0);
2451 #ifndef NETGRAPH
2452                                 sc->ifsppp.pp_if.if_ierrors++;
2453 #else   /* NETGRAPH */
2454                                 sc->ierrors[2]++;
2455 #endif /* NETGRAPH */
2456
2457                                 SRC_PUT8(hc->sca_base,
2458                                          sca->msci[mch].cmd,
2459                                          SCA_CMD_RXMSGREJ);
2460
2461                                 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE);
2462
2463 #if BUGGY > 0
2464                                 printf("sr%d: RX DMA Buffer overflow, "
2465                                        "rxpkts %lu, rxind %d, "
2466                                        "cda %x, eda %x, dsr %x. After\n",
2467                                        sc->unit,
2468 #ifndef NETGRAPH
2469                                        sc->ipackets,
2470 #else   /* NETGRAPH */
2471                                        sc->ifsppp.pp_if.if_ipackets,
2472 #endif /* NETGRAPH */
2473                                        sc->rxhind,
2474                                        SRC_GET16(hc->sca_base, dmac->cda),
2475                                        SRC_GET16(hc->sca_base, dmac->eda),
2476                                        SRC_GET8(hc->sca_base, dmac->dsr));
2477 #endif
2478
2479                                 if (hc->mempages)
2480                                         SRC_SET_OFF(hc->iobase);
2481                         }
2482                         /*
2483                          * End of Transfer
2484                          */
2485                         if (dsr & SCA_DSR_EOT) {
2486                                 /*
2487                                  * If this happen, it means that we are
2488                                  * receiving faster than what the processor
2489                                  * can handle.
2490                                  *
2491                                  * XXX We should enable the dma again.
2492                                  */
2493                                 printf("sr%d: RX End of xfer, rxpkts %lu.\n",
2494                                        sc->unit,
2495 #ifndef NETGRAPH
2496                                        sc->ifsppp.pp_if.if_ipackets);
2497                                 sc->ifsppp.pp_if.if_ierrors++;
2498 #else
2499                                        sc->ipackets);
2500                                 sc->ierrors[3]++;
2501 #endif /* NETGRAPH */
2502                         }
2503                 }
2504                 isr1 >>= 4;     /* process next half of ISR */
2505                 mch++;          /* and move to next channel */
2506         } while ((mch < NCHAN) && isr1);        /* loop for each chn */
2507
2508         /*
2509          * Now that we have done all the urgent things, see if we can fill
2510          * the transmit buffers.
2511          */
2512         for (mch = 0; mch < NCHAN; mch++) {
2513                 if (dotxstart & 0x0C) { /* TX initiation enabled? */
2514                         sc = &hc->sc[mch];
2515 #ifndef NETGRAPH
2516                         srstart(&sc->ifsppp.pp_if);
2517 #else
2518                         srstart(sc);
2519 #endif /* NETGRAPH */
2520                 }
2521                 dotxstart >>= 4;/* shift for next channel */
2522         }
2523 }
2524 #ifndef NETGRAPH
2525 #ifdef USE_MODEMCK
2526 /*
2527  * Perform timeout on an FR channel
2528  *
2529  * Establish a periodic check of open N2 ports;  If
2530  * a port is open/active, its DCD state is checked
2531  * and a loss of DCD is recognized (and eventually
2532  * processed).
2533  */
2534 static void
2535 sr_modemck(void *arg)
2536 {
2537         u_int s;
2538         int card;               /* card index in table */
2539         int cards;              /* card list index */
2540         int mch;                /* channel on card */
2541         u_char dcd_v;           /* Data Carrier Detect */
2542         u_char got_st0;         /* contents of ST0 */
2543         u_char got_st1;         /* contents of ST1 */
2544         u_char got_st2;         /* contents of ST2 */
2545         u_char got_st3;         /* contents of ST3 */
2546         struct sr_hardc *hc;    /* card's configuration */
2547         struct sr_hardc *Card[16];/* up to 16 cards in system */
2548         struct sr_softc *sc;    /* channel's softc structure */
2549         struct ifnet *ifp;      /* interface control table */
2550         msci_channel *msci;     /* regs specific to channel */
2551
2552         s = splimp();
2553
2554 #if     0
2555         if (sr_opens == 0) {    /* count of "up" channels */
2556                 sr_watcher = 0; /* indicate no watcher */
2557                 splx(s);
2558                 return;
2559         }
2560 #endif
2561
2562         sr_watcher = 1;         /* mark that we're online */
2563
2564         /*
2565          * Now we'll need a list of cards to process.  Since we can handle
2566          * both ISA and PCI cards (and I didn't think of making this logic
2567          * global YET) we'll generate a single table of card table
2568          * addresses.
2569          */
2570         cards = 0;
2571
2572         for (card = 0; card < NSR; card++) {
2573                 hc = &sr_hardc[card];
2574
2575                 if (hc->sc == (void *)0)
2576                         continue;
2577
2578                 Card[cards++] = hc;
2579         }
2580
2581         hc = sr_hardc_pci;
2582
2583         while (hc) {
2584                 Card[cards++] = hc;
2585                 hc = hc->next;
2586         }
2587
2588         /*
2589          * OK, we've got work we can do.  Let's do it... (Please note that
2590          * this code _only_ deals w/ ISA cards)
2591          */
2592         for (card = 0; card < cards; card++) {
2593                 hc = Card[card];/* get card table */
2594
2595                 for (mch = 0; mch < hc->numports; mch++) {
2596                         sc = &hc->sc[mch];
2597
2598                         ifp = &sc->ifsppp.pp_if;
2599
2600                         /*
2601                          * if this channel isn't "up", skip it
2602                          */
2603                         if ((ifp->if_flags & IFF_UP) == 0)
2604                                 continue;
2605
2606                         /*
2607                          * OK, now we can go looking at this channel's
2608                          * actual register contents...
2609                          */
2610                         msci = &hc->sca->msci[sc->scachan];
2611
2612                         /*
2613                          * OK, now we'll look into the actual status of this
2614                          * channel...
2615                          *
2616                          * I suck in more registers than strictly needed
2617                          */
2618                         got_st0 = SRC_GET8(hc->sca_base, msci->st0);
2619                         got_st1 = SRC_GET8(hc->sca_base, msci->st1);
2620                         got_st2 = SRC_GET8(hc->sca_base, msci->st2);
2621                         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2622
2623                         /*
2624                          * We want to see if the DCD signal is up (DCD is
2625                          * true if zero)
2626                          */
2627                         dcd_v = (got_st3 & SCA_ST3_DCD) == 0;
2628
2629                         if (dcd_v == 0)
2630                                 printf("sr%d: DCD lost\n", sc->unit);
2631                 }
2632         }
2633
2634         /*
2635          * OK, now set up for the next modem signal checking pass...
2636          */
2637         timeout(sr_modemck, NULL, hz);
2638
2639         splx(s);
2640 }
2641 #endif
2642 #else   /* NETGRAPH */
2643 /*
2644  * If a port is open/active, it's DCD state is checked
2645  * and a loss of DCD is recognized (and eventually processed?).
2646  */
2647 static void
2648 sr_modemck(struct sr_softc *sc )
2649 {
2650         u_int s;
2651         u_char got_st3;                 /* contents of ST3 */
2652         struct sr_hardc *hc = sc->hc;   /* card's configuration */
2653         msci_channel *msci;             /* regs specific to channel */
2654
2655         s = splimp();
2656
2657
2658         if (sc->running == 0)
2659                 return;
2660         /*
2661          * OK, now we can go looking at this channel's register contents...
2662          */
2663         msci = &hc->sca->msci[sc->scachan];
2664         got_st3 = SRC_GET8(hc->sca_base, msci->st3);
2665
2666         /*
2667          * We want to see if the DCD signal is up (DCD is true if zero)
2668          */
2669         sc->dcd = (got_st3 & SCA_ST3_DCD) == 0;
2670         splx(s);
2671 }
2672
2673 #endif  /* NETGRAPH */
2674 static void
2675 sr_msci_intr(struct sr_hardc *hc, u_char isr0)
2676 {
2677         printf("src%d: SRINTR: MSCI\n", hc->cunit);
2678 }
2679
2680 static void
2681 sr_timer_intr(struct sr_hardc *hc, u_char isr2)
2682 {
2683         printf("src%d: SRINTR: TIMER\n", hc->cunit);
2684 }
2685
2686 #ifdef  NETGRAPH
2687 /*****************************************
2688  * Device timeout/watchdog routine.
2689  * called once per second.
2690  * checks to see that if activity was expected, that it hapenned.
2691  * At present we only look to see if expected output was completed.
2692  */
2693 static void
2694 ngsr_watchdog_frame(void * arg)
2695 {
2696         struct sr_softc * sc = arg;
2697         int s;
2698         int     speed;
2699
2700         if (sc->running == 0)
2701                 return; /* if we are not running let timeouts die */
2702         /*
2703          * calculate the apparent throughputs
2704          *  XXX a real hack
2705          */
2706         s = splimp();
2707         speed = sc->inbytes - sc->lastinbytes;
2708         sc->lastinbytes = sc->inbytes;
2709         if ( sc->inrate < speed )
2710                 sc->inrate = speed;
2711         speed = sc->outbytes - sc->lastoutbytes;
2712         sc->lastoutbytes = sc->outbytes;
2713         if ( sc->outrate < speed )
2714                 sc->outrate = speed;
2715         sc->inlast++;
2716         splx(s);
2717
2718         if ((sc->inlast > QUITE_A_WHILE)
2719         && (sc->out_deficit > LOTS_OF_PACKETS)) {
2720                 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit);
2721                 s = splimp();
2722                 sr_down(sc);
2723                 sr_up(sc);
2724                 sc->inlast = sc->out_deficit = 0;
2725                 splx(s);
2726         } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */
2727                 if (sc->out_dog == 0) {
2728                         log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n",
2729                                         sc->unit);
2730                         s = splimp();
2731                         srwatchdog(sc);
2732 #if 0
2733                         sr_down(sc);
2734                         sr_up(sc);
2735 #endif
2736                         splx(s);
2737                         sc->inlast = sc->out_deficit = 0;
2738                 } else {
2739                         sc->out_dog--;
2740                 }
2741         }
2742         sr_modemck(sc);         /* update the DCD status */
2743         sc->handle = timeout(ngsr_watchdog_frame, sc, hz);
2744 }
2745
2746 /***********************************************************************
2747  * This section contains the methods for the Netgraph interface
2748  ***********************************************************************/
2749 /*
2750  * It is not possible or allowable to create a node of this type.
2751  * If the hardware exists, it will already have created it.
2752  */
2753 static  int
2754 ngsr_constructor(node_p *nodep)
2755 {
2756         return (EINVAL);
2757 }
2758
2759 /*
2760  * give our ok for a hook to be added...
2761  * If we are not running this should kick the device into life.
2762  * The hook's private info points to our stash of info about that
2763  * channel.
2764  */
2765 static int
2766 ngsr_newhook(node_p node, hook_p hook, const char *name)
2767 {
2768         struct sr_softc *       sc = node->private;
2769
2770         /*
2771          * check if it's our friend the debug hook
2772          */
2773         if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) {
2774                 hook->private = NULL; /* paranoid */
2775                 sc->debug_hook = hook;
2776                 return (0);
2777         }
2778
2779         /*
2780          * Check for raw mode hook.
2781          */
2782         if (strcmp(name, NG_SR_HOOK_RAW) != 0) {
2783                 return (EINVAL);
2784         }
2785         hook->private = sc;
2786         sc->hook = hook;
2787         sc->datahooks++;
2788         sr_up(sc);
2789         return (0);
2790 }
2791
2792 /*
2793  * incoming messages.
2794  * Just respond to the generic TEXT_STATUS message
2795  */
2796 static  int
2797 ngsr_rcvmsg(node_p node,
2798         struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp)
2799 {
2800         struct sr_softc *       sc;
2801         int error = 0;
2802
2803         sc = node->private;
2804         switch (msg->header.typecookie) {
2805             case        NG_SR_COOKIE:
2806                 error = EINVAL;
2807                 break;
2808             case        NGM_GENERIC_COOKIE:
2809                 switch(msg->header.cmd) {
2810                     case NGM_TEXT_STATUS: {
2811                             char        *arg;
2812                             int pos = 0;
2813                             int resplen = sizeof(struct ng_mesg) + 512;
2814                             MALLOC(*resp, struct ng_mesg *, resplen,
2815                                         M_NETGRAPH, M_NOWAIT | M_ZERO);
2816                             if (*resp == NULL) {
2817                                 error = ENOMEM;
2818                                 break;
2819                             }
2820                             arg = (*resp)->data;
2821
2822                             /*
2823                              * Put in the throughput information.
2824                              */
2825                             pos = sprintf(arg, "%ld bytes in, %ld bytes out\n"
2826                             "highest rate seen: %ld B/S in, %ld B/S out\n",
2827                             sc->inbytes, sc->outbytes,
2828                             sc->inrate, sc->outrate);
2829                             pos += sprintf(arg + pos,
2830                                 "%ld output errors\n",
2831                                 sc->oerrors);
2832                             pos += sprintf(arg + pos,
2833                                 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n",
2834                                 sc->ierrors[0],
2835                                 sc->ierrors[1],
2836                                 sc->ierrors[2],
2837                                 sc->ierrors[3],
2838                                 sc->ierrors[4],
2839                                 sc->ierrors[5]);
2840
2841                             (*resp)->header.version = NG_VERSION;
2842                             (*resp)->header.arglen = strlen(arg) + 1;
2843                             (*resp)->header.token = msg->header.token;
2844                             (*resp)->header.typecookie = NG_SR_COOKIE;
2845                             (*resp)->header.cmd = msg->header.cmd;
2846                             strncpy((*resp)->header.cmdstr, "status",
2847                                         NG_CMDSTRLEN);
2848                         }
2849                         break;
2850                     default:
2851                         error = EINVAL;
2852                         break;
2853                     }
2854                 break;
2855             default:
2856                 error = EINVAL;
2857                 break;
2858         }
2859         free(msg, M_NETGRAPH);
2860         return (error);
2861 }
2862
2863 /*
2864  * get data from another node and transmit it to the correct channel
2865  */
2866 static  int
2867 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta)
2868 {
2869         int s;
2870         int error = 0;
2871         struct sr_softc * sc = hook->node->private;
2872         struct ifqueue  *xmitq_p;
2873
2874         /*
2875          * data doesn't come in from just anywhere (e.g control hook)
2876          */
2877         if ( hook->private == NULL) {
2878                 error = ENETDOWN;
2879                 goto bad;
2880         }
2881
2882         /*
2883          * Now queue the data for when it can be sent
2884          */
2885         if (meta && meta->priority > 0) {
2886                 xmitq_p = (&sc->xmitq_hipri);
2887         } else {
2888                 xmitq_p = (&sc->xmitq);
2889         }
2890         s = splimp();
2891         if (IF_QFULL(xmitq_p)) {
2892                 IF_DROP(xmitq_p);
2893                 splx(s);
2894                 error = ENOBUFS;
2895                 goto bad;
2896         }
2897         IF_ENQUEUE(xmitq_p, m);
2898         srstart(sc);
2899         splx(s);
2900         return (0);
2901
2902 bad:
2903         /*
2904          * It was an error case.
2905          * check if we need to free the mbuf, and then return the error
2906          */
2907         NG_FREE_DATA(m, meta);
2908         return (error);
2909 }
2910
2911 /*
2912  * do local shutdown processing..
2913  * this node will refuse to go away, unless the hardware says to..
2914  * don't unref the node, or remove our name. just clear our links up.
2915  */
2916 static  int
2917 ngsr_rmnode(node_p node)
2918 {
2919         struct sr_softc * sc = node->private;
2920
2921         sr_down(sc);
2922         ng_cutlinks(node);
2923         node->flags &= ~NG_INVALID; /* bounce back to life */
2924         return (0);
2925 }
2926
2927 /* already linked */
2928 static  int
2929 ngsr_connect(hook_p hook)
2930 {
2931         /* be really amiable and just say "YUP that's OK by me! " */
2932         return (0);
2933 }
2934
2935 /*
2936  * notify on hook disconnection (destruction)
2937  *
2938  * Invalidate the private data associated with this dlci.
2939  * For this type, removal of the last link resets tries to destroy the node.
2940  * As the device still exists, the shutdown method will not actually
2941  * destroy the node, but reset the device and leave it 'fresh' :)
2942  *
2943  * The node removal code will remove all references except that owned by the
2944  * driver.
2945  */
2946 static  int
2947 ngsr_disconnect(hook_p hook)
2948 {
2949         struct sr_softc * sc = hook->node->private;
2950         int     s;
2951         /*
2952          * If it's the data hook, then free resources etc.
2953          */
2954         if (hook->private) {
2955                 s = splimp();
2956                 sc->datahooks--;
2957                 if (sc->datahooks == 0)
2958                         sr_down(sc);
2959                 splx(s);
2960         } else {
2961                 sc->debug_hook = NULL;
2962         }
2963         return (0);
2964 }
2965
2966 /*
2967  * called during bootup
2968  * or LKM loading to put this type into the list of known modules
2969  */
2970 static void
2971 ngsr_init(void *ignored)
2972 {
2973         if (ng_newtype(&typestruct))
2974                 printf("ngsr install failed\n");
2975         ngsr_done_init = 1;
2976 }
2977 #endif /* NETGRAPH */
2978
2979 /*
2980  ********************************* END ************************************
2981  */