2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * capi/iavc/iavc_card.c
26 * The AVM ISDN controllers' card specific support routines.
28 * $FreeBSD: src/sys/i4b/capi/iavc/iavc_card.c,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
29 * $DragonFly: src/sys/net/i4b/capi/iavc/iavc_card.c,v 1.2 2003/06/17 04:28:39 dillon Exp $
36 #if (NIAVC > 0) && (NI4BCAPI > 0)
38 #include <sys/param.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
42 #include <sys/socket.h>
45 #include <machine/clock.h>
47 #include <machine/bus.h>
48 #include <machine/resource.h>
52 #include <machine/i4b_debug.h>
53 #include <machine/i4b_ioctl.h>
54 #include <machine/i4b_trace.h>
56 #include <i4b/include/i4b_global.h>
57 #include <i4b/include/i4b_l3l4.h>
58 #include <i4b/include/i4b_mbuf.h>
60 #include <i4b/capi/capi.h>
62 #include <i4b/capi/iavc/iavc.h>
65 // AVM B1 (active BRI, PIO mode)
68 int b1_detect(iavc_softc_t *sc)
70 if ((iavc_read_port(sc, B1_INSTAT) & 0xfc) ||
71 (iavc_read_port(sc, B1_OUTSTAT) & 0xfc))
74 b1io_outp(sc, B1_INSTAT, 0x02);
75 b1io_outp(sc, B1_OUTSTAT, 0x02);
76 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) != 2 ||
77 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe) != 2)
80 b1io_outp(sc, B1_INSTAT, 0x00);
81 b1io_outp(sc, B1_OUTSTAT, 0x00);
82 if ((iavc_read_port(sc, B1_INSTAT) & 0xfe) ||
83 (iavc_read_port(sc, B1_OUTSTAT) & 0xfe))
86 return (0); /* found */
89 void b1_disable_irq(iavc_softc_t *sc)
91 b1io_outp(sc, B1_INSTAT, 0x00);
94 void b1_reset(iavc_softc_t *sc)
96 b1io_outp(sc, B1_RESET, 0);
99 b1io_outp(sc, B1_RESET, 1);
102 b1io_outp(sc, B1_RESET, 0);
107 // Newer PCI-based B1's, and T1's, supports DMA
110 int b1dma_detect(iavc_softc_t *sc)
112 AMCC_WRITE(sc, AMCC_MCSR, 0);
114 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
116 AMCC_WRITE(sc, AMCC_MCSR, 0);
119 AMCC_WRITE(sc, AMCC_RXLEN, 0);
120 AMCC_WRITE(sc, AMCC_TXLEN, 0);
122 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
124 if (AMCC_READ(sc, AMCC_INTCSR) != 0)
127 AMCC_WRITE(sc, AMCC_RXPTR, 0xffffffff);
128 AMCC_WRITE(sc, AMCC_TXPTR, 0xffffffff);
129 if ((AMCC_READ(sc, AMCC_RXPTR) != 0xfffffffc) ||
130 (AMCC_READ(sc, AMCC_TXPTR) != 0xfffffffc))
133 AMCC_WRITE(sc, AMCC_RXPTR, 0);
134 AMCC_WRITE(sc, AMCC_TXPTR, 0);
135 if ((AMCC_READ(sc, AMCC_RXPTR) != 0) ||
136 (AMCC_READ(sc, AMCC_TXPTR) != 0))
139 iavc_write_port(sc, 0x10, 0x00);
140 iavc_write_port(sc, 0x07, 0x00);
142 iavc_write_port(sc, 0x02, 0x02);
143 iavc_write_port(sc, 0x03, 0x02);
145 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x02) ||
146 (iavc_read_port(sc, 0x03) != 0x03))
149 iavc_write_port(sc, 0x02, 0x00);
150 iavc_write_port(sc, 0x03, 0x00);
152 if (((iavc_read_port(sc, 0x02) & 0xfe) != 0x00) ||
153 (iavc_read_port(sc, 0x03) != 0x01))
156 return (0); /* found */
159 void b1dma_reset(iavc_softc_t *sc)
164 AMCC_WRITE(sc, AMCC_INTCSR, sc->sc_csr);
165 AMCC_WRITE(sc, AMCC_MCSR, 0);
166 AMCC_WRITE(sc, AMCC_RXLEN, 0);
167 AMCC_WRITE(sc, AMCC_TXLEN, 0);
169 iavc_write_port(sc, 0x10, 0x00); /* XXX magic numbers from */
170 iavc_write_port(sc, 0x07, 0x00); /* XXX the linux driver */
174 AMCC_WRITE(sc, AMCC_MCSR, 0);
176 AMCC_WRITE(sc, AMCC_MCSR, 0x0f000000);
178 AMCC_WRITE(sc, AMCC_MCSR, 0);
183 // AVM T1 (active PRI)
186 /* XXX how do these differ from b1io_{read,write}_reg()? XXX */
188 static int b1dma_tx_empty(int iobase)
189 { return inb(iobase + 3) & 1; }
191 static int b1dma_rx_full(int iobase)
192 { return inb(iobase + 2) & 1; }
194 static int b1dma_tolink(iavc_softc_t *sc, void *buf, int len)
197 char *s = (char*) buf;
200 while (!b1dma_tx_empty(sc->sc_iobase) && spin < 100000)
202 if (!b1dma_tx_empty(sc->sc_iobase))
204 t1io_outp(sc, 1, *s++);
209 static int b1dma_fromlink(iavc_softc_t *sc, void *buf, int len)
212 char *s = (char*) buf;
215 while (!b1dma_rx_full(sc->sc_iobase) && spin < 100000)
217 if (!b1dma_rx_full(sc->sc_iobase))
219 *s++ = t1io_inp(sc, 0);
224 static int WriteReg(iavc_softc_t *sc, u_int32_t reg, u_int8_t val)
227 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
228 b1dma_tolink(sc, ®, 4) == 0) {
230 return b1dma_tolink(sc, &tmp, 4);
235 static u_int8_t ReadReg(iavc_softc_t *sc, u_int32_t reg)
238 if (b1dma_tolink(sc, &cmd, 1) == 0 &&
239 b1dma_tolink(sc, ®, 4) == 0) {
241 if (b1dma_fromlink(sc, &tmp, 4) == 0)
242 return (u_int8_t) tmp;
247 int t1_detect(iavc_softc_t *sc)
249 int ret = b1dma_detect(sc);
252 if ((WriteReg(sc, 0x80001000, 0x11) != 0) ||
253 (WriteReg(sc, 0x80101000, 0x22) != 0) ||
254 (WriteReg(sc, 0x80201000, 0x33) != 0) ||
255 (WriteReg(sc, 0x80301000, 0x44) != 0))
258 if ((ReadReg(sc, 0x80001000) != 0x11) ||
259 (ReadReg(sc, 0x80101000) != 0x22) ||
260 (ReadReg(sc, 0x80201000) != 0x33) ||
261 (ReadReg(sc, 0x80301000) != 0x44))
264 if ((WriteReg(sc, 0x80001000, 0x55) != 0) ||
265 (WriteReg(sc, 0x80101000, 0x66) != 0) ||
266 (WriteReg(sc, 0x80201000, 0x77) != 0) ||
267 (WriteReg(sc, 0x80301000, 0x88) != 0))
270 if ((ReadReg(sc, 0x80001000) != 0x55) ||
271 (ReadReg(sc, 0x80101000) != 0x66) ||
272 (ReadReg(sc, 0x80201000) != 0x77) ||
273 (ReadReg(sc, 0x80301000) != 0x88))
276 return 0; /* found */
279 void t1_disable_irq(iavc_softc_t *sc)
281 iavc_write_port(sc, T1_IRQMASTER, 0x00);
284 void t1_reset(iavc_softc_t *sc)
287 iavc_write_port(sc, B1_INSTAT, 0x00);
288 iavc_write_port(sc, B1_OUTSTAT, 0x00);
289 iavc_write_port(sc, T1_IRQMASTER, 0x00);
290 iavc_write_port(sc, T1_RESETBOARD, 0x0f);