2 * Copyright (c) 1991 The Regents of the University of California.
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33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.25 2006/10/23 21:50:31 dillon Exp $
37 #ifndef _ARCH_ISA_INTR_MACHDEP_H_
38 #define _ARCH_ISA_INTR_MACHDEP_H_
42 #include <sys/types.h>
47 * Low level interrupt code.
52 #define IDT_OFFSET 0x20
53 #define IDT_OFFSET_SYSCALL 0x80
54 #define IDT_OFFSET_IPI 0xe0
57 * Local APIC TPR priority vector levels:
59 * 0xff (255) +-------------+
60 * | | 15 (IPIs: Xcpustop, Xspuriousint)
61 * 0xf0 (240) +-------------+
62 * | | 14 (IPIs: Xinvltlb, Xipiq, Xtimer)
63 * 0xe0 (224) +-------------+
65 * 0xd0 (208) +-------------+
67 * 0xc0 (192) +-------------+
69 * 0xb0 (176) +-------------+
71 * 0xa0 (160) +-------------+
73 * 0x90 (144) +-------------+
74 * | | 8 (syscall at 0x80)
75 * 0x80 (128) +-------------+
77 * 0x70 (112) +-------------+
79 * 0x60 (96) +-------------+
81 * 0x50 (80) +-------------+
83 * 0x40 (64) +-------------+
85 * 0x30 (48) +-------------+
86 * | | 2 (hardware INTs)
87 * 0x20 (32) +-------------+
88 * | | 1 (exceptions, traps, etc.)
89 * 0x10 (16) +-------------+
90 * | | 0 (exceptions, traps, etc.)
91 * 0x00 (0) +-------------+
95 /* Local APIC Task Priority Register */
96 #define TPR_IPI (IDT_OFFSET_IPI - 1)
102 #define IDT_OFFSET_IPIG1 IDT_OFFSET_IPI
105 #define XINVLTLB_OFFSET (IDT_OFFSET_IPIG1 + 0)
107 /* IPI group1 1: unused (was inter-cpu clock handling) */
108 /* IPI group1 2: unused (was inter-cpu rendezvous) */
111 #define XIPIQ_OFFSET (IDT_OFFSET_IPIG1 + 3)
113 /* Local APIC TIMER */
114 #define XTIMER_OFFSET (IDT_OFFSET_IPIG1 + 4)
116 /* IPI group1 5 ~ 15: unused */
122 #define IDT_OFFSET_IPIG2 (IDT_OFFSET_IPIG1 + TPR_STEP)
124 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
125 #define XCPUSTOP_OFFSET (IDT_OFFSET_IPIG2 + 0)
127 /* IPI group2 1 ~ 14: unused */
129 /* NOTE: this vector MUST be xxxx1111 */
130 #define XSPURIOUSINT_OFFSET (IDT_OFFSET_IPIG2 + 15)
135 * Type of the first (asm) part of an interrupt handler.
137 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
139 #define IDTVEC(name) __CONCAT(X,name)
142 Xspuriousint, /* handle APIC "spurious INTs" */
143 Xtimer; /* handle LAPIC timer INT */
147 Xcpustop, /* CPU stops & waits for another CPU to restart it */
148 Xinvltlb, /* TLB shootdowns */
149 Xipiq; /* handle lwkt_send_ipiq() requests */
156 #endif /* !_ARCH_ISA_INTR_MACHDEP_H_ */