2996193e54aea6499f83e62f27f985b6a0385ccf
[dragonfly.git] / sys / dev / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2  */
3 /*
4  *
5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the
10  * "Software"), to deal in the Software without restriction, including
11  * without limitation the rights to use, copy, modify, merge, publish,
12  * distribute, sub license, and/or sell copies of the Software, and to
13  * permit persons to whom the Software is furnished to do so, subject to
14  * the following conditions:
15  *
16  * The above copyright notice and this permission notice (including the
17  * next paragraph) shall be included in all copies or substantial portions
18  * of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27  *
28  */
29
30 #include <drm/drmP.h>
31 #include <drm/i915_drm.h>
32 #include "i915_drv.h"
33 #include <drm/drm_pciids.h>
34 #include "intel_drv.h"
35
36 #include <linux/module.h>
37 #include <drm/drm_crtc_helper.h>
38
39 static int i915_modeset __read_mostly = 1;
40 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
41 module_param_named(modeset, i915_modeset, int, 0400);
42 MODULE_PARM_DESC(modeset,
43                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
44                 "1=on, -1=force vga console preference [default])");
45
46 unsigned int i915_fbpercrtc __always_unused = 0;
47 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
48
49 int i915_panel_ignore_lid __read_mostly = 1;
50 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53                 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54                 "-1=force lid closed, -2=force lid open)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
58 module_param_named(powersave, i915_powersave, int, 0600);
59 MODULE_PARM_DESC(powersave,
60                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61
62 int i915_semaphores __read_mostly = -1;
63 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
64 module_param_named(semaphores, i915_semaphores, int, 0400);
65 MODULE_PARM_DESC(semaphores,
66                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
67
68 int i915_enable_rc6 __read_mostly = -1;
69 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
70 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
71 MODULE_PARM_DESC(i915_enable_rc6,
72                 "Enable power-saving render C-state 6. "
73                 "Different stages can be selected via bitmask values "
74                 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
75                 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
76                 "default: -1 (use per-chip default)");
77
78 int i915_enable_fbc __read_mostly = -1;
79 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
80 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
81 MODULE_PARM_DESC(i915_enable_fbc,
82                 "Enable frame buffer compression for power savings "
83                 "(default: -1 (use per-chip default))");
84
85 unsigned int i915_lvds_downclock __read_mostly = 0;
86 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
87 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
88 MODULE_PARM_DESC(lvds_downclock,
89                 "Use panel (LVDS/eDP) downclocking for power savings "
90                 "(default: false)");
91
92 int i915_lvds_channel_mode __read_mostly = 0;
93 TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
94 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
95 MODULE_PARM_DESC(lvds_channel_mode,
96                  "Specify LVDS channel mode "
97                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
98
99 int i915_panel_use_ssc __read_mostly = -1;
100 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
101 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
102 MODULE_PARM_DESC(lvds_use_ssc,
103                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
104                 "(default: auto from VBT)");
105
106 int i915_vbt_sdvo_panel_type __read_mostly = -1;
107 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
108 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
109 MODULE_PARM_DESC(vbt_sdvo_panel_type,
110                 "Override/Ignore selection of SDVO panel mode in the VBT "
111                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
112
113 static int i915_try_reset = 1;
114 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
115 module_param_named(reset, i915_try_reset, bool, 0600);
116 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
117
118 bool i915_enable_hangcheck __read_mostly = true;
119 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
120 MODULE_PARM_DESC(enable_hangcheck,
121                 "Periodically check GPU activity for detecting hangs. "
122                 "WARNING: Disabling this can cause system wide hangs. "
123                 "(default: true)");
124
125 int i915_enable_ppgtt __read_mostly = -1;
126 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
127 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
128 MODULE_PARM_DESC(i915_enable_ppgtt,
129                 "Enable PPGTT (default: true)");
130
131 int i915_enable_psr __read_mostly = 0;
132 module_param_named(enable_psr, i915_enable_psr, int, 0600);
133 MODULE_PARM_DESC(enable_psr, "Enable PSR (default: false)");
134
135 unsigned int i915_preliminary_hw_support __read_mostly = 1;
136 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
137 MODULE_PARM_DESC(preliminary_hw_support,
138                 "Enable preliminary hardware support.");
139
140 int i915_disable_power_well __read_mostly = 1;
141 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
142 MODULE_PARM_DESC(disable_power_well,
143                  "Disable the power well when possible (default: true)");
144
145 int i915_enable_ips __read_mostly = 1;
146 module_param_named(enable_ips, i915_enable_ips, int, 0600);
147 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
148
149 bool i915_fastboot __read_mostly = 0;
150 module_param_named(fastboot, i915_fastboot, bool, 0600);
151 MODULE_PARM_DESC(fastboot, "Try to skip unnecessary mode sets at boot time "
152                  "(default: false)");
153
154 int i915_enable_pc8 __read_mostly = 1;
155 module_param_named(enable_pc8, i915_enable_pc8, int, 0600);
156 MODULE_PARM_DESC(enable_pc8, "Enable support for low power package C states (PC8+) (default: true)");
157
158 int i915_pc8_timeout __read_mostly = 5000;
159 module_param_named(pc8_timeout, i915_pc8_timeout, int, 0600);
160 MODULE_PARM_DESC(pc8_timeout, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
161
162 bool i915_prefault_disable __read_mostly;
163 module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
164 MODULE_PARM_DESC(prefault_disable,
165                 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
166
167 static struct drm_driver driver;
168
169 static const struct intel_device_info intel_i830_info = {
170         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
171         .has_overlay = 1, .overlay_needs_physical = 1,
172         .ring_mask = RENDER_RING,
173 };
174
175 static const struct intel_device_info intel_845g_info = {
176         .gen = 2, .num_pipes = 1,
177         .has_overlay = 1, .overlay_needs_physical = 1,
178         .ring_mask = RENDER_RING,
179 };
180
181 static const struct intel_device_info intel_i85x_info = {
182         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
183         .cursor_needs_physical = 1,
184         .has_overlay = 1, .overlay_needs_physical = 1,
185         .has_fbc = 1,
186         .ring_mask = RENDER_RING,
187 };
188
189 static const struct intel_device_info intel_i865g_info = {
190         .gen = 2, .num_pipes = 1,
191         .has_overlay = 1, .overlay_needs_physical = 1,
192         .ring_mask = RENDER_RING,
193 };
194
195 static const struct intel_device_info intel_i915g_info = {
196         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
197         .has_overlay = 1, .overlay_needs_physical = 1,
198         .ring_mask = RENDER_RING,
199 };
200 static const struct intel_device_info intel_i915gm_info = {
201         .gen = 3, .is_mobile = 1, .num_pipes = 2,
202         .cursor_needs_physical = 1,
203         .has_overlay = 1, .overlay_needs_physical = 1,
204         .supports_tv = 1,
205         .has_fbc = 1,
206         .ring_mask = RENDER_RING,
207 };
208 static const struct intel_device_info intel_i945g_info = {
209         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
210         .has_overlay = 1, .overlay_needs_physical = 1,
211         .ring_mask = RENDER_RING,
212 };
213 static const struct intel_device_info intel_i945gm_info = {
214         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
215         .has_hotplug = 1, .cursor_needs_physical = 1,
216         .has_overlay = 1, .overlay_needs_physical = 1,
217         .supports_tv = 1,
218         .has_fbc = 1,
219         .ring_mask = RENDER_RING,
220 };
221
222 static const struct intel_device_info intel_i965g_info = {
223         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
224         .has_hotplug = 1,
225         .has_overlay = 1,
226         .ring_mask = RENDER_RING,
227 };
228
229 static const struct intel_device_info intel_i965gm_info = {
230         .gen = 4, .is_crestline = 1, .num_pipes = 2,
231         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
232         .has_overlay = 1,
233         .supports_tv = 1,
234         .ring_mask = RENDER_RING,
235 };
236
237 static const struct intel_device_info intel_g33_info = {
238         .gen = 3, .is_g33 = 1, .num_pipes = 2,
239         .need_gfx_hws = 1, .has_hotplug = 1,
240         .has_overlay = 1,
241         .ring_mask = RENDER_RING,
242 };
243
244 static const struct intel_device_info intel_g45_info = {
245         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
246         .has_pipe_cxsr = 1, .has_hotplug = 1,
247         .ring_mask = RENDER_RING | BSD_RING,
248 };
249
250 static const struct intel_device_info intel_gm45_info = {
251         .gen = 4, .is_g4x = 1, .num_pipes = 2,
252         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
253         .has_pipe_cxsr = 1, .has_hotplug = 1,
254         .supports_tv = 1,
255         .ring_mask = RENDER_RING | BSD_RING,
256 };
257
258 static const struct intel_device_info intel_pineview_info = {
259         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
260         .need_gfx_hws = 1, .has_hotplug = 1,
261         .has_overlay = 1,
262 };
263
264 static const struct intel_device_info intel_ironlake_d_info = {
265         .gen = 5, .num_pipes = 2,
266         .need_gfx_hws = 1, .has_hotplug = 1,
267         .ring_mask = RENDER_RING | BSD_RING,
268 };
269
270 static const struct intel_device_info intel_ironlake_m_info = {
271         .gen = 5, .is_mobile = 1, .num_pipes = 2,
272         .need_gfx_hws = 1, .has_hotplug = 1,
273         .has_fbc = 1,
274         .ring_mask = RENDER_RING | BSD_RING,
275 };
276
277 static const struct intel_device_info intel_sandybridge_d_info = {
278         .gen = 6, .num_pipes = 2,
279         .need_gfx_hws = 1, .has_hotplug = 1,
280         .has_fbc = 1,
281         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
282         .has_llc = 1,
283 };
284
285 static const struct intel_device_info intel_sandybridge_m_info = {
286         .gen = 6, .is_mobile = 1, .num_pipes = 2,
287         .need_gfx_hws = 1, .has_hotplug = 1,
288         .has_fbc = 1,
289         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
290         .has_llc = 1,
291 };
292
293 #define GEN7_FEATURES  \
294         .gen = 7, .num_pipes = 3, \
295         .need_gfx_hws = 1, .has_hotplug = 1, \
296         .has_fbc = 1, \
297         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
298         .has_llc = 1
299
300 static const struct intel_device_info intel_ivybridge_d_info = {
301         GEN7_FEATURES,
302         .is_ivybridge = 1,
303 };
304
305 static const struct intel_device_info intel_ivybridge_m_info = {
306         GEN7_FEATURES,
307         .is_ivybridge = 1,
308         .is_mobile = 1,
309 };
310
311 static const struct intel_device_info intel_ivybridge_q_info = {
312         GEN7_FEATURES,
313         .is_ivybridge = 1,
314         .num_pipes = 0, /* legal, last one wins */
315 };
316
317 static const struct intel_device_info intel_valleyview_m_info = {
318         GEN7_FEATURES,
319         .is_mobile = 1,
320         .num_pipes = 2,
321         .is_valleyview = 1,
322         .display_mmio_offset = VLV_DISPLAY_BASE,
323         .has_fbc = 0, /* legal, last one wins */
324         .has_llc = 0, /* legal, last one wins */
325 };
326
327 static const struct intel_device_info intel_valleyview_d_info = {
328         GEN7_FEATURES,
329         .num_pipes = 2,
330         .is_valleyview = 1,
331         .display_mmio_offset = VLV_DISPLAY_BASE,
332         .has_fbc = 0, /* legal, last one wins */
333         .has_llc = 0, /* legal, last one wins */
334 };
335
336 static const struct intel_device_info intel_haswell_d_info = {
337         GEN7_FEATURES,
338         .is_haswell = 1,
339         .has_ddi = 1,
340         .has_fpga_dbg = 1,
341         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
342 };
343
344 static const struct intel_device_info intel_haswell_m_info = {
345         GEN7_FEATURES,
346         .is_haswell = 1,
347         .is_mobile = 1,
348         .has_ddi = 1,
349         .has_fpga_dbg = 1,
350         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
351 };
352
353 static const struct intel_device_info intel_broadwell_d_info = {
354         .gen = 8, .num_pipes = 3,
355         .need_gfx_hws = 1, .has_hotplug = 1,
356         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
357         .has_llc = 1,
358         .has_ddi = 1,
359 };
360
361 static const struct intel_device_info intel_broadwell_m_info = {
362         .gen = 8, .is_mobile = 1, .num_pipes = 3,
363         .need_gfx_hws = 1, .has_hotplug = 1,
364         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
365         .has_llc = 1,
366         .has_ddi = 1,
367 };
368
369 /*
370  * Make sure any device matches here are from most specific to most
371  * general.  For example, since the Quanta match is based on the subsystem
372  * and subvendor IDs, we need it to come before the more general IVB
373  * PCI ID matches, otherwise we'll use the wrong info struct above.
374  */
375 #define INTEL_PCI_IDS \
376         INTEL_I830_IDS(&intel_i830_info),       \
377         INTEL_I845G_IDS(&intel_845g_info),      \
378         INTEL_I85X_IDS(&intel_i85x_info),       \
379         INTEL_I865G_IDS(&intel_i865g_info),     \
380         INTEL_I915G_IDS(&intel_i915g_info),     \
381         INTEL_I915GM_IDS(&intel_i915gm_info),   \
382         INTEL_I945G_IDS(&intel_i945g_info),     \
383         INTEL_I945GM_IDS(&intel_i945gm_info),   \
384         INTEL_I965G_IDS(&intel_i965g_info),     \
385         INTEL_G33_IDS(&intel_g33_info),         \
386         INTEL_I965GM_IDS(&intel_i965gm_info),   \
387         INTEL_GM45_IDS(&intel_gm45_info),       \
388         INTEL_G45_IDS(&intel_g45_info),         \
389         INTEL_PINEVIEW_IDS(&intel_pineview_info),       \
390         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),   \
391         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),   \
392         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),     \
393         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),     \
394         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),       \
395         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),       \
396         INTEL_HSW_D_IDS(&intel_haswell_d_info), \
397         INTEL_HSW_M_IDS(&intel_haswell_m_info), \
398         INTEL_VLV_M_IDS(&intel_valleyview_m_info),      \
399         INTEL_VLV_D_IDS(&intel_valleyview_d_info),      \
400         INTEL_BDW_M_IDS(&intel_broadwell_m_info),       \
401         INTEL_BDW_D_IDS(&intel_broadwell_d_info)
402
403 static const struct pci_device_id pciidlist[] = {               /* aka */
404         INTEL_PCI_IDS,
405         {0, 0}
406 };
407
408 #define PCI_VENDOR_INTEL        0x8086
409
410 void intel_detect_pch(struct drm_device *dev)
411 {
412         struct drm_i915_private *dev_priv = dev->dev_private;
413         struct device *pch = NULL;
414
415         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
416          * (which really amounts to a PCH but no South Display).
417          */
418         if (INTEL_INFO(dev)->num_pipes == 0) {
419                 dev_priv->pch_type = PCH_NOP;
420                 return;
421         }
422
423         /* XXX The ISA bridge probe causes some old Core2 machines to hang */
424         if (INTEL_INFO(dev)->gen < 5)
425                 return;
426
427         /*
428          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
429          * make graphics device passthrough work easy for VMM, that only
430          * need to expose ISA bridge to let driver know the real hardware
431          * underneath. This is a requirement from virtualization team.
432          *
433          * In some virtualized environments (e.g. XEN), there is irrelevant
434          * ISA bridge in the system. To work reliably, we should scan trhough
435          * all the ISA bridge devices and check for the first match, instead
436          * of only checking the first one.
437          */
438         while ((pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA))) {
439                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
440                         unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
441                         dev_priv->pch_id = id;
442
443                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
444                                 dev_priv->pch_type = PCH_IBX;
445                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
446                                 WARN_ON(!IS_GEN5(dev));
447                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
448                                 dev_priv->pch_type = PCH_CPT;
449                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
450                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
451                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
452                                 /* PantherPoint is CPT compatible */
453                                 dev_priv->pch_type = PCH_CPT;
454                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
455                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
456                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
457                                 dev_priv->pch_type = PCH_LPT;
458                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
459                                 WARN_ON(!IS_HASWELL(dev));
460                                 WARN_ON(IS_ULT(dev));
461                         } else if (IS_BROADWELL(dev)) {
462                                 dev_priv->pch_type = PCH_LPT;
463                                 dev_priv->pch_id =
464                                         INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
465                                 DRM_DEBUG_KMS("This is Broadwell, assuming "
466                                               "LynxPoint LP PCH\n");
467                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
468                                 dev_priv->pch_type = PCH_LPT;
469                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
470                                 WARN_ON(!IS_HASWELL(dev));
471                                 WARN_ON(!IS_ULT(dev));
472                         } else
473                                 continue;
474
475                         break;
476                 }
477         }
478         if (!pch)
479                 DRM_DEBUG_KMS("No PCH found.\n");
480
481 #if 0
482         pci_dev_put(pch);
483 #endif
484 }
485
486 bool i915_semaphore_is_enabled(struct drm_device *dev)
487 {
488         if (INTEL_INFO(dev)->gen < 6)
489                 return false;
490
491         /* Until we get further testing... */
492         if (IS_GEN8(dev)) {
493                 WARN_ON(!i915_preliminary_hw_support);
494                 return false;
495         }
496
497         if (i915_semaphores >= 0)
498                 return i915_semaphores;
499
500 #ifdef CONFIG_INTEL_IOMMU
501         /* Enable semaphores on SNB when IO remapping is off */
502         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
503                 return false;
504 #endif
505
506         return true;
507 }
508
509 static int i915_drm_freeze(struct drm_device *dev)
510 {
511         struct drm_i915_private *dev_priv = dev->dev_private;
512         struct drm_crtc *crtc;
513
514         intel_runtime_pm_get(dev_priv);
515
516         /* ignore lid events during suspend */
517         mutex_lock(&dev_priv->modeset_restore_lock);
518         dev_priv->modeset_restore = MODESET_SUSPENDED;
519         mutex_unlock(&dev_priv->modeset_restore_lock);
520
521         /* We do a lot of poking in a lot of registers, make sure they work
522          * properly. */
523         hsw_disable_package_c8(dev_priv);
524         intel_display_set_init_power(dev, true);
525
526         drm_kms_helper_poll_disable(dev);
527
528 #if 0
529         pci_save_state(dev->pdev);
530 #endif
531
532         /* If KMS is active, we do the leavevt stuff here */
533         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
534                 int error;
535
536                 error = i915_gem_suspend(dev);
537                 if (error) {
538                         dev_err(dev->pdev->dev,
539                                 "GEM idle failed, resume might fail\n");
540                         return error;
541                 }
542
543                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
544
545                 drm_irq_uninstall(dev);
546                 dev_priv->enable_hotplug_processing = false;
547                 /*
548                  * Disable CRTCs directly since we want to preserve sw state
549                  * for _thaw.
550                  */
551                 mutex_lock(&dev->mode_config.mutex);
552                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
553                         dev_priv->display.crtc_disable(crtc);
554                 mutex_unlock(&dev->mode_config.mutex);
555
556                 intel_modeset_suspend_hw(dev);
557         }
558
559         i915_gem_suspend_gtt_mappings(dev);
560
561         i915_save_state(dev);
562
563         intel_opregion_fini(dev);
564
565 #if 0
566         console_lock();
567         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED);
568         console_unlock();
569 #endif
570
571         return 0;
572 }
573
574 int i915_suspend(device_t kdev)
575 {
576         struct drm_device *dev = device_get_softc(kdev);
577         int error;
578
579         if (!dev || !dev->dev_private) {
580                 DRM_ERROR("dev: %p\n", dev);
581                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
582                 return -ENODEV;
583         }
584
585         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
586                 return 0;
587
588         error = i915_drm_freeze(dev);
589         if (error)
590                 return error;
591
592 #if 0
593         if (state.event == PM_EVENT_SUSPEND) {
594                 /* Shut down the device */
595                 pci_disable_device(dev->pdev);
596                 pci_set_power_state(dev->pdev, PCI_D3hot);
597         }
598 #endif
599
600         error = bus_generic_suspend(kdev);
601         return (error);
602 }
603
604 #if 0
605 void intel_console_resume(struct work_struct *work)
606 {
607         struct drm_i915_private *dev_priv =
608                 container_of(work, struct drm_i915_private,
609                              console_resume_work);
610         struct drm_device *dev = dev_priv->dev;
611
612         console_lock();
613         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
614         console_unlock();
615 }
616 #endif
617
618 static void intel_resume_hotplug(struct drm_device *dev)
619 {
620         struct drm_mode_config *mode_config = &dev->mode_config;
621         struct intel_encoder *encoder;
622
623         mutex_lock(&mode_config->mutex);
624         DRM_DEBUG_KMS("running encoder hotplug functions\n");
625
626         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
627                 if (encoder->hot_plug)
628                         encoder->hot_plug(encoder);
629
630         mutex_unlock(&mode_config->mutex);
631
632         /* Just fire off a uevent and let userspace tell us what to do */
633         drm_helper_hpd_irq_event(dev);
634 }
635
636 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings)
637 {
638         struct drm_i915_private *dev_priv = dev->dev_private;
639         int error = 0;
640
641         intel_uncore_early_sanitize(dev);
642
643         intel_uncore_sanitize(dev);
644
645         if (drm_core_check_feature(dev, DRIVER_MODESET) &&
646             restore_gtt_mappings) {
647                 mutex_lock(&dev->struct_mutex);
648                 i915_gem_restore_gtt_mappings(dev);
649                 mutex_unlock(&dev->struct_mutex);
650         }
651
652         intel_power_domains_init_hw(dev);
653
654         i915_restore_state(dev);
655         intel_opregion_setup(dev);
656
657         /* KMS EnterVT equivalent */
658         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
659                 intel_init_pch_refclk(dev);
660
661                 mutex_lock(&dev->struct_mutex);
662
663                 error = i915_gem_init_hw(dev);
664                 mutex_unlock(&dev->struct_mutex);
665
666                 /* We need working interrupts for modeset enabling ... */
667                 drm_irq_install(dev);
668
669                 intel_modeset_init_hw(dev);
670
671                 drm_modeset_lock_all(dev);
672                 drm_mode_config_reset(dev);
673                 intel_modeset_setup_hw_state(dev, true);
674                 drm_modeset_unlock_all(dev);
675
676                 /*
677                  * ... but also need to make sure that hotplug processing
678                  * doesn't cause havoc. Like in the driver load code we don't
679                  * bother with the tiny race here where we might loose hotplug
680                  * notifications.
681                  * */
682                 intel_hpd_init(dev);
683                 dev_priv->enable_hotplug_processing = true;
684                 /* Config may have changed between suspend and resume */
685                 intel_resume_hotplug(dev);
686         }
687
688         intel_opregion_init(dev);
689
690         /*
691          * The console lock can be pretty contented on resume due
692          * to all the printk activity.  Try to keep it out of the hot
693          * path of resume if possible.
694          */
695 #if 0
696         if (console_trylock()) {
697                 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING);
698                 console_unlock();
699         } else {
700                 schedule_work(&dev_priv->console_resume_work);
701         }
702 #endif
703
704         /* Undo what we did at i915_drm_freeze so the refcount goes back to the
705          * expected level. */
706         hsw_enable_package_c8(dev_priv);
707
708         mutex_lock(&dev_priv->modeset_restore_lock);
709         dev_priv->modeset_restore = MODESET_DONE;
710         mutex_unlock(&dev_priv->modeset_restore_lock);
711
712         intel_runtime_pm_put(dev_priv);
713         return error;
714 }
715
716 #if 0
717 static int i915_drm_thaw(struct drm_device *dev)
718 {
719         if (drm_core_check_feature(dev, DRIVER_MODESET))
720                 i915_check_and_clear_faults(dev);
721
722         return __i915_drm_thaw(dev, true);
723 }
724 #endif
725
726 int i915_resume(struct drm_device *dev)
727 {
728         struct drm_i915_private *dev_priv = dev->dev_private;
729         int ret;
730
731 #if 0
732         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
733                 return 0;
734
735         if (pci_enable_device(dev->pdev))
736                 return -EIO;
737
738         pci_set_master(dev->pdev);
739 #endif
740
741         /*
742          * Platforms with opregion should have sane BIOS, older ones (gen3 and
743          * earlier) need to restore the GTT mappings since the BIOS might clear
744          * all our scratch PTEs.
745          */
746         ret = __i915_drm_thaw(dev, !dev_priv->opregion.header);
747         if (ret)
748                 return ret;
749
750         drm_kms_helper_poll_enable(dev);
751         return 0;
752 }
753
754 /* XXX Hack for the old *BSD drm code base
755  * The device id field is set at probe time */
756 static drm_pci_id_list_t i915_attach_list[] = {
757         {0x8086, 0, 0, "Intel i915 GPU"},
758         {0, 0, 0, NULL}
759 };
760
761 /* static int __init i915_init(void) */
762 static int
763 i915_attach(device_t kdev)
764 {
765         struct drm_device *dev;
766
767         dev = device_get_softc(kdev);
768
769         driver.num_ioctls = i915_max_ioctl;
770
771         if (i915_modeset == 1)
772                 driver.driver_features |= DRIVER_MODESET;
773
774         dev->driver = &driver;
775         return (drm_attach(kdev, i915_attach_list));
776 }
777
778 const struct intel_device_info *
779 i915_get_device_id(int device)
780 {
781         const struct pci_device_id *did;
782
783         for (did = &pciidlist[0]; did->device != 0; did++) {
784                 if (did->device != device)
785                         continue;
786                 return (struct intel_device_info *)did->driver_data;
787         }
788         return (NULL);
789 }
790
791 extern devclass_t drm_devclass;
792
793 /**
794  * i915_reset - reset chip after a hang
795  * @dev: drm device to reset
796  *
797  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
798  * reset or otherwise an error code.
799  *
800  * Procedure is fairly simple:
801  *   - reset the chip using the reset reg
802  *   - re-init context state
803  *   - re-init hardware status page
804  *   - re-init ring buffer
805  *   - re-init interrupt state
806  *   - re-init display
807  */
808 int i915_reset(struct drm_device *dev)
809 {
810         drm_i915_private_t *dev_priv = dev->dev_private;
811         bool simulated;
812         int ret;
813
814         if (!i915_try_reset)
815                 return 0;
816
817         mutex_lock(&dev->struct_mutex);
818
819         i915_gem_reset(dev);
820
821         simulated = dev_priv->gpu_error.stop_rings != 0;
822
823         ret = intel_gpu_reset(dev);
824
825         /* Also reset the gpu hangman. */
826         if (simulated) {
827                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
828                 dev_priv->gpu_error.stop_rings = 0;
829                 if (ret == -ENODEV) {
830                         DRM_INFO("Reset not implemented, but ignoring "
831                                  "error for simulated gpu hangs\n");
832                         ret = 0;
833                 }
834         }
835
836         if (ret) {
837                 DRM_ERROR("Failed to reset chip: %i\n", ret);
838                 mutex_unlock(&dev->struct_mutex);
839                 return ret;
840         }
841
842         /* Ok, now get things going again... */
843
844         /*
845          * Everything depends on having the GTT running, so we need to start
846          * there.  Fortunately we don't need to do this unless we reset the
847          * chip at a PCI level.
848          *
849          * Next we need to restore the context, but we don't use those
850          * yet either...
851          *
852          * Ring buffer needs to be re-initialized in the KMS case, or if X
853          * was running at the time of the reset (i.e. we weren't VT
854          * switched away).
855          */
856         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
857                         !dev_priv->ums.mm_suspended) {
858                 dev_priv->ums.mm_suspended = 0;
859
860                 ret = i915_gem_init_hw(dev);
861                 mutex_unlock(&dev->struct_mutex);
862                 if (ret) {
863                         DRM_ERROR("Failed hw init on reset %d\n", ret);
864                         return ret;
865                 }
866
867                 drm_irq_uninstall(dev);
868                 drm_irq_install(dev);
869                 intel_hpd_init(dev);
870         } else {
871                 mutex_unlock(&dev->struct_mutex);
872         }
873
874         return 0;
875 }
876
877 static int
878 i915_pci_probe(device_t kdev)
879 {
880         int device, i = 0;
881
882         if (pci_get_class(kdev) != PCIC_DISPLAY)
883                 return ENXIO;
884
885         if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
886                 return ENXIO;
887
888         device = pci_get_device(kdev);
889
890         for (i = 0; pciidlist[i].device != 0; i++) {
891                 if (pciidlist[i].device == device) {
892                         i915_attach_list[0].device = device;
893                         return 0;
894                 }
895         }
896
897         return ENXIO;
898 }
899
900 #if 0
901 static void
902 i915_pci_remove(struct pci_dev *pdev)
903 {
904         struct drm_device *dev = pci_get_drvdata(pdev);
905
906         drm_put_dev(dev);
907 }
908
909 static int i915_pm_suspend(struct device *dev)
910 {
911         struct pci_dev *pdev = to_pci_dev(dev);
912         struct drm_device *drm_dev = pci_get_drvdata(pdev);
913         int error;
914
915         if (!drm_dev || !drm_dev->dev_private) {
916                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
917                 return -ENODEV;
918         }
919
920         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
921                 return 0;
922
923         error = i915_drm_freeze(drm_dev);
924         if (error)
925                 return error;
926
927         pci_disable_device(pdev);
928         pci_set_power_state(pdev, PCI_D3hot);
929
930         return 0;
931 }
932
933 static int i915_pm_resume(struct device *dev)
934 {
935         struct pci_dev *pdev = to_pci_dev(dev);
936         struct drm_device *drm_dev = pci_get_drvdata(pdev);
937
938         return i915_resume(drm_dev);
939 }
940
941 static int i915_pm_freeze(struct device *dev)
942 {
943         struct pci_dev *pdev = to_pci_dev(dev);
944         struct drm_device *drm_dev = pci_get_drvdata(pdev);
945
946         if (!drm_dev || !drm_dev->dev_private) {
947                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
948                 return -ENODEV;
949         }
950
951         return i915_drm_freeze(drm_dev);
952 }
953
954 static int i915_pm_thaw(struct device *dev)
955 {
956         struct pci_dev *pdev = to_pci_dev(dev);
957         struct drm_device *drm_dev = pci_get_drvdata(pdev);
958
959         return i915_drm_thaw(drm_dev);
960 }
961
962 static int i915_pm_poweroff(struct device *dev)
963 {
964         struct pci_dev *pdev = to_pci_dev(dev);
965         struct drm_device *drm_dev = pci_get_drvdata(pdev);
966
967         return i915_drm_freeze(drm_dev);
968 }
969
970 static int i915_runtime_suspend(struct device *device)
971 {
972         struct pci_dev *pdev = to_pci_dev(device);
973         struct drm_device *dev = pci_get_drvdata(pdev);
974         struct drm_i915_private *dev_priv = dev->dev_private;
975
976         WARN_ON(!HAS_RUNTIME_PM(dev));
977
978         DRM_DEBUG_KMS("Suspending device\n");
979
980         i915_gem_release_all_mmaps(dev_priv);
981
982         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
983         dev_priv->pm.suspended = true;
984
985         /*
986          * current versions of firmware which depend on this opregion
987          * notification have repurposed the D1 definition to mean
988          * "runtime suspended" vs. what you would normally expect (D3)
989          * to distinguish it from notifications that might be sent
990          * via the suspend path.
991          */
992         intel_opregion_notify_adapter(dev, PCI_D1);
993
994         return 0;
995 }
996
997 static int i915_runtime_resume(struct device *device)
998 {
999         struct pci_dev *pdev = to_pci_dev(device);
1000         struct drm_device *dev = pci_get_drvdata(pdev);
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003         WARN_ON(!HAS_RUNTIME_PM(dev));
1004
1005         DRM_DEBUG_KMS("Resuming device\n");
1006
1007         intel_opregion_notify_adapter(dev, PCI_D0);
1008         dev_priv->pm.suspended = false;
1009
1010         return 0;
1011 }
1012
1013 static const struct dev_pm_ops i915_pm_ops = {
1014         .suspend = i915_pm_suspend,
1015         .resume = i915_pm_resume,
1016         .freeze = i915_pm_freeze,
1017         .thaw = i915_pm_thaw,
1018         .poweroff = i915_pm_poweroff,
1019         .restore = i915_pm_resume,
1020         .runtime_suspend = i915_runtime_suspend,
1021         .runtime_resume = i915_runtime_resume,
1022 };
1023
1024 static const struct vm_operations_struct i915_gem_vm_ops = {
1025         .fault = i915_gem_fault,
1026         .open = drm_gem_vm_open,
1027         .close = drm_gem_vm_close,
1028 };
1029
1030 static const struct file_operations i915_driver_fops = {
1031         .owner = THIS_MODULE,
1032         .open = drm_open,
1033         .release = drm_release,
1034         .unlocked_ioctl = drm_ioctl,
1035         .mmap = drm_gem_mmap,
1036         .poll = drm_poll,
1037         .read = drm_read,
1038 #ifdef CONFIG_COMPAT
1039         .compat_ioctl = i915_compat_ioctl,
1040 #endif
1041         .llseek = noop_llseek,
1042 };
1043 #endif
1044
1045 static struct cdev_pager_ops i915_gem_vm_ops = {
1046         .cdev_pg_fault  = i915_gem_fault,
1047         .cdev_pg_ctor   = i915_gem_pager_ctor,
1048         .cdev_pg_dtor   = i915_gem_pager_dtor
1049 };
1050
1051 static struct drm_driver driver = {
1052         /* Don't use MTRRs here; the Xserver or userspace app should
1053          * deal with them for Intel hardware.
1054          */
1055         .driver_features =
1056             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1057             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
1058
1059         .buf_priv_size  = sizeof(drm_i915_private_t),
1060         .load           = i915_driver_load,
1061         .open           = i915_driver_open,
1062         .unload         = i915_driver_unload,
1063         .preclose       = i915_driver_preclose,
1064         .lastclose      = i915_driver_lastclose,
1065         .postclose      = i915_driver_postclose,
1066         .device_is_agp  = i915_driver_device_is_agp,
1067         .gem_free_object = i915_gem_free_object,
1068         .gem_pager_ops  = &i915_gem_vm_ops,
1069         .dumb_create    = i915_gem_dumb_create,
1070         .dumb_map_offset = i915_gem_mmap_gtt,
1071         .dumb_destroy = drm_gem_dumb_destroy,
1072         .ioctls         = i915_ioctls,
1073
1074         .name           = DRIVER_NAME,
1075         .desc           = DRIVER_DESC,
1076         .date           = DRIVER_DATE,
1077         .major          = DRIVER_MAJOR,
1078         .minor          = DRIVER_MINOR,
1079         .patchlevel     = DRIVER_PATCHLEVEL,
1080 };
1081
1082 static device_method_t i915_methods[] = {
1083         /* Device interface */
1084         DEVMETHOD(device_probe,         i915_pci_probe),
1085         DEVMETHOD(device_attach,        i915_attach),
1086         DEVMETHOD(device_suspend,       i915_suspend),
1087         DEVMETHOD(device_resume,        i915_resume),
1088         DEVMETHOD(device_detach,        drm_release),
1089         DEVMETHOD_END
1090 };
1091
1092 static driver_t i915_driver = {
1093         "drm",
1094         i915_methods,
1095         sizeof(struct drm_device)
1096 };
1097
1098 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
1099     SI_ORDER_ANY);
1100 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
1101 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
1102 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
1103 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
1104 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);