sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         drm_i915_private_t *dev_priv = dev->dev_private;
  76         struct drm_i915_master_private *master_priv;
  77
  78         if (dev->primary->master) {
  79                 master_priv = dev->primary->master->driver_priv;
  80                 if (master_priv->sarea_priv)
  81                         master_priv->sarea_priv->last_dispatch =
  82                                 READ_BREADCRUMB(dev_priv);
  83         }
  84 }
  85
  86 static void i915_write_hws_pga(struct drm_device *dev)
  87 {
  88         drm_i915_private_t *dev_priv = dev->dev_private;
  89         u32 addr;
  90
  91         addr = dev_priv->status_page_dmah->busaddr;
  92         if (INTEL_INFO(dev)->gen >= 4)
  93                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  94         I915_WRITE(HWS_PGA, addr);
  95 }
  96
  97 /**
  98  * Frees the hardware status page, whether it's a physical address or a virtual
  99  * address set up by the X Server.
 100  */
 101 static void i915_free_hws(struct drm_device *dev)
 102 {
 103         drm_i915_private_t *dev_priv = dev->dev_private;
 104         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 105
 106         if (dev_priv->status_page_dmah) {
 107                 drm_pci_free(dev, dev_priv->status_page_dmah);
 108                 dev_priv->status_page_dmah = NULL;
 109         }
 110
 111         if (ring->status_page.gfx_addr) {
 112                 ring->status_page.gfx_addr = 0;
 113 #if 0   /* We don't care about dri1 */
 114                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 115 #endif
 116         }
 117
 118         /* Need to rewrite hardware status page */
 119         I915_WRITE(HWS_PGA, 0x1ffff000);
 120 }
 121
 122 void i915_kernel_lost_context(struct drm_device * dev)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         struct drm_i915_master_private *master_priv;
 126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 127
 128         /*
 129          * We should never lose context on the ring with modesetting
 130          * as we don't expose it to userspace
 131          */
 132         if (drm_core_check_feature(dev, DRIVER_MODESET))
 133                 return;
 134
 135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 137         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 138         if (ring->space < 0)
 139                 ring->space += ring->size;
 140
 141         if (!dev->primary->master)
 142                 return;
 143
 144         master_priv = dev->primary->master->driver_priv;
 145         if (ring->head == ring->tail && master_priv->sarea_priv)
 146                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 147 }
 148
 149 static int i915_dma_cleanup(struct drm_device * dev)
 150 {
 151         drm_i915_private_t *dev_priv = dev->dev_private;
 152         int i;
 153
 154
 155         /* Make sure interrupts are disabled here because the uninstall ioctl
 156          * may not have been called from userspace and after dev_private
 157          * is freed, it's too late.
 158          */
 159         if (dev->irq_enabled)
 160                 drm_irq_uninstall(dev);
 161
 162         mutex_lock(&dev->struct_mutex);
 163         for (i = 0; i < I915_NUM_RINGS; i++)
 164                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 165         mutex_unlock(&dev->struct_mutex);
 166
 167         /* Clear the HWS virtual address at teardown */
 168         if (I915_NEED_GFX_HWS(dev))
 169                 i915_free_hws(dev);
 170
 171         return 0;
 172 }
 173
 174 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 175 {
 176         drm_i915_private_t *dev_priv = dev->dev_private;
 177         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 178         int ret;
 179
 180         master_priv->sarea = drm_getsarea(dev);
 181         if (master_priv->sarea) {
 182                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 183                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 184         } else {
 185                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 186         }
 187
 188         if (init->ring_size != 0) {
 189                 if (LP_RING(dev_priv)->obj != NULL) {
 190                         i915_dma_cleanup(dev);
 191                         DRM_ERROR("Client tried to initialize ringbuffer in "
 192                                   "GEM mode\n");
 193                         return -EINVAL;
 194                 }
 195
 196                 ret = intel_render_ring_init_dri(dev,
 197                                                  init->ring_start,
 198                                                  init->ring_size);
 199                 if (ret) {
 200                         i915_dma_cleanup(dev);
 201                         return ret;
 202                 }
 203         }
 204
 205         dev_priv->dri1.cpp = init->cpp;
 206         dev_priv->dri1.back_offset = init->back_offset;
 207         dev_priv->dri1.front_offset = init->front_offset;
 208         dev_priv->dri1.current_page = 0;
 209         if (master_priv->sarea_priv)
 210                 master_priv->sarea_priv->pf_current_page = 0;
 211
 212         /* Allow hardware batchbuffers unless told otherwise.
 213          */
 214         dev_priv->dri1.allow_batchbuffer = 1;
 215
 216         return 0;
 217 }
 218
 219 static int i915_dma_resume(struct drm_device * dev)
 220 {
 221         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 222         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 223
 224         DRM_DEBUG_DRIVER("%s\n", __func__);
 225
 226         if (ring->virtual_start == NULL) {
 227                 DRM_ERROR("can not ioremap virtual address for"
 228                           " ring buffer\n");
 229                 return -ENOMEM;
 230         }
 231
 232         /* Program Hardware Status Page */
 233         if (!ring->status_page.page_addr) {
 234                 DRM_ERROR("Can not find hardware status page\n");
 235                 return -EINVAL;
 236         }
 237         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 238                                 ring->status_page.page_addr);
 239         if (ring->status_page.gfx_addr != 0)
 240                 intel_ring_setup_status_page(ring);
 241         else
 242                 i915_write_hws_pga(dev);
 243
 244         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 245
 246         return 0;
 247 }
 248
 249 static int i915_dma_init(struct drm_device *dev, void *data,
 250                          struct drm_file *file_priv)
 251 {
 252         drm_i915_init_t *init = data;
 253         int retcode = 0;
 254
 255         if (drm_core_check_feature(dev, DRIVER_MODESET))
 256                 return -ENODEV;
 257
 258         switch (init->func) {
 259         case I915_INIT_DMA:
 260                 retcode = i915_initialize(dev, init);
 261                 break;
 262         case I915_CLEANUP_DMA:
 263                 retcode = i915_dma_cleanup(dev);
 264                 break;
 265         case I915_RESUME_DMA:
 266                 retcode = i915_dma_resume(dev);
 267                 break;
 268         default:
 269                 retcode = -EINVAL;
 270                 break;
 271         }
 272
 273         return retcode;
 274 }
 275
 276 /* Implement basically the same security restrictions as hardware does
 277  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 278  *
 279  * Most of the calculations below involve calculating the size of a
 280  * particular instruction.  It's important to get the size right as
 281  * that tells us where the next instruction to check is.  Any illegal
 282  * instruction detected will be given a size of zero, which is a
 283  * signal to abort the rest of the buffer.
 284  */
 285 static int validate_cmd(int cmd)
 286 {
 287         switch (((cmd >> 29) & 0x7)) {
 288         case 0x0:
 289                 switch ((cmd >> 23) & 0x3f) {
 290                 case 0x0:
 291                         return 1;       /* MI_NOOP */
 292                 case 0x4:
 293                         return 1;       /* MI_FLUSH */
 294                 default:
 295                         return 0;       /* disallow everything else */
 296                 }
 297                 break;
 298         case 0x1:
 299                 return 0;       /* reserved */
 300         case 0x2:
 301                 return (cmd & 0xff) + 2;        /* 2d commands */
 302         case 0x3:
 303                 if (((cmd >> 24) & 0x1f) <= 0x18)
 304                         return 1;
 305
 306                 switch ((cmd >> 24) & 0x1f) {
 307                 case 0x1c:
 308                         return 1;
 309                 case 0x1d:
 310                         switch ((cmd >> 16) & 0xff) {
 311                         case 0x3:
 312                                 return (cmd & 0x1f) + 2;
 313                         case 0x4:
 314                                 return (cmd & 0xf) + 2;
 315                         default:
 316                                 return (cmd & 0xffff) + 2;
 317                         }
 318                 case 0x1e:
 319                         if (cmd & (1 << 23))
 320                                 return (cmd & 0xffff) + 1;
 321                         else
 322                                 return 1;
 323                 case 0x1f:
 324                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 325                                 return (cmd & 0x1ffff) + 2;
 326                         else if (cmd & (1 << 17))       /* indirect random */
 327                                 if ((cmd & 0xffff) == 0)
 328                                         return 0;       /* unknown length, too hard */
 329                                 else
 330                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 331                         else
 332                                 return 2;       /* indirect sequential */
 333                 default:
 334                         return 0;
 335                 }
 336         default:
 337                 return 0;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 344 {
 345         drm_i915_private_t *dev_priv = dev->dev_private;
 346         int i, ret;
 347
 348         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 349                 return -EINVAL;
 350
 351         for (i = 0; i < dwords;) {
 352                 int sz = validate_cmd(buffer[i]);
 353                 if (sz == 0 || i + sz > dwords)
 354                         return -EINVAL;
 355                 i += sz;
 356         }
 357
 358         ret = BEGIN_LP_RING((dwords+1)&~1);
 359         if (ret)
 360                 return ret;
 361
 362         for (i = 0; i < dwords; i++)
 363                 OUT_RING(buffer[i]);
 364         if (dwords & 1)
 365                 OUT_RING(0);
 366
 367         ADVANCE_LP_RING();
 368
 369         return 0;
 370 }
 371
 372 int
 373 i915_emit_box(struct drm_device *dev,
 374               struct drm_clip_rect *box,
 375               int DR1, int DR4)
 376 {
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378         int ret;
 379
 380         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 381             box->y2 <= 0 || box->x2 <= 0) {
 382                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 383                           box->x1, box->y1, box->x2, box->y2);
 384                 return -EINVAL;
 385         }
 386
 387         if (INTEL_INFO(dev)->gen >= 4) {
 388                 ret = BEGIN_LP_RING(4);
 389                 if (ret)
 390                         return ret;
 391
 392                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 393                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 394                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 395                 OUT_RING(DR4);
 396         } else {
 397                 ret = BEGIN_LP_RING(6);
 398                 if (ret)
 399                         return ret;
 400
 401                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 402                 OUT_RING(DR1);
 403                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 404                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 405                 OUT_RING(DR4);
 406                 OUT_RING(0);
 407         }
 408         ADVANCE_LP_RING();
 409
 410         return 0;
 411 }
 412
 413 /* XXX: Emitting the counter should really be moved to part of the IRQ
 414  * emit. For now, do it in both places:
 415  */
 416
 417 static void i915_emit_breadcrumb(struct drm_device *dev)
 418 {
 419         drm_i915_private_t *dev_priv = dev->dev_private;
 420         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 421
 422         dev_priv->dri1.counter++;
 423         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 424                 dev_priv->dri1.counter = 0;
 425         if (master_priv->sarea_priv)
 426                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 427
 428         if (BEGIN_LP_RING(4) == 0) {
 429                 OUT_RING(MI_STORE_DWORD_INDEX);
 430                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 431                 OUT_RING(dev_priv->dri1.counter);
 432                 OUT_RING(0);
 433                 ADVANCE_LP_RING();
 434         }
 435 }
 436
 437 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 438                                    drm_i915_cmdbuffer_t *cmd,
 439                                    struct drm_clip_rect *cliprects,
 440                                    void *cmdbuf)
 441 {
 442         int nbox = cmd->num_cliprects;
 443         int i = 0, count, ret;
 444
 445         if (cmd->sz & 0x3) {
 446                 DRM_ERROR("alignment");
 447                 return -EINVAL;
 448         }
 449
 450         i915_kernel_lost_context(dev);
 451
 452         count = nbox ? nbox : 1;
 453
 454         for (i = 0; i < count; i++) {
 455                 if (i < nbox) {
 456                         ret = i915_emit_box(dev, &cliprects[i],
 457                                             cmd->DR1, cmd->DR4);
 458                         if (ret)
 459                                 return ret;
 460                 }
 461
 462                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 463                 if (ret)
 464                         return ret;
 465         }
 466
 467         i915_emit_breadcrumb(dev);
 468         return 0;
 469 }
 470
 471 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 472                                      drm_i915_batchbuffer_t * batch,
 473                                      struct drm_clip_rect *cliprects)
 474 {
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         int nbox = batch->num_cliprects;
 477         int i, count, ret;
 478
 479         if ((batch->start | batch->used) & 0x7) {
 480                 DRM_ERROR("alignment");
 481                 return -EINVAL;
 482         }
 483
 484         i915_kernel_lost_context(dev);
 485
 486         count = nbox ? nbox : 1;
 487         for (i = 0; i < count; i++) {
 488                 if (i < nbox) {
 489                         ret = i915_emit_box(dev, &cliprects[i],
 490                                             batch->DR1, batch->DR4);
 491                         if (ret)
 492                                 return ret;
 493                 }
 494
 495                 if (!IS_I830(dev) && !IS_845G(dev)) {
 496                         ret = BEGIN_LP_RING(2);
 497                         if (ret)
 498                                 return ret;
 499
 500                         if (INTEL_INFO(dev)->gen >= 4) {
 501                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 502                                 OUT_RING(batch->start);
 503                         } else {
 504                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 505                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 506                         }
 507                 } else {
 508                         ret = BEGIN_LP_RING(4);
 509                         if (ret)
 510                                 return ret;
 511
 512                         OUT_RING(MI_BATCH_BUFFER);
 513                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 514                         OUT_RING(batch->start + batch->used - 4);
 515                         OUT_RING(0);
 516                 }
 517                 ADVANCE_LP_RING();
 518         }
 519
 520
 521         if (IS_G4X(dev) || IS_GEN5(dev)) {
 522                 if (BEGIN_LP_RING(2) == 0) {
 523                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 524                         OUT_RING(MI_NOOP);
 525                         ADVANCE_LP_RING();
 526                 }
 527         }
 528
 529         i915_emit_breadcrumb(dev);
 530         return 0;
 531 }
 532
 533 static int i915_dispatch_flip(struct drm_device * dev)
 534 {
 535         drm_i915_private_t *dev_priv = dev->dev_private;
 536         struct drm_i915_master_private *master_priv =
 537                 dev->primary->master->driver_priv;
 538         int ret;
 539
 540         if (!master_priv->sarea_priv)
 541                 return -EINVAL;
 542
 543         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 544                           __func__,
 545                          dev_priv->dri1.current_page,
 546                          master_priv->sarea_priv->pf_current_page);
 547
 548         i915_kernel_lost_context(dev);
 549
 550         ret = BEGIN_LP_RING(10);
 551         if (ret)
 552                 return ret;
 553
 554         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 555         OUT_RING(0);
 556
 557         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 558         OUT_RING(0);
 559         if (dev_priv->dri1.current_page == 0) {
 560                 OUT_RING(dev_priv->dri1.back_offset);
 561                 dev_priv->dri1.current_page = 1;
 562         } else {
 563                 OUT_RING(dev_priv->dri1.front_offset);
 564                 dev_priv->dri1.current_page = 0;
 565         }
 566         OUT_RING(0);
 567
 568         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 569         OUT_RING(0);
 570
 571         ADVANCE_LP_RING();
 572
 573         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 574
 575         if (BEGIN_LP_RING(4) == 0) {
 576                 OUT_RING(MI_STORE_DWORD_INDEX);
 577                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 578                 OUT_RING(dev_priv->dri1.counter);
 579                 OUT_RING(0);
 580                 ADVANCE_LP_RING();
 581         }
 582
 583         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 584         return 0;
 585 }
 586
 587 static int i915_quiescent(struct drm_device *dev)
 588 {
 589         i915_kernel_lost_context(dev);
 590         return intel_ring_idle(LP_RING(dev->dev_private));
 591 }
 592
 593 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 594                             struct drm_file *file_priv)
 595 {
 596         int ret;
 597
 598         if (drm_core_check_feature(dev, DRIVER_MODESET))
 599                 return -ENODEV;
 600
 601         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 602
 603         mutex_lock(&dev->struct_mutex);
 604         ret = i915_quiescent(dev);
 605         mutex_unlock(&dev->struct_mutex);
 606
 607         return ret;
 608 }
 609
 610 static int i915_batchbuffer(struct drm_device *dev, void *data,
 611                             struct drm_file *file_priv)
 612 {
 613         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 614         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 615         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 616             master_priv->sarea_priv;
 617         drm_i915_batchbuffer_t *batch = data;
 618         int ret;
 619         struct drm_clip_rect *cliprects = NULL;
 620
 621         if (drm_core_check_feature(dev, DRIVER_MODESET))
 622                 return -ENODEV;
 623
 624         if (!dev_priv->dri1.allow_batchbuffer) {
 625                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 626                 return -EINVAL;
 627         }
 628
 629         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 630                         batch->start, batch->used, batch->num_cliprects);
 631
 632         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 633
 634         if (batch->num_cliprects < 0)
 635                 return -EINVAL;
 636
 637         if (batch->num_cliprects) {
 638                 cliprects = kmalloc(batch->num_cliprects *
 639                                     sizeof(struct drm_clip_rect), M_DRM,
 640                                     M_WAITOK | M_ZERO);
 641                 if (cliprects == NULL)
 642                         return -ENOMEM;
 643
 644                 ret = copy_from_user(cliprects, batch->cliprects,
 645                                      batch->num_cliprects *
 646                                      sizeof(struct drm_clip_rect));
 647                 if (ret != 0) {
 648                         ret = -EFAULT;
 649                         goto fail_free;
 650                 }
 651         }
 652
 653         mutex_lock(&dev->struct_mutex);
 654         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 655         mutex_unlock(&dev->struct_mutex);
 656
 657         if (sarea_priv)
 658                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 659
 660 fail_free:
 661         kfree(cliprects, M_DRM);
 662         return ret;
 663 }
 664
 665 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 666                           struct drm_file *file_priv)
 667 {
 668         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 669         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 670         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 671             master_priv->sarea_priv;
 672         drm_i915_cmdbuffer_t *cmdbuf = data;
 673         struct drm_clip_rect *cliprects = NULL;
 674         void *batch_data;
 675         int ret;
 676
 677         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 678                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 679
 680         if (drm_core_check_feature(dev, DRIVER_MODESET))
 681                 return -ENODEV;
 682
 683         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 684
 685         if (cmdbuf->num_cliprects < 0)
 686                 return -EINVAL;
 687
 688         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 689         if (batch_data == NULL)
 690                 return -ENOMEM;
 691
 692         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 693         if (ret != 0) {
 694                 ret = -EFAULT;
 695                 goto fail_batch_free;
 696         }
 697
 698         if (cmdbuf->num_cliprects) {
 699                 cliprects = kmalloc(cmdbuf->num_cliprects *
 700                                     sizeof(struct drm_clip_rect), M_DRM,
 701                                     M_WAITOK | M_ZERO);
 702                 if (cliprects == NULL) {
 703                         ret = -ENOMEM;
 704                         goto fail_batch_free;
 705                 }
 706
 707                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 708                                      cmdbuf->num_cliprects *
 709                                      sizeof(struct drm_clip_rect));
 710                 if (ret != 0) {
 711                         ret = -EFAULT;
 712                         goto fail_clip_free;
 713                 }
 714         }
 715
 716         mutex_lock(&dev->struct_mutex);
 717         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 718         mutex_unlock(&dev->struct_mutex);
 719         if (ret) {
 720                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 721                 goto fail_clip_free;
 722         }
 723
 724         if (sarea_priv)
 725                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 726
 727 fail_clip_free:
 728         drm_free(cliprects, M_DRM);
 729 fail_batch_free:
 730         drm_free(batch_data, M_DRM);
 731         return ret;
 732 }
 733
 734 static int i915_emit_irq(struct drm_device * dev)
 735 {
 736         drm_i915_private_t *dev_priv = dev->dev_private;
 737         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 738
 739         i915_kernel_lost_context(dev);
 740
 741         DRM_DEBUG_DRIVER("\n");
 742
 743         dev_priv->dri1.counter++;
 744         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 745                 dev_priv->dri1.counter = 1;
 746         if (master_priv->sarea_priv)
 747                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 748
 749         if (BEGIN_LP_RING(4) == 0) {
 750                 OUT_RING(MI_STORE_DWORD_INDEX);
 751                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 752                 OUT_RING(dev_priv->dri1.counter);
 753                 OUT_RING(MI_USER_INTERRUPT);
 754                 ADVANCE_LP_RING();
 755         }
 756
 757         return dev_priv->dri1.counter;
 758 }
 759
 760 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 761 {
 762         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 763         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 764         int ret = 0;
 765         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 766
 767         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 768                   READ_BREADCRUMB(dev_priv));
 769
 770         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 771                 if (master_priv->sarea_priv)
 772                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 773                 return 0;
 774         }
 775
 776         if (master_priv->sarea_priv)
 777                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 778
 779         if (ring->irq_get(ring)) {
 780                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 781                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 782                 ring->irq_put(ring);
 783         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 784                 ret = -EBUSY;
 785
 786         if (ret == -EBUSY) {
 787                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 788                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 789         }
 790
 791         return ret;
 792 }
 793
 794 /* Needs the lock as it touches the ring.
 795  */
 796 static int i915_irq_emit(struct drm_device *dev, void *data,
 797                          struct drm_file *file_priv)
 798 {
 799         drm_i915_private_t *dev_priv = dev->dev_private;
 800         drm_i915_irq_emit_t *emit = data;
 801         int result;
 802
 803         if (drm_core_check_feature(dev, DRIVER_MODESET))
 804                 return -ENODEV;
 805
 806         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 807                 DRM_ERROR("called with no initialization\n");
 808                 return -EINVAL;
 809         }
 810
 811         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 812
 813         mutex_lock(&dev->struct_mutex);
 814         result = i915_emit_irq(dev);
 815         mutex_unlock(&dev->struct_mutex);
 816
 817         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 818                 DRM_ERROR("copy_to_user\n");
 819                 return -EFAULT;
 820         }
 821
 822         return 0;
 823 }
 824
 825 /* Doesn't need the hardware lock.
 826  */
 827 static int i915_irq_wait(struct drm_device *dev, void *data,
 828                          struct drm_file *file_priv)
 829 {
 830         drm_i915_private_t *dev_priv = dev->dev_private;
 831         drm_i915_irq_wait_t *irqwait = data;
 832
 833         if (drm_core_check_feature(dev, DRIVER_MODESET))
 834                 return -ENODEV;
 835
 836         if (!dev_priv) {
 837                 DRM_ERROR("called with no initialization\n");
 838                 return -EINVAL;
 839         }
 840
 841         return i915_wait_irq(dev, irqwait->irq_seq);
 842 }
 843
 844 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 845                          struct drm_file *file_priv)
 846 {
 847         drm_i915_private_t *dev_priv = dev->dev_private;
 848         drm_i915_vblank_pipe_t *pipe = data;
 849
 850         if (drm_core_check_feature(dev, DRIVER_MODESET))
 851                 return -ENODEV;
 852
 853         if (!dev_priv) {
 854                 DRM_ERROR("called with no initialization\n");
 855                 return -EINVAL;
 856         }
 857
 858         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 859
 860         return 0;
 861 }
 862
 863 /**
 864  * Schedule buffer swap at given vertical blank.
 865  */
 866 static int i915_vblank_swap(struct drm_device *dev, void *data,
 867                      struct drm_file *file_priv)
 868 {
 869         /* The delayed swap mechanism was fundamentally racy, and has been
 870          * removed.  The model was that the client requested a delayed flip/swap
 871          * from the kernel, then waited for vblank before continuing to perform
 872          * rendering.  The problem was that the kernel might wake the client
 873          * up before it dispatched the vblank swap (since the lock has to be
 874          * held while touching the ringbuffer), in which case the client would
 875          * clear and start the next frame before the swap occurred, and
 876          * flicker would occur in addition to likely missing the vblank.
 877          *
 878          * In the absence of this ioctl, userland falls back to a correct path
 879          * of waiting for a vblank, then dispatching the swap on its own.
 880          * Context switching to userland and back is plenty fast enough for
 881          * meeting the requirements of vblank swapping.
 882          */
 883         return -EINVAL;
 884 }
 885
 886 static int i915_flip_bufs(struct drm_device *dev, void *data,
 887                           struct drm_file *file_priv)
 888 {
 889         int ret;
 890
 891         if (drm_core_check_feature(dev, DRIVER_MODESET))
 892                 return -ENODEV;
 893
 894         DRM_DEBUG_DRIVER("%s\n", __func__);
 895
 896         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 897
 898         mutex_lock(&dev->struct_mutex);
 899         ret = i915_dispatch_flip(dev);
 900         mutex_unlock(&dev->struct_mutex);
 901
 902         return ret;
 903 }
 904
 905 static int i915_getparam(struct drm_device *dev, void *data,
 906                          struct drm_file *file_priv)
 907 {
 908         drm_i915_private_t *dev_priv = dev->dev_private;
 909         drm_i915_getparam_t *param = data;
 910         int value;
 911
 912         if (!dev_priv) {
 913                 DRM_ERROR("called with no initialization\n");
 914                 return -EINVAL;
 915         }
 916
 917         switch (param->param) {
 918         case I915_PARAM_IRQ_ACTIVE:
 919                 value = dev->irq_enabled ? 1 : 0;
 920                 break;
 921         case I915_PARAM_ALLOW_BATCHBUFFER:
 922                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 923                 break;
 924         case I915_PARAM_LAST_DISPATCH:
 925                 value = READ_BREADCRUMB(dev_priv);
 926                 break;
 927         case I915_PARAM_CHIPSET_ID:
 928                 value = dev->pci_device;
 929                 break;
 930         case I915_PARAM_HAS_GEM:
 931                 value = 1;
 932                 break;
 933         case I915_PARAM_NUM_FENCES_AVAIL:
 934                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 935                 break;
 936         case I915_PARAM_HAS_OVERLAY:
 937                 value = dev_priv->overlay ? 1 : 0;
 938                 break;
 939         case I915_PARAM_HAS_PAGEFLIPPING:
 940                 value = 1;
 941                 break;
 942         case I915_PARAM_HAS_EXECBUF2:
 943                 /* depends on GEM */
 944                 value = 1;
 945                 break;
 946         case I915_PARAM_HAS_BSD:
 947                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 948                 break;
 949         case I915_PARAM_HAS_BLT:
 950                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 951                 break;
 952         case I915_PARAM_HAS_RELAXED_FENCING:
 953                 value = 1;
 954                 break;
 955         case I915_PARAM_HAS_COHERENT_RINGS:
 956                 value = 1;
 957                 break;
 958         case I915_PARAM_HAS_EXEC_CONSTANTS:
 959                 value = INTEL_INFO(dev)->gen >= 4;
 960                 break;
 961         case I915_PARAM_HAS_RELAXED_DELTA:
 962                 value = 1;
 963                 break;
 964         case I915_PARAM_HAS_GEN7_SOL_RESET:
 965                 value = 1;
 966                 break;
 967         case I915_PARAM_HAS_LLC:
 968                 value = HAS_LLC(dev);
 969                 break;
 970         case I915_PARAM_HAS_ALIASING_PPGTT:
 971                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 972                 break;
 973         case I915_PARAM_HAS_WAIT_TIMEOUT:
 974                 value = 1;
 975                 break;
 976         case I915_PARAM_HAS_SEMAPHORES:
 977                 value = i915_semaphore_is_enabled(dev);
 978                 break;
 979         case I915_PARAM_HAS_PINNED_BATCHES:
 980                 value = 1;
 981                 break;
 982         case I915_PARAM_HAS_EXEC_NO_RELOC:
 983                 value = 1;
 984                 break;
 985         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 986                 value = 1;
 987                 break;
 988         default:
 989                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 990                                  param->param);
 991                 return -EINVAL;
 992         }
 993
 994         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 995                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 996                 return -EFAULT;
 997         }
 998
 999         return 0;
1000 }
1001
1002 static int i915_setparam(struct drm_device *dev, void *data,
1003                          struct drm_file *file_priv)
1004 {
1005         drm_i915_private_t *dev_priv = dev->dev_private;
1006         drm_i915_setparam_t *param = data;
1007
1008         if (!dev_priv) {
1009                 DRM_ERROR("called with no initialization\n");
1010                 return -EINVAL;
1011         }
1012
1013         switch (param->param) {
1014         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1015                 break;
1016         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1017                 break;
1018         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1019                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1020                 break;
1021         case I915_SETPARAM_NUM_USED_FENCES:
1022                 if (param->value > dev_priv->num_fence_regs ||
1023                     param->value < 0)
1024                         return -EINVAL;
1025                 /* Userspace can use first N regs */
1026                 dev_priv->fence_reg_start = param->value;
1027                 break;
1028         default:
1029                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1030                                         param->param);
1031                 return -EINVAL;
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int i915_set_status_page(struct drm_device *dev, void *data,
1038                                 struct drm_file *file_priv)
1039 {
1040         drm_i915_private_t *dev_priv = dev->dev_private;
1041         drm_i915_hws_addr_t *hws = data;
1042         struct intel_ring_buffer *ring;
1043
1044         if (drm_core_check_feature(dev, DRIVER_MODESET))
1045                 return -ENODEV;
1046
1047         if (!I915_NEED_GFX_HWS(dev))
1048                 return -EINVAL;
1049
1050         if (!dev_priv) {
1051                 DRM_ERROR("called with no initialization\n");
1052                 return -EINVAL;
1053         }
1054
1055         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1056                 WARN(1, "tried to set status page when mode setting active\n");
1057                 return 0;
1058         }
1059
1060         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1061
1062         ring = LP_RING(dev_priv);
1063         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1064
1065         dev_priv->dri1.gfx_hws_cpu_addr =
1066                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1067         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1068                 i915_dma_cleanup(dev);
1069                 ring->status_page.gfx_addr = 0;
1070                 DRM_ERROR("can not ioremap virtual address for"
1071                                 " G33 hw status page\n");
1072                 return -ENOMEM;
1073         }
1074
1075         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1076         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1077
1078         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1079                          ring->status_page.gfx_addr);
1080         DRM_DEBUG_DRIVER("load hws at %p\n",
1081                          ring->status_page.page_addr);
1082         return 0;
1083 }
1084
1085 static int i915_get_bridge_dev(struct drm_device *dev)
1086 {
1087         struct drm_i915_private *dev_priv = dev->dev_private;
1088         static struct pci_dev i915_bridge_dev;
1089
1090         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1091         if (!i915_bridge_dev.dev) {
1092                 DRM_ERROR("bridge device not found\n");
1093                 return -1;
1094         }
1095
1096         dev_priv->bridge_dev = &i915_bridge_dev;
1097         return 0;
1098 }
1099
1100 #define MCHBAR_I915 0x44
1101 #define MCHBAR_I965 0x48
1102 #define MCHBAR_SIZE (4*4096)
1103
1104 #define DEVEN_REG 0x54
1105 #define   DEVEN_MCHBAR_EN (1 << 28)
1106
1107 /* Allocate space for the MCH regs if needed, return nonzero on error */
1108 static int
1109 intel_alloc_mchbar_resource(struct drm_device *dev)
1110 {
1111         drm_i915_private_t *dev_priv = dev->dev_private;
1112         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1113         device_t vga;
1114         u32 temp_lo, temp_hi = 0;
1115         u64 mchbar_addr;
1116
1117         if (INTEL_INFO(dev)->gen >= 4)
1118                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1119         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1120         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1121
1122         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1123 #ifdef CONFIG_PNP
1124         if (mchbar_addr &&
1125             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1126                 return 0;
1127 #endif
1128
1129         /* Get some space for it */
1130         vga = device_get_parent(dev->dev);
1131         dev_priv->mch_res_rid = 0x100;
1132         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1133             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1134             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1135         if (dev_priv->mch_res == NULL) {
1136                 DRM_ERROR("failed mchbar resource alloc\n");
1137                 return (-ENOMEM);
1138         }
1139
1140         if (INTEL_INFO(dev)->gen >= 4)
1141                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1142                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1143
1144         pci_write_config_dword(dev_priv->bridge_dev, reg,
1145                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1146         return 0;
1147 }
1148
1149 /* Setup MCHBAR if possible, return true if we should disable it again */
1150 static void
1151 intel_setup_mchbar(struct drm_device *dev)
1152 {
1153         drm_i915_private_t *dev_priv = dev->dev_private;
1154         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1155         u32 temp;
1156         bool enabled;
1157
1158         dev_priv->mchbar_need_disable = false;
1159
1160         if (IS_I915G(dev) || IS_I915GM(dev)) {
1161                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1162                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1163         } else {
1164                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1165                 enabled = temp & 1;
1166         }
1167
1168         /* If it's already enabled, don't have to do anything */
1169         if (enabled)
1170                 return;
1171
1172         if (intel_alloc_mchbar_resource(dev))
1173                 return;
1174
1175         dev_priv->mchbar_need_disable = true;
1176
1177         /* Space is allocated or reserved, so enable it. */
1178         if (IS_I915G(dev) || IS_I915GM(dev)) {
1179                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1180                                        temp | DEVEN_MCHBAR_EN);
1181         } else {
1182                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1183                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1184         }
1185 }
1186
1187 static void
1188 intel_teardown_mchbar(struct drm_device *dev)
1189 {
1190         drm_i915_private_t *dev_priv = dev->dev_private;
1191         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1192         device_t vga;
1193         u32 temp;
1194
1195         if (dev_priv->mchbar_need_disable) {
1196                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1197                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1198                         temp &= ~DEVEN_MCHBAR_EN;
1199                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1200                 } else {
1201                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1202                         temp &= ~1;
1203                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1204                 }
1205         }
1206
1207         if (dev_priv->mch_res != NULL) {
1208                 vga = device_get_parent(dev->dev);
1209                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1210                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1211                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1212                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1213                 dev_priv->mch_res = NULL;
1214         }
1215 }
1216
1217 static int i915_load_modeset_init(struct drm_device *dev)
1218 {
1219         struct drm_i915_private *dev_priv = dev->dev_private;
1220         int ret;
1221
1222         ret = intel_parse_bios(dev);
1223         if (ret)
1224                 DRM_INFO("failed to find VBIOS tables\n");
1225
1226 #if 0
1227         /* If we have > 1 VGA cards, then we need to arbitrate access
1228          * to the common VGA resources.
1229          *
1230          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1231          * then we do not take part in VGA arbitration and the
1232          * vga_client_register() fails with -ENODEV.
1233          */
1234         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1235         if (ret && ret != -ENODEV)
1236                 goto out;
1237
1238         intel_register_dsm_handler();
1239
1240         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1241         if (ret)
1242                 goto cleanup_vga_client;
1243
1244         /* Initialise stolen first so that we may reserve preallocated
1245          * objects for the BIOS to KMS transition.
1246          */
1247         ret = i915_gem_init_stolen(dev);
1248         if (ret)
1249                 goto cleanup_vga_switcheroo;
1250 #endif
1251
1252         ret = drm_irq_install(dev);
1253         if (ret)
1254                 goto cleanup_gem_stolen;
1255
1256         /* Important: The output setup functions called by modeset_init need
1257          * working irqs for e.g. gmbus and dp aux transfers. */
1258         intel_modeset_init(dev);
1259
1260         ret = i915_gem_init(dev);
1261         if (ret)
1262                 goto cleanup_irq;
1263
1264 #if 0
1265         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1266 #endif
1267
1268         intel_modeset_gem_init(dev);
1269
1270         /* Always safe in the mode setting case. */
1271         /* FIXME: do pre/post-mode set stuff in core KMS code */
1272         dev->vblank_disable_allowed = 1;
1273
1274         ret = intel_fbdev_init(dev);
1275         if (ret)
1276                 goto cleanup_gem;
1277
1278         /* Only enable hotplug handling once the fbdev is fully set up. */
1279         intel_hpd_init(dev);
1280
1281         /*
1282          * Some ports require correctly set-up hpd registers for detection to
1283          * work properly (leading to ghost connected connector status), e.g. VGA
1284          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1285          * irqs are fully enabled. Now we should scan for the initial config
1286          * only once hotplug handling is enabled, but due to screwed-up locking
1287          * around kms/fbdev init we can't protect the fdbev initial config
1288          * scanning against hotplug events. Hence do this first and ignore the
1289          * tiny window where we will loose hotplug notifactions.
1290          */
1291         intel_fbdev_initial_config(dev);
1292
1293         /* Only enable hotplug handling once the fbdev is fully set up. */
1294         dev_priv->enable_hotplug_processing = true;
1295
1296         drm_kms_helper_poll_init(dev);
1297
1298         /* We're off and running w/KMS */
1299         dev_priv->mm.suspended = 0;
1300
1301         return 0;
1302
1303 cleanup_gem:
1304         mutex_lock(&dev->struct_mutex);
1305         i915_gem_cleanup_ringbuffer(dev);
1306         mutex_unlock(&dev->struct_mutex);
1307         i915_gem_cleanup_aliasing_ppgtt(dev);
1308 cleanup_irq:
1309         drm_irq_uninstall(dev);
1310 cleanup_gem_stolen:
1311 #if 0
1312         i915_gem_cleanup_stolen(dev);
1313 cleanup_vga_switcheroo:
1314         vga_switcheroo_unregister_client(dev->pdev);
1315 cleanup_vga_client:
1316         vga_client_register(dev->pdev, NULL, NULL, NULL);
1317 out:
1318 #endif
1319         return ret;
1320 }
1321
1322 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1323 {
1324         struct drm_i915_master_private *master_priv;
1325
1326         master_priv = kmalloc(sizeof(*master_priv), M_DRM, M_WAITOK | M_ZERO);
1327         if (!master_priv)
1328                 return -ENOMEM;
1329
1330         master->driver_priv = master_priv;
1331         return 0;
1332 }
1333
1334 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1335 {
1336         struct drm_i915_master_private *master_priv = master->driver_priv;
1337
1338         if (!master_priv)
1339                 return;
1340
1341         kfree(master_priv, M_DRM);
1342
1343         master->driver_priv = NULL;
1344 }
1345
1346 #if 0
1347 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1348 {
1349         struct apertures_struct *ap;
1350         struct pci_dev *pdev = dev_priv->dev->pdev;
1351         bool primary;
1352
1353         ap = alloc_apertures(1);
1354         if (!ap)
1355                 return;
1356
1357         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1358         ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1359
1360         primary =
1361                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1362
1363         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1364
1365         kfree(ap);
1366 }
1367 #endif
1368
1369 /**
1370  * i915_driver_load - setup chip and create an initial config
1371  * @dev: DRM device
1372  * @flags: startup flags
1373  *
1374  * The driver load routine has to do several things:
1375  *   - drive output discovery via intel_modeset_init()
1376  *   - initialize the memory manager
1377  *   - allocate initial config memory
1378  *   - setup the DRM framebuffer with the allocated memory
1379  */
1380 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1381 {
1382         struct drm_i915_private *dev_priv = dev->dev_private;
1383         unsigned long base, size;
1384         int ret = 0, mmio_bar;
1385         static struct pci_dev i915_pdev;
1386
1387         /* XXX: struct pci_dev */
1388         i915_pdev.dev = dev->dev;
1389         dev->pdev = &i915_pdev;
1390
1391         /* i915 has 4 more counters */
1392         dev->counters += 4;
1393         dev->types[6] = _DRM_STAT_IRQ;
1394         dev->types[7] = _DRM_STAT_PRIMARY;
1395         dev->types[8] = _DRM_STAT_SECONDARY;
1396         dev->types[9] = _DRM_STAT_DMA;
1397
1398         dev_priv = kmalloc(sizeof(drm_i915_private_t), M_DRM,
1399             M_ZERO | M_WAITOK);
1400         if (dev_priv == NULL)
1401                 return -ENOMEM;
1402
1403         dev->dev_private = (void *)dev_priv;
1404         dev_priv->dev = dev;
1405         dev_priv->info = i915_get_device_id(dev->pci_device);
1406
1407         if (i915_get_bridge_dev(dev)) {
1408                 ret = -EIO;
1409                 goto free_priv;
1410         }
1411
1412         ret = i915_gem_gtt_init(dev);
1413         if (ret)
1414                 goto put_bridge;
1415
1416 #if 0
1417         if (drm_core_check_feature(dev, DRIVER_MODESET))
1418                 i915_kick_out_firmware_fb(dev_priv);
1419
1420         pci_set_master(dev->pdev);
1421
1422         /* overlay on gen2 is broken and can't address above 1G */
1423         if (IS_GEN2(dev))
1424                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1425
1426         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1427          * using 32bit addressing, overwriting memory if HWS is located
1428          * above 4GB.
1429          *
1430          * The documentation also mentions an issue with undefined
1431          * behaviour if any general state is accessed within a page above 4GB,
1432          * which also needs to be handled carefully.
1433          */
1434         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1435                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1436 #endif
1437
1438         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1439         /* Before gen4, the registers and the GTT are behind different BARs.
1440          * However, from gen4 onwards, the registers and the GTT are shared
1441          * in the same BAR, so we want to restrict this ioremap from
1442          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1443          * the register BAR remains the same size for all the earlier
1444          * generations up to Ironlake.
1445          */
1446 #if 0
1447         if (info->gen < 5)
1448                 mmio_size = 512*1024;
1449         else
1450                 mmio_size = 2*1024*1024;
1451
1452         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1453         if (!dev_priv->regs) {
1454                 DRM_ERROR("failed to map registers\n");
1455                 ret = -EIO;
1456                 goto put_gmch;
1457         }
1458
1459         aperture_size = dev_priv->gtt.mappable_end;
1460
1461         dev_priv->gtt.mappable =
1462                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1463                                      aperture_size);
1464         if (dev_priv->gtt.mappable == NULL) {
1465                 ret = -EIO;
1466                 goto out_rmmap;
1467         }
1468
1469         i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1470                         aperture_size);
1471 #endif
1472
1473         base = drm_get_resource_start(dev, mmio_bar);
1474         size = drm_get_resource_len(dev, mmio_bar);
1475
1476         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1477             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1478
1479         /* The i915 workqueue is primarily used for batched retirement of
1480          * requests (and thus managing bo) once the task has been completed
1481          * by the GPU. i915_gem_retire_requests() is called directly when we
1482          * need high-priority retirement, such as waiting for an explicit
1483          * bo.
1484          *
1485          * It is also used for periodic low-priority events, such as
1486          * idle-timers and recording error state.
1487          *
1488          * All tasks on the workqueue are expected to acquire the dev mutex
1489          * so there is no point in running more than one instance of the
1490          * workqueue at any time.  Use an ordered one.
1491          */
1492         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1493         if (dev_priv->wq == NULL) {
1494                 DRM_ERROR("Failed to create our workqueue.\n");
1495                 ret = -ENOMEM;
1496                 goto out_mtrrfree;
1497         }
1498
1499         /* This must be called before any calls to HAS_PCH_* */
1500         intel_detect_pch(dev);
1501
1502         intel_irq_init(dev);
1503         intel_gt_init(dev);
1504
1505         /* Try to make sure MCHBAR is enabled before poking at it */
1506         intel_setup_mchbar(dev);
1507         intel_setup_gmbus(dev);
1508         intel_opregion_setup(dev);
1509
1510         intel_setup_bios(dev);
1511
1512         i915_gem_load(dev);
1513
1514         /* On the 945G/GM, the chipset reports the MSI capability on the
1515          * integrated graphics even though the support isn't actually there
1516          * according to the published specs.  It doesn't appear to function
1517          * correctly in testing on 945G.
1518          * This may be a side effect of MSI having been made available for PEG
1519          * and the registers being closely associated.
1520          *
1521          * According to chipset errata, on the 965GM, MSI interrupts may
1522          * be lost or delayed, but we use them anyways to avoid
1523          * stuck interrupts on some machines.
1524          */
1525 #if 0
1526         if (!IS_I945G(dev) && !IS_I945GM(dev))
1527                 pci_enable_msi(dev->pdev);
1528 #endif
1529
1530         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1531         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1532         spin_init(&dev_priv->rps.lock, "i915initrps");
1533         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1534
1535         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1536         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1537
1538         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1539                 dev_priv->num_pipe = 3;
1540         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1541                 dev_priv->num_pipe = 2;
1542         else
1543                 dev_priv->num_pipe = 1;
1544
1545         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1546         if (ret)
1547                 goto out_gem_unload;
1548
1549         /* Start out suspended */
1550         dev_priv->mm.suspended = 1;
1551
1552         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1553                 ret = i915_load_modeset_init(dev);
1554                 if (ret < 0) {
1555                         DRM_ERROR("failed to init modeset\n");
1556                         goto out_gem_unload;
1557                 }
1558         }
1559
1560 #if 0
1561         i915_setup_sysfs(dev);
1562 #endif
1563
1564         /* Must be done after probing outputs */
1565         intel_opregion_init(dev);
1566 #if 0
1567         acpi_video_register();
1568 #endif
1569
1570         if (IS_GEN5(dev))
1571                 intel_gpu_ips_init(dev_priv);
1572
1573         return 0;
1574
1575 out_gem_unload:
1576
1577         intel_teardown_gmbus(dev);
1578         intel_teardown_mchbar(dev);
1579         destroy_workqueue(dev_priv->wq);
1580 out_mtrrfree:
1581 put_bridge:
1582 free_priv:
1583         kfree(dev_priv, M_DRM);
1584         return ret;
1585 }
1586
1587 int i915_driver_unload(struct drm_device *dev)
1588 {
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         int ret;
1591
1592         intel_gpu_ips_teardown();
1593
1594 #if 0
1595         i915_teardown_sysfs(dev);
1596
1597         if (dev_priv->mm.inactive_shrinker.shrink)
1598                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1599 #endif
1600
1601         mutex_lock(&dev->struct_mutex);
1602         ret = i915_gpu_idle(dev);
1603         if (ret)
1604                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1605         i915_gem_retire_requests(dev);
1606         mutex_unlock(&dev->struct_mutex);
1607
1608         /* Cancel the retire work handler, which should be idle now. */
1609         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1610
1611 #if 0
1612         io_mapping_free(dev_priv->gtt.mappable);
1613         if (dev_priv->mm.gtt_mtrr >= 0) {
1614                 mtrr_del(dev_priv->mm.gtt_mtrr,
1615                          dev_priv->gtt.mappable_base,
1616                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1617                 dev_priv->mm.gtt_mtrr = -1;
1618         }
1619
1620         acpi_video_unregister();
1621 #endif
1622
1623         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1624                 intel_fbdev_fini(dev);
1625                 intel_modeset_cleanup(dev);
1626 #if 0
1627                 cancel_work_sync(&dev_priv->console_resume_work);
1628 #endif
1629
1630                 /*
1631                  * free the memory space allocated for the child device
1632                  * config parsed from VBT
1633                  */
1634                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1635                         kfree(dev_priv->child_dev, M_DRM);
1636                         dev_priv->child_dev = NULL;
1637                         dev_priv->child_dev_num = 0;
1638                 }
1639
1640         }
1641
1642         /* Free error state after interrupts are fully disabled. */
1643         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1644         cancel_work_sync(&dev_priv->gpu_error.work);
1645         i915_destroy_error_state(dev);
1646
1647         intel_opregion_fini(dev);
1648
1649         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1650                 /* Flush any outstanding unpin_work. */
1651                 flush_workqueue(dev_priv->wq);
1652
1653                 mutex_lock(&dev->struct_mutex);
1654                 i915_gem_free_all_phys_object(dev);
1655                 i915_gem_cleanup_ringbuffer(dev);
1656                 i915_gem_context_fini(dev);
1657                 mutex_unlock(&dev->struct_mutex);
1658                 i915_gem_cleanup_aliasing_ppgtt(dev);
1659 #if 0
1660                 i915_gem_cleanup_stolen(dev);
1661 #endif
1662
1663                 if (!I915_NEED_GFX_HWS(dev))
1664                         i915_free_hws(dev);
1665         }
1666
1667 #if 0
1668         if (dev_priv->regs != NULL)
1669                 pci_iounmap(dev->pdev, dev_priv->regs);
1670 #endif
1671
1672         intel_teardown_gmbus(dev);
1673         intel_teardown_mchbar(dev);
1674
1675         bus_generic_detach(dev->dev);
1676         drm_rmmap(dev, dev_priv->mmio_map);
1677         intel_teardown_gmbus(dev);
1678
1679         destroy_workqueue(dev_priv->wq);
1680         pm_qos_remove_request(&dev_priv->pm_qos);
1681
1682         pci_dev_put(dev_priv->bridge_dev);
1683         drm_free(dev->dev_private, M_DRM);
1684
1685         return 0;
1686 }
1687
1688 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1689 {
1690         struct drm_i915_file_private *file_priv;
1691
1692         DRM_DEBUG_DRIVER("\n");
1693         file_priv = kmalloc(sizeof(*file_priv), M_DRM, M_WAITOK);
1694         if (!file_priv)
1695                 return -ENOMEM;
1696
1697         file->driver_priv = file_priv;
1698
1699         spin_init(&file_priv->mm.lock, "i915_priv");
1700         INIT_LIST_HEAD(&file_priv->mm.request_list);
1701
1702         idr_init(&file_priv->context_idr);
1703
1704         return 0;
1705 }
1706
1707 /**
1708  * i915_driver_lastclose - clean up after all DRM clients have exited
1709  * @dev: DRM device
1710  *
1711  * Take care of cleaning up after all DRM clients have exited.  In the
1712  * mode setting case, we want to restore the kernel's initial mode (just
1713  * in case the last client left us in a bad state).
1714  *
1715  * Additionally, in the non-mode setting case, we'll tear down the GTT
1716  * and DMA structures, since the kernel won't be using them, and clea
1717  * up any GEM state.
1718  */
1719 void i915_driver_lastclose(struct drm_device * dev)
1720 {
1721         drm_i915_private_t *dev_priv = dev->dev_private;
1722
1723         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1724          * goes right around and calls lastclose. Check for this and don't clean
1725          * up anything. */
1726         if (!dev_priv)
1727                 return;
1728
1729         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1730 #if 0
1731                 intel_fb_restore_mode(dev);
1732                 vga_switcheroo_process_delayed_switch();
1733 #endif
1734                 return;
1735         }
1736
1737         i915_gem_lastclose(dev);
1738
1739         i915_dma_cleanup(dev);
1740 }
1741
1742 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1743 {
1744         i915_gem_context_close(dev, file_priv);
1745         i915_gem_release(dev, file_priv);
1746 }
1747
1748 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1749 {
1750         struct drm_i915_file_private *file_priv = file->driver_priv;
1751
1752         kfree(file_priv, M_DRM);
1753 }
1754
1755 struct drm_ioctl_desc i915_ioctls[] = {
1756         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1757         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1758         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1759         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1760         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1761         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1762         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1763         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1764         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1765         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1766         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1767         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1768         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1769         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1770         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1771         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1772         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1781         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1783         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1784         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1785         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1786         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1788         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1790         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1794         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1795         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1796         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1797         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1798         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1799         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1800         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1801         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1802         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1803         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1804 };
1805
1806 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1807
1808 /*
1809  * This is really ugly: Because old userspace abused the linux agp interface to
1810  * manage the gtt, we need to claim that all intel devices are agp.  For
1811  * otherwise the drm core refuses to initialize the agp support code.
1812  */
1813 int i915_driver_device_is_agp(struct drm_device * dev)
1814 {
1815         return 1;
1816 }