2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/mpapic.h>
61 #include <machine/psl.h>
62 #include <machine/segments.h>
63 #include <machine/tss.h>
64 #include <machine/specialreg.h>
65 #include <machine/globaldata.h>
66 #include <machine/pmap_inval.h>
68 #include <machine/md_var.h> /* setidt() */
69 #include <machine_base/icu/icu.h> /* IPIs */
70 #include <machine/intr_machdep.h> /* IPIs */
72 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
74 #define WARMBOOT_TARGET 0
75 #define WARMBOOT_OFF (KERNBASE + 0x0467)
76 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78 #define BIOS_BASE (0xf0000)
79 #define BIOS_BASE2 (0xe0000)
80 #define BIOS_SIZE (0x10000)
81 #define BIOS_COUNT (BIOS_SIZE/4)
83 #define CMOS_REG (0x70)
84 #define CMOS_DATA (0x71)
85 #define BIOS_RESET (0x0f)
86 #define BIOS_WARM (0x0a)
88 #define PROCENTRY_FLAG_EN 0x01
89 #define PROCENTRY_FLAG_BP 0x02
90 #define IOAPICENTRY_FLAG_EN 0x01
93 /* MP Floating Pointer Structure */
94 typedef struct MPFPS {
107 /* MP Configuration Table Header */
108 typedef struct MPCTH {
110 u_short base_table_length;
114 u_char product_id[12];
115 void *oem_table_pointer;
116 u_short oem_table_size;
119 u_short extended_table_length;
120 u_char extended_table_checksum;
125 typedef struct PROCENTRY {
130 u_long cpu_signature;
131 u_long feature_flags;
136 typedef struct BUSENTRY {
142 typedef struct IOAPICENTRY {
148 } *io_apic_entry_ptr;
150 typedef struct INTENTRY {
160 /* descriptions of MP basetable entries */
161 typedef struct BASETABLE_ENTRY {
170 vm_size_t mp_cth_mapsz;
173 #define MPTABLE_POS_USE_DEFAULT(mpt) \
174 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
178 int mb_type; /* MPTABLE_BUS_ */
179 TAILQ_ENTRY(mptable_bus) mb_link;
182 #define MPTABLE_BUS_ISA 0
183 #define MPTABLE_BUS_PCI 1
185 struct mptable_bus_info {
186 TAILQ_HEAD(, mptable_bus) mbi_list;
189 struct mptable_pci_int {
196 TAILQ_ENTRY(mptable_pci_int) mpci_link;
199 struct mptable_ioapic {
205 TAILQ_ENTRY(mptable_ioapic) mio_link;
208 typedef int (*mptable_iter_func)(void *, const void *, int);
211 * this code MUST be enabled here and in mpboot.s.
212 * it follows the very early stages of AP boot by placing values in CMOS ram.
213 * it NORMALLY will never be needed and thus the primitive method for enabling.
216 #if defined(CHECK_POINTS)
217 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
218 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
220 #define CHECK_INIT(D); \
221 CHECK_WRITE(0x34, (D)); \
222 CHECK_WRITE(0x35, (D)); \
223 CHECK_WRITE(0x36, (D)); \
224 CHECK_WRITE(0x37, (D)); \
225 CHECK_WRITE(0x38, (D)); \
226 CHECK_WRITE(0x39, (D));
228 #define CHECK_PRINT(S); \
229 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
238 #else /* CHECK_POINTS */
240 #define CHECK_INIT(D)
241 #define CHECK_PRINT(S)
243 #endif /* CHECK_POINTS */
246 * Values to send to the POST hardware.
248 #define MP_BOOTADDRESS_POST 0x10
249 #define MP_PROBE_POST 0x11
250 #define MPTABLE_PASS1_POST 0x12
252 #define MP_START_POST 0x13
253 #define MP_ENABLE_POST 0x14
254 #define MPTABLE_PASS2_POST 0x15
256 #define START_ALL_APS_POST 0x16
257 #define INSTALL_AP_TRAMP_POST 0x17
258 #define START_AP_POST 0x18
260 #define MP_ANNOUNCE_POST 0x19
262 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
263 int current_postcode;
265 /** XXX FIXME: what system files declare these??? */
266 extern struct region_descriptor r_gdt, r_idt;
268 int mp_naps; /* # of Applications processors */
271 u_int32_t cpu_apic_versions[MAXCPU];
273 extern int64_t tsc_offsets[];
275 extern u_long ebda_addr;
277 #ifdef SMP /* APIC-IO */
278 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
282 * APIC ID logical/physical mapping structures.
283 * We oversize these to simplify boot-time config.
285 int cpu_num_to_apic_id[NAPICID];
286 int apic_id_to_logical[NAPICID];
288 /* AP uses this during bootstrap. Do not staticize. */
292 /* Hotwire a 0->4MB V==P mapping */
293 extern pt_entry_t *KPTphys;
296 * SMP page table page. Setup by locore to point to a page table
297 * page from which we allocate per-cpu privatespace areas io_apics,
301 #define IO_MAPPING_START_INDEX \
302 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
304 extern pt_entry_t *SMPpt;
305 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
307 struct pcb stoppcbs[MAXCPU];
309 static basetable_entry basetable_entry_types[] =
311 {0, 20, "Processor"},
319 * Local data and functions.
322 static u_int boot_address;
323 static u_int base_memory;
324 static int mp_finish;
325 static int mp_finish_lapic;
327 static void mp_enable(u_int boot_addr);
329 static int mptable_iterate_entries(const mpcth_t,
330 mptable_iter_func, void *);
331 static int mptable_search(void);
332 static int mptable_search_sig(u_int32_t target, int count);
333 static int mptable_hyperthread_fixup(cpumask_t, int);
334 static int mptable_map(struct mptable_pos *);
335 static void mptable_unmap(struct mptable_pos *);
336 static void mptable_bus_info_alloc(const mpcth_t,
337 struct mptable_bus_info *);
338 static void mptable_bus_info_free(struct mptable_bus_info *);
340 static int mptable_lapic_probe(struct lapic_enumerator *);
341 static void mptable_lapic_enumerate(struct lapic_enumerator *);
342 static void mptable_lapic_default(void);
344 static int mptable_ioapic_probe(struct ioapic_enumerator *);
345 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
347 static int start_all_aps(u_int boot_addr);
348 static void install_ap_tramp(u_int boot_addr);
349 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
350 static int smitest(void);
352 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
353 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
354 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
355 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
359 static vm_paddr_t mptable_fps_phyaddr;
360 static int mptable_use_default;
361 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
362 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
363 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
364 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
367 * Calculate usable address in base memory for AP trampoline code.
370 mp_bootaddress(u_int basemem)
372 POSTCODE(MP_BOOTADDRESS_POST);
374 base_memory = basemem;
376 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
377 if ((base_memory - boot_address) < bootMP_size)
378 boot_address -= 4096; /* not enough, lower by 4k */
387 struct mptable_pos mpt;
390 KKASSERT(mptable_fps_phyaddr == 0);
392 mptable_fps_phyaddr = mptable_search();
393 if (mptable_fps_phyaddr == 0)
396 error = mptable_map(&mpt);
398 mptable_fps_phyaddr = 0;
402 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
403 kprintf("MPTABLE: use default configuration\n");
404 mptable_use_default = 1;
406 if (mpt.mp_fps->mpfb2 & 0x80)
411 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
414 * Look for an Intel MP spec table (ie, SMP capable hardware).
423 * Make sure our SMPpt[] page table is big enough to hold all the
426 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
428 POSTCODE(MP_PROBE_POST);
430 /* see if EBDA exists */
431 if (ebda_addr != 0) {
432 /* search first 1K of EBDA */
433 target = (u_int32_t)ebda_addr;
434 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
437 /* last 1K of base memory, effective 'top of base' passed in */
438 target = (u_int32_t)(base_memory - 0x400);
439 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
443 /* search the BIOS */
444 target = (u_int32_t)BIOS_BASE;
445 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
448 /* search the extended BIOS */
449 target = (u_int32_t)BIOS_BASE2;
450 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
458 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
460 int count, total_size;
461 const void *position;
463 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
464 total_size = cth->base_table_length - sizeof(struct MPCTH);
465 position = (const uint8_t *)cth + sizeof(struct MPCTH);
466 count = cth->entry_count;
471 KKASSERT(total_size >= 0);
472 if (total_size == 0) {
473 kprintf("invalid base MP table, "
474 "entry count and length mismatch\n");
478 type = *(const uint8_t *)position;
480 case 0: /* processor_entry */
481 case 1: /* bus_entry */
482 case 2: /* io_apic_entry */
483 case 3: /* int_entry */
484 case 4: /* int_entry */
487 kprintf("unknown base MP table entry type %d\n", type);
491 if (total_size < basetable_entry_types[type].length) {
492 kprintf("invalid base MP table length, "
493 "does not contain all entries\n");
496 total_size -= basetable_entry_types[type].length;
498 error = func(arg, position, type);
502 position = (const uint8_t *)position +
503 basetable_entry_types[type].length;
510 * Startup the SMP processors.
515 POSTCODE(MP_START_POST);
516 mp_enable(boot_address);
521 * Print various information about the SMP system hardware and setup.
528 POSTCODE(MP_ANNOUNCE_POST);
530 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
531 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
532 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
533 for (x = 1; x <= mp_naps; ++x) {
534 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
535 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
539 kprintf(" Warning: APIC I/O disabled\n");
543 * AP cpu's call this to sync up protected mode.
545 * WARNING! We must ensure that the cpu is sufficiently initialized to
546 * be able to use to the FP for our optimized bzero/bcopy code before
547 * we enter more mainstream C code.
549 * WARNING! %fs is not set up on entry. This routine sets up %fs.
555 int x, myid = bootAP;
557 struct mdglobaldata *md;
558 struct privatespace *ps;
560 ps = &CPU_prvspace[myid];
562 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
563 gdt_segs[GPROC0_SEL].ssd_base =
564 (int) &ps->mdglobaldata.gd_common_tss;
565 ps->mdglobaldata.mi.gd_prvspace = ps;
567 for (x = 0; x < NGDT; x++) {
568 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
571 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
572 r_gdt.rd_base = (int) &gdt[myid * NGDT];
573 lgdt(&r_gdt); /* does magic intra-segment return */
578 mdcpu->gd_currentldt = _default_ldt;
580 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
581 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
583 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
585 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
586 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
587 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
588 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
589 md->gd_common_tssd = *md->gd_tss_gdt;
593 * Set to a known state:
594 * Set by mpboot.s: CR0_PG, CR0_PE
595 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
598 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
600 pmap_set_opt(); /* PSE/4MB pages, etc */
602 /* set up CPU registers and state */
605 /* set up FPU state on the AP */
606 npxinit(__INITIAL_NPXCW__);
608 /* set up SSE registers */
612 /*******************************************************************
613 * local functions and data
617 * start the SMP system
620 mp_enable(u_int boot_addr)
622 POSTCODE(MP_ENABLE_POST);
626 /* Initialize BSP's local APIC */
629 /* start each Application Processor */
630 start_all_aps(boot_addr);
636 MachIntrABI.finalize();
641 * look for the MP spec signature
644 /* string defined by the Intel MP Spec as identifying the MP table */
645 #define MP_SIG 0x5f504d5f /* _MP_ */
646 #define NEXT(X) ((X) += 4)
648 mptable_search_sig(u_int32_t target, int count)
654 KKASSERT(target != 0);
656 map_size = count * sizeof(u_int32_t);
657 addr = pmap_mapdev((vm_paddr_t)target, map_size);
660 for (x = 0; x < count; NEXT(x)) {
661 if (addr[x] == MP_SIG) {
662 /* make array index a byte index */
663 ret = target + (x * sizeof(u_int32_t));
668 pmap_unmapdev((vm_offset_t)addr, map_size);
673 typedef struct BUSDATA {
675 enum busTypes bus_type;
678 typedef struct INTDATA {
688 typedef struct BUSTYPENAME {
693 static int processor_entry (const struct PROCENTRY *entry, int cpu);
696 * Check if we should perform a hyperthreading "fix-up" to
697 * enumerate any logical CPU's that aren't already listed
700 * XXX: We assume that all of the physical CPUs in the
701 * system have the same number of logical CPUs.
703 * XXX: We assume that APIC ID's are allocated such that
704 * the APIC ID's for a physical processor are aligned
705 * with the number of logical CPU's in the processor.
708 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
710 int i, id, lcpus_max, logical_cpus;
712 if ((cpu_feature & CPUID_HTT) == 0)
715 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
719 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
721 * INSTRUCTION SET REFERENCE, A-M (#253666)
722 * Page 3-181, Table 3-20
723 * "The nearest power-of-2 integer that is not smaller
724 * than EBX[23:16] is the number of unique initial APIC
725 * IDs reserved for addressing different logical
726 * processors in a physical package."
729 if ((1 << i) >= lcpus_max) {
736 KKASSERT(cpu_count != 0);
737 if (cpu_count == lcpus_max) {
738 /* We have nothing to fix */
740 } else if (cpu_count == 1) {
741 /* XXX this may be incorrect */
742 logical_cpus = lcpus_max;
747 * Calculate the distances between two nearest
748 * APIC IDs. If all such distances are same,
749 * then it is the number of missing cpus that
750 * we are going to fill later.
752 dist = cur = prev = -1;
753 for (id = 0; id < MAXCPU; ++id) {
754 if ((id_mask & CPUMASK(id)) == 0)
759 int new_dist = cur - prev;
765 * Make sure that all distances
766 * between two nearest APIC IDs
769 if (dist != new_dist)
777 /* Must be power of 2 */
778 if (dist & (dist - 1))
781 /* Can't exceed CPU package capacity */
782 if (dist > lcpus_max)
783 logical_cpus = lcpus_max;
789 * For each APIC ID of a CPU that is set in the mask,
790 * scan the other candidate APIC ID's for this
791 * physical processor. If any of those ID's are
792 * already in the table, then kill the fixup.
794 for (id = 0; id < MAXCPU; id++) {
795 if ((id_mask & CPUMASK(id)) == 0)
797 /* First, make sure we are on a logical_cpus boundary. */
798 if (id % logical_cpus != 0)
800 for (i = id + 1; i < id + logical_cpus; i++)
801 if ((id_mask & CPUMASK(i)) != 0)
808 mptable_map(struct mptable_pos *mpt)
812 vm_size_t cth_mapsz = 0;
814 KKASSERT(mptable_fps_phyaddr != 0);
816 bzero(mpt, sizeof(*mpt));
818 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
821 * Map configuration table header to get
822 * the base table size
824 cth = pmap_mapdev(fps->pap, sizeof(*cth));
825 cth_mapsz = cth->base_table_length;
826 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
828 if (cth_mapsz < sizeof(*cth)) {
829 kprintf("invalid base MP table length %d\n",
831 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
838 cth = pmap_mapdev(fps->pap, cth_mapsz);
843 mpt->mp_cth_mapsz = cth_mapsz;
849 mptable_unmap(struct mptable_pos *mpt)
851 if (mpt->mp_cth != NULL) {
852 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
854 mpt->mp_cth_mapsz = 0;
856 if (mpt->mp_fps != NULL) {
857 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
863 mp_set_cpuids(int cpu_id, int apic_id)
865 CPU_TO_ID(cpu_id) = apic_id;
866 ID_TO_CPU(apic_id) = cpu_id;
870 processor_entry(const struct PROCENTRY *entry, int cpu)
874 /* check for usability */
875 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
878 /* check for BSP flag */
879 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
880 mp_set_cpuids(0, entry->apic_id);
881 return 0; /* its already been counted */
884 /* add another AP to list, if less than max number of CPUs */
885 else if (cpu < MAXCPU) {
886 mp_set_cpuids(cpu, entry->apic_id);
894 * Map a physical memory address representing I/O into KVA. The I/O
895 * block is assumed not to cross a page boundary.
898 ioapic_map(vm_paddr_t pa)
904 KKASSERT(pa < 0x100000000LL);
906 pgeflag = 0; /* not used for SMP yet */
909 * If the requested physical address has already been incidently
910 * mapped, just use the existing mapping. Otherwise create a new
913 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
914 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
915 ((vm_offset_t)pa & PG_FRAME)) {
919 if (i == SMPpt_alloc_index) {
920 if (i == NPTEPG - 2) {
921 panic("permanent_io_mapping: We ran out of space"
924 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
925 ((vm_offset_t)pa & PG_FRAME));
928 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
929 ((vm_offset_t)pa & PAGE_MASK);
930 return ((void *)vaddr);
934 * start each AP in our list
937 start_all_aps(u_int boot_addr)
945 u_long mpbioswarmvec;
946 struct mdglobaldata *gd;
947 struct privatespace *ps;
951 POSTCODE(START_ALL_APS_POST);
953 /* install the AP 1st level boot code */
954 install_ap_tramp(boot_addr);
957 /* save the current value of the warm-start vector */
958 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
959 outb(CMOS_REG, BIOS_RESET);
960 mpbiosreason = inb(CMOS_DATA);
962 /* setup a vector to our boot code */
963 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
964 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
965 outb(CMOS_REG, BIOS_RESET);
966 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
969 * If we have a TSC we can figure out the SMI interrupt rate.
970 * The SMI does not necessarily use a constant rate. Spend
971 * up to 250ms trying to figure it out.
974 if (cpu_feature & CPUID_TSC) {
975 set_apic_timer(275000);
976 smilast = read_apic_timer();
977 for (x = 0; x < 20 && read_apic_timer(); ++x) {
978 smicount = smitest();
979 if (smibest == 0 || smilast - smicount < smibest)
980 smibest = smilast - smicount;
983 if (smibest > 250000)
986 smibest = smibest * (int64_t)1000000 /
987 get_apic_timer_frequency();
991 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
992 1000000 / smibest, smibest);
995 /* set up temporary P==V mapping for AP boot */
996 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
997 kptbase = (uintptr_t)(void *)KPTphys;
998 for (x = 0; x < NKPT; x++) {
999 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1000 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1005 for (x = 1; x <= mp_naps; ++x) {
1007 /* This is a bit verbose, it will go away soon. */
1009 /* first page of AP's private space */
1010 pg = x * i386_btop(sizeof(struct privatespace));
1012 /* allocate new private data page(s) */
1013 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
1014 MDGLOBALDATA_BASEALLOC_SIZE);
1015 /* wire it into the private page table page */
1016 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
1017 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
1018 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
1020 pg += MDGLOBALDATA_BASEALLOC_PAGES;
1022 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
1023 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
1024 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
1025 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
1027 /* allocate and set up an idle stack data page */
1028 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
1029 for (i = 0; i < UPAGES; i++) {
1030 SMPpt[pg + 4 + i] = (pt_entry_t)
1031 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
1034 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
1035 bzero(gd, sizeof(*gd));
1036 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
1038 /* prime data page for it to use */
1039 mi_gdinit(&gd->mi, x);
1041 gd->gd_CMAP1 = &SMPpt[pg + 0];
1042 gd->gd_CMAP2 = &SMPpt[pg + 1];
1043 gd->gd_CMAP3 = &SMPpt[pg + 2];
1044 gd->gd_PMAP1 = &SMPpt[pg + 3];
1045 gd->gd_CADDR1 = ps->CPAGE1;
1046 gd->gd_CADDR2 = ps->CPAGE2;
1047 gd->gd_CADDR3 = ps->CPAGE3;
1048 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
1051 * Per-cpu pmap for get_ptbase().
1053 gd->gd_GDADDR1= (unsigned *)
1054 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
1055 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
1057 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
1058 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
1061 * Setup the AP boot stack
1063 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
1066 /* attempt to start the Application Processor */
1067 CHECK_INIT(99); /* setup checkpoints */
1068 if (!start_ap(gd, boot_addr, smibest)) {
1069 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1070 CHECK_PRINT("trace"); /* show checkpoints */
1071 /* better panic as the AP may be running loose */
1072 kprintf("panic y/n? [y] ");
1073 if (cngetc() != 'n')
1076 CHECK_PRINT("trace"); /* show checkpoints */
1078 /* record its version info */
1079 cpu_apic_versions[x] = cpu_apic_versions[0];
1082 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
1085 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
1086 for (shift = 0; (1 << shift) <= ncpus; ++shift)
1089 ncpus2_shift = shift;
1090 ncpus2 = 1 << shift;
1091 ncpus2_mask = ncpus2 - 1;
1093 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
1094 if ((1 << shift) < ncpus)
1096 ncpus_fit = 1 << shift;
1097 ncpus_fit_mask = ncpus_fit - 1;
1099 /* build our map of 'other' CPUs */
1100 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1101 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1102 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1104 /* fill in our (BSP) APIC version */
1105 cpu_apic_versions[0] = lapic.version;
1107 /* restore the warmstart vector */
1108 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1109 outb(CMOS_REG, BIOS_RESET);
1110 outb(CMOS_DATA, mpbiosreason);
1113 * NOTE! The idlestack for the BSP was setup by locore. Finish
1114 * up, clean out the P==V mapping we did earlier.
1116 for (x = 0; x < NKPT; x++)
1121 * Wait all APs to finish initializing LAPIC
1123 mp_finish_lapic = 1;
1125 kprintf("SMP: Waiting APs LAPIC initialization\n");
1126 if (cpu_feature & CPUID_TSC)
1127 tsc0_offset = rdtsc();
1130 while (smp_lapic_mask != smp_startup_mask) {
1132 if (cpu_feature & CPUID_TSC)
1133 tsc0_offset = rdtsc();
1135 while (try_mplock() == 0)
1138 /* number of APs actually started */
1143 * load the 1st level AP boot code into base memory.
1146 /* targets for relocation */
1147 extern void bigJump(void);
1148 extern void bootCodeSeg(void);
1149 extern void bootDataSeg(void);
1150 extern void MPentry(void);
1151 extern u_int MP_GDT;
1152 extern u_int mp_gdtbase;
1155 install_ap_tramp(u_int boot_addr)
1158 int size = *(int *) ((u_long) & bootMP_size);
1159 u_char *src = (u_char *) ((u_long) bootMP);
1160 u_char *dst = (u_char *) boot_addr + KERNBASE;
1161 u_int boot_base = (u_int) bootMP;
1166 POSTCODE(INSTALL_AP_TRAMP_POST);
1168 for (x = 0; x < size; ++x)
1172 * modify addresses in code we just moved to basemem. unfortunately we
1173 * need fairly detailed info about mpboot.s for this to work. changes
1174 * to mpboot.s might require changes here.
1177 /* boot code is located in KERNEL space */
1178 dst = (u_char *) boot_addr + KERNBASE;
1180 /* modify the lgdt arg */
1181 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1182 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1184 /* modify the ljmp target for MPentry() */
1185 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1186 *dst32 = ((u_int) MPentry - KERNBASE);
1188 /* modify the target for boot code segment */
1189 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1190 dst8 = (u_int8_t *) (dst16 + 1);
1191 *dst16 = (u_int) boot_addr & 0xffff;
1192 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1194 /* modify the target for boot data segment */
1195 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1196 dst8 = (u_int8_t *) (dst16 + 1);
1197 *dst16 = (u_int) boot_addr & 0xffff;
1198 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1203 * This function starts the AP (application processor) identified
1204 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1205 * to accomplish this. This is necessary because of the nuances
1206 * of the different hardware we might encounter. It ain't pretty,
1207 * but it seems to work.
1209 * NOTE: eventually an AP gets to ap_init(), which is called just
1210 * before the AP goes into the LWKT scheduler's idle loop.
1213 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
1217 u_long icr_lo, icr_hi;
1219 POSTCODE(START_AP_POST);
1221 /* get the PHYSICAL APIC ID# */
1222 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
1224 /* calculate the vector */
1225 vector = (boot_addr >> 12) & 0xff;
1227 /* We don't want anything interfering */
1230 /* Make sure the target cpu sees everything */
1234 * Try to detect when a SMI has occurred, wait up to 200ms.
1236 * If a SMI occurs during an AP reset but before we issue
1237 * the STARTUP command, the AP may brick. To work around
1238 * this problem we hold off doing the AP startup until
1239 * after we have detected the SMI. Hopefully another SMI
1240 * will not occur before we finish the AP startup.
1242 * Retries don't seem to help. SMIs have a window of opportunity
1243 * and if USB->legacy keyboard emulation is enabled in the BIOS
1244 * the interrupt rate can be quite high.
1246 * NOTE: Don't worry about the L1 cache load, it might bloat
1247 * ldelta a little but ndelta will be so huge when the SMI
1248 * occurs the detection logic will still work fine.
1251 set_apic_timer(200000);
1256 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1257 * and running the target CPU. OR this INIT IPI might be latched (P5
1258 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1261 * see apic/apicreg.h for icr bit definitions.
1263 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
1267 * Setup the address for the target AP. We can setup
1268 * icr_hi once and then just trigger operations with
1271 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1272 icr_hi |= (physical_cpu << 24);
1273 icr_lo = lapic.icr_lo & 0xfff00000;
1274 lapic.icr_hi = icr_hi;
1277 * Do an INIT IPI: assert RESET
1279 * Use edge triggered mode to assert INIT
1281 lapic.icr_lo = icr_lo | 0x0000c500;
1282 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1286 * The spec calls for a 10ms delay but we may have to use a
1287 * MUCH lower delay to avoid bricking an AP due to a fast SMI
1288 * interrupt. We have other loops here too and dividing by 2
1289 * doesn't seem to be enough even after subtracting 350us,
1290 * so we divide by 4.
1292 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
1293 * interrupt was detected we use the full 10ms.
1297 else if (smibest < 150 * 4 + 350)
1299 else if ((smibest - 350) / 4 < 10000)
1300 u_sleep((smibest - 350) / 4);
1305 * Do an INIT IPI: deassert RESET
1307 * Use level triggered mode to deassert. It is unclear
1308 * why we need to do this.
1310 lapic.icr_lo = icr_lo | 0x00008500;
1311 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1313 u_sleep(150); /* wait 150us */
1316 * Next we do a STARTUP IPI: the previous INIT IPI might still be
1317 * latched, (P5 bug) this 1st STARTUP would then terminate
1318 * immediately, and the previously started INIT IPI would continue. OR
1319 * the previous INIT IPI has already run. and this STARTUP IPI will
1320 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1323 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1324 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1326 u_sleep(200); /* wait ~200uS */
1329 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1330 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1331 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1332 * recognized after hardware RESET or INIT IPI.
1334 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1335 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1338 /* Resume normal operation */
1341 /* wait for it to start, see ap_init() */
1342 set_apic_timer(5000000);/* == 5 seconds */
1343 while (read_apic_timer()) {
1344 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
1345 return 1; /* return SUCCESS */
1348 return 0; /* return FAILURE */
1363 while (read_apic_timer()) {
1365 for (count = 0; count < 100; ++count)
1366 ntsc = rdtsc(); /* force loop to occur */
1368 ndelta = ntsc - ltsc;
1369 if (ldelta > ndelta)
1371 if (ndelta > ldelta * 2)
1374 ldelta = ntsc - ltsc;
1377 return(read_apic_timer());
1381 * Lazy flush the TLB on all other CPU's. DEPRECATED.
1383 * If for some reason we were unable to start all cpus we cannot safely
1384 * use broadcast IPIs.
1387 static cpumask_t smp_invltlb_req;
1388 #define SMP_INVLTLB_DEBUG
1394 struct mdglobaldata *md = mdcpu;
1395 #ifdef SMP_INVLTLB_DEBUG
1400 crit_enter_gd(&md->mi);
1401 md->gd_invltlb_ret = 0;
1402 ++md->mi.gd_cnt.v_smpinvltlb;
1403 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1404 #ifdef SMP_INVLTLB_DEBUG
1407 if (smp_startup_mask == smp_active_mask) {
1408 all_but_self_ipi(XINVLTLB_OFFSET);
1410 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
1411 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1414 #ifdef SMP_INVLTLB_DEBUG
1416 kprintf("smp_invltlb: ipi sent\n");
1418 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
1419 (smp_active_mask & ~md->mi.gd_cpumask)) {
1422 #ifdef SMP_INVLTLB_DEBUG
1424 if (++count == 400000000) {
1425 print_backtrace(-1);
1426 kprintf("smp_invltlb: endless loop %08lx %08lx, "
1427 "rflags %016lx retry",
1428 (long)md->gd_invltlb_ret,
1429 (long)smp_invltlb_req,
1430 (long)read_eflags());
1431 __asm __volatile ("sti");
1434 lwkt_process_ipiq();
1436 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
1437 ~md->mi.gd_cpumask &
1440 kprintf("bcpu %d\n", bcpu);
1441 xgd = globaldata_find(bcpu);
1442 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
1451 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1452 crit_exit_gd(&md->mi);
1459 * Called from Xinvltlb assembly with interrupts disabled. We didn't
1460 * bother to bump the critical section count or nested interrupt count
1461 * so only do very low level operations here.
1464 smp_invltlb_intr(void)
1466 struct mdglobaldata *md = mdcpu;
1467 struct mdglobaldata *omd;
1471 mask = smp_invltlb_req;
1475 cpu = BSFCPUMASK(mask);
1476 mask &= ~CPUMASK(cpu);
1477 omd = (struct mdglobaldata *)globaldata_find(cpu);
1478 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
1485 * When called the executing CPU will send an IPI to all other CPUs
1486 * requesting that they halt execution.
1488 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1490 * - Signals all CPUs in map to stop.
1491 * - Waits for each to stop.
1498 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1499 * from executing at same time.
1502 stop_cpus(cpumask_t map)
1504 map &= smp_active_mask;
1506 /* send the Xcpustop IPI to all CPUs in map */
1507 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1509 while ((stopped_cpus & map) != map)
1517 * Called by a CPU to restart stopped CPUs.
1519 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1521 * - Signals all CPUs in map to restart.
1522 * - Waits for each to restart.
1530 restart_cpus(cpumask_t map)
1532 /* signal other cpus to restart */
1533 started_cpus = map & smp_active_mask;
1535 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
1542 * This is called once the mpboot code has gotten us properly relocated
1543 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1544 * and when it returns the scheduler will call the real cpu_idle() main
1545 * loop for the idlethread. Interrupts are disabled on entry and should
1546 * remain disabled at return.
1554 * Adjust smp_startup_mask to signal the BSP that we have started
1555 * up successfully. Note that we do not yet hold the BGL. The BSP
1556 * is waiting for our signal.
1558 * We can't set our bit in smp_active_mask yet because we are holding
1559 * interrupts physically disabled and remote cpus could deadlock
1560 * trying to send us an IPI.
1562 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
1566 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1567 * non-zero, then get the MP lock.
1569 * Note: We are in a critical section.
1571 * Note: we are the idle thread, we can only spin.
1573 * Note: The load fence is memory volatile and prevents the compiler
1574 * from improperly caching mp_finish_lapic, and the cpu from improperly
1577 while (mp_finish_lapic == 0)
1579 while (try_mplock() == 0)
1582 if (cpu_feature & CPUID_TSC) {
1584 * The BSP is constantly updating tsc0_offset, figure out
1585 * the relative difference to synchronize ktrdump.
1587 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1590 /* BSP may have changed PTD while we're waiting for the lock */
1593 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1597 /* Build our map of 'other' CPUs. */
1598 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1600 /* A quick check from sanity claus */
1601 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
1602 if (mycpu->gd_cpuid != apic_id) {
1603 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1604 kprintf("SMP: apic_id = %d\n", apic_id);
1605 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1606 panic("cpuid mismatch! boom!!");
1609 /* Initialize AP's local APIC for irq's */
1612 /* LAPIC initialization is done */
1613 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1616 /* Let BSP move onto the next initialization stage */
1620 * Interlock for finalization. Wait until mp_finish is non-zero,
1621 * then get the MP lock.
1623 * Note: We are in a critical section.
1625 * Note: we are the idle thread, we can only spin.
1627 * Note: The load fence is memory volatile and prevents the compiler
1628 * from improperly caching mp_finish, and the cpu from improperly
1631 while (mp_finish == 0)
1633 while (try_mplock() == 0)
1636 /* BSP may have changed PTD while we're waiting for the lock */
1639 /* Set memory range attributes for this CPU to match the BSP */
1640 mem_range_AP_init();
1643 * Once we go active we must process any IPIQ messages that may
1644 * have been queued, because no actual IPI will occur until we
1645 * set our bit in the smp_active_mask. If we don't the IPI
1646 * message interlock could be left set which would also prevent
1649 * The idle loop doesn't expect the BGL to be held and while
1650 * lwkt_switch() normally cleans things up this is a special case
1651 * because we returning almost directly into the idle loop.
1653 * The idle thread is never placed on the runq, make sure
1654 * nothing we've done put it there.
1656 KKASSERT(get_mplock_count(curthread) == 1);
1657 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1660 * Enable interrupts here. idle_restore will also do it, but
1661 * doing it here lets us clean up any strays that got posted to
1662 * the CPU during the AP boot while we are still in a critical
1665 __asm __volatile("sti; pause; pause"::);
1666 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1668 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1669 lwkt_process_ipiq();
1672 * Releasing the mp lock lets the BSP finish up the SMP init
1675 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1679 * Get SMP fully working before we start initializing devices.
1687 kprintf("Finish MP startup\n");
1689 while (smp_active_mask != smp_startup_mask)
1691 while (try_mplock() == 0)
1694 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1697 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1700 cpu_send_ipiq(int dcpu)
1702 if (CPUMASK(dcpu) & smp_active_mask)
1703 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1706 #if 0 /* single_apic_ipi_passive() not working yet */
1708 * Returns 0 on failure, 1 on success
1711 cpu_send_ipiq_passive(int dcpu)
1714 if (CPUMASK(dcpu) & smp_active_mask) {
1715 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1716 APIC_DELMODE_FIXED);
1723 mptable_bus_info_callback(void *xarg, const void *pos, int type)
1725 struct mptable_bus_info *bus_info = xarg;
1726 const struct BUSENTRY *ent;
1727 struct mptable_bus *bus;
1733 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
1734 if (bus->mb_id == ent->bus_id) {
1735 kprintf("mptable_bus_info_alloc: duplicated bus id "
1736 "(%d)\n", bus->mb_id);
1742 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
1743 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1744 bus->mb_type = MPTABLE_BUS_PCI;
1745 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
1746 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1747 bus->mb_type = MPTABLE_BUS_ISA;
1751 bus->mb_id = ent->bus_id;
1752 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
1758 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
1762 bzero(bus_info, sizeof(*bus_info));
1763 TAILQ_INIT(&bus_info->mbi_list);
1765 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
1767 mptable_bus_info_free(bus_info);
1771 mptable_bus_info_free(struct mptable_bus_info *bus_info)
1773 struct mptable_bus *bus;
1775 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
1776 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
1781 struct mptable_lapic_cbarg1 {
1784 u_int ht_apicid_mask;
1788 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
1790 const struct PROCENTRY *ent;
1791 struct mptable_lapic_cbarg1 *arg = xarg;
1797 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1801 if (ent->apic_id < 32) {
1802 arg->ht_apicid_mask |= 1 << ent->apic_id;
1803 } else if (arg->ht_fixup) {
1804 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
1810 struct mptable_lapic_cbarg2 {
1817 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
1819 const struct PROCENTRY *ent;
1820 struct mptable_lapic_cbarg2 *arg = xarg;
1826 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1827 KKASSERT(!arg->found_bsp);
1831 if (processor_entry(ent, arg->cpu))
1834 if (arg->logical_cpus) {
1835 struct PROCENTRY proc;
1839 * Create fake mptable processor entries
1840 * and feed them to processor_entry() to
1841 * enumerate the logical CPUs.
1843 bzero(&proc, sizeof(proc));
1845 proc.cpu_flags = PROCENTRY_FLAG_EN;
1846 proc.apic_id = ent->apic_id;
1848 for (i = 1; i < arg->logical_cpus; i++) {
1850 processor_entry(&proc, arg->cpu);
1858 mptable_lapic_default(void)
1860 int ap_apicid, bsp_apicid;
1862 mp_naps = 1; /* exclude BSP */
1864 /* Map local apic before the id field is accessed */
1865 lapic_map(DEFAULT_APIC_BASE);
1867 bsp_apicid = APIC_ID(lapic.id);
1868 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
1871 mp_set_cpuids(0, bsp_apicid);
1872 /* one and only AP */
1873 mp_set_cpuids(1, ap_apicid);
1879 * ID_TO_CPU(N), APIC ID to logical CPU table
1880 * CPU_TO_ID(N), logical CPU to APIC ID table
1883 mptable_lapic_enumerate(struct lapic_enumerator *e)
1885 struct mptable_pos mpt;
1886 struct mptable_lapic_cbarg1 arg1;
1887 struct mptable_lapic_cbarg2 arg2;
1889 int error, logical_cpus = 0;
1890 vm_offset_t lapic_addr;
1892 if (mptable_use_default) {
1893 mptable_lapic_default();
1897 error = mptable_map(&mpt);
1899 panic("mptable_lapic_enumerate mptable_map failed\n");
1900 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1904 /* Save local apic address */
1905 lapic_addr = (vm_offset_t)cth->apic_address;
1906 KKASSERT(lapic_addr != 0);
1909 * Find out how many CPUs do we have
1911 bzero(&arg1, sizeof(arg1));
1912 arg1.ht_fixup = 1; /* Apply ht fixup by default */
1914 error = mptable_iterate_entries(cth,
1915 mptable_lapic_pass1_callback, &arg1);
1917 panic("mptable_iterate_entries(lapic_pass1) failed\n");
1918 KKASSERT(arg1.cpu_count != 0);
1920 /* See if we need to fixup HT logical CPUs. */
1921 if (arg1.ht_fixup) {
1922 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
1924 if (logical_cpus != 0)
1925 arg1.cpu_count *= logical_cpus;
1927 mp_naps = arg1.cpu_count;
1929 /* Qualify the numbers again, after possible HT fixup */
1930 if (mp_naps > MAXCPU) {
1931 kprintf("Warning: only using %d of %d available CPUs!\n",
1936 --mp_naps; /* subtract the BSP */
1939 * Link logical CPU id to local apic id
1941 bzero(&arg2, sizeof(arg2));
1943 arg2.logical_cpus = logical_cpus;
1945 error = mptable_iterate_entries(cth,
1946 mptable_lapic_pass2_callback, &arg2);
1948 panic("mptable_iterate_entries(lapic_pass2) failed\n");
1949 KKASSERT(arg2.found_bsp);
1951 /* Map local apic */
1952 lapic_map(lapic_addr);
1954 mptable_unmap(&mpt);
1957 struct mptable_lapic_probe_cbarg {
1963 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
1965 const struct PROCENTRY *ent;
1966 struct mptable_lapic_probe_cbarg *arg = xarg;
1972 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1976 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1977 if (arg->found_bsp) {
1978 kprintf("more than one BSP in base MP table\n");
1987 mptable_lapic_probe(struct lapic_enumerator *e)
1989 struct mptable_pos mpt;
1990 struct mptable_lapic_probe_cbarg arg;
1994 if (mptable_fps_phyaddr == 0)
1997 if (mptable_use_default)
2000 error = mptable_map(&mpt);
2003 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2008 if (cth->apic_address == 0)
2011 bzero(&arg, sizeof(arg));
2012 error = mptable_iterate_entries(cth,
2013 mptable_lapic_probe_callback, &arg);
2015 if (arg.cpu_count == 0) {
2016 kprintf("MP table contains no processor entries\n");
2018 } else if (!arg.found_bsp) {
2019 kprintf("MP table does not contains BSP entry\n");
2024 mptable_unmap(&mpt);
2028 static struct lapic_enumerator mptable_lapic_enumerator = {
2029 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2030 .lapic_probe = mptable_lapic_probe,
2031 .lapic_enumerate = mptable_lapic_enumerate
2035 mptable_lapic_enum_register(void)
2037 lapic_enumerator_register(&mptable_lapic_enumerator);
2039 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2040 mptable_lapic_enum_register, 0);
2043 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
2045 const struct IOAPICENTRY *ent;
2046 struct mptable_ioapic *nioapic, *ioapic;
2052 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
2055 if (ent->apic_address == 0) {
2056 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
2060 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2061 if (ioapic->mio_apic_id == ent->apic_id) {
2062 kprintf("mptable_ioapic_create_list: duplicated "
2063 "apic id %d\n", ioapic->mio_apic_id);
2066 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
2067 kprintf("mptable_ioapic_create_list: overlapped "
2068 "IOAPIC addr 0x%08x", ioapic->mio_addr);
2073 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2074 nioapic->mio_apic_id = ent->apic_id;
2075 nioapic->mio_addr = (uint32_t)ent->apic_address;
2078 * Create IOAPIC list in ascending order of APIC ID
2080 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
2081 mptable_ioapic_list, mio_link) {
2082 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
2083 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
2084 ioapic, nioapic, mio_link);
2089 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
2095 mptable_ioapic_create_list(void)
2097 struct mptable_ioapic *ioapic;
2098 struct mptable_pos mpt;
2101 if (mptable_fps_phyaddr == 0)
2104 if (mptable_use_default) {
2105 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2106 ioapic->mio_idx = 0;
2107 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
2108 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
2110 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
2114 error = mptable_map(&mpt);
2116 panic("mptable_ioapic_create_list: mptable_map failed\n");
2117 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2119 error = mptable_iterate_entries(mpt.mp_cth,
2120 mptable_ioapic_list_callback, NULL);
2122 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
2123 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
2124 kfree(ioapic, M_DEVBUF);
2130 * Assign index number for each IOAPIC
2133 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2134 ioapic->mio_idx = idx;
2138 mptable_unmap(&mpt);
2140 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
2141 mptable_ioapic_create_list, 0);
2144 mptable_pci_int_callback(void *xarg, const void *pos, int type)
2146 const struct mptable_bus_info *bus_info = xarg;
2147 const struct mptable_ioapic *ioapic;
2148 const struct mptable_bus *bus;
2149 struct mptable_pci_int *pci_int;
2150 const struct INTENTRY *ent;
2151 int pci_pin, pci_dev;
2157 if (ent->int_type != 0)
2160 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2161 if (bus->mb_type == MPTABLE_BUS_PCI &&
2162 bus->mb_id == ent->src_bus_id)
2168 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2169 if (ioapic->mio_apic_id == ent->dst_apic_id)
2172 if (ioapic == NULL) {
2173 kprintf("MPTABLE: warning PCI int dst apic id %d "
2174 "does not exist\n", ent->dst_apic_id);
2178 pci_pin = ent->src_bus_irq & 0x3;
2179 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
2181 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2182 if (pci_int->mpci_bus == ent->src_bus_id &&
2183 pci_int->mpci_dev == pci_dev &&
2184 pci_int->mpci_pin == pci_pin) {
2185 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
2186 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
2187 kprintf("MPTABLE: warning duplicated "
2188 "PCI int entry for "
2189 "bus %d, dev %d, pin %d\n",
2195 kprintf("mptable_pci_int_register: "
2196 "conflict PCI int entry for "
2197 "bus %d, dev %d, pin %d, "
2198 "IOAPIC %d.%d -> %d.%d\n",
2202 pci_int->mpci_ioapic_idx,
2203 pci_int->mpci_ioapic_pin,
2211 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
2213 pci_int->mpci_bus = ent->src_bus_id;
2214 pci_int->mpci_dev = pci_dev;
2215 pci_int->mpci_pin = pci_pin;
2216 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
2217 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
2219 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
2225 mptable_pci_int_register(void)
2227 struct mptable_bus_info bus_info;
2228 const struct mptable_bus *bus;
2229 struct mptable_pci_int *pci_int;
2230 struct mptable_pos mpt;
2231 int error, force_pci0, npcibus;
2234 if (mptable_fps_phyaddr == 0)
2237 if (mptable_use_default)
2240 if (TAILQ_EMPTY(&mptable_ioapic_list))
2243 error = mptable_map(&mpt);
2245 panic("mptable_pci_int_register: mptable_map failed\n");
2246 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2250 mptable_bus_info_alloc(cth, &bus_info);
2251 if (TAILQ_EMPTY(&bus_info.mbi_list))
2256 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
2257 if (bus->mb_type == MPTABLE_BUS_PCI)
2261 mptable_bus_info_free(&bus_info);
2263 } else if (npcibus == 1) {
2267 error = mptable_iterate_entries(cth,
2268 mptable_pci_int_callback, &bus_info);
2270 mptable_bus_info_free(&bus_info);
2273 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
2274 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
2275 kfree(pci_int, M_DEVBUF);
2281 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
2282 pci_int->mpci_bus = 0;
2285 mptable_unmap(&mpt);
2287 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2288 mptable_pci_int_register, 0);
2290 struct mptable_ioapic_probe_cbarg {
2291 const struct mptable_bus_info *bus_info;
2295 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
2297 struct mptable_ioapic_probe_cbarg *arg = xarg;
2298 const struct mptable_ioapic *ioapic;
2299 const struct mptable_bus *bus;
2300 const struct INTENTRY *ent;
2306 if (ent->int_type != 0)
2309 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2310 if (bus->mb_type == MPTABLE_BUS_ISA &&
2311 bus->mb_id == ent->src_bus_id)
2317 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2318 if (ioapic->mio_apic_id == ent->dst_apic_id)
2321 if (ioapic == NULL) {
2322 kprintf("MPTABLE: warning ISA int dst apic id %d "
2323 "does not exist\n", ent->dst_apic_id);
2327 /* XXX magic number */
2328 if (ent->src_bus_irq >= 16) {
2329 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
2337 mptable_ioapic_probe(struct ioapic_enumerator *e)
2339 struct mptable_ioapic_probe_cbarg arg;
2340 struct mptable_bus_info bus_info;
2341 struct mptable_pos mpt;
2345 if (mptable_fps_phyaddr == 0)
2348 if (mptable_use_default)
2351 if (TAILQ_EMPTY(&mptable_ioapic_list))
2354 error = mptable_map(&mpt);
2356 panic("mptable_ioapic_probe: mptable_map failed\n");
2357 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2361 mptable_bus_info_alloc(cth, &bus_info);
2363 bzero(&arg, sizeof(arg));
2364 arg.bus_info = &bus_info;
2366 error = mptable_iterate_entries(cth,
2367 mptable_ioapic_probe_callback, &arg);
2369 mptable_bus_info_free(&bus_info);
2370 mptable_unmap(&mpt);
2375 struct mptable_ioapic_int_cbarg {
2376 const struct mptable_bus_info *bus_info;
2381 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
2383 struct mptable_ioapic_int_cbarg *arg = xarg;
2384 const struct mptable_ioapic *ioapic;
2385 const struct mptable_bus *bus;
2386 const struct INTENTRY *ent;
2395 if (ent->int_type != 0)
2398 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2399 if (bus->mb_type == MPTABLE_BUS_ISA &&
2400 bus->mb_id == ent->src_bus_id)
2406 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2407 if (ioapic->mio_apic_id == ent->dst_apic_id)
2410 if (ioapic == NULL) {
2411 kprintf("MPTABLE: warning ISA int dst apic id %d "
2412 "does not exist\n", ent->dst_apic_id);
2416 if (ent->dst_apic_int >= ioapic->mio_npin) {
2417 panic("mptable_ioapic_enumerate: invalid I/O APIC "
2418 "pin %d, should be < %d",
2419 ent->dst_apic_int, ioapic->mio_npin);
2421 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
2423 if (ent->src_bus_irq != gsi) {
2425 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
2426 ent->src_bus_irq, gsi);
2428 ioapic_intsrc(ent->src_bus_irq, gsi,
2429 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2435 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
2437 struct mptable_bus_info bus_info;
2438 struct mptable_ioapic *ioapic;
2439 struct mptable_pos mpt;
2443 KKASSERT(mptable_fps_phyaddr != 0);
2444 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
2446 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2447 const struct mptable_ioapic *prev_ioapic;
2451 addr = ioapic_map(ioapic->mio_addr);
2453 ver = ioapic_read(addr, IOAPIC_VER);
2454 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
2455 >> MAXREDIRSHIFT) + 1;
2457 prev_ioapic = TAILQ_PREV(ioapic,
2458 mptable_ioapic_list, mio_link);
2459 if (prev_ioapic == NULL) {
2460 ioapic->mio_gsi_base = 0;
2462 ioapic->mio_gsi_base =
2463 prev_ioapic->mio_gsi_base +
2464 prev_ioapic->mio_npin;
2466 ioapic_add(addr, ioapic->mio_gsi_base,
2470 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
2471 "apic id %d, idx %d, gsi base %d, npin %d\n",
2473 ioapic->mio_apic_id,
2475 ioapic->mio_gsi_base,
2480 if (mptable_use_default) {
2482 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
2483 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2487 error = mptable_map(&mpt);
2489 panic("mptable_ioapic_probe: mptable_map failed\n");
2490 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2494 mptable_bus_info_alloc(cth, &bus_info);
2496 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
2498 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
2499 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2501 struct mptable_ioapic_int_cbarg arg;
2503 bzero(&arg, sizeof(arg));
2504 arg.bus_info = &bus_info;
2506 error = mptable_iterate_entries(cth,
2507 mptable_ioapic_int_callback, &arg);
2509 panic("mptable_ioapic_int failed\n");
2511 if (arg.ioapic_nint == 0) {
2513 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
2516 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
2517 INTR_POLARITY_HIGH);
2521 mptable_bus_info_free(&bus_info);
2523 mptable_unmap(&mpt);
2526 static struct ioapic_enumerator mptable_ioapic_enumerator = {
2527 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
2528 .ioapic_probe = mptable_ioapic_probe,
2529 .ioapic_enumerate = mptable_ioapic_enumerate
2533 mptable_ioapic_enum_register(void)
2535 ioapic_enumerator_register(&mptable_ioapic_enumerator);
2537 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2538 mptable_ioapic_enum_register, 0);
2541 mptable_pci_int_dump(void)
2543 const struct mptable_pci_int *pci_int;
2545 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2546 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
2549 pci_int->mpci_pin + 'A',
2550 pci_int->mpci_ioapic_idx,
2551 pci_int->mpci_ioapic_pin);
2556 mptable_pci_int_route(int bus, int dev, int pin, int intline)
2558 const struct mptable_pci_int *pci_int;
2562 --pin; /* zero based */
2564 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2565 if (pci_int->mpci_bus == bus &&
2566 pci_int->mpci_dev == dev &&
2567 pci_int->mpci_pin == pin)
2570 if (pci_int != NULL) {
2573 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
2574 pci_int->mpci_ioapic_pin);
2576 irq = ioapic_abi_find_gsi(gsi,
2577 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2583 kprintf("MPTABLE: fixed interrupt routing "
2584 "for %d:%d INT%c\n", bus, dev, pin + 'A');
2587 irq = ioapic_abi_find_irq(intline,
2588 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2591 if (irq >= 0 && bootverbose) {
2592 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
2593 bus, dev, pin + 'A', irq);