x86_64: Split mp_enable() into multiple SYSINITs
[dragonfly.git] / sys / platform / pc64 / apic / ioapic_abi.c
1 /*
2  * Copyright (c) 1991 The Regents of the University of California.
3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
4  * Copyright (c) 2005,2008 The DragonFly Project.  All rights reserved.
5  * All rights reserved.
6  * 
7  * This code is derived from software contributed to The DragonFly Project
8  * by Matthew Dillon <dillon@backplane.com>
9  *
10  * This code is derived from software contributed to Berkeley by
11  * William Jolitz.
12  * 
13  * Redistribution and use in source and binary forms, with or without
14  * modification, are permitted provided that the following conditions
15  * are met:
16  * 
17  * 1. Redistributions of source code must retain the above copyright
18  *    notice, this list of conditions and the following disclaimer.
19  * 2. Redistributions in binary form must reproduce the above copyright
20  *    notice, this list of conditions and the following disclaimer in
21  *    the documentation and/or other materials provided with the
22  *    distribution.
23  * 3. Neither the name of The DragonFly Project nor the names of its
24  *    contributors may be used to endorse or promote products derived
25  *    from this software without specific, prior written permission.
26  * 
27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  * $DragonFly: src/sys/platform/pc64/apic/apic_abi.c,v 1.1 2008/08/29 17:07:12 dillon Exp $
41  */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/machintr.h>
47 #include <sys/interrupt.h>
48 #include <sys/bus.h>
49
50 #include <machine/smp.h>
51 #include <machine/segments.h>
52 #include <machine/md_var.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/globaldata.h>
55
56 #include <sys/thread2.h>
57
58 #include <machine_base/icu/icu.h>
59 #include <machine_base/icu/icu_var.h>
60 #include <machine_base/apic/ioapic.h>
61 #include <machine_base/apic/ioapic_abi.h>
62 #include <machine_base/apic/ioapic_ipl.h>
63
64 #ifdef SMP /* APIC-IO */
65
66 extern inthand_t
67         IDTVEC(ioapic_intr0),
68         IDTVEC(ioapic_intr1),
69         IDTVEC(ioapic_intr2),
70         IDTVEC(ioapic_intr3),
71         IDTVEC(ioapic_intr4),
72         IDTVEC(ioapic_intr5),
73         IDTVEC(ioapic_intr6),
74         IDTVEC(ioapic_intr7),
75         IDTVEC(ioapic_intr8),
76         IDTVEC(ioapic_intr9),
77         IDTVEC(ioapic_intr10),
78         IDTVEC(ioapic_intr11),
79         IDTVEC(ioapic_intr12),
80         IDTVEC(ioapic_intr13),
81         IDTVEC(ioapic_intr14),
82         IDTVEC(ioapic_intr15),
83         IDTVEC(ioapic_intr16),
84         IDTVEC(ioapic_intr17),
85         IDTVEC(ioapic_intr18),
86         IDTVEC(ioapic_intr19),
87         IDTVEC(ioapic_intr20),
88         IDTVEC(ioapic_intr21),
89         IDTVEC(ioapic_intr22),
90         IDTVEC(ioapic_intr23),
91         IDTVEC(ioapic_intr24),
92         IDTVEC(ioapic_intr25),
93         IDTVEC(ioapic_intr26),
94         IDTVEC(ioapic_intr27),
95         IDTVEC(ioapic_intr28),
96         IDTVEC(ioapic_intr29),
97         IDTVEC(ioapic_intr30),
98         IDTVEC(ioapic_intr31),
99         IDTVEC(ioapic_intr32),
100         IDTVEC(ioapic_intr33),
101         IDTVEC(ioapic_intr34),
102         IDTVEC(ioapic_intr35),
103         IDTVEC(ioapic_intr36),
104         IDTVEC(ioapic_intr37),
105         IDTVEC(ioapic_intr38),
106         IDTVEC(ioapic_intr39),
107         IDTVEC(ioapic_intr40),
108         IDTVEC(ioapic_intr41),
109         IDTVEC(ioapic_intr42),
110         IDTVEC(ioapic_intr43),
111         IDTVEC(ioapic_intr44),
112         IDTVEC(ioapic_intr45),
113         IDTVEC(ioapic_intr46),
114         IDTVEC(ioapic_intr47),
115         IDTVEC(ioapic_intr48),
116         IDTVEC(ioapic_intr49),
117         IDTVEC(ioapic_intr50),
118         IDTVEC(ioapic_intr51),
119         IDTVEC(ioapic_intr52),
120         IDTVEC(ioapic_intr53),
121         IDTVEC(ioapic_intr54),
122         IDTVEC(ioapic_intr55),
123         IDTVEC(ioapic_intr56),
124         IDTVEC(ioapic_intr57),
125         IDTVEC(ioapic_intr58),
126         IDTVEC(ioapic_intr59),
127         IDTVEC(ioapic_intr60),
128         IDTVEC(ioapic_intr61),
129         IDTVEC(ioapic_intr62),
130         IDTVEC(ioapic_intr63),
131         IDTVEC(ioapic_intr64),
132         IDTVEC(ioapic_intr65),
133         IDTVEC(ioapic_intr66),
134         IDTVEC(ioapic_intr67),
135         IDTVEC(ioapic_intr68),
136         IDTVEC(ioapic_intr69),
137         IDTVEC(ioapic_intr70),
138         IDTVEC(ioapic_intr71),
139         IDTVEC(ioapic_intr72),
140         IDTVEC(ioapic_intr73),
141         IDTVEC(ioapic_intr74),
142         IDTVEC(ioapic_intr75),
143         IDTVEC(ioapic_intr76),
144         IDTVEC(ioapic_intr77),
145         IDTVEC(ioapic_intr78),
146         IDTVEC(ioapic_intr79),
147         IDTVEC(ioapic_intr80),
148         IDTVEC(ioapic_intr81),
149         IDTVEC(ioapic_intr82),
150         IDTVEC(ioapic_intr83),
151         IDTVEC(ioapic_intr84),
152         IDTVEC(ioapic_intr85),
153         IDTVEC(ioapic_intr86),
154         IDTVEC(ioapic_intr87),
155         IDTVEC(ioapic_intr88),
156         IDTVEC(ioapic_intr89),
157         IDTVEC(ioapic_intr90),
158         IDTVEC(ioapic_intr91),
159         IDTVEC(ioapic_intr92),
160         IDTVEC(ioapic_intr93),
161         IDTVEC(ioapic_intr94),
162         IDTVEC(ioapic_intr95),
163         IDTVEC(ioapic_intr96),
164         IDTVEC(ioapic_intr97),
165         IDTVEC(ioapic_intr98),
166         IDTVEC(ioapic_intr99),
167         IDTVEC(ioapic_intr100),
168         IDTVEC(ioapic_intr101),
169         IDTVEC(ioapic_intr102),
170         IDTVEC(ioapic_intr103),
171         IDTVEC(ioapic_intr104),
172         IDTVEC(ioapic_intr105),
173         IDTVEC(ioapic_intr106),
174         IDTVEC(ioapic_intr107),
175         IDTVEC(ioapic_intr108),
176         IDTVEC(ioapic_intr109),
177         IDTVEC(ioapic_intr110),
178         IDTVEC(ioapic_intr111),
179         IDTVEC(ioapic_intr112),
180         IDTVEC(ioapic_intr113),
181         IDTVEC(ioapic_intr114),
182         IDTVEC(ioapic_intr115),
183         IDTVEC(ioapic_intr116),
184         IDTVEC(ioapic_intr117),
185         IDTVEC(ioapic_intr118),
186         IDTVEC(ioapic_intr119),
187         IDTVEC(ioapic_intr120),
188         IDTVEC(ioapic_intr121),
189         IDTVEC(ioapic_intr122),
190         IDTVEC(ioapic_intr123),
191         IDTVEC(ioapic_intr124),
192         IDTVEC(ioapic_intr125),
193         IDTVEC(ioapic_intr126),
194         IDTVEC(ioapic_intr127),
195         IDTVEC(ioapic_intr128),
196         IDTVEC(ioapic_intr129),
197         IDTVEC(ioapic_intr130),
198         IDTVEC(ioapic_intr131),
199         IDTVEC(ioapic_intr132),
200         IDTVEC(ioapic_intr133),
201         IDTVEC(ioapic_intr134),
202         IDTVEC(ioapic_intr135),
203         IDTVEC(ioapic_intr136),
204         IDTVEC(ioapic_intr137),
205         IDTVEC(ioapic_intr138),
206         IDTVEC(ioapic_intr139),
207         IDTVEC(ioapic_intr140),
208         IDTVEC(ioapic_intr141),
209         IDTVEC(ioapic_intr142),
210         IDTVEC(ioapic_intr143),
211         IDTVEC(ioapic_intr144),
212         IDTVEC(ioapic_intr145),
213         IDTVEC(ioapic_intr146),
214         IDTVEC(ioapic_intr147),
215         IDTVEC(ioapic_intr148),
216         IDTVEC(ioapic_intr149),
217         IDTVEC(ioapic_intr150),
218         IDTVEC(ioapic_intr151),
219         IDTVEC(ioapic_intr152),
220         IDTVEC(ioapic_intr153),
221         IDTVEC(ioapic_intr154),
222         IDTVEC(ioapic_intr155),
223         IDTVEC(ioapic_intr156),
224         IDTVEC(ioapic_intr157),
225         IDTVEC(ioapic_intr158),
226         IDTVEC(ioapic_intr159),
227         IDTVEC(ioapic_intr160),
228         IDTVEC(ioapic_intr161),
229         IDTVEC(ioapic_intr162),
230         IDTVEC(ioapic_intr163),
231         IDTVEC(ioapic_intr164),
232         IDTVEC(ioapic_intr165),
233         IDTVEC(ioapic_intr166),
234         IDTVEC(ioapic_intr167),
235         IDTVEC(ioapic_intr168),
236         IDTVEC(ioapic_intr169),
237         IDTVEC(ioapic_intr170),
238         IDTVEC(ioapic_intr171),
239         IDTVEC(ioapic_intr172),
240         IDTVEC(ioapic_intr173),
241         IDTVEC(ioapic_intr174),
242         IDTVEC(ioapic_intr175),
243         IDTVEC(ioapic_intr176),
244         IDTVEC(ioapic_intr177),
245         IDTVEC(ioapic_intr178),
246         IDTVEC(ioapic_intr179),
247         IDTVEC(ioapic_intr180),
248         IDTVEC(ioapic_intr181),
249         IDTVEC(ioapic_intr182),
250         IDTVEC(ioapic_intr183),
251         IDTVEC(ioapic_intr184),
252         IDTVEC(ioapic_intr185),
253         IDTVEC(ioapic_intr186),
254         IDTVEC(ioapic_intr187),
255         IDTVEC(ioapic_intr188),
256         IDTVEC(ioapic_intr189),
257         IDTVEC(ioapic_intr190),
258         IDTVEC(ioapic_intr191);
259
260 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
261         &IDTVEC(ioapic_intr0),
262         &IDTVEC(ioapic_intr1),
263         &IDTVEC(ioapic_intr2),
264         &IDTVEC(ioapic_intr3),
265         &IDTVEC(ioapic_intr4),
266         &IDTVEC(ioapic_intr5),
267         &IDTVEC(ioapic_intr6),
268         &IDTVEC(ioapic_intr7),
269         &IDTVEC(ioapic_intr8),
270         &IDTVEC(ioapic_intr9),
271         &IDTVEC(ioapic_intr10),
272         &IDTVEC(ioapic_intr11),
273         &IDTVEC(ioapic_intr12),
274         &IDTVEC(ioapic_intr13),
275         &IDTVEC(ioapic_intr14),
276         &IDTVEC(ioapic_intr15),
277         &IDTVEC(ioapic_intr16),
278         &IDTVEC(ioapic_intr17),
279         &IDTVEC(ioapic_intr18),
280         &IDTVEC(ioapic_intr19),
281         &IDTVEC(ioapic_intr20),
282         &IDTVEC(ioapic_intr21),
283         &IDTVEC(ioapic_intr22),
284         &IDTVEC(ioapic_intr23),
285         &IDTVEC(ioapic_intr24),
286         &IDTVEC(ioapic_intr25),
287         &IDTVEC(ioapic_intr26),
288         &IDTVEC(ioapic_intr27),
289         &IDTVEC(ioapic_intr28),
290         &IDTVEC(ioapic_intr29),
291         &IDTVEC(ioapic_intr30),
292         &IDTVEC(ioapic_intr31),
293         &IDTVEC(ioapic_intr32),
294         &IDTVEC(ioapic_intr33),
295         &IDTVEC(ioapic_intr34),
296         &IDTVEC(ioapic_intr35),
297         &IDTVEC(ioapic_intr36),
298         &IDTVEC(ioapic_intr37),
299         &IDTVEC(ioapic_intr38),
300         &IDTVEC(ioapic_intr39),
301         &IDTVEC(ioapic_intr40),
302         &IDTVEC(ioapic_intr41),
303         &IDTVEC(ioapic_intr42),
304         &IDTVEC(ioapic_intr43),
305         &IDTVEC(ioapic_intr44),
306         &IDTVEC(ioapic_intr45),
307         &IDTVEC(ioapic_intr46),
308         &IDTVEC(ioapic_intr47),
309         &IDTVEC(ioapic_intr48),
310         &IDTVEC(ioapic_intr49),
311         &IDTVEC(ioapic_intr50),
312         &IDTVEC(ioapic_intr51),
313         &IDTVEC(ioapic_intr52),
314         &IDTVEC(ioapic_intr53),
315         &IDTVEC(ioapic_intr54),
316         &IDTVEC(ioapic_intr55),
317         &IDTVEC(ioapic_intr56),
318         &IDTVEC(ioapic_intr57),
319         &IDTVEC(ioapic_intr58),
320         &IDTVEC(ioapic_intr59),
321         &IDTVEC(ioapic_intr60),
322         &IDTVEC(ioapic_intr61),
323         &IDTVEC(ioapic_intr62),
324         &IDTVEC(ioapic_intr63),
325         &IDTVEC(ioapic_intr64),
326         &IDTVEC(ioapic_intr65),
327         &IDTVEC(ioapic_intr66),
328         &IDTVEC(ioapic_intr67),
329         &IDTVEC(ioapic_intr68),
330         &IDTVEC(ioapic_intr69),
331         &IDTVEC(ioapic_intr70),
332         &IDTVEC(ioapic_intr71),
333         &IDTVEC(ioapic_intr72),
334         &IDTVEC(ioapic_intr73),
335         &IDTVEC(ioapic_intr74),
336         &IDTVEC(ioapic_intr75),
337         &IDTVEC(ioapic_intr76),
338         &IDTVEC(ioapic_intr77),
339         &IDTVEC(ioapic_intr78),
340         &IDTVEC(ioapic_intr79),
341         &IDTVEC(ioapic_intr80),
342         &IDTVEC(ioapic_intr81),
343         &IDTVEC(ioapic_intr82),
344         &IDTVEC(ioapic_intr83),
345         &IDTVEC(ioapic_intr84),
346         &IDTVEC(ioapic_intr85),
347         &IDTVEC(ioapic_intr86),
348         &IDTVEC(ioapic_intr87),
349         &IDTVEC(ioapic_intr88),
350         &IDTVEC(ioapic_intr89),
351         &IDTVEC(ioapic_intr90),
352         &IDTVEC(ioapic_intr91),
353         &IDTVEC(ioapic_intr92),
354         &IDTVEC(ioapic_intr93),
355         &IDTVEC(ioapic_intr94),
356         &IDTVEC(ioapic_intr95),
357         &IDTVEC(ioapic_intr96),
358         &IDTVEC(ioapic_intr97),
359         &IDTVEC(ioapic_intr98),
360         &IDTVEC(ioapic_intr99),
361         &IDTVEC(ioapic_intr100),
362         &IDTVEC(ioapic_intr101),
363         &IDTVEC(ioapic_intr102),
364         &IDTVEC(ioapic_intr103),
365         &IDTVEC(ioapic_intr104),
366         &IDTVEC(ioapic_intr105),
367         &IDTVEC(ioapic_intr106),
368         &IDTVEC(ioapic_intr107),
369         &IDTVEC(ioapic_intr108),
370         &IDTVEC(ioapic_intr109),
371         &IDTVEC(ioapic_intr110),
372         &IDTVEC(ioapic_intr111),
373         &IDTVEC(ioapic_intr112),
374         &IDTVEC(ioapic_intr113),
375         &IDTVEC(ioapic_intr114),
376         &IDTVEC(ioapic_intr115),
377         &IDTVEC(ioapic_intr116),
378         &IDTVEC(ioapic_intr117),
379         &IDTVEC(ioapic_intr118),
380         &IDTVEC(ioapic_intr119),
381         &IDTVEC(ioapic_intr120),
382         &IDTVEC(ioapic_intr121),
383         &IDTVEC(ioapic_intr122),
384         &IDTVEC(ioapic_intr123),
385         &IDTVEC(ioapic_intr124),
386         &IDTVEC(ioapic_intr125),
387         &IDTVEC(ioapic_intr126),
388         &IDTVEC(ioapic_intr127),
389         &IDTVEC(ioapic_intr128),
390         &IDTVEC(ioapic_intr129),
391         &IDTVEC(ioapic_intr130),
392         &IDTVEC(ioapic_intr131),
393         &IDTVEC(ioapic_intr132),
394         &IDTVEC(ioapic_intr133),
395         &IDTVEC(ioapic_intr134),
396         &IDTVEC(ioapic_intr135),
397         &IDTVEC(ioapic_intr136),
398         &IDTVEC(ioapic_intr137),
399         &IDTVEC(ioapic_intr138),
400         &IDTVEC(ioapic_intr139),
401         &IDTVEC(ioapic_intr140),
402         &IDTVEC(ioapic_intr141),
403         &IDTVEC(ioapic_intr142),
404         &IDTVEC(ioapic_intr143),
405         &IDTVEC(ioapic_intr144),
406         &IDTVEC(ioapic_intr145),
407         &IDTVEC(ioapic_intr146),
408         &IDTVEC(ioapic_intr147),
409         &IDTVEC(ioapic_intr148),
410         &IDTVEC(ioapic_intr149),
411         &IDTVEC(ioapic_intr150),
412         &IDTVEC(ioapic_intr151),
413         &IDTVEC(ioapic_intr152),
414         &IDTVEC(ioapic_intr153),
415         &IDTVEC(ioapic_intr154),
416         &IDTVEC(ioapic_intr155),
417         &IDTVEC(ioapic_intr156),
418         &IDTVEC(ioapic_intr157),
419         &IDTVEC(ioapic_intr158),
420         &IDTVEC(ioapic_intr159),
421         &IDTVEC(ioapic_intr160),
422         &IDTVEC(ioapic_intr161),
423         &IDTVEC(ioapic_intr162),
424         &IDTVEC(ioapic_intr163),
425         &IDTVEC(ioapic_intr164),
426         &IDTVEC(ioapic_intr165),
427         &IDTVEC(ioapic_intr166),
428         &IDTVEC(ioapic_intr167),
429         &IDTVEC(ioapic_intr168),
430         &IDTVEC(ioapic_intr169),
431         &IDTVEC(ioapic_intr170),
432         &IDTVEC(ioapic_intr171),
433         &IDTVEC(ioapic_intr172),
434         &IDTVEC(ioapic_intr173),
435         &IDTVEC(ioapic_intr174),
436         &IDTVEC(ioapic_intr175),
437         &IDTVEC(ioapic_intr176),
438         &IDTVEC(ioapic_intr177),
439         &IDTVEC(ioapic_intr178),
440         &IDTVEC(ioapic_intr179),
441         &IDTVEC(ioapic_intr180),
442         &IDTVEC(ioapic_intr181),
443         &IDTVEC(ioapic_intr182),
444         &IDTVEC(ioapic_intr183),
445         &IDTVEC(ioapic_intr184),
446         &IDTVEC(ioapic_intr185),
447         &IDTVEC(ioapic_intr186),
448         &IDTVEC(ioapic_intr187),
449         &IDTVEC(ioapic_intr188),
450         &IDTVEC(ioapic_intr189),
451         &IDTVEC(ioapic_intr190),
452         &IDTVEC(ioapic_intr191)
453 };
454
455 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
456
457 static struct ioapic_irqmap {
458         int                     im_type;        /* IOAPIC_IMT_ */
459         enum intr_trigger       im_trig;
460         enum intr_polarity      im_pola;
461         int                     im_gsi;
462         uint32_t                im_flags;       /* IOAPIC_IMF_ */
463 } ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
464
465 #define IOAPIC_IMT_UNUSED       0
466 #define IOAPIC_IMT_RESERVED     1
467 #define IOAPIC_IMT_LINE         2
468 #define IOAPIC_IMT_SYSCALL      3
469
470 #define IOAPIC_IMF_CONF         0x1
471
472 extern void     IOAPIC_INTREN(int);
473 extern void     IOAPIC_INTRDIS(int);
474
475 extern int      imcr_present;
476
477 static int      ioapic_setvar(int, const void *);
478 static int      ioapic_getvar(int, void *);
479 static int      ioapic_vectorctl(int, int, int);
480 static void     ioapic_finalize(void);
481 static void     ioapic_cleanup(void);
482 static void     ioapic_setdefault(void);
483 static void     ioapic_stabilize(void);
484 static void     ioapic_initmap(void);
485 static void     ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
486 static void     ioapic_abi_intren(int);
487 static void     ioapic_abi_intrdis(int);
488
489 struct machintr_abi MachIntrABI_IOAPIC = {
490         MACHINTR_IOAPIC,
491         .intrdis        = ioapic_abi_intrdis,
492         .intren         = ioapic_abi_intren,
493         .vectorctl      = ioapic_vectorctl,
494         .setvar         = ioapic_setvar,
495         .getvar         = ioapic_getvar,
496         .finalize       = ioapic_finalize,
497         .cleanup        = ioapic_cleanup,
498         .setdefault     = ioapic_setdefault,
499         .stabilize      = ioapic_stabilize,
500         .initmap        = ioapic_initmap,
501         .intr_config    = ioapic_intr_config
502 };
503
504 static int      ioapic_abi_extint_irq = -1;
505
506 struct apic_intmapinfo  int_to_apicintpin[APIC_INTMAPSIZE];
507
508 static void
509 ioapic_abi_intren(int irq)
510 {
511         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
512                 kprintf("ioapic_abi_intren invalid irq %d\n", irq);
513                 return;
514         }
515         IOAPIC_INTREN(irq);
516 }
517
518 static void
519 ioapic_abi_intrdis(int irq)
520 {
521         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
522                 kprintf("ioapic_abi_intrdis invalid irq %d\n", irq);
523                 return;
524         }
525         IOAPIC_INTRDIS(irq);
526 }
527
528 static int
529 ioapic_setvar(int varid, const void *buf)
530 {
531         return ENOENT;
532 }
533
534 static int
535 ioapic_getvar(int varid, void *buf)
536 {
537         return ENOENT;
538 }
539
540 static void
541 ioapic_finalize(void)
542 {
543         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
544         KKASSERT(ioapic_enable);
545
546         /*
547          * If an IMCR is present, program bit 0 to disconnect the 8259
548          * from the BSP.
549          */
550         if (imcr_present) {
551                 outb(0x22, 0x70);       /* select IMCR */
552                 outb(0x23, 0x01);       /* disconnect 8259 */
553         }
554 }
555
556 /*
557  * This routine is called after physical interrupts are enabled but before
558  * the critical section is released.  We need to clean out any interrupts
559  * that had already been posted to the cpu.
560  */
561 static void
562 ioapic_cleanup(void)
563 {
564         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
565 }
566
567 /* Must never be called */
568 static void
569 ioapic_stabilize(void)
570 {
571         panic("ioapic_stabilize is called\n");
572 }
573
574 static int
575 ioapic_vectorctl(int op, int intr, int flags)
576 {
577         int error;
578         int vector;
579         int select;
580         uint32_t value;
581         register_t ef;
582
583         if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
584             intr == IOAPIC_HWI_SYSCALL)
585                 return EINVAL;
586
587         ef = read_rflags();
588         cpu_disable_intr();
589         error = 0;
590
591         switch(op) {
592         case MACHINTR_VECTOR_SETUP:
593                 vector = IDT_OFFSET + intr;
594                 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
595
596                 /*
597                  * Now reprogram the vector in the IO APIC.  In order to avoid
598                  * losing an EOI for a level interrupt, which is vector based,
599                  * make sure that the IO APIC is programmed for edge-triggering
600                  * first, then reprogrammed with the new vector.  This should
601                  * clear the IRR bit.
602                  */
603                 if (int_to_apicintpin[intr].ioapic >= 0) {
604                         imen_lock();
605
606                         select = int_to_apicintpin[intr].redirindex;
607                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
608                                             select);
609                         value |= IOART_INTMSET;
610
611                         ioapic_write(int_to_apicintpin[intr].apic_address,
612                                      select, (value & ~APIC_TRIGMOD_MASK));
613                         ioapic_write(int_to_apicintpin[intr].apic_address,
614                                      select, (value & ~IOART_INTVEC) | vector);
615
616                         imen_unlock();
617                 }
618
619                 machintr_intren(intr);
620                 break;
621
622         case MACHINTR_VECTOR_TEARDOWN:
623                 /*
624                  * Teardown an interrupt vector.  The vector should already be
625                  * installed in the cpu's IDT, but make sure.
626                  */
627                 machintr_intrdis(intr);
628
629                 vector = IDT_OFFSET + intr;
630                 setidt(vector, ioapic_intr[intr], SDT_SYSIGT, SEL_KPL, 0);
631
632                 /*
633                  * In order to avoid losing an EOI for a level interrupt, which
634                  * is vector based, make sure that the IO APIC is programmed for
635                  * edge-triggering first, then reprogrammed with the new vector.
636                  * This should clear the IRR bit.
637                  */
638                 if (int_to_apicintpin[intr].ioapic >= 0) {
639                         imen_lock();
640
641                         select = int_to_apicintpin[intr].redirindex;
642                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
643                                             select);
644
645                         ioapic_write(int_to_apicintpin[intr].apic_address,
646                                      select, (value & ~APIC_TRIGMOD_MASK));
647                         ioapic_write(int_to_apicintpin[intr].apic_address,
648                                      select, (value & ~IOART_INTVEC) | vector);
649
650                         imen_unlock();
651                 }
652                 break;
653
654         default:
655                 error = EOPNOTSUPP;
656                 break;
657         }
658
659         write_rflags(ef);
660         return error;
661 }
662
663 static void
664 ioapic_setdefault(void)
665 {
666         int intr;
667
668         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
669                 if (intr == IOAPIC_HWI_SYSCALL)
670                         continue;
671                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYSIGT,
672                        SEL_KPL, 0);
673         }
674 }
675
676 static void
677 ioapic_initmap(void)
678 {
679         int i;
680
681         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
682                 ioapic_irqmaps[i].im_gsi = -1;
683         ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
684 }
685
686 void
687 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
688     enum intr_polarity pola)
689 {
690         struct apic_intmapinfo *info;
691         struct ioapic_irqmap *map;
692         void *ioaddr;
693         int pin;
694
695         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
696         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
697
698         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
699         map = &ioapic_irqmaps[irq];
700
701         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
702         map->im_type = IOAPIC_IMT_LINE;
703
704         map->im_gsi = gsi;
705         map->im_trig = trig;
706         map->im_pola = pola;
707
708         if (bootverbose) {
709                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
710                         irq, map->im_gsi,
711                         intr_str_trigger(map->im_trig),
712                         intr_str_polarity(map->im_pola));
713         }
714
715         pin = ioapic_gsi_pin(map->im_gsi);
716         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
717
718         info = &int_to_apicintpin[irq];
719
720         imen_lock();
721
722         info->ioapic = 0; /* XXX unused */
723         info->int_pin = pin;
724         info->apic_address = ioaddr;
725         info->redirindex = IOAPIC_REDTBL + (2 * pin);
726         info->flags = IOAPIC_IM_FLAG_MASKED;
727         if (map->im_trig == INTR_TRIGGER_LEVEL)
728                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
729
730         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
731             map->im_trig, map->im_pola);
732
733         imen_unlock();
734 }
735
736 void
737 ioapic_abi_fixup_irqmap(void)
738 {
739         int i;
740
741         for (i = 0; i < 16; ++i) {
742                 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
743
744                 if (map->im_type == IOAPIC_IMT_UNUSED) {
745                         map->im_type = IOAPIC_IMT_RESERVED;
746                         if (bootverbose)
747                                 kprintf("IOAPIC: irq %d reserved\n", i);
748                 }
749         }
750 }
751
752 int
753 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
754 {
755         int irq;
756
757         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
758         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
759
760         for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
761                 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
762
763                 if (map->im_gsi == gsi) {
764                         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
765
766                         if (map->im_flags & IOAPIC_IMF_CONF) {
767                                 if (map->im_trig != trig ||
768                                     map->im_pola != pola)
769                                         return -1;
770                         }
771                         return irq;
772                 }
773         }
774         return -1;
775 }
776
777 int
778 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
779 {
780         const struct ioapic_irqmap *map;
781
782         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
783         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
784
785         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
786                 return -1;
787         map = &ioapic_irqmaps[irq];
788
789         if (map->im_type != IOAPIC_IMT_LINE)
790                 return -1;
791
792         if (map->im_flags & IOAPIC_IMF_CONF) {
793                 if (map->im_trig != trig || map->im_pola != pola)
794                         return -1;
795         }
796         return irq;
797 }
798
799 static void
800 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
801 {
802         struct apic_intmapinfo *info;
803         struct ioapic_irqmap *map;
804         void *ioaddr;
805         int pin;
806
807         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
808         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
809
810         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
811         map = &ioapic_irqmaps[irq];
812
813         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
814
815 #ifdef notyet
816         if (map->im_flags & IOAPIC_IMF_CONF) {
817                 if (trig != map->im_trig) {
818                         panic("ioapic_intr_config: trig %s -> %s\n",
819                               intr_str_trigger(map->im_trig),
820                               intr_str_trigger(trig));
821                 }
822                 if (pola != map->im_pola) {
823                         panic("ioapic_intr_config: pola %s -> %s\n",
824                               intr_str_polarity(map->im_pola),
825                               intr_str_polarity(pola));
826                 }
827                 return;
828         }
829 #endif
830         map->im_flags |= IOAPIC_IMF_CONF;
831
832         if (trig == map->im_trig && pola == map->im_pola)
833                 return;
834
835         if (bootverbose) {
836                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
837                         irq, map->im_gsi,
838                         intr_str_trigger(map->im_trig),
839                         intr_str_polarity(map->im_pola),
840                         intr_str_trigger(trig),
841                         intr_str_polarity(pola));
842         }
843         map->im_trig = trig;
844         map->im_pola = pola;
845
846         pin = ioapic_gsi_pin(map->im_gsi);
847         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
848
849         info = &int_to_apicintpin[irq];
850
851         imen_lock();
852
853         info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
854         if (map->im_trig == INTR_TRIGGER_LEVEL)
855                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
856
857         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
858             map->im_trig, map->im_pola);
859
860         imen_unlock();
861 }
862
863 int
864 ioapic_abi_extint_irqmap(int irq)
865 {
866         struct apic_intmapinfo *info;
867         struct ioapic_irqmap *map;
868         void *ioaddr;
869         int pin, error, vec;
870
871         vec = IDT_OFFSET + irq;
872
873         if (ioapic_abi_extint_irq == irq)
874                 return 0;
875         else if (ioapic_abi_extint_irq >= 0)
876                 return EEXIST;
877
878         error = icu_ioapic_extint(irq, vec);
879         if (error)
880                 return error;
881
882         map = &ioapic_irqmaps[irq];
883
884         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
885                  map->im_type == IOAPIC_IMT_LINE);
886         if (map->im_type == IOAPIC_IMT_LINE) {
887                 if (map->im_flags & IOAPIC_IMF_CONF)
888                         return EEXIST;
889         }
890         ioapic_abi_extint_irq = irq;
891
892         map->im_type = IOAPIC_IMT_LINE;
893         map->im_trig = INTR_TRIGGER_EDGE;
894         map->im_pola = INTR_POLARITY_HIGH;
895         map->im_flags = IOAPIC_IMF_CONF;
896
897         map->im_gsi = ioapic_extpin_gsi();
898         KKASSERT(map->im_gsi >= 0);
899
900         if (bootverbose) {
901                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
902                         irq, map->im_gsi,
903                         intr_str_trigger(map->im_trig),
904                         intr_str_polarity(map->im_pola));
905         }
906
907         pin = ioapic_gsi_pin(map->im_gsi);
908         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
909
910         info = &int_to_apicintpin[irq];
911
912         imen_lock();
913
914         info->ioapic = 0; /* XXX unused */
915         info->int_pin = pin;
916         info->apic_address = ioaddr;
917         info->redirindex = IOAPIC_REDTBL + (2 * pin);
918         info->flags = IOAPIC_IM_FLAG_MASKED;
919
920         ioapic_extpin_setup(ioaddr, pin, vec);
921
922         imen_unlock();
923
924         return 0;
925 }
926
927 #endif  /* SMP */