sys/net/i4b/layer1/isic/i4b_drn_ngo.c

   1 /*
   2  * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_drn_ngo.c - Dr. Neuhaus Niccy GO@ and SAGEM Cybermod
  28  *      --------------------------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/isic/i4b_drn_ngo.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
  31  * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_drn_ngo.c,v 1.5 2006/12/22 23:44:56 swildner Exp $
  32  *
  33  *      last edit-date: [Wed Jan 24 09:07:44 2001]
  34  *
  35  *---------------------------------------------------------------------------*/
  36
  37 #include "use_isic.h"
  38 #include "opt_i4b.h"
  39
  40 #if (NISIC > 0) && defined(DRN_NGO)
  41
  42 #include <sys/param.h>
  43 #include <sys/systm.h>
  44 #include <sys/socket.h>
  45 #include <net/if.h>
  46
  47 #include <net/i4b/include/machine/i4b_ioctl.h>
  48
  49 #include "i4b_isic.h"
  50 #include "i4b_hscx.h"
  51
  52 /*---------------------------------------------------------------------------*
  53  *      Niccy GO@ definitions
  54  *
  55  *      the card uses 2 i/o addressranges each using 2 bytes
  56  *
  57  *      addressrange 0:
  58  *              offset 0 - ISAC dataregister
  59  *              offset 1 - HSCX dataregister
  60  *      addressrange 1:
  61  *              offset 0 - ISAC addressregister
  62  *              offset 1 - HSCX addressregister
  63  *
  64  *      to access an ISAC/HSCX register, you have to write the register
  65  *      number into the ISAC or HSCX addressregister and then read/write
  66  *      data for the ISAC/HSCX register into/from the corresponding
  67  *      dataregister.
  68  *
  69  *      Thanks to Klaus Muehle of Dr. Neuhaus Telekommunikation for giving
  70  *      out this information!
  71  *
  72  *---------------------------------------------------------------------------*/
  73 #define NICCY_PORT_MIN  0x200
  74 #define NICCY_PORT_MAX  0x3e0
  75
  76 #define HSCX_ABIT       0x1000          /* flag, HSCX A is meant */
  77 #define HSCX_BBIT       0x2000          /* flag, HSCX B is meant */
  78
  79 #define HSCX_BOFF       0x40
  80
  81 #define ADDR_OFF        2               /* address register range offset */
  82
  83 #define ISAC_DATA       0
  84 #define HSCX_DATA       1
  85
  86 #define ISAC_ADDR       0
  87 #define HSCX_ADDR       1
  88
  89 /*---------------------------------------------------------------------------*
  90  *      Dr. Neuhaus Niccy GO@ read fifo routine
  91  *---------------------------------------------------------------------------*/
  92 static void
  93 drnngo_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
  94 {
  95         bus_space_tag_t tdata, tadr;
  96         bus_space_handle_t hdata, hadr;
  97
  98         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
  99         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 100         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 101         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 102
 103         switch(what)
 104         {
 105                 case ISIC_WHAT_ISAC:
 106                         bus_space_write_1     (tadr ,hadr, ISAC_ADDR,0x0);
 107                         bus_space_read_multi_1(tdata,hdata,ISAC_DATA,buf,size);
 108                         break;
 109                 case ISIC_WHAT_HSCXA:
 110                         bus_space_write_1     (tadr ,hadr ,HSCX_ADDR,0x0);
 111                         bus_space_read_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 112                         break;
 113                 case ISIC_WHAT_HSCXB:
 114                         bus_space_write_1     (tadr ,hadr ,HSCX_ADDR,HSCX_BOFF);
 115                         bus_space_read_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 116                         break;
 117         }
 118 }
 119
 120 /*---------------------------------------------------------------------------*
 121  *      Dr. Neuhaus Niccy GO@ write fifo routine
 122  *---------------------------------------------------------------------------*/
 123 static void
 124 drnngo_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
 125 {
 126         bus_space_tag_t tdata, tadr;
 127         bus_space_handle_t hdata, hadr;
 128
 129         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 130         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 131         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 132         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 133
 134         switch(what)
 135         {
 136                 case ISIC_WHAT_ISAC:
 137                         bus_space_write_1      (tadr ,hadr, ISAC_ADDR,0x0);
 138                         bus_space_write_multi_1(tdata,hdata,ISAC_DATA,buf,size);
 139                         break;
 140                 case ISIC_WHAT_HSCXA:
 141                         bus_space_write_1      (tadr ,hadr ,HSCX_ADDR,0x0);
 142                         bus_space_write_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 143                         break;
 144                 case ISIC_WHAT_HSCXB:
 145                         bus_space_write_1      (tadr ,hadr ,HSCX_ADDR,HSCX_BOFF);
 146                         bus_space_write_multi_1(tdata,hdata,HSCX_DATA,buf,size);
 147                         break;
 148         }
 149 }
 150
 151 /*---------------------------------------------------------------------------*
 152  *      Dr. Neuhaus Niccy GO@ write register routine
 153  *---------------------------------------------------------------------------*/
 154 static void
 155 drnngo_write_reg(struct l1_softc *sc, int what, bus_size_t reg, u_int8_t data)
 156 {
 157         bus_space_tag_t tdata, tadr;
 158         bus_space_handle_t hdata, hadr;
 159
 160         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 161         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 162         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 163         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 164
 165         switch(what)
 166         {
 167                 case ISIC_WHAT_ISAC:
 168                         bus_space_write_1(tadr ,hadr, ISAC_ADDR,reg);
 169                         bus_space_write_1(tdata,hdata,ISAC_DATA,data);
 170                         break;
 171                 case ISIC_WHAT_HSCXA:
 172                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg);
 173                         bus_space_write_1(tdata,hdata,HSCX_DATA,data);
 174                         break;
 175                 case ISIC_WHAT_HSCXB:
 176                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg+HSCX_BOFF);
 177                         bus_space_write_1(tdata,hdata,HSCX_DATA,data);
 178                         break;
 179         }
 180 }
 181
 182 /*---------------------------------------------------------------------------*
 183  *      Dr. Neuhaus Niccy GO@ read register routine
 184  *---------------------------------------------------------------------------*/
 185 static u_int8_t
 186 drnngo_read_reg(struct l1_softc *sc, int what, bus_size_t reg)
 187 {
 188         bus_space_tag_t tdata, tadr;
 189         bus_space_handle_t hdata, hadr;
 190
 191         tdata = rman_get_bustag(sc->sc_resources.io_base[0]);
 192         hdata = rman_get_bushandle(sc->sc_resources.io_base[0]);
 193         tadr = rman_get_bustag(sc->sc_resources.io_base[1]);
 194         hadr = rman_get_bushandle(sc->sc_resources.io_base[1]);
 195
 196         switch(what)
 197         {
 198                 case ISIC_WHAT_ISAC:
 199                         bus_space_write_1(tadr ,hadr, ISAC_ADDR,reg);
 200                         return bus_space_read_1(tdata,hdata,ISAC_DATA);
 201                 case ISIC_WHAT_HSCXA:
 202                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg);
 203                         return bus_space_read_1(tdata,hdata,HSCX_DATA);
 204                 case ISIC_WHAT_HSCXB:
 205                         bus_space_write_1(tadr ,hadr ,HSCX_ADDR,reg+HSCX_BOFF);
 206                         return bus_space_read_1(tdata,hdata,HSCX_DATA);
 207                 default:
 208                         return 0;
 209         }
 210 }
 211
 212 /*---------------------------------------------------------------------------*
 213  *      probe for ISA PnP cards
 214  *---------------------------------------------------------------------------*/
 215 int
 216 isic_attach_drnngo(device_t dev)
 217 {
 218         int unit = device_get_unit(dev);
 219         struct l1_softc *sc = &l1_sc[unit];
 220
 221         sc->sc_resources.io_rid[1] = 1;
 222
 223         /*
 224          * this card needs a second io_base,
 225          * free resources if we don't get it
 226          */
 227
 228         if(!(sc->sc_resources.io_base[1] =
 229                         bus_alloc_resource(dev, SYS_RES_IOPORT,
 230                                         &sc->sc_resources.io_rid[1],
 231                                         0UL, ~0UL, 1, RF_ACTIVE)))
 232         {
 233                 kprintf("isic%d: Failed to get second io base.\n", unit);
 234                 isic_detach_common(dev);
 235                 return ENXIO;
 236         }
 237
 238         /* setup ISAC access routines */
 239
 240         sc->clearirq = NULL;
 241         sc->readreg = drnngo_read_reg;
 242         sc->writereg = drnngo_write_reg;
 243
 244         sc->readfifo = drnngo_read_fifo;
 245         sc->writefifo = drnngo_write_fifo;
 246
 247         /* setup card type */
 248
 249         sc->sc_cardtyp = CARD_TYPEP_DRNNGO;
 250
 251         /* setup IOM bus type */
 252
 253         sc->sc_bustyp = BUS_TYPE_IOM2;
 254
 255         sc->sc_ipac = 0;
 256         sc->sc_bfifolen = HSCX_FIFO_LEN;
 257
 258         return (0);
 259 }
 260
 261 #endif /* (NISIC > 0) && defined(DRN_NGO) */