sys/net/i4b/layer1/itjc/i4b_itjc_isac.c

   1 /*
   2  * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  *---------------------------------------------------------------------------
  26  *
  27  *      i4b_itjc_isac.c - i4b NetJet-S ISAC handler
  28  *      --------------------------------------------
  29  *
  30  * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_isac.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
  31  *
  32  *      last edit-date: [Wed Jan 10 17:15:54 2001]
  33  *
  34  *---------------------------------------------------------------------------*/
  35
  36 #include "use_itjc.h"
  37
  38 #if (NITJC > 0)
  39
  40 #include "opt_i4b.h"
  41
  42 #include <sys/param.h>
  43 #include <sys/kernel.h>
  44 #include <sys/systm.h>
  45 #include <sys/mbuf.h>
  46 #include <sys/socket.h>
  47
  48 #include <machine/stdarg.h>
  49 #include <machine/clock.h>
  50
  51 #include <net/if.h>
  52
  53 #include <net/i4b/include/machine/i4b_debug.h>
  54 #include <net/i4b/include/machine/i4b_ioctl.h>
  55 #include <net/i4b/include/machine/i4b_trace.h>
  56
  57 #include "../i4b_l1.h"
  58
  59 #include "../isic/i4b_isic.h"
  60 #include "../isic/i4b_isac.h"
  61
  62 #include "i4b_itjc_ext.h"
  63
  64 #include "../../include/i4b_global.h"
  65 #include "../../include/i4b_mbuf.h"
  66
  67 static u_char itjc_isac_exir_hdlr(struct l1_softc *sc, u_char exir);
  68 static void itjc_isac_ind_hdlr(struct l1_softc *sc, int ind);
  69
  70 /*---------------------------------------------------------------------------*
  71  *      ISAC interrupt service routine
  72  *---------------------------------------------------------------------------*/
  73 void
  74 itjc_isac_irq(struct l1_softc *sc, int ista)
  75 {
  76         u_char c = 0;
  77         NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
  78
  79         if(ista & ISAC_ISTA_EXI)        /* extended interrupt */
  80         {
  81                 c |= itjc_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
  82         }
  83
  84         if(ista & ISAC_ISTA_RME)        /* receive message end */
  85         {
  86                 int rest;
  87                 u_char rsta;
  88
  89                 /* get rx status register */
  90
  91                 rsta = ISAC_READ(I_RSTA);
  92
  93                 if((rsta & ISAC_RSTA_MASK) != 0x20)
  94                 {
  95                         int error = 0;
  96
  97                         if(!(rsta & ISAC_RSTA_CRC))     /* CRC error */
  98                         {
  99                                 error++;
 100                                 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
 101                         }
 102
 103                         if(rsta & ISAC_RSTA_RDO)        /* ReceiveDataOverflow */
 104                         {
 105                                 error++;
 106                                 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
 107                         }
 108
 109                         if(rsta & ISAC_RSTA_RAB)        /* ReceiveABorted */
 110                         {
 111                                 error++;
 112                                 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
 113                         }
 114
 115                         if(error == 0)
 116                                 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
 117
 118                         i4b_Dfreembuf(sc->sc_ibuf);
 119
 120                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 121
 122                         sc->sc_ibuf = NULL;
 123                         sc->sc_ib = NULL;
 124                         sc->sc_ilen = 0;
 125
 126                         ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
 127                         ISACCMDRWRDELAY();
 128
 129                         return;
 130                 }
 131
 132                 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
 133
 134                 if(rest == 0)
 135                         rest = ISAC_FIFO_LEN;
 136
 137                 if(sc->sc_ibuf == NULL)
 138                 {
 139                         if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
 140                                 sc->sc_ib = sc->sc_ibuf->m_data;
 141                         else
 142                                 panic("itjc_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
 143                         sc->sc_ilen = 0;
 144                 }
 145
 146                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
 147                 {
 148                         ISAC_RDFIFO(sc->sc_ib, rest);
 149                         sc->sc_ilen += rest;
 150
 151                         sc->sc_ibuf->m_pkthdr.len =
 152                                 sc->sc_ibuf->m_len = sc->sc_ilen;
 153
 154                         if(sc->sc_trace & TRACE_D_RX)
 155                         {
 156                                 i4b_trace_hdr_t hdr;
 157                                 hdr.unit = L0ITJCUNIT(sc->sc_unit);
 158                                 hdr.type = TRC_CH_D;
 159                                 hdr.dir = FROM_NT;
 160                                 hdr.count = ++sc->sc_trace_dcount;
 161                                 MICROTIME(hdr.time);
 162                                 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
 163                         }
 164
 165                         c |= ISAC_CMDR_RMC;
 166
 167                         if(sc->sc_enabled &&
 168                            (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
 169                         {
 170                                 i4b_l1_ph_data_ind(L0ITJCUNIT(sc->sc_unit), sc->sc_ibuf);
 171                         }
 172                         else
 173                         {
 174                                 i4b_Dfreembuf(sc->sc_ibuf);
 175                         }
 176                 }
 177                 else
 178                 {
 179                         NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
 180                         i4b_Dfreembuf(sc->sc_ibuf);
 181                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 182                 }
 183
 184                 sc->sc_ibuf = NULL;
 185                 sc->sc_ib = NULL;
 186                 sc->sc_ilen = 0;
 187         }
 188
 189         if(ista & ISAC_ISTA_RPF)        /* receive fifo full */
 190         {
 191                 if(sc->sc_ibuf == NULL)
 192                 {
 193                         if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
 194                                 sc->sc_ib= sc->sc_ibuf->m_data;
 195                         else
 196                                 panic("itjc_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
 197                         sc->sc_ilen = 0;
 198                 }
 199
 200                 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
 201                 {
 202                         ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
 203                         sc->sc_ilen += ISAC_FIFO_LEN;
 204                         sc->sc_ib += ISAC_FIFO_LEN;
 205                         c |= ISAC_CMDR_RMC;
 206                 }
 207                 else
 208                 {
 209                         NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
 210                         i4b_Dfreembuf(sc->sc_ibuf);
 211                         sc->sc_ibuf = NULL;
 212                         sc->sc_ib = NULL;
 213                         sc->sc_ilen = 0;
 214                         c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 215                 }
 216         }
 217
 218         if(ista & ISAC_ISTA_XPR)        /* transmit fifo empty (XPR bit set) */
 219         {
 220                 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
 221                 {
 222                         sc->sc_freeflag = sc->sc_freeflag2;
 223                         sc->sc_obuf = sc->sc_obuf2;
 224                         sc->sc_op = sc->sc_obuf->m_data;
 225                         sc->sc_ol = sc->sc_obuf->m_len;
 226                         sc->sc_obuf2 = NULL;
 227                 }
 228
 229                 if(sc->sc_obuf)
 230                 {
 231                         ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
 232
 233                         if(sc->sc_ol > ISAC_FIFO_LEN)   /* length > 32 ? */
 234                         {
 235                                 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
 236                                 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
 237                                 c |= ISAC_CMDR_XTF;         /* set XTF bit */
 238                         }
 239                         else
 240                         {
 241                                 if(sc->sc_freeflag)
 242                                 {
 243                                         i4b_Dfreembuf(sc->sc_obuf);
 244                                         sc->sc_freeflag = 0;
 245                                 }
 246                                 sc->sc_obuf = NULL;
 247                                 sc->sc_op = NULL;
 248                                 sc->sc_ol = 0;
 249
 250                                 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
 251                         }
 252                 }
 253                 else
 254                 {
 255                         sc->sc_state &= ~ISAC_TX_ACTIVE;
 256                 }
 257         }
 258
 259         if(ista & ISAC_ISTA_CISQ)       /* channel status change CISQ */
 260         {
 261                 u_char ci;
 262
 263                 /* get command/indication rx register*/
 264
 265                 ci = ISAC_READ(I_CIRR);
 266
 267                 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
 268
 269                 if(ci & ISAC_CIRR_SQC)
 270                         ISAC_READ(I_SQRR);
 271
 272                 /* C/I code change IRQ (flag already cleared by CIRR read) */
 273
 274                 if(ci & ISAC_CIRR_CIC0)
 275                         itjc_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
 276         }
 277
 278         if(c)
 279         {
 280                 ISAC_WRITE(I_CMDR, c);
 281                 ISACCMDRWRDELAY();
 282         }
 283 }
 284
 285 /*---------------------------------------------------------------------------*
 286  *      ISAC L1 Extended IRQ handler
 287  *---------------------------------------------------------------------------*/
 288 static u_char
 289 itjc_isac_exir_hdlr(struct l1_softc *sc, u_char exir)
 290 {
 291         u_char c = 0;
 292
 293         if(exir & ISAC_EXIR_XMR)
 294         {
 295                 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
 296
 297                 c |= ISAC_CMDR_XRES;
 298         }
 299
 300         if(exir & ISAC_EXIR_XDU)
 301         {
 302                 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
 303
 304                 c |= ISAC_CMDR_XRES;
 305         }
 306
 307         if(exir & ISAC_EXIR_PCE)
 308         {
 309                 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
 310         }
 311
 312         if(exir & ISAC_EXIR_RFO)
 313         {
 314                 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
 315
 316                 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
 317         }
 318
 319         if(exir & ISAC_EXIR_SOV)
 320         {
 321                 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
 322         }
 323
 324         if(exir & ISAC_EXIR_MOS)
 325         {
 326                 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
 327         }
 328
 329         if(exir & ISAC_EXIR_SAW)
 330         {
 331                 /* cannot happen, STCR:TSF is set to 0 */
 332
 333                 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
 334         }
 335
 336         if(exir & ISAC_EXIR_WOV)
 337         {
 338                 /* cannot happen, STCR:TSF is set to 0 */
 339
 340                 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
 341         }
 342
 343         return(c);
 344 }
 345
 346 /*---------------------------------------------------------------------------*
 347  *      ISAC L1 Indication handler
 348  *---------------------------------------------------------------------------*/
 349 static void
 350 itjc_isac_ind_hdlr(struct l1_softc *sc, int ind)
 351 {
 352         int event;
 353
 354         switch(ind)
 355         {
 356                 case ISAC_CIRR_IAI8:
 357                         NDBGL1(L1_I_CICO, "rx AI8 in state %s", itjc_printstate(sc));
 358                         itjc_isac_l1_cmd(sc, CMD_AR8);
 359                         event = EV_INFO48;
 360                         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 361                         break;
 362
 363                 case ISAC_CIRR_IAI10:
 364                         NDBGL1(L1_I_CICO, "rx AI10 in state %s", itjc_printstate(sc));
 365                         itjc_isac_l1_cmd(sc, CMD_AR10);
 366                         event = EV_INFO410;
 367                         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
 368                         break;
 369
 370                 case ISAC_CIRR_IRSY:
 371                         NDBGL1(L1_I_CICO, "rx RSY in state %s", itjc_printstate(sc));
 372                         event = EV_RSY;
 373                         break;
 374
 375                 case ISAC_CIRR_IPU:
 376                         NDBGL1(L1_I_CICO, "rx PU in state %s", itjc_printstate(sc));
 377                         event = EV_PU;
 378                         break;
 379
 380                 case ISAC_CIRR_IDR:
 381                         NDBGL1(L1_I_CICO, "rx DR in state %s", itjc_printstate(sc));
 382                         itjc_isac_l1_cmd(sc, CMD_DIU);
 383                         event = EV_DR;
 384                         break;
 385
 386                 case ISAC_CIRR_IDID:
 387                         NDBGL1(L1_I_CICO, "rx DID in state %s", itjc_printstate(sc));
 388                         event = EV_INFO0;
 389                         i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
 390                         break;
 391
 392                 case ISAC_CIRR_IDIS:
 393                         NDBGL1(L1_I_CICO, "rx DIS in state %s", itjc_printstate(sc));
 394                         event = EV_DIS;
 395                         break;
 396
 397                 case ISAC_CIRR_IEI:
 398                         NDBGL1(L1_I_CICO, "rx EI in state %s", itjc_printstate(sc));
 399                         itjc_isac_l1_cmd(sc, CMD_DIU);
 400                         event = EV_EI;
 401                         break;
 402
 403                 case ISAC_CIRR_IARD:
 404                         NDBGL1(L1_I_CICO, "rx ARD in state %s", itjc_printstate(sc));
 405                         event = EV_INFO2;
 406                         break;
 407
 408                 case ISAC_CIRR_ITI:
 409                         NDBGL1(L1_I_CICO, "rx TI in state %s", itjc_printstate(sc));
 410                         event = EV_INFO0;
 411                         break;
 412
 413                 case ISAC_CIRR_IATI:
 414                         NDBGL1(L1_I_CICO, "rx ATI in state %s", itjc_printstate(sc));
 415                         event = EV_INFO0;
 416                         break;
 417
 418                 case ISAC_CIRR_ISD:
 419                         NDBGL1(L1_I_CICO, "rx SD in state %s", itjc_printstate(sc));
 420                         event = EV_INFO0;
 421                         break;
 422
 423                 default:
 424                         NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, itjc_printstate(sc));
 425                         event = EV_INFO0;
 426                         break;
 427         }
 428         itjc_next_state(sc, event);
 429 }
 430
 431 /*---------------------------------------------------------------------------*
 432  *      execute a layer 1 command
 433  *---------------------------------------------------------------------------*/
 434 void
 435 itjc_isac_l1_cmd(struct l1_softc *sc, int command)
 436 {
 437         u_char cmd;
 438
 439         if(command < 0 || command > CMD_ILL)
 440         {
 441                 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, itjc_printstate(sc));
 442                 return;
 443         }
 444
 445         cmd = ISAC_CIX0_LOW;
 446
 447         switch(command)
 448         {
 449                 case CMD_TIM:
 450                         NDBGL1(L1_I_CICO, "tx TIM in state %s", itjc_printstate(sc));
 451                         cmd |= (ISAC_CIXR_CTIM << 2);
 452                         break;
 453
 454                 case CMD_RS:
 455                         NDBGL1(L1_I_CICO, "tx RS in state %s", itjc_printstate(sc));
 456                         cmd |= (ISAC_CIXR_CRS << 2);
 457                         break;
 458
 459                 case CMD_AR8:
 460                         NDBGL1(L1_I_CICO, "tx AR8 in state %s", itjc_printstate(sc));
 461                         cmd |= (ISAC_CIXR_CAR8 << 2);
 462                         break;
 463
 464                 case CMD_AR10:
 465                         NDBGL1(L1_I_CICO, "tx AR10 in state %s", itjc_printstate(sc));
 466                         cmd |= (ISAC_CIXR_CAR10 << 2);
 467                         break;
 468
 469                 case CMD_DIU:
 470                         NDBGL1(L1_I_CICO, "tx DIU in state %s", itjc_printstate(sc));
 471                         cmd |= (ISAC_CIXR_CDIU << 2);
 472                         break;
 473         }
 474         ISAC_WRITE(I_CIXR, cmd);
 475 }
 476
 477 /*---------------------------------------------------------------------------*
 478  *      L1 ISAC initialization
 479  *---------------------------------------------------------------------------*/
 480 int
 481 itjc_isac_init(struct l1_softc *sc)
 482 {
 483         ISAC_IMASK = 0xff;              /* disable all irqs */
 484
 485         ISAC_WRITE(I_MASK, ISAC_IMASK);
 486
 487         NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
 488
 489         /* ADF2: Select mode IOM-2 */
 490         ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
 491
 492         /* SPCR: serial port control register:
 493          *      SPU - software power up = 0
 494          *      SPM - timing mode 0
 495          *      TLP - test loop = 0
 496          *      C1C, C2C - B1 + C1 and B2 + IC2 monitoring
 497          */
 498         ISAC_WRITE(I_SPCR, 0x00);
 499
 500         /* SQXR: S/Q channel xmit register:
 501          *      IDC  - IOM direction = 0 (master)
 502          *      CFS  - Config Select = 0 (clock always active)
 503          *      CI1E - C/I channel 1 IRQ enable = 0
 504                  *      SQIE - S/Q IRQ enable = 0
 505          *      SQX1-4 - Fa bits = 1
 506          */
 507         ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
 508
 509         /* ADF1: additional feature reg 1:
 510          *      WTC - watchdog = 0
 511          *      TEM - test mode = 0
 512          *      PFS - pre-filter = 0
 513          *      IOF - IOM i/f off = 0
 514          *      ITF - interframe fill = idle
 515          */
 516         ISAC_WRITE(I_ADF1, 0x00);
 517
 518         /* STCR: sync transfer control reg:
 519          *      TSF - terminal secific functions = 0
 520          *      TBA - TIC bus address = 7
 521          *      STx/SCx = 0
 522          */
 523         ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
 524
 525         /* MODE: Mode Register:
 526          *      MDSx - transparent mode 2
 527          *      TMD  - timer mode = external
 528          *      RAC  - Receiver enabled
 529          *      DIMx - digital i/f mode
 530          */
 531         ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
 532
 533         /* enabled interrupts:
 534          * ===================
 535          * RME  - receive message end
 536          * RPF  - receive pool full
 537          * XPR  - transmit pool ready
 538          * CISQ - CI or S/Q channel change
 539          * EXI  - extended interrupt
 540          */
 541
 542         ISAC_IMASK = ISAC_MASK_RSC |    /* auto mode only       */
 543                      ISAC_MASK_TIN |    /* timer irq            */
 544                      ISAC_MASK_SIN;     /* sync xfer irq        */
 545
 546         ISAC_WRITE(I_MASK, ISAC_IMASK);
 547
 548         return(0);
 549 }
 550
 551 #endif /* NITJC > 0 */