2 * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
4 * Copyright (c) 2000, 2001 Hellmuth Michaelis. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 *---------------------------------------------------------------------------
29 * i4b_iwic - isdn4bsd Winbond W6692 driver
30 * ----------------------------------------
32 * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic_bchan.c,v 1.7.2.1 2001/08/10 14:08:40 obrien Exp $
33 * $DragonFly: src/sys/net/i4b/layer1/iwic/i4b_iwic_bchan.c,v 1.6 2005/06/14 21:19:19 joerg Exp $
35 * last edit-date: [Tue Jan 16 13:21:24 2001]
37 *---------------------------------------------------------------------------*/
43 #if (NIWIC > 0) && (NPCI > 0)
45 #include <sys/param.h>
46 #include <sys/systm.h>
48 #include <sys/socket.h>
49 #include <sys/thread2.h>
53 #include <net/i4b/include/machine/i4b_debug.h>
54 #include <net/i4b/include/machine/i4b_ioctl.h>
55 #include <net/i4b/include/machine/i4b_trace.h>
57 #include "../i4b_l1.h"
60 #include "i4b_w6692.h"
62 #include "../../include/i4b_global.h"
63 #include "../../include/i4b_mbuf.h"
65 static void iwic_bchan_init(struct iwic_softc *sc, int chan_no, int activate);
67 /*---------------------------------------------------------------------------*
68 * B-channel interrupt handler
69 *---------------------------------------------------------------------------*/
71 iwic_bchan_xirq(struct iwic_softc *sc, int chan_no)
74 struct iwic_bchan *chan;
78 chan = &sc->sc_bchan[chan_no];
80 irq_stat = IWIC_READ(sc, chan->offset + B_EXIR);
82 NDBGL1(L1_H_IRQ, "irq_stat = 0x%x", irq_stat);
84 if((irq_stat & (B_EXIR_RMR | B_EXIR_RME | B_EXIR_RDOV | B_EXIR_XFR | B_EXIR_XDUN)) == 0)
86 NDBGL1(L1_H_XFRERR, "spurious IRQ!");
90 if (irq_stat & B_EXIR_RDOV)
92 NDBGL1(L1_H_XFRERR, "iwic%d: EXIR B-channel Receive Data Overflow", sc->sc_unit);
95 if (irq_stat & B_EXIR_XDUN)
97 NDBGL1(L1_H_XFRERR, "iwic%d: EXIR B-channel Transmit Data Underrun", sc->sc_unit);
98 cmd |= (B_CMDR_XRST); /*XXX must retransmit frame ! */
101 /* RX message end interrupt */
103 if(irq_stat & B_EXIR_RME)
107 NDBGL1(L1_H_IRQ, "B_EXIR_RME");
109 error = (IWIC_READ(sc,chan->offset+B_STAR) &
110 (B_STAR_RDOV | B_STAR_CRCE | B_STAR_RMB));
114 if(error & B_STAR_RDOV)
115 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel Receive Data Overflow", sc->sc_unit);
116 if(error & B_STAR_CRCE)
117 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel CRC Error", sc->sc_unit);
118 if(error & B_STAR_RMB)
119 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel Receive Message Aborted", sc->sc_unit);
122 /* all error conditions checked, now decide and take action */
127 fifo_data_len = ((IWIC_READ(sc,chan->offset+B_RBCL)) &
128 ((IWIC_BCHAN_FIFO_LEN)-1));
130 if(fifo_data_len == 0)
131 fifo_data_len = IWIC_BCHAN_FIFO_LEN;
134 if(chan->in_mbuf == NULL)
136 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
137 panic("L1 iwic_bchan_irq: RME, cannot allocate mbuf!\n");
138 chan->in_cbptr = chan->in_mbuf->m_data;
142 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
144 /* read data from fifo */
146 NDBGL1(L1_H_IRQ, "B_EXIR_RME, rd fifo, len = %d", fifo_data_len);
148 IWIC_RDBFIFO(sc, chan, chan->in_cbptr, fifo_data_len);
150 cmd |= (B_CMDR_RACK | B_CMDR_RACT);
151 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
154 chan->in_len += fifo_data_len;
155 chan->rxcount += fifo_data_len;
157 /* setup mbuf data length */
159 chan->in_mbuf->m_len = chan->in_len;
160 chan->in_mbuf->m_pkthdr.len = chan->in_len;
162 if(sc->sc_trace & TRACE_B_RX)
165 hdr.unit = L0IWICUNIT(sc->sc_unit);
166 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
168 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
170 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
173 (*chan->iwic_drvr_linktab->bch_rx_data_ready)(chan->iwic_drvr_linktab->unit);
177 /* mark buffer ptr as unused */
179 chan->in_mbuf = NULL;
180 chan->in_cbptr = NULL;
185 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RME, in_len=%d, fifolen=%d", chan->in_len, fifo_data_len);
186 chan->in_cbptr = chan->in_mbuf->m_data;
188 cmd |= (B_CMDR_RRST | B_CMDR_RACK);
193 if (chan->in_mbuf != NULL)
195 i4b_Bfreembuf(chan->in_mbuf);
196 chan->in_mbuf = NULL;
197 chan->in_cbptr = NULL;
200 cmd |= (B_CMDR_RRST | B_CMDR_RACK);
204 /* RX fifo full interrupt */
206 if(irq_stat & B_EXIR_RMR)
208 NDBGL1(L1_H_IRQ, "B_EXIR_RMR");
210 if(chan->in_mbuf == NULL)
212 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
213 panic("L1 iwic_bchan_irq: RMR, cannot allocate mbuf!\n");
214 chan->in_cbptr = chan->in_mbuf->m_data;
218 chan->rxcount += IWIC_BCHAN_FIFO_LEN;
220 if((chan->in_len + IWIC_BCHAN_FIFO_LEN) <= BCH_MAX_DATALEN)
222 /* read data from fifo */
224 NDBGL1(L1_H_IRQ, "B_EXIR_RMR, rd fifo, len = max (64)");
226 IWIC_RDBFIFO(sc, chan, chan->in_cbptr, IWIC_BCHAN_FIFO_LEN);
228 chan->in_cbptr += IWIC_BCHAN_FIFO_LEN;
229 chan->in_len += IWIC_BCHAN_FIFO_LEN;
233 if(chan->bprot == BPROT_NONE)
235 /* setup mbuf data length */
237 chan->in_mbuf->m_len = chan->in_len;
238 chan->in_mbuf->m_pkthdr.len = chan->in_len;
240 if(sc->sc_trace & TRACE_B_RX)
243 hdr.unit = L0IWICUNIT(sc->sc_unit);
244 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
246 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
248 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
251 /* silence detection */
253 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
256 if(!(IF_QFULL(&chan->rx_queue)))
258 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
262 i4b_Bfreembuf(chan->in_mbuf);
264 /* signal upper driver that data is available */
266 (*chan->iwic_drvr_linktab->bch_rx_data_ready)(chan->iwic_drvr_linktab->unit);
268 /* alloc new buffer */
270 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
271 panic("L1 iwic_bchan_irq: RMR, cannot allocate new mbuf!\n");
273 /* setup new data ptr */
275 chan->in_cbptr = chan->in_mbuf->m_data;
277 /* read data from fifo */
279 NDBGL1(L1_H_IRQ, "B_EXIR_RMR, rd fifo1, len = max (64)");
281 IWIC_RDBFIFO(sc, chan, chan->in_cbptr, IWIC_BCHAN_FIFO_LEN);
283 chan->in_cbptr += IWIC_BCHAN_FIFO_LEN;
284 chan->in_len = IWIC_BCHAN_FIFO_LEN;
286 chan->rxcount += IWIC_BCHAN_FIFO_LEN;
290 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
291 chan->in_cbptr = chan->in_mbuf->m_data;
293 cmd |= (B_CMDR_RRST | B_CMDR_RACK);
297 /* command to release fifo space */
304 if (irq_stat & B_EXIR_XFR)
306 /* transmit fifo empty, new data can be written to fifo */
312 NDBGL1(L1_H_IRQ, "B_EXIR_XFR");
314 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
316 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
318 if(chan->out_mbuf_head == NULL)
320 chan->state &= ~ST_TX_ACTIVE;
321 (*chan->iwic_drvr_linktab->bch_tx_queue_empty)(chan->iwic_drvr_linktab->unit);
325 chan->state |= ST_TX_ACTIVE;
326 chan->out_mbuf_cur = chan->out_mbuf_head;
327 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
328 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
330 if(sc->sc_trace & TRACE_B_TX)
333 hdr.unit = L0IWICUNIT(sc->sc_unit);
334 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
336 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
338 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
341 if(chan->bprot == BPROT_NONE)
343 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
355 while(chan->out_mbuf_cur && len != IWIC_BCHAN_FIFO_LEN)
357 nextlen = min(chan->out_mbuf_cur_len, IWIC_BCHAN_FIFO_LEN - len);
359 NDBGL1(L1_H_IRQ, "B_EXIR_XFR, wr fifo, len = %d", nextlen);
361 IWIC_WRBFIFO(sc, chan, chan->out_mbuf_cur_ptr, nextlen);
366 chan->txcount += nextlen;
368 chan->out_mbuf_cur_ptr += nextlen;
369 chan->out_mbuf_cur_len -= nextlen;
371 if(chan->out_mbuf_cur_len == 0)
373 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
375 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
376 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
378 if(sc->sc_trace & TRACE_B_TX)
381 hdr.unit = L0IWICUNIT(sc->sc_unit);
382 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
384 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
386 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
391 if (chan->bprot != BPROT_NONE)
393 i4b_Bfreembuf(chan->out_mbuf_head);
394 chan->out_mbuf_head = NULL;
402 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
406 /*---------------------------------------------------------------------------*
407 * initialize one B channels rx/tx data structures
408 *---------------------------------------------------------------------------*/
410 iwic_bchannel_setup(int unit, int chan_no, int bprot, int activate)
412 struct iwic_softc *sc = &iwic_sc[unit];
413 struct iwic_bchan *chan = &sc->sc_bchan[chan_no];
417 NDBGL1(L1_BCHAN, "unit %d, chan %d, bprot %d, activate %d", unit, chan_no, bprot, activate);
421 chan->bprot = bprot; /* B channel protocol */
422 chan->state = ST_IDLE; /* B channel state */
427 iwic_bchan_init(sc, chan_no, activate);
432 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
434 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
436 chan->rxcount = 0; /* reset rx counter */
438 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
440 chan->in_mbuf = NULL; /* reset mbuf ptr */
441 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
442 chan->in_len = 0; /* reset mbuf data len */
444 /* transmitter part */
446 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
448 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
450 chan->txcount = 0; /* reset tx counter */
452 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
454 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
455 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
456 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
457 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
462 iwic_bchan_init(sc, chan_no, activate);
468 /*---------------------------------------------------------------------------*
469 * initalize / deinitialize B-channel hardware
470 *---------------------------------------------------------------------------*/
472 iwic_bchan_init(struct iwic_softc *sc, int chan_no, int activate)
474 struct iwic_bchan *bchan = &sc->sc_bchan[chan_no];
476 NDBGL1(L1_BCHAN, "chan %d, activate %d", chan_no, activate);
480 if(bchan->bprot == BPROT_NONE)
482 /* Extended transparent mode */
483 IWIC_WRITE(sc, bchan->offset + B_MODE, B_MODE_MMS);
487 /* Transparent mode */
488 IWIC_WRITE(sc, bchan->offset + B_MODE, 0);
489 /* disable address comparation */
490 IWIC_WRITE (sc, bchan->offset+B_ADM1, 0xff);
491 IWIC_WRITE (sc, bchan->offset+B_ADM2, 0xff);
494 /* reset & start receiver */
495 IWIC_WRITE(sc, bchan->offset + B_CMDR, B_CMDR_RRST|B_CMDR_RACT);
498 IWIC_WRITE(sc, bchan->offset + B_EXIM, 0);
503 IWIC_WRITE(sc, bchan->offset + B_EXIM, 0xff);
506 IWIC_WRITE(sc, bchan->offset + B_MODE, 0);
508 /* Bring interface down */
509 IWIC_WRITE(sc, bchan->offset + B_CMDR, B_CMDR_RRST | B_CMDR_XRST);
511 /* Flush pending interrupts */
512 IWIC_READ(sc, bchan->offset + B_EXIR);
516 /*---------------------------------------------------------------------------*
517 * start transmission on a b channel
518 *---------------------------------------------------------------------------*/
520 iwic_bchannel_start(int unit, int chan_no)
522 struct iwic_softc *sc = &iwic_sc[unit];
523 struct iwic_bchan *chan = &sc->sc_bchan[chan_no];
531 NDBGL1(L1_BCHAN, "unit %d, channel %d", unit, chan_no);
533 if(chan->state & ST_TX_ACTIVE) /* already running ? */
536 return; /* yes, leave */
539 /* get next mbuf from queue */
541 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
543 if(chan->out_mbuf_head == NULL) /* queue empty ? */
546 return; /* yes, exit */
549 /* init current mbuf values */
551 chan->out_mbuf_cur = chan->out_mbuf_head;
552 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
553 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
555 /* activity indicator for timeout handling */
557 if(chan->bprot == BPROT_NONE)
559 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
567 chan->state |= ST_TX_ACTIVE; /* we start transmitting */
569 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
572 hdr.unit = L0IWICUNIT(unit);
573 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
575 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
577 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
580 len = 0; /* # of chars put into tx fifo this time */
583 * fill the tx fifo with data from the current mbuf. if
584 * current mbuf holds less data than fifo length, try to
585 * get the next mbuf from (a possible) mbuf chain. if there is
586 * not enough data in a single mbuf or in a chain, then this
587 * is the last mbuf and we tell the chip that it has to send
588 * CRC and closing flag
591 while((len < IWIC_BCHAN_FIFO_LEN) && chan->out_mbuf_cur)
594 * put as much data into the fifo as is
595 * available from the current mbuf
598 if((len + chan->out_mbuf_cur_len) >= IWIC_BCHAN_FIFO_LEN)
599 next_len = IWIC_BCHAN_FIFO_LEN - len;
601 next_len = chan->out_mbuf_cur_len;
603 /* write what we have from current mbuf to fifo */
605 IWIC_WRBFIFO(sc, chan, chan->out_mbuf_cur_ptr, next_len);
607 len += next_len; /* update # of bytes written */
608 chan->txcount += next_len; /* statistics */
609 chan->out_mbuf_cur_ptr += next_len; /* data ptr */
610 chan->out_mbuf_cur_len -= next_len; /* data len */
613 * in case the current mbuf (of a possible chain) data
614 * has been put into the fifo, check if there is a next
615 * mbuf in the chain. If there is one, get ptr to it
616 * and update the data ptr and the length
619 if((chan->out_mbuf_cur_len <= 0) &&
620 ((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL))
622 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
623 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
625 if(sc->sc_trace & TRACE_B_TX)
628 hdr.unit = L0IWICUNIT(unit);
629 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
631 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
633 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
639 * if there is either still data in the current mbuf and/or
640 * there is a successor on the chain available issue just
641 * a XTF (transmit) command to the chip. if there is no more
642 * data available from the current mbuf (-chain), issue
643 * an XTF and an XME (message end) command which will then
644 * send the CRC and the closing HDLC flag sequence
647 if(chan->out_mbuf_cur && (chan->out_mbuf_cur_len > 0))
650 * more data available, send current fifo out.
651 * next xfer to tx fifo is done in the
659 /* end of mbuf chain */
661 if(chan->bprot == BPROT_NONE)
664 cmd |= (B_CMDR_XMS | B_CMDR_XME);
666 i4b_Bfreembuf(chan->out_mbuf_head); /* free mbuf chain */
668 chan->out_mbuf_head = NULL;
669 chan->out_mbuf_cur = NULL;
670 chan->out_mbuf_cur_ptr = NULL;
671 chan->out_mbuf_cur_len = 0;
674 /* call timeout handling routine */
676 if(activity == ACT_RX || activity == ACT_TX)
677 (*chan->iwic_drvr_linktab->bch_activity)(chan->iwic_drvr_linktab->unit, activity);
682 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
688 /*---------------------------------------------------------------------------*
689 * return B-channel statistics
690 *---------------------------------------------------------------------------*/
692 iwic_bchannel_stat(int unit, int chan_no, bchan_statistics_t *bsp)
694 struct iwic_softc *sc = iwic_find_sc(unit);
695 struct iwic_bchan *bchan = &sc->sc_bchan[chan_no];
699 bsp->outbytes = bchan->txcount;
700 bsp->inbytes = bchan->rxcount;
708 /*---------------------------------------------------------------------------*
709 * initialize our local linktab
710 *---------------------------------------------------------------------------*/
712 iwic_init_linktab(struct iwic_softc *sc)
714 struct iwic_bchan *chan;
717 /* make sure the hardware driver is known to layer 4 */
718 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
719 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
723 chan = &sc->sc_bchan[IWIC_BCH_A];
724 lt = &chan->iwic_isdn_linktab;
726 lt->unit = sc->sc_unit;
727 lt->channel = IWIC_BCH_A;
728 lt->bch_config = iwic_bchannel_setup;
729 lt->bch_tx_start = iwic_bchannel_start;
730 lt->bch_stat = iwic_bchannel_stat;
731 lt->tx_queue = &chan->tx_queue;
733 /* used by non-HDLC data transfers, i.e. telephony drivers */
734 lt->rx_queue = &chan->rx_queue;
736 /* used by HDLC data transfers, i.e. ipr and isp drivers */
737 lt->rx_mbuf = &chan->in_mbuf;
741 chan = &sc->sc_bchan[IWIC_BCH_B];
742 lt = &chan->iwic_isdn_linktab;
744 lt->unit = sc->sc_unit;
745 lt->channel = IWIC_BCH_B;
746 lt->bch_config = iwic_bchannel_setup;
747 lt->bch_tx_start = iwic_bchannel_start;
748 lt->bch_stat = iwic_bchannel_stat;
749 lt->tx_queue = &chan->tx_queue;
751 /* used by non-HDLC data transfers, i.e. telephony drivers */
752 lt->rx_queue = &chan->rx_queue;
754 /* used by HDLC data transfers, i.e. ipr and isp drivers */
755 lt->rx_mbuf = &chan->in_mbuf;
758 #endif /* NIWIC > 0 */