2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/i386/i386/Attic/mp_machdep.c,v 1.24 2004/03/01 06:33:16 dillon Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
40 #include <vm/vm_param.h>
42 #include <vm/vm_kern.h>
43 #include <vm/vm_extern.h>
45 #include <vm/vm_map.h>
51 #include <machine/smp.h>
52 #include <machine/apicreg.h>
53 #include <machine/atomic.h>
54 #include <machine/cpufunc.h>
55 #include <machine/mpapic.h>
56 #include <machine/psl.h>
57 #include <machine/segments.h>
58 #include <machine/smptests.h> /** TEST_DEFAULT_CONFIG, TEST_TEST1 */
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
64 #include <machine/md_var.h> /* setidt() */
65 #include <i386/isa/icu.h> /* IPIs */
66 #include <i386/isa/intr_machdep.h> /* IPIs */
69 #if defined(TEST_DEFAULT_CONFIG)
70 #define MPFPS_MPFB1 TEST_DEFAULT_CONFIG
72 #define MPFPS_MPFB1 mpfps->mpfb1
73 #endif /* TEST_DEFAULT_CONFIG */
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
80 #define BIOS_BASE (0xe8000)
81 #define BIOS_SIZE (0x18000)
83 #define BIOS_BASE (0xf0000)
84 #define BIOS_SIZE (0x10000)
86 #define BIOS_COUNT (BIOS_SIZE/4)
88 #define CMOS_REG (0x70)
89 #define CMOS_DATA (0x71)
90 #define BIOS_RESET (0x0f)
91 #define BIOS_WARM (0x0a)
93 #define PROCENTRY_FLAG_EN 0x01
94 #define PROCENTRY_FLAG_BP 0x02
95 #define IOAPICENTRY_FLAG_EN 0x01
98 /* MP Floating Pointer Structure */
99 typedef struct MPFPS {
112 /* MP Configuration Table Header */
113 typedef struct MPCTH {
115 u_short base_table_length;
119 u_char product_id[12];
120 void *oem_table_pointer;
121 u_short oem_table_size;
124 u_short extended_table_length;
125 u_char extended_table_checksum;
130 typedef struct PROCENTRY {
135 u_long cpu_signature;
136 u_long feature_flags;
141 typedef struct BUSENTRY {
147 typedef struct IOAPICENTRY {
153 } *io_apic_entry_ptr;
155 typedef struct INTENTRY {
165 /* descriptions of MP basetable entries */
166 typedef struct BASETABLE_ENTRY {
173 * this code MUST be enabled here and in mpboot.s.
174 * it follows the very early stages of AP boot by placing values in CMOS ram.
175 * it NORMALLY will never be needed and thus the primitive method for enabling.
178 #if defined(CHECK_POINTS) && !defined(PC98)
179 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
180 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
182 #define CHECK_INIT(D); \
183 CHECK_WRITE(0x34, (D)); \
184 CHECK_WRITE(0x35, (D)); \
185 CHECK_WRITE(0x36, (D)); \
186 CHECK_WRITE(0x37, (D)); \
187 CHECK_WRITE(0x38, (D)); \
188 CHECK_WRITE(0x39, (D));
190 #define CHECK_PRINT(S); \
191 printf("%s: %d, %d, %d, %d, %d, %d\n", \
200 #else /* CHECK_POINTS */
202 #define CHECK_INIT(D)
203 #define CHECK_PRINT(S)
205 #endif /* CHECK_POINTS */
208 * Values to send to the POST hardware.
210 #define MP_BOOTADDRESS_POST 0x10
211 #define MP_PROBE_POST 0x11
212 #define MPTABLE_PASS1_POST 0x12
214 #define MP_START_POST 0x13
215 #define MP_ENABLE_POST 0x14
216 #define MPTABLE_PASS2_POST 0x15
218 #define START_ALL_APS_POST 0x16
219 #define INSTALL_AP_TRAMP_POST 0x17
220 #define START_AP_POST 0x18
222 #define MP_ANNOUNCE_POST 0x19
224 static int need_hyperthreading_fixup;
225 static u_int logical_cpus;
226 u_int logical_cpus_mask;
228 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229 int current_postcode;
231 /** XXX FIXME: what system files declare these??? */
232 extern struct region_descriptor r_gdt, r_idt;
234 int bsp_apic_ready = 0; /* flags useability of BSP apic */
235 int mp_naps; /* # of Applications processors */
236 int mp_nbusses; /* # of busses */
237 int mp_napics; /* # of IO APICs */
238 int boot_cpu_id; /* designated BSP */
239 vm_offset_t cpu_apic_address;
240 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
243 u_int32_t cpu_apic_versions[MAXCPU];
244 u_int32_t *io_apic_versions;
246 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
248 #ifdef APIC_INTR_REORDER
250 volatile int *location;
252 } apic_isrbit_location[32];
257 * APIC ID logical/physical mapping structures.
258 * We oversize these to simplify boot-time config.
260 int cpu_num_to_apic_id[NAPICID];
261 int io_num_to_apic_id[NAPICID];
262 int apic_id_to_logical[NAPICID];
264 /* AP uses this during bootstrap. Do not staticize. */
268 /* Hotwire a 0->4MB V==P mapping */
269 extern pt_entry_t *KPTphys;
271 /* SMP page table page */
272 extern pt_entry_t *SMPpt;
274 struct pcb stoppcbs[MAXCPU];
277 * Local data and functions.
280 static int mp_capable;
281 static u_int boot_address;
282 static u_int base_memory;
283 static int mp_finish;
285 static int picmode; /* 0: virtual wire mode, 1: PIC mode */
286 static mpfps_t mpfps;
287 static int search_for_sig(u_int32_t target, int count);
288 static void mp_enable(u_int boot_addr);
290 static void mptable_hyperthread_fixup(u_int id_mask);
291 static void mptable_pass1(void);
292 static int mptable_pass2(void);
293 static void default_mp_table(int type);
294 static void fix_mp_table(void);
295 static void setup_apic_irq_mapping(void);
296 static int start_all_aps(u_int boot_addr);
297 static void install_ap_tramp(u_int boot_addr);
298 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
299 static int apic_int_is_bus_type(int intr, int bus_type);
301 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
302 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
303 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
306 * Calculate usable address in base memory for AP trampoline code.
309 mp_bootaddress(u_int basemem)
311 POSTCODE(MP_BOOTADDRESS_POST);
313 base_memory = basemem * 1024; /* convert to bytes */
315 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
316 if ((base_memory - boot_address) < bootMP_size)
317 boot_address -= 4096; /* not enough, lower by 4k */
324 * Look for an Intel MP spec table (ie, SMP capable hardware).
333 POSTCODE(MP_PROBE_POST);
335 /* see if EBDA exists */
336 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
337 /* search first 1K of EBDA */
338 target = (u_int32_t) (segment << 4);
339 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
342 /* last 1K of base memory, effective 'top of base' passed in */
343 target = (u_int32_t) (base_memory - 0x400);
344 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
348 /* search the BIOS */
349 target = (u_int32_t) BIOS_BASE;
350 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
359 /* calculate needed resources */
363 /* flag fact that we are running multiple processors */
370 * Startup the SMP processors.
375 POSTCODE(MP_START_POST);
377 /* look for MP capable motherboard */
379 mp_enable(boot_address);
381 panic("MP hardware not found!");
386 * Print various information about the SMP system hardware and setup.
393 POSTCODE(MP_ANNOUNCE_POST);
395 printf("FreeBSD/SMP: Multiprocessor motherboard\n");
396 printf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
397 printf(", version: 0x%08x", cpu_apic_versions[0]);
398 printf(", at 0x%08x\n", cpu_apic_address);
399 for (x = 1; x <= mp_naps; ++x) {
400 printf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
401 printf(", version: 0x%08x", cpu_apic_versions[x]);
402 printf(", at 0x%08x\n", cpu_apic_address);
406 for (x = 0; x < mp_napics; ++x) {
407 printf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
408 printf(", version: 0x%08x", io_apic_versions[x]);
409 printf(", at 0x%08x\n", io_apic_address[x]);
412 printf(" Warning: APIC I/O disabled\n");
417 * AP cpu's call this to sync up protected mode.
423 int x, myid = bootAP;
425 struct mdglobaldata *md;
426 struct privatespace *ps;
428 ps = &CPU_prvspace[myid];
430 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
431 gdt_segs[GPROC0_SEL].ssd_base =
432 (int) &ps->mdglobaldata.gd_common_tss;
433 ps->mdglobaldata.mi.gd_prvspace = ps;
435 for (x = 0; x < NGDT; x++) {
436 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
439 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
440 r_gdt.rd_base = (int) &gdt[myid * NGDT];
441 lgdt(&r_gdt); /* does magic intra-segment return */
446 mdcpu->gd_currentldt = _default_ldt;
448 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
449 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
451 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
453 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
454 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
455 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
456 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
457 md->gd_common_tssd = *md->gd_tss_gdt;
461 * Set to a known state:
462 * Set by mpboot.s: CR0_PG, CR0_PE
463 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
466 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
475 * Final configuration of the BSP's local APIC:
476 * - disable 'pic mode'.
477 * - disable 'virtual wire mode'.
481 bsp_apic_configure(void)
486 /* leave 'pic mode' if necessary */
488 outb(0x22, 0x70); /* select IMCR */
489 byte = inb(0x23); /* current contents */
490 byte |= 0x01; /* mask external INTR */
491 outb(0x23, byte); /* disconnect 8259s/NMI */
494 /* mask lint0 (the 8259 'virtual wire' connection) */
495 temp = lapic.lvt_lint0;
496 temp |= APIC_LVT_M; /* set the mask */
497 lapic.lvt_lint0 = temp;
499 /* setup lint1 to handle NMI */
500 temp = lapic.lvt_lint1;
501 temp &= ~APIC_LVT_M; /* clear the mask */
502 lapic.lvt_lint1 = temp;
505 apic_dump("bsp_apic_configure()");
510 /*******************************************************************
511 * local functions and data
515 * start the SMP system
518 mp_enable(u_int boot_addr)
526 POSTCODE(MP_ENABLE_POST);
528 /* turn on 4MB of V == P addressing so we can get to MP table */
529 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
532 /* examine the MP table for needed info, uses physical addresses */
538 /* can't process default configs till the CPU APIC is pmapped */
542 /* post scan cleanup */
544 setup_apic_irq_mapping();
548 /* fill the LOGICAL io_apic_versions table */
549 for (apic = 0; apic < mp_napics; ++apic) {
550 ux = io_apic_read(apic, IOAPIC_VER);
551 io_apic_versions[apic] = ux;
552 io_apic_set_id(apic, IO_TO_ID(apic));
555 /* program each IO APIC in the system */
556 for (apic = 0; apic < mp_napics; ++apic)
557 if (io_apic_setup(apic) < 0)
558 panic("IO APIC setup failure");
560 /* install a 'Spurious INTerrupt' vector */
561 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
562 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
564 /* install an inter-CPU IPI for TLB invalidation */
565 setidt(XINVLTLB_OFFSET, Xinvltlb,
566 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
568 /* install an inter-CPU IPI for IPIQ messaging */
569 setidt(XIPIQ_OFFSET, Xipiq,
570 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
572 /* install an inter-CPU IPI for all-CPU rendezvous */
573 setidt(XRENDEZVOUS_OFFSET, Xrendezvous,
574 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
576 /* install an inter-CPU IPI for CPU stop/restart */
577 setidt(XCPUSTOP_OFFSET, Xcpustop,
578 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
580 #if defined(TEST_TEST1)
581 /* install a "fake hardware INTerrupt" vector */
582 setidt(XTEST1_OFFSET, Xtest1,
583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
584 #endif /** TEST_TEST1 */
588 /* start each Application Processor */
589 start_all_aps(boot_addr);
594 * look for the MP spec signature
597 /* string defined by the Intel MP Spec as identifying the MP table */
598 #define MP_SIG 0x5f504d5f /* _MP_ */
599 #define NEXT(X) ((X) += 4)
601 search_for_sig(u_int32_t target, int count)
604 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
606 for (x = 0; x < count; NEXT(x))
607 if (addr[x] == MP_SIG)
608 /* make array index a byte index */
609 return (target + (x * sizeof(u_int32_t)));
615 static basetable_entry basetable_entry_types[] =
617 {0, 20, "Processor"},
624 typedef struct BUSDATA {
626 enum busTypes bus_type;
629 typedef struct INTDATA {
639 typedef struct BUSTYPENAME {
644 static bus_type_name bus_type_table[] =
650 {UNKNOWN_BUSTYPE, "---"},
653 {UNKNOWN_BUSTYPE, "---"},
654 {UNKNOWN_BUSTYPE, "---"},
655 {UNKNOWN_BUSTYPE, "---"},
656 {UNKNOWN_BUSTYPE, "---"},
657 {UNKNOWN_BUSTYPE, "---"},
659 {UNKNOWN_BUSTYPE, "---"},
660 {UNKNOWN_BUSTYPE, "---"},
661 {UNKNOWN_BUSTYPE, "---"},
662 {UNKNOWN_BUSTYPE, "---"},
664 {UNKNOWN_BUSTYPE, "---"}
666 /* from MP spec v1.4, table 5-1 */
667 static int default_data[7][5] =
669 /* nbus, id0, type0, id1, type1 */
670 {1, 0, ISA, 255, 255},
671 {1, 0, EISA, 255, 255},
672 {1, 0, EISA, 255, 255},
673 {1, 0, MCA, 255, 255},
675 {2, 0, EISA, 1, PCI},
681 static bus_datum *bus_data;
683 /* the IO INT data, one entry per possible APIC INTerrupt */
684 static io_int *io_apic_ints;
688 static int processor_entry (proc_entry_ptr entry, int cpu);
689 static int bus_entry (bus_entry_ptr entry, int bus);
690 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
691 static int int_entry (int_entry_ptr entry, int intr);
692 static int lookup_bus_type (char *name);
696 * 1st pass on motherboard's Intel MP specification table.
702 * cpu_apic_address (common to all CPUs)
720 POSTCODE(MPTABLE_PASS1_POST);
722 /* clear various tables */
723 for (x = 0; x < NAPICID; ++x) {
724 io_apic_address[x] = ~0; /* IO APIC address table */
727 /* init everything to empty */
734 /* check for use of 'default' configuration */
735 if (MPFPS_MPFB1 != 0) {
736 /* use default addresses */
737 cpu_apic_address = DEFAULT_APIC_BASE;
738 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
740 /* fill in with defaults */
741 mp_naps = 2; /* includes BSP */
742 mp_nbusses = default_data[MPFPS_MPFB1 - 1][0];
749 if ((cth = mpfps->pap) == 0)
750 panic("MP Configuration Table Header MISSING!");
752 cpu_apic_address = (vm_offset_t) cth->apic_address;
754 /* walk the table, recording info of interest */
755 totalSize = cth->base_table_length - sizeof(struct MPCTH);
756 position = (u_char *) cth + sizeof(struct MPCTH);
757 count = cth->entry_count;
760 switch (type = *(u_char *) position) {
761 case 0: /* processor_entry */
762 if (((proc_entry_ptr)position)->cpu_flags
763 & PROCENTRY_FLAG_EN) {
766 ((proc_entry_ptr)position)->apic_id;
769 case 1: /* bus_entry */
772 case 2: /* io_apic_entry */
773 if (((io_apic_entry_ptr)position)->apic_flags
774 & IOAPICENTRY_FLAG_EN)
775 io_apic_address[mp_napics++] =
776 (vm_offset_t)((io_apic_entry_ptr)
777 position)->apic_address;
779 case 3: /* int_entry */
782 case 4: /* int_entry */
785 panic("mpfps Base Table HOSED!");
789 totalSize -= basetable_entry_types[type].length;
790 (u_char*)position += basetable_entry_types[type].length;
794 /* qualify the numbers */
795 if (mp_naps > MAXCPU) {
796 printf("Warning: only using %d of %d available CPUs!\n",
801 /* See if we need to fixup HT logical CPUs. */
802 mptable_hyperthread_fixup(id_mask);
806 * This is also used as a counter while starting the APs.
810 --mp_naps; /* subtract the BSP */
815 * 2nd pass on motherboard's Intel MP specification table.
819 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
820 * CPU_TO_ID(N), logical CPU to APIC ID table
821 * IO_TO_ID(N), logical IO to APIC ID table
828 struct PROCENTRY proc;
835 int apic, bus, cpu, intr;
839 POSTCODE(MPTABLE_PASS2_POST);
841 /* Initialize fake proc entry for use with HT fixup. */
842 bzero(&proc, sizeof(proc));
844 proc.cpu_flags = PROCENTRY_FLAG_EN;
846 pgeflag = 0; /* XXX - Not used under SMP yet. */
848 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
850 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
852 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + 1),
854 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
857 bzero(ioapic, sizeof(ioapic_t *) * mp_napics);
859 for (i = 0; i < mp_napics; i++) {
860 for (j = 0; j < mp_napics; j++) {
861 /* same page frame as a previous IO apic? */
862 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) ==
863 (io_apic_address[i] & PG_FRAME)) {
864 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
865 + (NPTEPG-2-j) * PAGE_SIZE
866 + (io_apic_address[i] & PAGE_MASK));
869 /* use this slot if available */
870 if (((vm_offset_t)SMPpt[NPTEPG-2-j] & PG_FRAME) == 0) {
871 SMPpt[NPTEPG-2-j] = (pt_entry_t)(PG_V | PG_RW |
872 pgeflag | (io_apic_address[i] & PG_FRAME));
873 ioapic[i] = (ioapic_t *)((u_int)CPU_prvspace
874 + (NPTEPG-2-j) * PAGE_SIZE
875 + (io_apic_address[i] & PAGE_MASK));
881 /* clear various tables */
882 for (x = 0; x < NAPICID; ++x) {
883 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
884 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
885 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
888 /* clear bus data table */
889 for (x = 0; x < mp_nbusses; ++x)
890 bus_data[x].bus_id = 0xff;
892 /* clear IO APIC INT table */
893 for (x = 0; x < (nintrs + 1); ++x) {
894 io_apic_ints[x].int_type = 0xff;
895 io_apic_ints[x].int_vector = 0xff;
898 /* setup the cpu/apic mapping arrays */
901 /* record whether PIC or virtual-wire mode */
902 picmode = (mpfps->mpfb2 & 0x80) ? 1 : 0;
904 /* check for use of 'default' configuration */
905 if (MPFPS_MPFB1 != 0)
906 return MPFPS_MPFB1; /* return default configuration type */
908 if ((cth = mpfps->pap) == 0)
909 panic("MP Configuration Table Header MISSING!");
911 /* walk the table, recording info of interest */
912 totalSize = cth->base_table_length - sizeof(struct MPCTH);
913 position = (u_char *) cth + sizeof(struct MPCTH);
914 count = cth->entry_count;
915 apic = bus = intr = 0;
916 cpu = 1; /* pre-count the BSP */
919 switch (type = *(u_char *) position) {
921 if (processor_entry(position, cpu))
924 if (need_hyperthreading_fixup) {
926 * Create fake mptable processor entries
927 * and feed them to processor_entry() to
928 * enumerate the logical CPUs.
930 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
931 for (i = 1; i < logical_cpus; i++) {
933 (void)processor_entry(&proc, cpu);
934 logical_cpus_mask |= (1 << cpu);
940 if (bus_entry(position, bus))
944 if (io_apic_entry(position, apic))
948 if (int_entry(position, intr))
952 /* int_entry(position); */
955 panic("mpfps Base Table HOSED!");
959 totalSize -= basetable_entry_types[type].length;
960 (u_char *) position += basetable_entry_types[type].length;
963 if (boot_cpu_id == -1)
964 panic("NO BSP found!");
966 /* report fact that its NOT a default configuration */
971 * Check if we should perform a hyperthreading "fix-up" to
972 * enumerate any logical CPU's that aren't already listed
975 * XXX: We assume that all of the physical CPUs in the
976 * system have the same number of logical CPUs.
978 * XXX: We assume that APIC ID's are allocated such that
979 * the APIC ID's for a physical processor are aligned
980 * with the number of logical CPU's in the processor.
983 mptable_hyperthread_fixup(u_int id_mask)
987 /* Nothing to do if there is no HTT support. */
988 if ((cpu_feature & CPUID_HTT) == 0)
990 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
991 if (logical_cpus <= 1)
995 * For each APIC ID of a CPU that is set in the mask,
996 * scan the other candidate APIC ID's for this
997 * physical processor. If any of those ID's are
998 * already in the table, then kill the fixup.
1000 for (id = 0; id <= MAXCPU; id++) {
1001 if ((id_mask & 1 << id) == 0)
1003 /* First, make sure we are on a logical_cpus boundary. */
1004 if (id % logical_cpus != 0)
1006 for (i = id + 1; i < id + logical_cpus; i++)
1007 if ((id_mask & 1 << i) != 0)
1012 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1013 * mp_naps right now.
1015 need_hyperthreading_fixup = 1;
1016 mp_naps *= logical_cpus;
1020 assign_apic_irq(int apic, int intpin, int irq)
1024 if (int_to_apicintpin[irq].ioapic != -1)
1025 panic("assign_apic_irq: inconsistent table");
1027 int_to_apicintpin[irq].ioapic = apic;
1028 int_to_apicintpin[irq].int_pin = intpin;
1029 int_to_apicintpin[irq].apic_address = ioapic[apic];
1030 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1032 for (x = 0; x < nintrs; x++) {
1033 if ((io_apic_ints[x].int_type == 0 ||
1034 io_apic_ints[x].int_type == 3) &&
1035 io_apic_ints[x].int_vector == 0xff &&
1036 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1037 io_apic_ints[x].dst_apic_int == intpin)
1038 io_apic_ints[x].int_vector = irq;
1043 revoke_apic_irq(int irq)
1049 if (int_to_apicintpin[irq].ioapic == -1)
1050 panic("revoke_apic_irq: inconsistent table");
1052 oldapic = int_to_apicintpin[irq].ioapic;
1053 oldintpin = int_to_apicintpin[irq].int_pin;
1055 int_to_apicintpin[irq].ioapic = -1;
1056 int_to_apicintpin[irq].int_pin = 0;
1057 int_to_apicintpin[irq].apic_address = NULL;
1058 int_to_apicintpin[irq].redirindex = 0;
1060 for (x = 0; x < nintrs; x++) {
1061 if ((io_apic_ints[x].int_type == 0 ||
1062 io_apic_ints[x].int_type == 3) &&
1063 io_apic_ints[x].int_vector != 0xff &&
1064 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1065 io_apic_ints[x].dst_apic_int == oldintpin)
1066 io_apic_ints[x].int_vector = 0xff;
1072 allocate_apic_irq(int intr)
1078 if (io_apic_ints[intr].int_vector != 0xff)
1079 return; /* Interrupt handler already assigned */
1081 if (io_apic_ints[intr].int_type != 0 &&
1082 (io_apic_ints[intr].int_type != 3 ||
1083 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1084 io_apic_ints[intr].dst_apic_int == 0)))
1085 return; /* Not INT or ExtInt on != (0, 0) */
1088 while (irq < APIC_INTMAPSIZE &&
1089 int_to_apicintpin[irq].ioapic != -1)
1092 if (irq >= APIC_INTMAPSIZE)
1093 return; /* No free interrupt handlers */
1095 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1096 intpin = io_apic_ints[intr].dst_apic_int;
1098 assign_apic_irq(apic, intpin, irq);
1099 io_apic_setup_intpin(apic, intpin);
1104 swap_apic_id(int apic, int oldid, int newid)
1111 return; /* Nothing to do */
1113 printf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1114 apic, oldid, newid);
1116 /* Swap physical APIC IDs in interrupt entries */
1117 for (x = 0; x < nintrs; x++) {
1118 if (io_apic_ints[x].dst_apic_id == oldid)
1119 io_apic_ints[x].dst_apic_id = newid;
1120 else if (io_apic_ints[x].dst_apic_id == newid)
1121 io_apic_ints[x].dst_apic_id = oldid;
1124 /* Swap physical APIC IDs in IO_TO_ID mappings */
1125 for (oapic = 0; oapic < mp_napics; oapic++)
1126 if (IO_TO_ID(oapic) == newid)
1129 if (oapic < mp_napics) {
1130 printf("Changing APIC ID for IO APIC #%d from "
1131 "%d to %d in MP table\n",
1132 oapic, newid, oldid);
1133 IO_TO_ID(oapic) = oldid;
1135 IO_TO_ID(apic) = newid;
1140 fix_id_to_io_mapping(void)
1144 for (x = 0; x < NAPICID; x++)
1147 for (x = 0; x <= mp_naps; x++)
1148 if (CPU_TO_ID(x) < NAPICID)
1149 ID_TO_IO(CPU_TO_ID(x)) = x;
1151 for (x = 0; x < mp_napics; x++)
1152 if (IO_TO_ID(x) < NAPICID)
1153 ID_TO_IO(IO_TO_ID(x)) = x;
1158 first_free_apic_id(void)
1162 for (freeid = 0; freeid < NAPICID; freeid++) {
1163 for (x = 0; x <= mp_naps; x++)
1164 if (CPU_TO_ID(x) == freeid)
1168 for (x = 0; x < mp_napics; x++)
1169 if (IO_TO_ID(x) == freeid)
1180 io_apic_id_acceptable(int apic, int id)
1182 int cpu; /* Logical CPU number */
1183 int oapic; /* Logical IO APIC number for other IO APIC */
1186 return 0; /* Out of range */
1188 for (cpu = 0; cpu <= mp_naps; cpu++)
1189 if (CPU_TO_ID(cpu) == id)
1190 return 0; /* Conflict with CPU */
1192 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1193 if (IO_TO_ID(oapic) == id)
1194 return 0; /* Conflict with other APIC */
1196 return 1; /* ID is acceptable for IO APIC */
1201 * parse an Intel MP specification table
1208 int bus_0 = 0; /* Stop GCC warning */
1209 int bus_pci = 0; /* Stop GCC warning */
1211 int apic; /* IO APIC unit number */
1212 int freeid; /* Free physical APIC ID */
1213 int physid; /* Current physical IO APIC ID */
1216 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1217 * did it wrong. The MP spec says that when more than 1 PCI bus
1218 * exists the BIOS must begin with bus entries for the PCI bus and use
1219 * actual PCI bus numbering. This implies that when only 1 PCI bus
1220 * exists the BIOS can choose to ignore this ordering, and indeed many
1221 * MP motherboards do ignore it. This causes a problem when the PCI
1222 * sub-system makes requests of the MP sub-system based on PCI bus
1223 * numbers. So here we look for the situation and renumber the
1224 * busses and associated INTs in an effort to "make it right".
1227 /* find bus 0, PCI bus, count the number of PCI busses */
1228 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1229 if (bus_data[x].bus_id == 0) {
1232 if (bus_data[x].bus_type == PCI) {
1238 * bus_0 == slot of bus with ID of 0
1239 * bus_pci == slot of last PCI bus encountered
1242 /* check the 1 PCI bus case for sanity */
1243 /* if it is number 0 all is well */
1244 if (num_pci_bus == 1 &&
1245 bus_data[bus_pci].bus_id != 0) {
1247 /* mis-numbered, swap with whichever bus uses slot 0 */
1249 /* swap the bus entry types */
1250 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1251 bus_data[bus_0].bus_type = PCI;
1253 /* swap each relavant INTerrupt entry */
1254 id = bus_data[bus_pci].bus_id;
1255 for (x = 0; x < nintrs; ++x) {
1256 if (io_apic_ints[x].src_bus_id == id) {
1257 io_apic_ints[x].src_bus_id = 0;
1259 else if (io_apic_ints[x].src_bus_id == 0) {
1260 io_apic_ints[x].src_bus_id = id;
1265 /* Assign IO APIC IDs.
1267 * First try the existing ID. If a conflict is detected, try
1268 * the ID in the MP table. If a conflict is still detected, find
1271 * We cannot use the ID_TO_IO table before all conflicts has been
1272 * resolved and the table has been corrected.
1274 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1276 /* First try to use the value set by the BIOS */
1277 physid = io_apic_get_id(apic);
1278 if (io_apic_id_acceptable(apic, physid)) {
1279 if (IO_TO_ID(apic) != physid)
1280 swap_apic_id(apic, IO_TO_ID(apic), physid);
1284 /* Then check if the value in the MP table is acceptable */
1285 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1288 /* Last resort, find a free APIC ID and use it */
1289 freeid = first_free_apic_id();
1290 if (freeid >= NAPICID)
1291 panic("No free physical APIC IDs found");
1293 if (io_apic_id_acceptable(apic, freeid)) {
1294 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1297 panic("Free physical APIC ID not usable");
1299 fix_id_to_io_mapping();
1301 /* detect and fix broken Compaq MP table */
1302 if (apic_int_type(0, 0) == -1) {
1303 printf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1304 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1305 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1306 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1307 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1308 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1314 /* Assign low level interrupt handlers */
1316 setup_apic_irq_mapping(void)
1322 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1323 int_to_apicintpin[x].ioapic = -1;
1324 int_to_apicintpin[x].int_pin = 0;
1325 int_to_apicintpin[x].apic_address = NULL;
1326 int_to_apicintpin[x].redirindex = 0;
1329 /* First assign ISA/EISA interrupts */
1330 for (x = 0; x < nintrs; x++) {
1331 int_vector = io_apic_ints[x].src_bus_irq;
1332 if (int_vector < APIC_INTMAPSIZE &&
1333 io_apic_ints[x].int_vector == 0xff &&
1334 int_to_apicintpin[int_vector].ioapic == -1 &&
1335 (apic_int_is_bus_type(x, ISA) ||
1336 apic_int_is_bus_type(x, EISA)) &&
1337 io_apic_ints[x].int_type == 0) {
1338 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1339 io_apic_ints[x].dst_apic_int,
1344 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1345 for (x = 0; x < nintrs; x++) {
1346 if (io_apic_ints[x].dst_apic_int == 0 &&
1347 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1348 io_apic_ints[x].int_vector == 0xff &&
1349 int_to_apicintpin[0].ioapic == -1 &&
1350 io_apic_ints[x].int_type == 3) {
1351 assign_apic_irq(0, 0, 0);
1355 /* PCI interrupt assignment is deferred */
1360 processor_entry(proc_entry_ptr entry, int cpu)
1362 /* check for usability */
1363 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1366 if(entry->apic_id >= NAPICID)
1367 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1368 /* check for BSP flag */
1369 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1370 boot_cpu_id = entry->apic_id;
1371 CPU_TO_ID(0) = entry->apic_id;
1372 ID_TO_CPU(entry->apic_id) = 0;
1373 return 0; /* its already been counted */
1376 /* add another AP to list, if less than max number of CPUs */
1377 else if (cpu < MAXCPU) {
1378 CPU_TO_ID(cpu) = entry->apic_id;
1379 ID_TO_CPU(entry->apic_id) = cpu;
1388 bus_entry(bus_entry_ptr entry, int bus)
1393 /* encode the name into an index */
1394 for (x = 0; x < 6; ++x) {
1395 if ((c = entry->bus_type[x]) == ' ')
1401 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1402 panic("unknown bus type: '%s'", name);
1404 bus_data[bus].bus_id = entry->bus_id;
1405 bus_data[bus].bus_type = x;
1412 io_apic_entry(io_apic_entry_ptr entry, int apic)
1414 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1417 IO_TO_ID(apic) = entry->apic_id;
1418 if (entry->apic_id < NAPICID)
1419 ID_TO_IO(entry->apic_id) = apic;
1426 lookup_bus_type(char *name)
1430 for (x = 0; x < MAX_BUSTYPE; ++x)
1431 if (strcmp(bus_type_table[x].name, name) == 0)
1432 return bus_type_table[x].type;
1434 return UNKNOWN_BUSTYPE;
1439 int_entry(int_entry_ptr entry, int intr)
1443 io_apic_ints[intr].int_type = entry->int_type;
1444 io_apic_ints[intr].int_flags = entry->int_flags;
1445 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1446 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1447 if (entry->dst_apic_id == 255) {
1448 /* This signal goes to all IO APICS. Select an IO APIC
1449 with sufficient number of interrupt pins */
1450 for (apic = 0; apic < mp_napics; apic++)
1451 if (((io_apic_read(apic, IOAPIC_VER) &
1452 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1453 entry->dst_apic_int)
1455 if (apic < mp_napics)
1456 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1458 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1460 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1461 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1468 apic_int_is_bus_type(int intr, int bus_type)
1472 for (bus = 0; bus < mp_nbusses; ++bus)
1473 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1474 && ((int) bus_data[bus].bus_type == bus_type))
1482 * Given a traditional ISA INT mask, return an APIC mask.
1485 isa_apic_mask(u_int isa_mask)
1490 #if defined(SKIP_IRQ15_REDIRECT)
1491 if (isa_mask == (1 << 15)) {
1492 printf("skipping ISA IRQ15 redirect\n");
1495 #endif /* SKIP_IRQ15_REDIRECT */
1497 isa_irq = ffs(isa_mask); /* find its bit position */
1498 if (isa_irq == 0) /* doesn't exist */
1500 --isa_irq; /* make it zero based */
1502 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1506 return (1 << apic_pin); /* convert pin# to a mask */
1511 * Determine which APIC pin an ISA/EISA INT is attached to.
1513 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1514 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1515 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1516 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1518 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1520 isa_apic_irq(int isa_irq)
1524 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1525 if (INTTYPE(intr) == 0) { /* standard INT */
1526 if (SRCBUSIRQ(intr) == isa_irq) {
1527 if (apic_int_is_bus_type(intr, ISA) ||
1528 apic_int_is_bus_type(intr, EISA)) {
1529 if (INTIRQ(intr) == 0xff)
1530 return -1; /* unassigned */
1531 return INTIRQ(intr); /* found */
1536 return -1; /* NOT found */
1541 * Determine which APIC pin a PCI INT is attached to.
1543 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1544 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1545 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1547 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1551 --pciInt; /* zero based */
1553 for (intr = 0; intr < nintrs; ++intr) /* check each record */
1554 if ((INTTYPE(intr) == 0) /* standard INT */
1555 && (SRCBUSID(intr) == pciBus)
1556 && (SRCBUSDEVICE(intr) == pciDevice)
1557 && (SRCBUSLINE(intr) == pciInt)) /* a candidate IRQ */
1558 if (apic_int_is_bus_type(intr, PCI)) {
1559 if (INTIRQ(intr) == 0xff)
1560 allocate_apic_irq(intr);
1561 if (INTIRQ(intr) == 0xff)
1562 return -1; /* unassigned */
1563 return INTIRQ(intr); /* exact match */
1566 return -1; /* NOT found */
1570 next_apic_irq(int irq)
1577 for (intr = 0; intr < nintrs; intr++) {
1578 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1580 bus = SRCBUSID(intr);
1581 bustype = apic_bus_type(bus);
1582 if (bustype != ISA &&
1588 if (intr >= nintrs) {
1591 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1592 if (INTTYPE(ointr) != 0)
1594 if (bus != SRCBUSID(ointr))
1596 if (bustype == PCI) {
1597 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1599 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1602 if (bustype == ISA || bustype == EISA) {
1603 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1606 if (INTPIN(intr) == INTPIN(ointr))
1610 if (ointr >= nintrs) {
1613 return INTIRQ(ointr);
1627 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1630 * Exactly what this means is unclear at this point. It is a solution
1631 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1632 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1633 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1637 undirect_isa_irq(int rirq)
1641 printf("Freeing redirected ISA irq %d.\n", rirq);
1642 /** FIXME: tickle the MB redirector chip */
1646 printf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1653 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1656 undirect_pci_irq(int rirq)
1660 printf("Freeing redirected PCI irq %d.\n", rirq);
1662 /** FIXME: tickle the MB redirector chip */
1666 printf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1674 * given a bus ID, return:
1675 * the bus type if found
1679 apic_bus_type(int id)
1683 for (x = 0; x < mp_nbusses; ++x)
1684 if (bus_data[x].bus_id == id)
1685 return bus_data[x].bus_type;
1692 * given a LOGICAL APIC# and pin#, return:
1693 * the associated src bus ID if found
1697 apic_src_bus_id(int apic, int pin)
1701 /* search each of the possible INTerrupt sources */
1702 for (x = 0; x < nintrs; ++x)
1703 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1704 (pin == io_apic_ints[x].dst_apic_int))
1705 return (io_apic_ints[x].src_bus_id);
1707 return -1; /* NOT found */
1712 * given a LOGICAL APIC# and pin#, return:
1713 * the associated src bus IRQ if found
1717 apic_src_bus_irq(int apic, int pin)
1721 for (x = 0; x < nintrs; x++)
1722 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1723 (pin == io_apic_ints[x].dst_apic_int))
1724 return (io_apic_ints[x].src_bus_irq);
1726 return -1; /* NOT found */
1731 * given a LOGICAL APIC# and pin#, return:
1732 * the associated INTerrupt type if found
1736 apic_int_type(int apic, int pin)
1740 /* search each of the possible INTerrupt sources */
1741 for (x = 0; x < nintrs; ++x)
1742 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1743 (pin == io_apic_ints[x].dst_apic_int))
1744 return (io_apic_ints[x].int_type);
1746 return -1; /* NOT found */
1750 apic_irq(int apic, int pin)
1755 for (x = 0; x < nintrs; ++x)
1756 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1757 (pin == io_apic_ints[x].dst_apic_int)) {
1758 res = io_apic_ints[x].int_vector;
1761 if (apic != int_to_apicintpin[res].ioapic)
1762 panic("apic_irq: inconsistent table");
1763 if (pin != int_to_apicintpin[res].int_pin)
1764 panic("apic_irq inconsistent table (2)");
1772 * given a LOGICAL APIC# and pin#, return:
1773 * the associated trigger mode if found
1777 apic_trigger(int apic, int pin)
1781 /* search each of the possible INTerrupt sources */
1782 for (x = 0; x < nintrs; ++x)
1783 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1784 (pin == io_apic_ints[x].dst_apic_int))
1785 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1787 return -1; /* NOT found */
1792 * given a LOGICAL APIC# and pin#, return:
1793 * the associated 'active' level if found
1797 apic_polarity(int apic, int pin)
1801 /* search each of the possible INTerrupt sources */
1802 for (x = 0; x < nintrs; ++x)
1803 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1804 (pin == io_apic_ints[x].dst_apic_int))
1805 return (io_apic_ints[x].int_flags & 0x03);
1807 return -1; /* NOT found */
1812 * set data according to MP defaults
1813 * FIXME: probably not complete yet...
1816 default_mp_table(int type)
1819 #if defined(APIC_IO)
1822 #endif /* APIC_IO */
1825 printf(" MP default config type: %d\n", type);
1828 printf(" bus: ISA, APIC: 82489DX\n");
1831 printf(" bus: EISA, APIC: 82489DX\n");
1834 printf(" bus: EISA, APIC: 82489DX\n");
1837 printf(" bus: MCA, APIC: 82489DX\n");
1840 printf(" bus: ISA+PCI, APIC: Integrated\n");
1843 printf(" bus: EISA+PCI, APIC: Integrated\n");
1846 printf(" bus: MCA+PCI, APIC: Integrated\n");
1849 printf(" future type\n");
1855 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1856 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1859 CPU_TO_ID(0) = boot_cpu_id;
1860 ID_TO_CPU(boot_cpu_id) = 0;
1862 /* one and only AP */
1863 CPU_TO_ID(1) = ap_cpu_id;
1864 ID_TO_CPU(ap_cpu_id) = 1;
1866 #if defined(APIC_IO)
1867 /* one and only IO APIC */
1868 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1871 * sanity check, refer to MP spec section 3.6.6, last paragraph
1872 * necessary as some hardware isn't properly setting up the IO APIC
1874 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1875 if (io_apic_id != 2) {
1877 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1878 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1879 io_apic_set_id(0, 2);
1882 IO_TO_ID(0) = io_apic_id;
1883 ID_TO_IO(io_apic_id) = 0;
1884 #endif /* APIC_IO */
1886 /* fill out bus entries */
1895 bus_data[0].bus_id = default_data[type - 1][1];
1896 bus_data[0].bus_type = default_data[type - 1][2];
1897 bus_data[1].bus_id = default_data[type - 1][3];
1898 bus_data[1].bus_type = default_data[type - 1][4];
1901 /* case 4: case 7: MCA NOT supported */
1902 default: /* illegal/reserved */
1903 panic("BAD default MP config: %d", type);
1907 #if defined(APIC_IO)
1908 /* general cases from MP v1.4, table 5-2 */
1909 for (pin = 0; pin < 16; ++pin) {
1910 io_apic_ints[pin].int_type = 0;
1911 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1912 io_apic_ints[pin].src_bus_id = 0;
1913 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1914 io_apic_ints[pin].dst_apic_id = io_apic_id;
1915 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1918 /* special cases from MP v1.4, table 5-2 */
1920 io_apic_ints[2].int_type = 0xff; /* N/C */
1921 io_apic_ints[13].int_type = 0xff; /* N/C */
1922 #if !defined(APIC_MIXED_MODE)
1924 panic("sorry, can't support type 2 default yet");
1925 #endif /* APIC_MIXED_MODE */
1928 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1931 io_apic_ints[0].int_type = 0xff; /* N/C */
1933 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1934 #endif /* APIC_IO */
1938 * start each AP in our list
1941 start_all_aps(u_int boot_addr)
1944 u_char mpbiosreason;
1945 u_long mpbioswarmvec;
1946 struct mdglobaldata *gd;
1947 struct privatespace *ps;
1951 POSTCODE(START_ALL_APS_POST);
1953 /* initialize BSP's local APIC */
1957 /* install the AP 1st level boot code */
1958 install_ap_tramp(boot_addr);
1961 /* save the current value of the warm-start vector */
1962 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1964 outb(CMOS_REG, BIOS_RESET);
1965 mpbiosreason = inb(CMOS_DATA);
1968 /* set up temporary P==V mapping for AP boot */
1969 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1970 kptbase = (uintptr_t)(void *)KPTphys;
1971 for (x = 0; x < NKPT; x++)
1972 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1973 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1977 for (x = 1; x <= mp_naps; ++x) {
1979 /* This is a bit verbose, it will go away soon. */
1981 /* first page of AP's private space */
1982 pg = x * i386_btop(sizeof(struct privatespace));
1984 /* allocate a new private data page */
1985 gd = (struct mdglobaldata *)kmem_alloc(kernel_map, PAGE_SIZE);
1987 /* wire it into the private page table page */
1988 SMPpt[pg] = (pt_entry_t)(PG_V | PG_RW | vtophys_pte(gd));
1990 /* allocate and set up an idle stack data page */
1991 stack = (char *)kmem_alloc(kernel_map, UPAGES*PAGE_SIZE);
1992 for (i = 0; i < UPAGES; i++) {
1993 SMPpt[pg + 5 + i] = (pt_entry_t)
1994 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
1997 SMPpt[pg + 1] = 0; /* *gd_CMAP1 */
1998 SMPpt[pg + 2] = 0; /* *gd_CMAP2 */
1999 SMPpt[pg + 3] = 0; /* *gd_CMAP3 */
2000 SMPpt[pg + 4] = 0; /* *gd_PMAP1 */
2002 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2003 bzero(gd, sizeof(*gd));
2004 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2006 /* prime data page for it to use */
2007 mi_gdinit(&gd->mi, x);
2009 gd->gd_CMAP1 = &SMPpt[pg + 1];
2010 gd->gd_CMAP2 = &SMPpt[pg + 2];
2011 gd->gd_CMAP3 = &SMPpt[pg + 3];
2012 gd->gd_PMAP1 = &SMPpt[pg + 4];
2013 gd->gd_CADDR1 = ps->CPAGE1;
2014 gd->gd_CADDR2 = ps->CPAGE2;
2015 gd->gd_CADDR3 = ps->CPAGE3;
2016 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2017 gd->mi.gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2018 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2020 /* setup a vector to our boot code */
2021 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2022 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2024 outb(CMOS_REG, BIOS_RESET);
2025 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2029 * Setup the AP boot stack
2031 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2034 /* attempt to start the Application Processor */
2035 CHECK_INIT(99); /* setup checkpoints */
2036 if (!start_ap(gd, boot_addr)) {
2037 printf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2038 CHECK_PRINT("trace"); /* show checkpoints */
2039 /* better panic as the AP may be running loose */
2040 printf("panic y/n? [y] ");
2041 if (cngetc() != 'n')
2044 CHECK_PRINT("trace"); /* show checkpoints */
2046 /* record its version info */
2047 cpu_apic_versions[x] = cpu_apic_versions[0];
2050 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2053 /* build our map of 'other' CPUs */
2054 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2055 mycpu->gd_ipiq = (void *)kmem_alloc(kernel_map, sizeof(lwkt_ipiq) * ncpus);
2056 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2058 /* fill in our (BSP) APIC version */
2059 cpu_apic_versions[0] = lapic.version;
2061 /* restore the warmstart vector */
2062 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2064 outb(CMOS_REG, BIOS_RESET);
2065 outb(CMOS_DATA, mpbiosreason);
2069 * NOTE! The idlestack for the BSP was setup by locore. Finish
2070 * up, clean out the P==V mapping we did earlier.
2072 for (x = 0; x < NKPT; x++)
2076 /* number of APs actually started */
2082 * load the 1st level AP boot code into base memory.
2085 /* targets for relocation */
2086 extern void bigJump(void);
2087 extern void bootCodeSeg(void);
2088 extern void bootDataSeg(void);
2089 extern void MPentry(void);
2090 extern u_int MP_GDT;
2091 extern u_int mp_gdtbase;
2094 install_ap_tramp(u_int boot_addr)
2097 int size = *(int *) ((u_long) & bootMP_size);
2098 u_char *src = (u_char *) ((u_long) bootMP);
2099 u_char *dst = (u_char *) boot_addr + KERNBASE;
2100 u_int boot_base = (u_int) bootMP;
2105 POSTCODE(INSTALL_AP_TRAMP_POST);
2107 for (x = 0; x < size; ++x)
2111 * modify addresses in code we just moved to basemem. unfortunately we
2112 * need fairly detailed info about mpboot.s for this to work. changes
2113 * to mpboot.s might require changes here.
2116 /* boot code is located in KERNEL space */
2117 dst = (u_char *) boot_addr + KERNBASE;
2119 /* modify the lgdt arg */
2120 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2121 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2123 /* modify the ljmp target for MPentry() */
2124 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2125 *dst32 = ((u_int) MPentry - KERNBASE);
2127 /* modify the target for boot code segment */
2128 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2129 dst8 = (u_int8_t *) (dst16 + 1);
2130 *dst16 = (u_int) boot_addr & 0xffff;
2131 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2133 /* modify the target for boot data segment */
2134 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2135 dst8 = (u_int8_t *) (dst16 + 1);
2136 *dst16 = (u_int) boot_addr & 0xffff;
2137 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2142 * this function starts the AP (application processor) identified
2143 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2144 * to accomplish this. This is necessary because of the nuances
2145 * of the different hardware we might encounter. It ain't pretty,
2146 * but it seems to work.
2148 * NOTE: eventually an AP gets to ap_init(), which is called just
2149 * before the AP goes into the LWKT scheduler's idle loop.
2152 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2156 u_long icr_lo, icr_hi;
2158 POSTCODE(START_AP_POST);
2160 /* get the PHYSICAL APIC ID# */
2161 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2163 /* calculate the vector */
2164 vector = (boot_addr >> 12) & 0xff;
2166 /* Make sure the target cpu sees everything */
2170 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2171 * and running the target CPU. OR this INIT IPI might be latched (P5
2172 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2176 /* setup the address for the target AP */
2177 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2178 icr_hi |= (physical_cpu << 24);
2179 lapic.icr_hi = icr_hi;
2181 /* do an INIT IPI: assert RESET */
2182 icr_lo = lapic.icr_lo & 0xfff00000;
2183 lapic.icr_lo = icr_lo | 0x0000c500;
2185 /* wait for pending status end */
2186 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2189 /* do an INIT IPI: deassert RESET */
2190 lapic.icr_lo = icr_lo | 0x00008500;
2192 /* wait for pending status end */
2193 u_sleep(10000); /* wait ~10mS */
2194 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2198 * next we do a STARTUP IPI: the previous INIT IPI might still be
2199 * latched, (P5 bug) this 1st STARTUP would then terminate
2200 * immediately, and the previously started INIT IPI would continue. OR
2201 * the previous INIT IPI has already run. and this STARTUP IPI will
2202 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2206 /* do a STARTUP IPI */
2207 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2208 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2210 u_sleep(200); /* wait ~200uS */
2213 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2214 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2215 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2216 * recognized after hardware RESET or INIT IPI.
2219 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2220 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2222 u_sleep(200); /* wait ~200uS */
2224 /* wait for it to start, see ap_init() */
2225 set_apic_timer(5000000);/* == 5 seconds */
2226 while (read_apic_timer()) {
2227 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2228 return 1; /* return SUCCESS */
2230 return 0; /* return FAILURE */
2235 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2237 * If for some reason we were unable to start all cpus we cannot safely
2238 * use broadcast IPIs.
2243 #if defined(APIC_IO)
2244 if (smp_startup_mask == smp_active_mask) {
2245 all_but_self_ipi(XINVLTLB_OFFSET);
2247 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2248 APIC_DELMODE_FIXED);
2250 #endif /* APIC_IO */
2254 * When called the executing CPU will send an IPI to all other CPUs
2255 * requesting that they halt execution.
2257 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2259 * - Signals all CPUs in map to stop.
2260 * - Waits for each to stop.
2267 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2268 * from executing at same time.
2271 stop_cpus(u_int map)
2273 map &= smp_active_mask;
2275 /* send the Xcpustop IPI to all CPUs in map */
2276 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2278 while ((stopped_cpus & map) != map)
2286 * Called by a CPU to restart stopped CPUs.
2288 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2290 * - Signals all CPUs in map to restart.
2291 * - Waits for each to restart.
2299 restart_cpus(u_int map)
2301 /* signal other cpus to restart */
2302 started_cpus = map & smp_active_mask;
2304 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2311 * This is called once the mpboot code has gotten us properly relocated
2312 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2313 * and when it returns the scheduler will call the real cpu_idle() main
2314 * loop for the idlethread. Interrupts are disabled on entry and should
2315 * remain disabled at return.
2323 * Adjust smp_startup_mask to signal the BSP that we have started
2324 * up successfully. Note that we do not yet hold the BGL. The BSP
2325 * is waiting for our signal.
2327 * We can't set our bit in smp_active_mask yet because we are holding
2328 * interrupts physically disabled and remote cpus could deadlock
2329 * trying to send us an IPI.
2331 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2335 * Interlock for finalization. Wait until mp_finish is non-zero,
2336 * then get the MP lock.
2338 * Note: We are in a critical section.
2340 * Note: We have to synchronize td_mpcount to our desired MP state
2341 * before calling cpu_try_mplock().
2343 * Note: we are the idle thread, we can only spin.
2345 * Note: cpu_mb1() is memory volatile and prevents mp_finish from
2348 ++curthread->td_mpcount;
2349 while (mp_finish == 0)
2351 while (cpu_try_mplock() == 0)
2354 /* BSP may have changed PTD while we're waiting for the lock */
2357 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2361 /* Build our map of 'other' CPUs. */
2362 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2364 printf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2366 /* set up CPU registers and state */
2369 /* set up FPU state on the AP */
2370 npxinit(__INITIAL_NPXCW__);
2372 /* set up SSE registers */
2375 /* A quick check from sanity claus */
2376 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2377 if (mycpu->gd_cpuid != apic_id) {
2378 printf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2379 printf("SMP: apic_id = %d\n", apic_id);
2380 printf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2381 panic("cpuid mismatch! boom!!");
2384 /* Init local apic for irq's */
2387 /* Set memory range attributes for this CPU to match the BSP */
2388 mem_range_AP_init();
2390 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2393 * The idle loop doesn't expect the BGL to be held and while
2394 * lwkt_switch() normally cleans things up this is a special case
2395 * because we returning almost directly into the idle loop.
2397 * The idle thread is never placed on the runq, make sure
2398 * nothing we've done put it thre.
2400 KKASSERT(curthread->td_mpcount == 1);
2401 smp_active_mask |= 1 << mycpu->gd_cpuid;
2403 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2407 * Get SMP fully working before we start initializing devices.
2415 printf("Finish MP startup");
2417 while (smp_active_mask != smp_startup_mask)
2419 while (cpu_try_mplock() == 0)
2422 printf("Active CPU Mask: %08x\n", smp_active_mask);
2425 SYSINIT(finishsmp, SI_SUB_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2427 #ifdef APIC_INTR_REORDER
2429 * Maintain mapping from softintr vector to isr bit in local apic.
2432 set_lapic_isrloc(int intr, int vector)
2434 if (intr < 0 || intr > 32)
2435 panic("set_apic_isrloc: bad intr argument: %d",intr);
2436 if (vector < ICU_OFFSET || vector > 255)
2437 panic("set_apic_isrloc: bad vector argument: %d",vector);
2438 apic_isrbit_location[intr].location = &lapic.isr0 + ((vector>>5)<<2);
2439 apic_isrbit_location[intr].bit = (1<<(vector & 31));
2446 * All-CPU rendezvous. CPUs are signalled, all execute the setup function
2447 * (if specified), rendezvous, execute the action function (if specified),
2448 * rendezvous again, execute the teardown function (if specified), and then
2451 * Note that the supplied external functions _must_ be reentrant and aware
2452 * that they are running in parallel and in an unknown lock context.
2454 static void (*smp_rv_setup_func)(void *arg);
2455 static void (*smp_rv_action_func)(void *arg);
2456 static void (*smp_rv_teardown_func)(void *arg);
2457 static void *smp_rv_func_arg;
2458 static volatile int smp_rv_waiters[2];
2461 smp_rendezvous_action(void)
2463 /* setup function */
2464 if (smp_rv_setup_func != NULL)
2465 smp_rv_setup_func(smp_rv_func_arg);
2466 /* spin on entry rendezvous */
2467 atomic_add_int(&smp_rv_waiters[0], 1);
2468 while (smp_rv_waiters[0] < ncpus)
2470 /* action function */
2471 if (smp_rv_action_func != NULL)
2472 smp_rv_action_func(smp_rv_func_arg);
2473 /* spin on exit rendezvous */
2474 atomic_add_int(&smp_rv_waiters[1], 1);
2475 while (smp_rv_waiters[1] < ncpus)
2477 /* teardown function */
2478 if (smp_rv_teardown_func != NULL)
2479 smp_rv_teardown_func(smp_rv_func_arg);
2483 smp_rendezvous(void (* setup_func)(void *),
2484 void (* action_func)(void *),
2485 void (* teardown_func)(void *),
2488 /* obtain rendezvous lock. This disables interrupts */
2489 spin_lock(&smp_rv_spinlock); /* XXX sleep here? NOWAIT flag? */
2491 /* set static function pointers */
2492 smp_rv_setup_func = setup_func;
2493 smp_rv_action_func = action_func;
2494 smp_rv_teardown_func = teardown_func;
2495 smp_rv_func_arg = arg;
2496 smp_rv_waiters[0] = 0;
2497 smp_rv_waiters[1] = 0;
2500 * Signal other processors which will enter the IPI with interrupts
2501 * disabled. We cannot safely use broadcast IPIs if some of our
2502 * cpus failed to start.
2504 if (smp_startup_mask == smp_active_mask) {
2505 all_but_self_ipi(XRENDEZVOUS_OFFSET);
2507 selected_apic_ipi(smp_active_mask, XRENDEZVOUS_OFFSET,
2508 APIC_DELMODE_FIXED);
2511 /* call executor function */
2512 smp_rendezvous_action();
2515 spin_unlock(&smp_rv_spinlock);
2519 cpu_send_ipiq(int dcpu)
2521 if ((1 << dcpu) & smp_active_mask)
2522 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2525 #if 0 /* single_apic_ipi_passive() not working yet */
2527 * Returns 0 on failure, 1 on success
2530 cpu_send_ipiq_passive(int dcpu)
2533 if ((1 << dcpu) & smp_active_mask) {
2534 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2535 APIC_DELMODE_FIXED);