2 * Copyright (c) 2009 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/globaldata.h>
39 #include <machine/md_var.h>
40 #include <machine/cpufunc.h>
41 #include <machine/cpufreq.h>
42 #include <machine/specialreg.h>
45 #include "acpi_cpu_pstate.h"
47 #define AMD_APMI_HWPSTATE 0x80
49 #define AMD_MSR_PSTATE_CSR_MASK 0x7ULL
50 #define AMD1X_MSR_PSTATE_CTL 0xc0010062
51 #define AMD1X_MSR_PSTATE_ST 0xc0010063
53 #define AMD_MSR_PSTATE_EN 0x8000000000000000ULL
55 #define AMD10_MSR_PSTATE_START 0xc0010064
56 #define AMD10_MSR_PSTATE_COUNT 5
58 #define AMD0F_PST_CTL_FID(cval) (((cval) >> 0) & 0x3f)
59 #define AMD0F_PST_CTL_VID(cval) (((cval) >> 6) & 0x1f)
60 #define AMD0F_PST_CTL_VST(cval) (((cval) >> 11) & 0x7f)
61 #define AMD0F_PST_CTL_MVS(cval) (((cval) >> 18) & 0x3)
62 #define AMD0F_PST_CTL_PLLTIME(cval) (((cval) >> 20) & 0x7f)
63 #define AMD0F_PST_CTL_RVO(cval) (((cval) >> 28) & 0x3)
64 #define AMD0F_PST_CTL_IRT(cval) (((cval) >> 30) & 0x3)
66 #define AMD0F_PST_ST_FID(sval) (((sval) >> 0) & 0x3f)
67 #define AMD0F_PST_ST_VID(sval) (((sval) >> 6) & 0x3f)
69 #define INTEL_MSR_MISC_ENABLE 0x1a0
70 #define INTEL_MSR_MISC_EST_EN 0x10000ULL
72 #define INTEL_MSR_PERF_STATUS 0x198
73 #define INTEL_MSR_PERF_CTL 0x199
74 #define INTEL_MSR_PERF_MASK 0xffffULL
76 static const struct acpi_pst_md *
77 acpi_pst_amd_probe(void);
78 static int acpi_pst_amd_check_csr(const struct acpi_pst_res *,
79 const struct acpi_pst_res *);
80 static int acpi_pst_amd1x_check_pstates(const struct acpi_pstate *, int,
82 static int acpi_pst_amd10_check_pstates(const struct acpi_pstate *, int);
83 static int acpi_pst_amd0f_check_pstates(const struct acpi_pstate *, int);
84 static int acpi_pst_amd_init(const struct acpi_pst_res *,
85 const struct acpi_pst_res *);
86 static int acpi_pst_amd1x_set_pstate(const struct acpi_pst_res *,
87 const struct acpi_pst_res *, const struct acpi_pstate *);
88 static int acpi_pst_amd0f_set_pstate(const struct acpi_pst_res *,
89 const struct acpi_pst_res *, const struct acpi_pstate *);
90 static const struct acpi_pstate *
91 acpi_pst_amd1x_get_pstate(const struct acpi_pst_res *,
92 const struct acpi_pstate *, int);
93 static const struct acpi_pstate *
94 acpi_pst_amd0f_get_pstate(const struct acpi_pst_res *,
95 const struct acpi_pstate *, int);
97 static const struct acpi_pst_md *
98 acpi_pst_intel_probe(void);
99 static int acpi_pst_intel_check_csr(const struct acpi_pst_res *,
100 const struct acpi_pst_res *);
101 static int acpi_pst_intel_check_pstates(const struct acpi_pstate *, int);
102 static int acpi_pst_intel_init(const struct acpi_pst_res *,
103 const struct acpi_pst_res *);
104 static int acpi_pst_intel_set_pstate(const struct acpi_pst_res *,
105 const struct acpi_pst_res *, const struct acpi_pstate *);
106 static const struct acpi_pstate *
107 acpi_pst_intel_get_pstate(const struct acpi_pst_res *,
108 const struct acpi_pstate *, int);
110 static int acpi_pst_md_gas_asz(const ACPI_GENERIC_ADDRESS *);
111 static int acpi_pst_md_gas_verify(const ACPI_GENERIC_ADDRESS *);
112 static uint32_t acpi_pst_md_res_read(const struct acpi_pst_res *);
113 static void acpi_pst_md_res_write(const struct acpi_pst_res *, uint32_t);
115 static const struct acpi_pst_md acpi_pst_amd10 = {
116 .pmd_check_csr = acpi_pst_amd_check_csr,
117 .pmd_check_pstates = acpi_pst_amd10_check_pstates,
118 .pmd_init = acpi_pst_amd_init,
119 .pmd_set_pstate = acpi_pst_amd1x_set_pstate,
120 .pmd_get_pstate = acpi_pst_amd1x_get_pstate
123 static const struct acpi_pst_md acpi_pst_amd0f = {
124 .pmd_check_csr = acpi_pst_amd_check_csr,
125 .pmd_check_pstates = acpi_pst_amd0f_check_pstates,
126 .pmd_init = acpi_pst_amd_init,
127 .pmd_set_pstate = acpi_pst_amd0f_set_pstate,
128 .pmd_get_pstate = acpi_pst_amd0f_get_pstate
131 static const struct acpi_pst_md acpi_pst_intel = {
132 .pmd_check_csr = acpi_pst_intel_check_csr,
133 .pmd_check_pstates = acpi_pst_intel_check_pstates,
134 .pmd_init = acpi_pst_intel_init,
135 .pmd_set_pstate = acpi_pst_intel_set_pstate,
136 .pmd_get_pstate = acpi_pst_intel_get_pstate
139 const struct acpi_pst_md *
140 acpi_pst_md_probe(void)
142 if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
143 return acpi_pst_amd_probe();
144 else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
145 return acpi_pst_intel_probe();
149 static const struct acpi_pst_md *
150 acpi_pst_amd_probe(void)
152 uint32_t regs[4], ext_family;
154 if ((cpu_id & 0x00000f00) != 0x00000f00)
157 /* Check whether APMI exists */
158 do_cpuid(0x80000000, regs);
159 if (regs[0] < 0x80000007)
163 do_cpuid(0x80000007, regs);
165 ext_family = cpu_id & 0x0ff00000;
166 switch (ext_family) {
167 case 0x00000000: /* Family 0fh */
168 if ((regs[3] & 0x06) == 0x06)
169 return &acpi_pst_amd0f;
172 case 0x00100000: /* Family 10h */
174 return &acpi_pst_amd10;
184 acpi_pst_amd_check_csr(const struct acpi_pst_res *ctrl,
185 const struct acpi_pst_res *status)
187 if (ctrl->pr_gas.SpaceId != ACPI_ADR_SPACE_FIXED_HARDWARE) {
188 kprintf("cpu%d: Invalid P-State control register\n", mycpuid);
191 if (status->pr_gas.SpaceId != ACPI_ADR_SPACE_FIXED_HARDWARE) {
192 kprintf("cpu%d: Invalid P-State status register\n", mycpuid);
199 acpi_pst_amd1x_check_pstates(const struct acpi_pstate *pstates, int npstates,
200 uint32_t msr_start, uint32_t msr_end)
205 * Make sure that related MSR P-State registers are enabled.
208 * We don't check status register value here;
209 * it will not be used.
211 for (i = 0; i < npstates; ++i) {
216 (pstates[i].st_cval & AMD_MSR_PSTATE_CSR_MASK);
217 if (msr >= msr_end) {
218 kprintf("cpu%d: MSR P-State register %#08x "
219 "does not exist\n", mycpuid, msr);
224 if ((pstate & AMD_MSR_PSTATE_EN) == 0) {
225 kprintf("cpu%d: MSR P-State register %#08x "
226 "is not enabled\n", mycpuid, msr);
234 acpi_pst_amd10_check_pstates(const struct acpi_pstate *pstates, int npstates)
236 /* Only P0-P4 are supported */
237 if (npstates > AMD10_MSR_PSTATE_COUNT) {
238 kprintf("cpu%d: only P0-P4 is allowed\n", mycpuid);
242 return acpi_pst_amd1x_check_pstates(pstates, npstates,
243 AMD10_MSR_PSTATE_START,
244 AMD10_MSR_PSTATE_START + AMD10_MSR_PSTATE_COUNT);
248 acpi_pst_amd1x_set_pstate(const struct acpi_pst_res *ctrl __unused,
249 const struct acpi_pst_res *status __unused,
250 const struct acpi_pstate *pstate)
254 cval = pstate->st_cval & AMD_MSR_PSTATE_CSR_MASK;
255 wrmsr(AMD1X_MSR_PSTATE_CTL, cval);
258 * Don't check AMD1X_MSR_PSTATE_ST here, since it is
259 * affected by various P-State limits.
262 * AMD Family 10h Processor BKDG Rev 3.20 (#31116)
263 * 2.4.2.4 P-state Transition Behavior
269 static const struct acpi_pstate *
270 acpi_pst_amd1x_get_pstate(const struct acpi_pst_res *status __unused,
271 const struct acpi_pstate *pstates, int npstates)
276 sval = rdmsr(AMD1X_MSR_PSTATE_ST) & AMD_MSR_PSTATE_CSR_MASK;
277 for (i = 0; i < npstates; ++i) {
278 if ((pstates[i].st_sval & AMD_MSR_PSTATE_CSR_MASK) == sval)
285 acpi_pst_amd0f_check_pstates(const struct acpi_pstate *pstates, int npstates)
287 struct amd0f_fidvid fv_max, fv_min;
290 amd0f_fidvid_limit(&fv_min, &fv_max);
292 for (i = 0; i < npstates; ++i) {
293 const struct acpi_pstate *p = &pstates[i];
294 uint32_t fid, vid, mvs, rvo;
297 fid = AMD0F_PST_CTL_FID(p->st_cval);
298 vid = AMD0F_PST_CTL_VID(p->st_cval);
300 if (fid > fv_max.fid || fid < fv_min.fid) {
301 kprintf("cpu%d: Invalid FID %#x [%#x, %#x]\n",
302 mycpuid, fid, fv_min.fid, fv_max.fid);
305 if (vid < fv_max.vid || vid > fv_min.vid) {
306 kprintf("cpu%d: Invalid VID %#x [%#x, %#x]\n",
307 mycpuid, vid, fv_max.vid, fv_min.fid);
311 mvs = AMD0F_PST_CTL_MVS(p->st_cval);
312 rvo = AMD0F_PST_CTL_RVO(p->st_cval);
314 /* Only 0 is allowed, i.e. 25mV stepping */
316 kprintf("cpu%d: Invalid MVS %#x\n", mycpuid, mvs);
321 mvs_mv = 25 * (1 << mvs);
323 if (rvo_mv % mvs_mv != 0) {
324 kprintf("cpu%d: Invalid MVS/RVO (%#x/%#x)\n",
333 acpi_pst_amd0f_set_pstate(const struct acpi_pst_res *ctrl __unused,
334 const struct acpi_pst_res *status __unused,
335 const struct acpi_pstate *pstate)
337 struct amd0f_fidvid fv;
338 struct amd0f_xsit xsit;
340 fv.fid = AMD0F_PST_CTL_FID(pstate->st_cval);
341 fv.vid = AMD0F_PST_CTL_VID(pstate->st_cval);
343 xsit.rvo = AMD0F_PST_CTL_RVO(pstate->st_cval);
344 xsit.mvs = AMD0F_PST_CTL_MVS(pstate->st_cval);
345 xsit.vst = AMD0F_PST_CTL_VST(pstate->st_cval);
346 xsit.pll_time = AMD0F_PST_CTL_PLLTIME(pstate->st_cval);
347 xsit.irt = AMD0F_PST_CTL_IRT(pstate->st_cval);
349 return amd0f_set_fidvid(&fv, &xsit);
352 static const struct acpi_pstate *
353 acpi_pst_amd0f_get_pstate(const struct acpi_pst_res *status __unused,
354 const struct acpi_pstate *pstates, int npstates)
356 struct amd0f_fidvid fv;
359 error = amd0f_get_fidvid(&fv);
363 for (i = 0; i < npstates; ++i) {
364 const struct acpi_pstate *p = &pstates[i];
366 if (fv.fid == AMD0F_PST_ST_FID(p->st_sval) &&
367 fv.vid == AMD0F_PST_ST_VID(p->st_sval))
374 acpi_pst_amd_init(const struct acpi_pst_res *ctrl __unused,
375 const struct acpi_pst_res *status __unused)
380 static const struct acpi_pst_md *
381 acpi_pst_intel_probe(void)
385 if ((cpu_feature2 & CPUID2_EST) == 0)
388 family = cpu_id & 0xf00;
389 if (family != 0xf00 && family != 0x600)
391 return &acpi_pst_intel;
395 acpi_pst_intel_check_csr(const struct acpi_pst_res *ctrl,
396 const struct acpi_pst_res *status)
400 if (ctrl->pr_gas.SpaceId != status->pr_gas.SpaceId) {
401 kprintf("cpu%d: P-State control(%d)/status(%d) registers have "
402 "different SpaceId", mycpuid,
403 ctrl->pr_gas.SpaceId, status->pr_gas.SpaceId);
407 switch (ctrl->pr_gas.SpaceId) {
408 case ACPI_ADR_SPACE_FIXED_HARDWARE:
409 if (ctrl->pr_res != NULL || status->pr_res != NULL) {
410 /* XXX should panic() */
411 kprintf("cpu%d: Allocated resource for fixed hardware "
412 "registers\n", mycpuid);
417 case ACPI_ADR_SPACE_SYSTEM_IO:
418 if (ctrl->pr_res == NULL) {
419 kprintf("cpu%d: ioport allocation failed for control "
420 "register\n", mycpuid);
423 error = acpi_pst_md_gas_verify(&ctrl->pr_gas);
425 kprintf("cpu%d: Invalid control register GAS\n",
430 if (status->pr_res == NULL) {
431 kprintf("cpu%d: ioport allocation failed for status "
432 "register\n", mycpuid);
435 error = acpi_pst_md_gas_verify(&status->pr_gas);
437 kprintf("cpu%d: Invalid status register GAS\n",
444 kprintf("cpu%d: Invalid P-State control/status register "
445 "SpaceId %d\n", mycpuid, ctrl->pr_gas.SpaceId);
452 acpi_pst_intel_check_pstates(const struct acpi_pstate *pstates __unused,
453 int npstates __unused)
459 acpi_pst_intel_init(const struct acpi_pst_res *ctrl __unused,
460 const struct acpi_pst_res *status __unused)
462 uint32_t family, model;
463 uint64_t misc_enable;
465 family = cpu_id & 0xf00;
466 if (family == 0xf00) {
467 /* EST enable bit is reserved in INTEL_MSR_MISC_ENABLE */
470 KKASSERT(family == 0x600);
472 model = ((cpu_id & 0xf0000) >> 12) | ((cpu_id & 0xf0) >> 4);
474 /* EST enable bit is reserved in INTEL_MSR_MISC_ENABLE */
478 misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
479 if ((misc_enable & INTEL_MSR_MISC_EST_EN) == 0) {
480 misc_enable |= INTEL_MSR_MISC_EST_EN;
481 wrmsr(INTEL_MSR_MISC_ENABLE, misc_enable);
483 misc_enable = rdmsr(INTEL_MSR_MISC_ENABLE);
484 if ((misc_enable & INTEL_MSR_MISC_EST_EN) == 0) {
485 kprintf("cpu%d: Can't enable EST\n", mycpuid);
493 acpi_pst_intel_set_pstate(const struct acpi_pst_res *ctrl,
494 const struct acpi_pst_res *status __unused,
495 const struct acpi_pstate *pstate)
497 if (ctrl->pr_res != NULL) {
498 acpi_pst_md_res_write(ctrl, pstate->st_cval);
502 ctl = rdmsr(INTEL_MSR_PERF_CTL);
503 ctl &= ~INTEL_MSR_PERF_MASK;
504 ctl |= (pstate->st_cval & INTEL_MSR_PERF_MASK);
505 wrmsr(INTEL_MSR_PERF_CTL, ctl);
510 static const struct acpi_pstate *
511 acpi_pst_intel_get_pstate(const struct acpi_pst_res *status,
512 const struct acpi_pstate *pstates, int npstates)
516 if (status->pr_res != NULL) {
519 st = acpi_pst_md_res_read(status);
520 for (i = 0; i < npstates; ++i) {
521 if (pstates[i].st_sval == st)
527 sval = rdmsr(INTEL_MSR_PERF_STATUS) & INTEL_MSR_PERF_MASK;
528 for (i = 0; i < npstates; ++i) {
529 if ((pstates[i].st_sval & INTEL_MSR_PERF_MASK) == sval)
537 acpi_pst_md_gas_asz(const ACPI_GENERIC_ADDRESS *gas)
541 if (gas->AccessWidth != 0)
542 asz = gas->AccessWidth;
544 asz = gas->BitWidth / NBBY;
558 acpi_pst_md_gas_verify(const ACPI_GENERIC_ADDRESS *gas)
562 if (gas->BitOffset % NBBY != 0)
565 end = gas->BitWidth / NBBY;
566 reg = gas->BitOffset / NBBY;
571 asz = acpi_pst_md_gas_asz(gas);
581 acpi_pst_md_res_read(const struct acpi_pst_res *res)
585 KKASSERT(res->pr_res != NULL);
586 asz = acpi_pst_md_gas_asz(&res->pr_gas);
587 reg = res->pr_gas.BitOffset / NBBY;
591 return bus_space_read_1(res->pr_bt, res->pr_bh, reg);
593 return bus_space_read_2(res->pr_bt, res->pr_bh, reg);
595 return bus_space_read_4(res->pr_bt, res->pr_bh, reg);
597 panic("unsupported access width %d\n", asz);
604 acpi_pst_md_res_write(const struct acpi_pst_res *res, uint32_t val)
608 KKASSERT(res->pr_res != NULL);
609 asz = acpi_pst_md_gas_asz(&res->pr_gas);
610 reg = res->pr_gas.BitOffset / NBBY;
614 bus_space_write_1(res->pr_bt, res->pr_bh, reg, val);
617 bus_space_write_2(res->pr_bt, res->pr_bh, reg, val);
620 bus_space_write_4(res->pr_bt, res->pr_bh, reg, val);
623 panic("unsupported access width %d\n", asz);