sys/dev/drm/radeon/atombios_dp.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  *          Jerome Glisse
  26  *
  27  * $FreeBSD: head/sys/dev/drm2/radeon/atombios_dp.c 254885 2013-08-25 19:37:15Z dumbbell $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include "radeon.h"
  33
  34 #include "atom.h"
  35 #include "atom-bits.h"
  36 #include <drm/drm_dp_helper.h>
  37
  38 /* move these to drm_dp_helper.c/h */
  39 #define DP_LINK_CONFIGURATION_SIZE 9
  40 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  41
  42 static char *voltage_names[] = {
  43         "0.4V", "0.6V", "0.8V", "1.2V"
  44 };
  45 static char *pre_emph_names[] = {
  46         "0dB", "3.5dB", "6dB", "9.5dB"
  47 };
  48
  49 /***** radeon AUX functions *****/
  50
  51 /* Atom needs data in little endian format
  52  * so swap as appropriate when copying data to
  53  * or from atom. Note that atom operates on
  54  * dw units.
  55  */
  56 static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  57 {
  58 #ifdef __BIG_ENDIAN
  59         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  60         u32 *dst32, *src32;
  61         int i;
  62
  63         memcpy(src_tmp, src, num_bytes);
  64         src32 = (u32 *)src_tmp;
  65         dst32 = (u32 *)dst_tmp;
  66         if (to_le) {
  67                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  68                         dst32[i] = cpu_to_le32(src32[i]);
  69                 memcpy(dst, dst_tmp, num_bytes);
  70         } else {
  71                 u8 dws = num_bytes & ~3;
  72                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  73                         dst32[i] = le32_to_cpu(src32[i]);
  74                 memcpy(dst, dst_tmp, dws);
  75                 if (num_bytes % 4) {
  76                         for (i = 0; i < (num_bytes % 4); i++)
  77                                 dst[dws+i] = dst_tmp[dws+i];
  78                 }
  79         }
  80 #else
  81         memcpy(dst, src, num_bytes);
  82 #endif
  83 }
  84
  85 union aux_channel_transaction {
  86         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  87         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  88 };
  89
  90 static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  91                                  u8 *send, int send_bytes,
  92                                  u8 *recv, int recv_size,
  93                                  u8 delay, u8 *ack)
  94 {
  95         struct drm_device *dev = chan->dev;
  96         struct radeon_device *rdev = dev->dev_private;
  97         union aux_channel_transaction args;
  98         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  99         unsigned char *base;
 100         int recv_bytes;
 101
 102         memset(&args, 0, sizeof(args));
 103
 104         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
 105
 106         radeon_copy_swap(base, send, send_bytes, true);
 107
 108         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
 109         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
 110         args.v1.ucDataOutLen = 0;
 111         args.v1.ucChannelID = chan->rec.i2c_id;
 112         args.v1.ucDelay = delay / 10;
 113         if (ASIC_IS_DCE4(rdev))
 114                 args.v2.ucHPD_ID = chan->rec.hpd;
 115
 116         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 117
 118         *ack = args.v1.ucReplyStatus;
 119
 120         /* timeout */
 121         if (args.v1.ucReplyStatus == 1) {
 122                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
 123                 return -ETIMEDOUT;
 124         }
 125
 126         /* flags not zero */
 127         if (args.v1.ucReplyStatus == 2) {
 128                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
 129                 return -EBUSY;
 130         }
 131
 132         /* error */
 133         if (args.v1.ucReplyStatus == 3) {
 134                 DRM_DEBUG_KMS("dp_aux_ch error\n");
 135                 return -EIO;
 136         }
 137
 138         recv_bytes = args.v1.ucDataOutLen;
 139         if (recv_bytes > recv_size)
 140                 recv_bytes = recv_size;
 141
 142         if (recv && recv_size)
 143                 radeon_copy_swap(recv, base + 16, recv_bytes, false);
 144
 145         return recv_bytes;
 146 }
 147
 148 static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
 149                                       u16 address, u8 *send, u8 send_bytes, u8 delay)
 150 {
 151         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 152         int ret;
 153         u8 msg[20];
 154         int msg_bytes = send_bytes + 4;
 155         u8 ack;
 156         unsigned retry;
 157
 158         if (send_bytes > 16)
 159                 return -1;
 160
 161         msg[0] = address;
 162         msg[1] = address >> 8;
 163         msg[2] = DP_AUX_NATIVE_WRITE << 4;
 164         msg[3] = (msg_bytes << 4) | (send_bytes - 1);
 165         memcpy(&msg[4], send, send_bytes);
 166
 167         for (retry = 0; retry < 4; retry++) {
 168                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 169                                             msg, msg_bytes, NULL, 0, delay, &ack);
 170                 if (ret == -EBUSY)
 171                         continue;
 172                 else if (ret < 0)
 173                         return ret;
 174                 ack >>= 4;
 175                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 176                         return send_bytes;
 177                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 178                         DRM_UDELAY(400);
 179                 else
 180                         return -EIO;
 181         }
 182
 183         return -EIO;
 184 }
 185
 186 static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
 187                                      u16 address, u8 *recv, int recv_bytes, u8 delay)
 188 {
 189         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 190         u8 msg[4];
 191         int msg_bytes = 4;
 192         u8 ack;
 193         int ret;
 194         unsigned retry;
 195
 196         msg[0] = address;
 197         msg[1] = address >> 8;
 198         msg[2] = DP_AUX_NATIVE_READ << 4;
 199         msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
 200
 201         for (retry = 0; retry < 4; retry++) {
 202                 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
 203                                             msg, msg_bytes, recv, recv_bytes, delay, &ack);
 204                 if (ret == -EBUSY)
 205                         continue;
 206                 else if (ret < 0)
 207                         return ret;
 208                 ack >>= 4;
 209                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 210                         return ret;
 211                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 212                         DRM_UDELAY(400);
 213                 else if (ret == 0)
 214                         return -EPROTO;
 215                 else
 216                         return -EIO;
 217         }
 218
 219         return -EIO;
 220 }
 221
 222 static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
 223                                  u16 reg, u8 val)
 224 {
 225         radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
 226 }
 227
 228 static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
 229                                u16 reg)
 230 {
 231         u8 val = 0;
 232
 233         radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
 234
 235         return val;
 236 }
 237
 238 int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
 239 {
 240         struct i2c_algo_dp_aux_data *algo_data = device_get_softc(dev);
 241         struct radeon_i2c_chan *auxch = algo_data->priv;
 242         u16 address = algo_data->address;
 243         u8 msg[5];
 244         u8 reply[2];
 245         unsigned retry;
 246         int msg_bytes;
 247         int reply_bytes = 1;
 248         int ret;
 249         u8 ack;
 250
 251         /* Set up the command byte */
 252         if (mode & MODE_I2C_READ)
 253                 msg[2] = DP_AUX_I2C_READ << 4;
 254         else
 255                 msg[2] = DP_AUX_I2C_WRITE << 4;
 256
 257         if (!(mode & MODE_I2C_STOP))
 258                 msg[2] |= DP_AUX_I2C_MOT << 4;
 259
 260         msg[0] = address;
 261         msg[1] = address >> 8;
 262
 263         switch (mode) {
 264         case MODE_I2C_WRITE:
 265                 msg_bytes = 5;
 266                 msg[3] = msg_bytes << 4;
 267                 msg[4] = write_byte;
 268                 break;
 269         case MODE_I2C_READ:
 270                 msg_bytes = 4;
 271                 msg[3] = msg_bytes << 4;
 272                 break;
 273         default:
 274                 msg_bytes = 4;
 275                 msg[3] = 3 << 4;
 276                 break;
 277         }
 278
 279         for (retry = 0; retry < 4; retry++) {
 280                 ret = radeon_process_aux_ch(auxch,
 281                                             msg, msg_bytes, reply, reply_bytes, 0, &ack);
 282                 if (ret == -EBUSY)
 283                         continue;
 284                 else if (ret < 0) {
 285                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 286                         return ret;
 287                 }
 288
 289                 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 290                 case DP_AUX_NATIVE_REPLY_ACK:
 291                         /* I2C-over-AUX Reply field is only valid
 292                          * when paired with AUX ACK.
 293                          */
 294                         break;
 295                 case DP_AUX_NATIVE_REPLY_NACK:
 296                         DRM_DEBUG_KMS("aux_ch native nack\n");
 297                         return -EREMOTEIO;
 298                 case DP_AUX_NATIVE_REPLY_DEFER:
 299                         DRM_DEBUG_KMS("aux_ch native defer\n");
 300                         DRM_UDELAY(400);
 301                         continue;
 302                 default:
 303                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
 304                         return -EREMOTEIO;
 305                 }
 306
 307                 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
 308                 case DP_AUX_I2C_REPLY_ACK:
 309                         if (mode == MODE_I2C_READ)
 310                                 *read_byte = reply[0];
 311                         return ret;
 312                 case DP_AUX_I2C_REPLY_NACK:
 313                         DRM_DEBUG_KMS("aux_i2c nack\n");
 314                         return -EREMOTEIO;
 315                 case DP_AUX_I2C_REPLY_DEFER:
 316                         DRM_DEBUG_KMS("aux_i2c defer\n");
 317                         DRM_UDELAY(400);
 318                         break;
 319                 default:
 320                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
 321                         return -EREMOTEIO;
 322                 }
 323         }
 324
 325         DRM_DEBUG_KMS("aux i2c too many retries, giving up\n");
 326         return -EREMOTEIO;
 327 }
 328
 329 /***** general DP utility functions *****/
 330
 331 #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
 332 #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
 333
 334 static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
 335                                 int lane_count,
 336                                 u8 train_set[4])
 337 {
 338         u8 v = 0;
 339         u8 p = 0;
 340         int lane;
 341
 342         for (lane = 0; lane < lane_count; lane++) {
 343                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 344                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 345
 346                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
 347                           lane,
 348                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 349                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 350
 351                 if (this_v > v)
 352                         v = this_v;
 353                 if (this_p > p)
 354                         p = this_p;
 355         }
 356
 357         if (v >= DP_VOLTAGE_MAX)
 358                 v |= DP_TRAIN_MAX_SWING_REACHED;
 359
 360         if (p >= DP_PRE_EMPHASIS_MAX)
 361                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 362
 363         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
 364                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
 365                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
 366
 367         for (lane = 0; lane < 4; lane++)
 368                 train_set[lane] = v | p;
 369 }
 370
 371 /* convert bits per color to bits per pixel */
 372 /* get bpc from the EDID */
 373 static int convert_bpc_to_bpp(int bpc)
 374 {
 375         if (bpc == 0)
 376                 return 24;
 377         else
 378                 return bpc * 3;
 379 }
 380
 381 /* get the max pix clock supported by the link rate and lane num */
 382 static int dp_get_max_dp_pix_clock(int link_rate,
 383                                    int lane_num,
 384                                    int bpp)
 385 {
 386         return (link_rate * lane_num * 8) / bpp;
 387 }
 388
 389 /***** radeon specific DP functions *****/
 390
 391 /* First get the min lane# when low rate is used according to pixel clock
 392  * (prefer low rate), second check max lane# supported by DP panel,
 393  * if the max lane# < low rate lane# then use max lane# instead.
 394  */
 395 static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
 396                                         u8 dpcd[DP_DPCD_SIZE],
 397                                         int pix_clock)
 398 {
 399         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 400         int max_link_rate = drm_dp_max_link_rate(dpcd);
 401         int max_lane_num = drm_dp_max_lane_count(dpcd);
 402         int lane_num;
 403         int max_dp_pix_clock;
 404
 405         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
 406                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
 407                 if (pix_clock <= max_dp_pix_clock)
 408                         break;
 409         }
 410
 411         return lane_num;
 412 }
 413
 414 static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
 415                                        u8 dpcd[DP_DPCD_SIZE],
 416                                        int pix_clock)
 417 {
 418         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
 419         int lane_num, max_pix_clock;
 420
 421         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
 422             ENCODER_OBJECT_ID_NUTMEG)
 423                 return 270000;
 424
 425         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
 426         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
 427         if (pix_clock <= max_pix_clock)
 428                 return 162000;
 429         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
 430         if (pix_clock <= max_pix_clock)
 431                 return 270000;
 432         if (radeon_connector_is_dp12_capable(connector)) {
 433                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
 434                 if (pix_clock <= max_pix_clock)
 435                         return 540000;
 436         }
 437
 438         return drm_dp_max_link_rate(dpcd);
 439 }
 440
 441 static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
 442                                     int action, int dp_clock,
 443                                     u8 ucconfig, u8 lane_num)
 444 {
 445         DP_ENCODER_SERVICE_PARAMETERS args;
 446         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 447
 448         memset(&args, 0, sizeof(args));
 449         args.ucLinkClock = dp_clock / 10;
 450         args.ucConfig = ucconfig;
 451         args.ucAction = action;
 452         args.ucLaneNum = lane_num;
 453         args.ucStatus = 0;
 454
 455         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 456         return args.ucStatus;
 457 }
 458
 459 u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
 460 {
 461         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 462         struct drm_device *dev = radeon_connector->base.dev;
 463         struct radeon_device *rdev = dev->dev_private;
 464
 465         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
 466                                          dig_connector->dp_i2c_bus->rec.i2c_id, 0);
 467 }
 468
 469 static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
 470 {
 471         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 472         u8 buf[3];
 473
 474         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
 475                 return;
 476
 477         if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0))
 478                 DRM_DEBUG_KMS("Sink OUI: %02hhx%02hhx%02hhx\n",
 479                               buf[0], buf[1], buf[2]);
 480
 481         if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0))
 482                 DRM_DEBUG_KMS("Branch OUI: %02hhx%02hhx%02hhx\n",
 483                               buf[0], buf[1], buf[2]);
 484 }
 485
 486 bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
 487 {
 488         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 489         u8 msg[DP_DPCD_SIZE];
 490         int ret, i;
 491
 492         ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg,
 493                                         DP_DPCD_SIZE, 0);
 494         if (ret > 0) {
 495                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
 496                 DRM_DEBUG_KMS("DPCD: ");
 497                 for (i = 0; i < DP_DPCD_SIZE; i++)
 498                         DRM_DEBUG_KMS("%02x ", msg[i]);
 499                 DRM_DEBUG_KMS("\n");
 500
 501                 radeon_dp_probe_oui(radeon_connector);
 502
 503                 return true;
 504         }
 505         dig_connector->dpcd[0] = 0;
 506         return false;
 507 }
 508
 509 int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
 510                              struct drm_connector *connector)
 511 {
 512         struct drm_device *dev = encoder->dev;
 513         struct radeon_device *rdev = dev->dev_private;
 514         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 515         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 516         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
 517         u8 tmp;
 518
 519         if (!ASIC_IS_DCE4(rdev))
 520                 return panel_mode;
 521
 522         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
 523                 /* DP bridge chips */
 524                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 525                 if (tmp & 1)
 526                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 527                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
 528                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
 529                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
 530                 else
 531                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
 532         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
 533                 /* eDP */
 534                 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
 535                 if (tmp & 1)
 536                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
 537         }
 538
 539         return panel_mode;
 540 }
 541
 542 void radeon_dp_set_link_config(struct drm_connector *connector,
 543                                const struct drm_display_mode *mode)
 544 {
 545         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 546         struct radeon_connector_atom_dig *dig_connector;
 547
 548         if (!radeon_connector->con_priv)
 549                 return;
 550         dig_connector = radeon_connector->con_priv;
 551
 552         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 553             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 554                 dig_connector->dp_clock =
 555                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 556                 dig_connector->dp_lane_count =
 557                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
 558         }
 559 }
 560
 561 int radeon_dp_mode_valid_helper(struct drm_connector *connector,
 562                                 struct drm_display_mode *mode)
 563 {
 564         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 565         struct radeon_connector_atom_dig *dig_connector;
 566         int dp_clock;
 567
 568         if (!radeon_connector->con_priv)
 569                 return MODE_CLOCK_HIGH;
 570         dig_connector = radeon_connector->con_priv;
 571
 572         dp_clock =
 573                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
 574
 575         if ((dp_clock == 540000) &&
 576             (!radeon_connector_is_dp12_capable(connector)))
 577                 return MODE_CLOCK_HIGH;
 578
 579         return MODE_OK;
 580 }
 581
 582 static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
 583                                       u8 link_status[DP_LINK_STATUS_SIZE])
 584 {
 585         int ret;
 586         ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
 587                                         link_status, DP_LINK_STATUS_SIZE, 100);
 588         if (ret <= 0) {
 589                 return false;
 590         }
 591
 592         DRM_DEBUG_KMS("link status %*ph\n", 6, link_status);
 593         return true;
 594 }
 595
 596 bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
 597 {
 598         u8 link_status[DP_LINK_STATUS_SIZE];
 599         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 600
 601         if (!radeon_dp_get_link_status(radeon_connector, link_status))
 602                 return false;
 603         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
 604                 return false;
 605         return true;
 606 }
 607
 608 struct radeon_dp_link_train_info {
 609         struct radeon_device *rdev;
 610         struct drm_encoder *encoder;
 611         struct drm_connector *connector;
 612         struct radeon_connector *radeon_connector;
 613         int enc_id;
 614         int dp_clock;
 615         int dp_lane_count;
 616         bool tp3_supported;
 617         u8 dpcd[DP_RECEIVER_CAP_SIZE];
 618         u8 train_set[4];
 619         u8 link_status[DP_LINK_STATUS_SIZE];
 620         u8 tries;
 621         bool use_dpencoder;
 622 };
 623
 624 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
 625 {
 626         /* set the initial vs/emph on the source */
 627         atombios_dig_transmitter_setup(dp_info->encoder,
 628                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
 629                                        0, dp_info->train_set[0]); /* sets all lanes at once */
 630
 631         /* set the vs/emph on the sink */
 632         radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
 633                                    dp_info->train_set, dp_info->dp_lane_count, 0);
 634 }
 635
 636 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
 637 {
 638         int rtp = 0;
 639
 640         /* set training pattern on the source */
 641         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
 642                 switch (tp) {
 643                 case DP_TRAINING_PATTERN_1:
 644                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
 645                         break;
 646                 case DP_TRAINING_PATTERN_2:
 647                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
 648                         break;
 649                 case DP_TRAINING_PATTERN_3:
 650                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
 651                         break;
 652                 }
 653                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
 654         } else {
 655                 switch (tp) {
 656                 case DP_TRAINING_PATTERN_1:
 657                         rtp = 0;
 658                         break;
 659                 case DP_TRAINING_PATTERN_2:
 660                         rtp = 1;
 661                         break;
 662                 }
 663                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
 664                                           dp_info->dp_clock, dp_info->enc_id, rtp);
 665         }
 666
 667         /* enable training pattern on the sink */
 668         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
 669 }
 670
 671 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 672 {
 673         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
 674         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 675         u8 tmp;
 676
 677         /* power up the sink */
 678         if (dp_info->dpcd[0] >= 0x11)
 679                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 680                                       DP_SET_POWER, DP_SET_POWER_D0);
 681
 682         /* possibly enable downspread on the sink */
 683         if (dp_info->dpcd[3] & 0x1)
 684                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 685                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
 686         else
 687                 radeon_write_dpcd_reg(dp_info->radeon_connector,
 688                                       DP_DOWNSPREAD_CTRL, 0);
 689
 690         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
 691             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
 692                 radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1);
 693         }
 694
 695         /* set the lane count on the sink */
 696         tmp = dp_info->dp_lane_count;
 697         if (dp_info->dpcd[DP_DPCD_REV] >= 0x11 &&
 698             dp_info->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)
 699                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 700         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
 701
 702         /* set the link rate on the sink */
 703         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
 704         radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
 705
 706         /* start training on the source */
 707         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 708                 atombios_dig_encoder_setup(dp_info->encoder,
 709                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
 710         else
 711                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
 712                                           dp_info->dp_clock, dp_info->enc_id, 0);
 713
 714         /* disable the training pattern on the sink */
 715         radeon_write_dpcd_reg(dp_info->radeon_connector,
 716                               DP_TRAINING_PATTERN_SET,
 717                               DP_TRAINING_PATTERN_DISABLE);
 718
 719         return 0;
 720 }
 721
 722 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 723 {
 724         DRM_UDELAY(400);
 725
 726         /* disable the training pattern on the sink */
 727         radeon_write_dpcd_reg(dp_info->radeon_connector,
 728                               DP_TRAINING_PATTERN_SET,
 729                               DP_TRAINING_PATTERN_DISABLE);
 730
 731         /* disable the training pattern on the source */
 732         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
 733                 atombios_dig_encoder_setup(dp_info->encoder,
 734                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
 735         else
 736                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
 737                                           dp_info->dp_clock, dp_info->enc_id, 0);
 738
 739         return 0;
 740 }
 741
 742 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
 743 {
 744         bool clock_recovery;
 745         u8 voltage;
 746         int i;
 747
 748         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
 749         memset(dp_info->train_set, 0, 4);
 750         radeon_dp_update_vs_emph(dp_info);
 751
 752         DRM_UDELAY(400);
 753
 754         /* clock recovery loop */
 755         clock_recovery = false;
 756         dp_info->tries = 0;
 757         voltage = 0xff;
 758         while (1) {
 759                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
 760
 761                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 762                         DRM_ERROR("displayport link status failed\n");
 763                         break;
 764                 }
 765
 766                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 767                         clock_recovery = true;
 768                         break;
 769                 }
 770
 771                 for (i = 0; i < dp_info->dp_lane_count; i++) {
 772                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
 773                                 break;
 774                 }
 775                 if (i == dp_info->dp_lane_count) {
 776                         DRM_ERROR("clock recovery reached max voltage\n");
 777                         break;
 778                 }
 779
 780                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
 781                         ++dp_info->tries;
 782                         if (dp_info->tries == 5) {
 783                                 DRM_ERROR("clock recovery tried 5 times\n");
 784                                 break;
 785                         }
 786                 } else
 787                         dp_info->tries = 0;
 788
 789                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 790
 791                 /* Compute new train_set as requested by sink */
 792                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 793
 794                 radeon_dp_update_vs_emph(dp_info);
 795         }
 796         if (!clock_recovery) {
 797                 DRM_ERROR("clock recovery failed\n");
 798                 return -1;
 799         } else {
 800                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
 801                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 802                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 803                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
 804                 return 0;
 805         }
 806 }
 807
 808 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
 809 {
 810         bool channel_eq;
 811
 812         if (dp_info->tp3_supported)
 813                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
 814         else
 815                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
 816
 817         /* channel equalization loop */
 818         dp_info->tries = 0;
 819         channel_eq = false;
 820         while (1) {
 821                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
 822
 823                 if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) {
 824                         DRM_ERROR("displayport link status failed\n");
 825                         break;
 826                 }
 827
 828                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
 829                         channel_eq = true;
 830                         break;
 831                 }
 832
 833                 /* Try 5 times */
 834                 if (dp_info->tries > 5) {
 835                         DRM_ERROR("channel eq failed: 5 tries\n");
 836                         break;
 837                 }
 838
 839                 /* Compute new train_set as requested by sink */
 840                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
 841
 842                 radeon_dp_update_vs_emph(dp_info);
 843                 dp_info->tries++;
 844         }
 845
 846         if (!channel_eq) {
 847                 DRM_ERROR("channel eq failed\n");
 848                 return -1;
 849         } else {
 850                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
 851                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
 852                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
 853                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
 854                 return 0;
 855         }
 856 }
 857
 858 void radeon_dp_link_train(struct drm_encoder *encoder,
 859                           struct drm_connector *connector)
 860 {
 861         struct drm_device *dev = encoder->dev;
 862         struct radeon_device *rdev = dev->dev_private;
 863         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 864         struct radeon_encoder_atom_dig *dig;
 865         struct radeon_connector *radeon_connector;
 866         struct radeon_connector_atom_dig *dig_connector;
 867         struct radeon_dp_link_train_info dp_info;
 868         int index;
 869         u8 tmp, frev, crev;
 870
 871         if (!radeon_encoder->enc_priv)
 872                 return;
 873         dig = radeon_encoder->enc_priv;
 874
 875         radeon_connector = to_radeon_connector(connector);
 876         if (!radeon_connector->con_priv)
 877                 return;
 878         dig_connector = radeon_connector->con_priv;
 879
 880         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
 881             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
 882                 return;
 883
 884         /* DPEncoderService newer than 1.1 can't program properly the
 885          * training pattern. When facing such version use the
 886          * DIGXEncoderControl (X== 1 | 2)
 887          */
 888         dp_info.use_dpencoder = true;
 889         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
 890         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
 891                 if (crev > 1) {
 892                         dp_info.use_dpencoder = false;
 893                 }
 894         }
 895
 896         dp_info.enc_id = 0;
 897         if (dig->dig_encoder)
 898                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
 899         else
 900                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
 901         if (dig->linkb)
 902                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
 903         else
 904                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
 905
 906         tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
 907         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
 908                 dp_info.tp3_supported = true;
 909         else
 910                 dp_info.tp3_supported = false;
 911
 912         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
 913         dp_info.rdev = rdev;
 914         dp_info.encoder = encoder;
 915         dp_info.connector = connector;
 916         dp_info.radeon_connector = radeon_connector;
 917         dp_info.dp_lane_count = dig_connector->dp_lane_count;
 918         dp_info.dp_clock = dig_connector->dp_clock;
 919
 920         if (radeon_dp_link_train_init(&dp_info))
 921                 goto done;
 922         if (radeon_dp_link_train_cr(&dp_info))
 923                 goto done;
 924         if (radeon_dp_link_train_ce(&dp_info))
 925                 goto done;
 926 done:
 927         if (radeon_dp_link_train_finish(&dp_info))
 928                 return;
 929 }