drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / atombios_encoders.c
1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  *
26  * $FreeBSD: head/sys/dev/drm2/radeon/atombios_encoders.c 254885 2013-08-25 19:37:15Z dumbbell $
27  */
28
29 #include <drm/drmP.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <uapi_drm/radeon_drm.h>
32 #include "radeon.h"
33 #include "radeon_asic.h" /* Declares several prototypes; clang is pleased. */
34 #include "atom.h"
35
36 static u8
37 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
38 {
39         u8 backlight_level;
40         u32 bios_2_scratch;
41
42         if (rdev->family >= CHIP_R600)
43                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
44         else
45                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
46
47         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
48                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
49
50         return backlight_level;
51 }
52
53 static void
54 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
55                                        u8 backlight_level)
56 {
57         u32 bios_2_scratch;
58
59         if (rdev->family >= CHIP_R600)
60                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
61         else
62                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
63
64         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
65         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
66                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
67
68         if (rdev->family >= CHIP_R600)
69                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
70         else
71                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
72 }
73
74 u8
75 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
76 {
77         struct drm_device *dev = radeon_encoder->base.dev;
78         struct radeon_device *rdev = dev->dev_private;
79
80         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
81                 return 0;
82
83         return radeon_atom_get_backlight_level_from_reg(rdev);
84 }
85
86 void
87 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
88 {
89         struct drm_encoder *encoder = &radeon_encoder->base;
90         struct drm_device *dev = radeon_encoder->base.dev;
91         struct radeon_device *rdev = dev->dev_private;
92         struct radeon_encoder_atom_dig *dig;
93         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
94         int index;
95
96         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
97                 return;
98
99         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
100             radeon_encoder->enc_priv) {
101                 dig = radeon_encoder->enc_priv;
102                 dig->backlight_level = level;
103                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
104
105                 switch (radeon_encoder->encoder_id) {
106                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
107                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
108                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
109                         if (dig->backlight_level == 0) {
110                                 args.ucAction = ATOM_LCD_BLOFF;
111                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
112                         } else {
113                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
114                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
115                                 args.ucAction = ATOM_LCD_BLON;
116                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
117                         }
118                         break;
119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
120                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
123                         if (dig->backlight_level == 0)
124                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
125                         else {
126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
127                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
128                         }
129                         break;
130                 default:
131                         break;
132                 }
133         }
134 }
135
136 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
137
138 static u8 radeon_atom_bl_level(struct backlight_device *bd)
139 {
140         u8 level;
141
142         /* Convert brightness to hardware level */
143         if (bd->props.brightness < 0)
144                 level = 0;
145         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
146                 level = RADEON_MAX_BL_LEVEL;
147         else
148                 level = bd->props.brightness;
149
150         return level;
151 }
152
153 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
154 {
155         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
156         struct radeon_encoder *radeon_encoder = pdata->encoder;
157
158         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
159
160         return 0;
161 }
162
163 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
164 {
165         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
166         struct radeon_encoder *radeon_encoder = pdata->encoder;
167         struct drm_device *dev = radeon_encoder->base.dev;
168         struct radeon_device *rdev = dev->dev_private;
169
170         return radeon_atom_get_backlight_level_from_reg(rdev);
171 }
172
173 static const struct backlight_ops radeon_atom_backlight_ops = {
174         .get_brightness = radeon_atom_backlight_get_brightness,
175         .update_status  = radeon_atom_backlight_update_status,
176 };
177
178 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
179                                 struct drm_connector *drm_connector)
180 {
181         struct drm_device *dev = radeon_encoder->base.dev;
182         struct radeon_device *rdev = dev->dev_private;
183         struct backlight_device *bd;
184         struct backlight_properties props;
185         struct radeon_backlight_privdata *pdata;
186         struct radeon_encoder_atom_dig *dig;
187         u8 backlight_level;
188         char bl_name[16];
189
190         /* Mac laptops with multiple GPUs use the gmux driver for backlight
191          * so don't register a backlight device
192          */
193         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
194             (rdev->ddev->pci_device == 0x6741))
195                 return;
196
197         if (!radeon_encoder->enc_priv)
198                 return;
199
200         if (!rdev->is_atom_bios)
201                 return;
202
203         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
204                 return;
205
206         pdata = kmalloc(sizeof(struct radeon_backlight_privdata),
207                         M_DRM, M_WAITOK);
208         if (!pdata) {
209                 DRM_ERROR("Memory allocation failed\n");
210                 goto error;
211         }
212
213         memset(&props, 0, sizeof(props));
214         props.max_brightness = RADEON_MAX_BL_LEVEL;
215         props.type = BACKLIGHT_RAW;
216         snprintf(bl_name, sizeof(bl_name),
217                  "radeon_bl%d", dev->primary->index);
218         bd = backlight_device_register(bl_name, &drm_connector->kdev,
219                                        pdata, &radeon_atom_backlight_ops, &props);
220         if (IS_ERR(bd)) {
221                 DRM_ERROR("Backlight registration failed\n");
222                 goto error;
223         }
224
225         pdata->encoder = radeon_encoder;
226
227         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
228
229         dig = radeon_encoder->enc_priv;
230         dig->bl_dev = bd;
231
232         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
233         bd->props.power = FB_BLANK_UNBLANK;
234         backlight_update_status(bd);
235
236         DRM_INFO("radeon atom DIG backlight initialized\n");
237
238         return;
239
240 error:
241         drm_free(pdata, M_DRM);
242         return;
243 }
244
245 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
246 {
247         struct drm_device *dev = radeon_encoder->base.dev;
248         struct radeon_device *rdev = dev->dev_private;
249         struct backlight_device *bd = NULL;
250         struct radeon_encoder_atom_dig *dig;
251
252         if (!radeon_encoder->enc_priv)
253                 return;
254
255         if (!rdev->is_atom_bios)
256                 return;
257
258         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
259                 return;
260
261         dig = radeon_encoder->enc_priv;
262         bd = dig->bl_dev;
263         dig->bl_dev = NULL;
264
265         if (bd) {
266                 struct radeon_legacy_backlight_privdata *pdata;
267
268                 pdata = bl_get_data(bd);
269                 backlight_device_unregister(bd);
270                 drm_free(pdata, M_DRM);
271
272                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
273         }
274 }
275
276 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
277
278 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
279                                 struct drm_connector *drm_connector)
280 {
281 }
282
283 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
284 {
285 }
286
287 #endif
288
289
290 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
291 {
292         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
293         switch (radeon_encoder->encoder_id) {
294         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
295         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
296         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
297         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
298         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
299         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
300         case ENCODER_OBJECT_ID_INTERNAL_DDI:
301         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
302         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
303         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
304         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
305         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
306                 return true;
307         default:
308                 return false;
309         }
310 }
311
312 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
313                                    const struct drm_display_mode *mode,
314                                    struct drm_display_mode *adjusted_mode)
315 {
316         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
317         struct drm_device *dev = encoder->dev;
318         struct radeon_device *rdev = dev->dev_private;
319
320         /* set the active encoder to connector routing */
321         radeon_encoder_set_active_device(encoder);
322         drm_mode_set_crtcinfo(adjusted_mode, 0);
323
324         /* hw bug */
325         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
326             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
327                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
328
329         /* get the native mode for LVDS */
330         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
331                 radeon_panel_mode_fixup(encoder, adjusted_mode);
332
333         /* get the native mode for TV */
334         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
335                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
336                 if (tv_dac) {
337                         if (tv_dac->tv_std == TV_STD_NTSC ||
338                             tv_dac->tv_std == TV_STD_NTSC_J ||
339                             tv_dac->tv_std == TV_STD_PAL_M)
340                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
341                         else
342                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
343                 }
344         }
345
346         if (ASIC_IS_DCE3(rdev) &&
347             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
348              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
349                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
350                 radeon_dp_set_link_config(connector, adjusted_mode);
351         }
352
353         return true;
354 }
355
356 static void
357 atombios_dac_setup(struct drm_encoder *encoder, int action)
358 {
359         struct drm_device *dev = encoder->dev;
360         struct radeon_device *rdev = dev->dev_private;
361         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
362         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
363         int index = 0;
364         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
365
366         memset(&args, 0, sizeof(args));
367
368         switch (radeon_encoder->encoder_id) {
369         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
370         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
371                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
372                 break;
373         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
374         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
375                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
376                 break;
377         }
378
379         args.ucAction = action;
380
381         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
382                 args.ucDacStandard = ATOM_DAC1_PS2;
383         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
384                 args.ucDacStandard = ATOM_DAC1_CV;
385         else {
386                 switch (dac_info->tv_std) {
387                 case TV_STD_PAL:
388                 case TV_STD_PAL_M:
389                 case TV_STD_SCART_PAL:
390                 case TV_STD_SECAM:
391                 case TV_STD_PAL_CN:
392                         args.ucDacStandard = ATOM_DAC1_PAL;
393                         break;
394                 case TV_STD_NTSC:
395                 case TV_STD_NTSC_J:
396                 case TV_STD_PAL_60:
397                 default:
398                         args.ucDacStandard = ATOM_DAC1_NTSC;
399                         break;
400                 }
401         }
402         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
403
404         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
405
406 }
407
408 static void
409 atombios_tv_setup(struct drm_encoder *encoder, int action)
410 {
411         struct drm_device *dev = encoder->dev;
412         struct radeon_device *rdev = dev->dev_private;
413         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
414         TV_ENCODER_CONTROL_PS_ALLOCATION args;
415         int index = 0;
416         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
417
418         memset(&args, 0, sizeof(args));
419
420         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
421
422         args.sTVEncoder.ucAction = action;
423
424         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
425                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
426         else {
427                 switch (dac_info->tv_std) {
428                 case TV_STD_NTSC:
429                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
430                         break;
431                 case TV_STD_PAL:
432                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
433                         break;
434                 case TV_STD_PAL_M:
435                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
436                         break;
437                 case TV_STD_PAL_60:
438                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
439                         break;
440                 case TV_STD_NTSC_J:
441                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
442                         break;
443                 case TV_STD_SCART_PAL:
444                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
445                         break;
446                 case TV_STD_SECAM:
447                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
448                         break;
449                 case TV_STD_PAL_CN:
450                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
451                         break;
452                 default:
453                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
454                         break;
455                 }
456         }
457
458         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
459
460         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
461
462 }
463
464 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
465 {
466         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
467         int bpc = 8;
468
469         if (connector)
470                 bpc = radeon_get_monitor_bpc(connector);
471
472         switch (bpc) {
473         case 0:
474                 return PANEL_BPC_UNDEFINE;
475         case 6:
476                 return PANEL_6BIT_PER_COLOR;
477         case 8:
478         default:
479                 return PANEL_8BIT_PER_COLOR;
480         case 10:
481                 return PANEL_10BIT_PER_COLOR;
482         case 12:
483                 return PANEL_12BIT_PER_COLOR;
484         case 16:
485                 return PANEL_16BIT_PER_COLOR;
486         }
487 }
488
489 union dvo_encoder_control {
490         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
491         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
492         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
493         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
494 };
495
496 void
497 atombios_dvo_setup(struct drm_encoder *encoder, int action)
498 {
499         struct drm_device *dev = encoder->dev;
500         struct radeon_device *rdev = dev->dev_private;
501         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
502         union dvo_encoder_control args;
503         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
504         uint8_t frev, crev;
505
506         memset(&args, 0, sizeof(args));
507
508         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
509                 return;
510
511         /* some R4xx chips have the wrong frev */
512         if (rdev->family <= CHIP_RV410)
513                 frev = 1;
514
515         switch (frev) {
516         case 1:
517                 switch (crev) {
518                 case 1:
519                         /* R4xx, R5xx */
520                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
521
522                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
523                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
524
525                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
526                         break;
527                 case 2:
528                         /* RS600/690/740 */
529                         args.dvo.sDVOEncoder.ucAction = action;
530                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
531                         /* DFP1, CRT1, TV1 depending on the type of port */
532                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
533
534                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
535                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
536                         break;
537                 case 3:
538                         /* R6xx */
539                         args.dvo_v3.ucAction = action;
540                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
541                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
542                         break;
543                 case 4:
544                         /* DCE8 */
545                         args.dvo_v4.ucAction = action;
546                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
547                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
548                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
549                         break;
550                 default:
551                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
552                         break;
553                 }
554                 break;
555         default:
556                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
557                 break;
558         }
559
560         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
561 }
562
563 union lvds_encoder_control {
564         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
565         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
566 };
567
568 void
569 atombios_digital_setup(struct drm_encoder *encoder, int action)
570 {
571         struct drm_device *dev = encoder->dev;
572         struct radeon_device *rdev = dev->dev_private;
573         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
574         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
575         union lvds_encoder_control args;
576         int index = 0;
577         int hdmi_detected = 0;
578         uint8_t frev, crev;
579
580         if (!dig)
581                 return;
582
583         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
584                 hdmi_detected = 1;
585
586         memset(&args, 0, sizeof(args));
587
588         switch (radeon_encoder->encoder_id) {
589         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
590                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
591                 break;
592         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
593         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
594                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
595                 break;
596         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
597                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
598                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
599                 else
600                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
601                 break;
602         }
603
604         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
605                 return;
606
607         switch (frev) {
608         case 1:
609         case 2:
610                 switch (crev) {
611                 case 1:
612                         args.v1.ucMisc = 0;
613                         args.v1.ucAction = action;
614                         if (hdmi_detected)
615                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
616                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
617                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
618                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
619                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
620                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
621                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
622                         } else {
623                                 if (dig->linkb)
624                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
625                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
626                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
627                                 /*if (pScrn->rgbBits == 8) */
628                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
629                         }
630                         break;
631                 case 2:
632                 case 3:
633                         args.v2.ucMisc = 0;
634                         args.v2.ucAction = action;
635                         if (crev == 3) {
636                                 if (dig->coherent_mode)
637                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
638                         }
639                         if (hdmi_detected)
640                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
641                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
642                         args.v2.ucTruncate = 0;
643                         args.v2.ucSpatial = 0;
644                         args.v2.ucTemporal = 0;
645                         args.v2.ucFRC = 0;
646                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
647                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
648                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
649                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
650                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
651                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
652                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
653                                 }
654                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
655                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
656                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
657                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
658                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
659                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
660                                 }
661                         } else {
662                                 if (dig->linkb)
663                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
664                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
665                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
666                         }
667                         break;
668                 default:
669                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
670                         break;
671                 }
672                 break;
673         default:
674                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
675                 break;
676         }
677
678         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
679 }
680
681 int
682 atombios_get_encoder_mode(struct drm_encoder *encoder)
683 {
684         struct drm_device *dev = encoder->dev;
685         struct radeon_device *rdev = dev->dev_private;
686         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
687         struct drm_connector *connector;
688         struct radeon_connector *radeon_connector;
689         struct radeon_connector_atom_dig *dig_connector;
690
691         /* dp bridges are always DP */
692         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
693                 return ATOM_ENCODER_MODE_DP;
694
695         /* DVO is always DVO */
696         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
697             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
698                 return ATOM_ENCODER_MODE_DVO;
699
700         connector = radeon_get_connector_for_encoder(encoder);
701         /* if we don't have an active device yet, just use one of
702          * the connectors tied to the encoder.
703          */
704         if (!connector)
705                 connector = radeon_get_connector_for_encoder_init(encoder);
706         radeon_connector = to_radeon_connector(connector);
707
708         switch (connector->connector_type) {
709         case DRM_MODE_CONNECTOR_DVII:
710         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
711                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
712                     radeon_audio &&
713                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
714                         return ATOM_ENCODER_MODE_HDMI;
715                 else if (radeon_connector->use_digital)
716                         return ATOM_ENCODER_MODE_DVI;
717                 else
718                         return ATOM_ENCODER_MODE_CRT;
719                 break;
720         case DRM_MODE_CONNECTOR_DVID:
721         case DRM_MODE_CONNECTOR_HDMIA:
722         default:
723                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
724                     radeon_audio &&
725                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
726                         return ATOM_ENCODER_MODE_HDMI;
727                 else
728                         return ATOM_ENCODER_MODE_DVI;
729                 break;
730         case DRM_MODE_CONNECTOR_LVDS:
731                 return ATOM_ENCODER_MODE_LVDS;
732                 break;
733         case DRM_MODE_CONNECTOR_DisplayPort:
734                 dig_connector = radeon_connector->con_priv;
735                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
736                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
737                         return ATOM_ENCODER_MODE_DP;
738                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
739                          radeon_audio &&
740                          !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
741                         return ATOM_ENCODER_MODE_HDMI;
742                 else
743                         return ATOM_ENCODER_MODE_DVI;
744                 break;
745         case DRM_MODE_CONNECTOR_eDP:
746                 return ATOM_ENCODER_MODE_DP;
747         case DRM_MODE_CONNECTOR_DVIA:
748         case DRM_MODE_CONNECTOR_VGA:
749                 return ATOM_ENCODER_MODE_CRT;
750                 break;
751         case DRM_MODE_CONNECTOR_Composite:
752         case DRM_MODE_CONNECTOR_SVIDEO:
753         case DRM_MODE_CONNECTOR_9PinDIN:
754                 /* fix me */
755                 return ATOM_ENCODER_MODE_TV;
756                 /*return ATOM_ENCODER_MODE_CV;*/
757                 break;
758         }
759 }
760
761 /*
762  * DIG Encoder/Transmitter Setup
763  *
764  * DCE 3.0/3.1
765  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
766  * Supports up to 3 digital outputs
767  * - 2 DIG encoder blocks.
768  * DIG1 can drive UNIPHY link A or link B
769  * DIG2 can drive UNIPHY link B or LVTMA
770  *
771  * DCE 3.2
772  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
773  * Supports up to 5 digital outputs
774  * - 2 DIG encoder blocks.
775  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
776  *
777  * DCE 4.0/5.0/6.0
778  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
779  * Supports up to 6 digital outputs
780  * - 6 DIG encoder blocks.
781  * - DIG to PHY mapping is hardcoded
782  * DIG1 drives UNIPHY0 link A, A+B
783  * DIG2 drives UNIPHY0 link B
784  * DIG3 drives UNIPHY1 link A, A+B
785  * DIG4 drives UNIPHY1 link B
786  * DIG5 drives UNIPHY2 link A, A+B
787  * DIG6 drives UNIPHY2 link B
788  *
789  * DCE 4.1
790  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
791  * Supports up to 6 digital outputs
792  * - 2 DIG encoder blocks.
793  * llano
794  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
795  * ontario
796  * DIG1 drives UNIPHY0/1/2 link A
797  * DIG2 drives UNIPHY0/1/2 link B
798  *
799  * Routing
800  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
801  * Examples:
802  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
803  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
804  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
805  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
806  */
807
808 union dig_encoder_control {
809         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
810         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
811         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
812         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
813 };
814
815 void
816 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
817 {
818         struct drm_device *dev = encoder->dev;
819         struct radeon_device *rdev = dev->dev_private;
820         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
821         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
822         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
823         union dig_encoder_control args;
824         int index = 0;
825         uint8_t frev, crev;
826         int dp_clock = 0;
827         int dp_lane_count = 0;
828         int hpd_id = RADEON_HPD_NONE;
829
830         if (connector) {
831                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
832                 struct radeon_connector_atom_dig *dig_connector =
833                         radeon_connector->con_priv;
834
835                 dp_clock = dig_connector->dp_clock;
836                 dp_lane_count = dig_connector->dp_lane_count;
837                 hpd_id = radeon_connector->hpd.hpd;
838         }
839
840         /* no dig encoder assigned */
841         if (dig->dig_encoder == -1)
842                 return;
843
844         memset(&args, 0, sizeof(args));
845
846         if (ASIC_IS_DCE4(rdev))
847                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
848         else {
849                 if (dig->dig_encoder)
850                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
851                 else
852                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
853         }
854
855         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
856                 return;
857
858         switch (frev) {
859         case 1:
860                 switch (crev) {
861                 case 1:
862                         args.v1.ucAction = action;
863                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
864                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
865                                 args.v3.ucPanelMode = panel_mode;
866                         else
867                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
868
869                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
870                                 args.v1.ucLaneNum = dp_lane_count;
871                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
872                                 args.v1.ucLaneNum = 8;
873                         else
874                                 args.v1.ucLaneNum = 4;
875
876                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
877                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
878                         switch (radeon_encoder->encoder_id) {
879                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
880                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
881                                 break;
882                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
883                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
884                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
885                                 break;
886                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
887                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
888                                 break;
889                         }
890                         if (dig->linkb)
891                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
892                         else
893                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
894                         break;
895                 case 2:
896                 case 3:
897                         args.v3.ucAction = action;
898                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
899                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
900                                 args.v3.ucPanelMode = panel_mode;
901                         else
902                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
903
904                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
905                                 args.v3.ucLaneNum = dp_lane_count;
906                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
907                                 args.v3.ucLaneNum = 8;
908                         else
909                                 args.v3.ucLaneNum = 4;
910
911                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
912                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
913                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
914                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
915                         break;
916                 case 4:
917                         args.v4.ucAction = action;
918                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
919                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
920                                 args.v4.ucPanelMode = panel_mode;
921                         else
922                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
923
924                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
925                                 args.v4.ucLaneNum = dp_lane_count;
926                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
927                                 args.v4.ucLaneNum = 8;
928                         else
929                                 args.v4.ucLaneNum = 4;
930
931                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
932                                 if (dp_clock == 540000)
933                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
934                                 else if (dp_clock == 324000)
935                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
936                                 else if (dp_clock == 270000)
937                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
938                                 else
939                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
940                         }
941                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
942                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
943                         if (hpd_id == RADEON_HPD_NONE)
944                                 args.v4.ucHPD_ID = 0;
945                         else
946                                 args.v4.ucHPD_ID = hpd_id + 1;
947                         break;
948                 default:
949                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
950                         break;
951                 }
952                 break;
953         default:
954                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
955                 break;
956         }
957
958         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
959
960 }
961
962 union dig_transmitter_control {
963         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
964         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
965         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
966         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
967         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
968 };
969
970 void
971 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
972 {
973         struct drm_device *dev = encoder->dev;
974         struct radeon_device *rdev = dev->dev_private;
975         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
976         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
977         struct drm_connector *connector;
978         union dig_transmitter_control args;
979         int index = 0;
980         uint8_t frev, crev;
981         bool is_dp = false;
982         int pll_id = 0;
983         int dp_clock = 0;
984         int dp_lane_count = 0;
985         int connector_object_id = 0;
986         int igp_lane_info = 0;
987         int dig_encoder = dig->dig_encoder;
988         int hpd_id = RADEON_HPD_NONE;
989
990         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
991                 connector = radeon_get_connector_for_encoder_init(encoder);
992                 /* just needed to avoid bailing in the encoder check.  the encoder
993                  * isn't used for init
994                  */
995                 dig_encoder = 0;
996         } else
997                 connector = radeon_get_connector_for_encoder(encoder);
998
999         if (connector) {
1000                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1001                 struct radeon_connector_atom_dig *dig_connector =
1002                         radeon_connector->con_priv;
1003
1004                 hpd_id = radeon_connector->hpd.hpd;
1005                 dp_clock = dig_connector->dp_clock;
1006                 dp_lane_count = dig_connector->dp_lane_count;
1007                 connector_object_id =
1008                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1009                 igp_lane_info = dig_connector->igp_lane_info;
1010         }
1011
1012         if (encoder->crtc) {
1013                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1014                 pll_id = radeon_crtc->pll_id;
1015         }
1016
1017         /* no dig encoder assigned */
1018         if (dig_encoder == -1)
1019                 return;
1020
1021         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1022                 is_dp = true;
1023
1024         memset(&args, 0, sizeof(args));
1025
1026         switch (radeon_encoder->encoder_id) {
1027         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1028                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1029                 break;
1030         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1031         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1032         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1033         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1034                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1035                 break;
1036         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1037                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1038                 break;
1039         }
1040
1041         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1042                 return;
1043
1044         switch (frev) {
1045         case 1:
1046                 switch (crev) {
1047                 case 1:
1048                         args.v1.ucAction = action;
1049                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1050                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1051                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1052                                 args.v1.asMode.ucLaneSel = lane_num;
1053                                 args.v1.asMode.ucLaneSet = lane_set;
1054                         } else {
1055                                 if (is_dp)
1056                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1057                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1058                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1059                                 else
1060                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1061                         }
1062
1063                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1064
1065                         if (dig_encoder)
1066                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1067                         else
1068                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1069
1070                         if ((rdev->flags & RADEON_IS_IGP) &&
1071                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1072                                 if (is_dp ||
1073                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1074                                         if (igp_lane_info & 0x1)
1075                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1076                                         else if (igp_lane_info & 0x2)
1077                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1078                                         else if (igp_lane_info & 0x4)
1079                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1080                                         else if (igp_lane_info & 0x8)
1081                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1082                                 } else {
1083                                         if (igp_lane_info & 0x3)
1084                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1085                                         else if (igp_lane_info & 0xc)
1086                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1087                                 }
1088                         }
1089
1090                         if (dig->linkb)
1091                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1092                         else
1093                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1094
1095                         if (is_dp)
1096                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1097                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1098                                 if (dig->coherent_mode)
1099                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1100                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1101                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1102                         }
1103                         break;
1104                 case 2:
1105                         args.v2.ucAction = action;
1106                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1107                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1108                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1109                                 args.v2.asMode.ucLaneSel = lane_num;
1110                                 args.v2.asMode.ucLaneSet = lane_set;
1111                         } else {
1112                                 if (is_dp)
1113                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1114                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1115                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1116                                 else
1117                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1118                         }
1119
1120                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1121                         if (dig->linkb)
1122                                 args.v2.acConfig.ucLinkSel = 1;
1123
1124                         switch (radeon_encoder->encoder_id) {
1125                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1126                                 args.v2.acConfig.ucTransmitterSel = 0;
1127                                 break;
1128                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1129                                 args.v2.acConfig.ucTransmitterSel = 1;
1130                                 break;
1131                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1132                                 args.v2.acConfig.ucTransmitterSel = 2;
1133                                 break;
1134                         }
1135
1136                         if (is_dp) {
1137                                 args.v2.acConfig.fCoherentMode = 1;
1138                                 args.v2.acConfig.fDPConnector = 1;
1139                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1140                                 if (dig->coherent_mode)
1141                                         args.v2.acConfig.fCoherentMode = 1;
1142                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1143                                         args.v2.acConfig.fDualLinkConnector = 1;
1144                         }
1145                         break;
1146                 case 3:
1147                         args.v3.ucAction = action;
1148                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1149                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1150                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1151                                 args.v3.asMode.ucLaneSel = lane_num;
1152                                 args.v3.asMode.ucLaneSet = lane_set;
1153                         } else {
1154                                 if (is_dp)
1155                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1156                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1157                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1158                                 else
1159                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1160                         }
1161
1162                         if (is_dp)
1163                                 args.v3.ucLaneNum = dp_lane_count;
1164                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1165                                 args.v3.ucLaneNum = 8;
1166                         else
1167                                 args.v3.ucLaneNum = 4;
1168
1169                         if (dig->linkb)
1170                                 args.v3.acConfig.ucLinkSel = 1;
1171                         if (dig_encoder & 1)
1172                                 args.v3.acConfig.ucEncoderSel = 1;
1173
1174                         /* Select the PLL for the PHY
1175                          * DP PHY should be clocked from external src if there is
1176                          * one.
1177                          */
1178                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1179                         if (is_dp && rdev->clock.dp_extclk)
1180                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1181                         else
1182                                 args.v3.acConfig.ucRefClkSource = pll_id;
1183
1184                         switch (radeon_encoder->encoder_id) {
1185                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1186                                 args.v3.acConfig.ucTransmitterSel = 0;
1187                                 break;
1188                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1189                                 args.v3.acConfig.ucTransmitterSel = 1;
1190                                 break;
1191                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1192                                 args.v3.acConfig.ucTransmitterSel = 2;
1193                                 break;
1194                         }
1195
1196                         if (is_dp)
1197                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1198                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1199                                 if (dig->coherent_mode)
1200                                         args.v3.acConfig.fCoherentMode = 1;
1201                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1202                                         args.v3.acConfig.fDualLinkConnector = 1;
1203                         }
1204                         break;
1205                 case 4:
1206                         args.v4.ucAction = action;
1207                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1208                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1209                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1210                                 args.v4.asMode.ucLaneSel = lane_num;
1211                                 args.v4.asMode.ucLaneSet = lane_set;
1212                         } else {
1213                                 if (is_dp)
1214                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1215                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1216                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1217                                 else
1218                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1219                         }
1220
1221                         if (is_dp)
1222                                 args.v4.ucLaneNum = dp_lane_count;
1223                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1224                                 args.v4.ucLaneNum = 8;
1225                         else
1226                                 args.v4.ucLaneNum = 4;
1227
1228                         if (dig->linkb)
1229                                 args.v4.acConfig.ucLinkSel = 1;
1230                         if (dig_encoder & 1)
1231                                 args.v4.acConfig.ucEncoderSel = 1;
1232
1233                         /* Select the PLL for the PHY
1234                          * DP PHY should be clocked from external src if there is
1235                          * one.
1236                          */
1237                         /* On DCE5 DCPLL usually generates the DP ref clock */
1238                         if (is_dp) {
1239                                 if (rdev->clock.dp_extclk)
1240                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1241                                 else
1242                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1243                         } else
1244                                 args.v4.acConfig.ucRefClkSource = pll_id;
1245
1246                         switch (radeon_encoder->encoder_id) {
1247                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1248                                 args.v4.acConfig.ucTransmitterSel = 0;
1249                                 break;
1250                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1251                                 args.v4.acConfig.ucTransmitterSel = 1;
1252                                 break;
1253                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1254                                 args.v4.acConfig.ucTransmitterSel = 2;
1255                                 break;
1256                         }
1257
1258                         if (is_dp)
1259                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1260                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1261                                 if (dig->coherent_mode)
1262                                         args.v4.acConfig.fCoherentMode = 1;
1263                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1264                                         args.v4.acConfig.fDualLinkConnector = 1;
1265                         }
1266                         break;
1267                 case 5:
1268                         args.v5.ucAction = action;
1269                         if (is_dp)
1270                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1271                         else
1272                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1273
1274                         switch (radeon_encoder->encoder_id) {
1275                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1276                                 if (dig->linkb)
1277                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1278                                 else
1279                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1280                                 break;
1281                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1282                                 if (dig->linkb)
1283                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1284                                 else
1285                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1286                                 break;
1287                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1288                                 if (dig->linkb)
1289                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1290                                 else
1291                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1292                                 break;
1293                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1294                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1295                                 break;
1296                         }
1297                         if (is_dp)
1298                                 args.v5.ucLaneNum = dp_lane_count;
1299                         else if (radeon_encoder->pixel_clock > 165000)
1300                                 args.v5.ucLaneNum = 8;
1301                         else
1302                                 args.v5.ucLaneNum = 4;
1303                         args.v5.ucConnObjId = connector_object_id;
1304                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1305
1306                         if (is_dp && rdev->clock.dp_extclk)
1307                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1308                         else
1309                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1310
1311                         if (is_dp)
1312                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1313                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1314                                 if (dig->coherent_mode)
1315                                         args.v5.asConfig.ucCoherentMode = 1;
1316                         }
1317                         if (hpd_id == RADEON_HPD_NONE)
1318                                 args.v5.asConfig.ucHPDSel = 0;
1319                         else
1320                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1321                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1322                         args.v5.ucDPLaneSet = lane_set;
1323                         break;
1324                 default:
1325                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1326                         break;
1327                 }
1328                 break;
1329         default:
1330                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1331                 break;
1332         }
1333
1334         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1335 }
1336
1337 bool
1338 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1339 {
1340         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1341         struct drm_device *dev = radeon_connector->base.dev;
1342         struct radeon_device *rdev = dev->dev_private;
1343         union dig_transmitter_control args;
1344         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1345         uint8_t frev, crev;
1346
1347         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1348                 goto done;
1349
1350         if (!ASIC_IS_DCE4(rdev))
1351                 goto done;
1352
1353         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1354             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1355                 goto done;
1356
1357         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1358                 goto done;
1359
1360         memset(&args, 0, sizeof(args));
1361
1362         args.v1.ucAction = action;
1363
1364         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1365
1366         /* wait for the panel to power up */
1367         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1368                 int i;
1369
1370                 for (i = 0; i < 300; i++) {
1371                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1372                                 return true;
1373                         DRM_MDELAY(1);
1374                 }
1375                 return false;
1376         }
1377 done:
1378         return true;
1379 }
1380
1381 union external_encoder_control {
1382         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1383         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1384 };
1385
1386 static void
1387 atombios_external_encoder_setup(struct drm_encoder *encoder,
1388                                 struct drm_encoder *ext_encoder,
1389                                 int action)
1390 {
1391         struct drm_device *dev = encoder->dev;
1392         struct radeon_device *rdev = dev->dev_private;
1393         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1394         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1395         union external_encoder_control args;
1396         struct drm_connector *connector;
1397         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1398         u8 frev, crev;
1399         int dp_clock = 0;
1400         int dp_lane_count = 0;
1401         int connector_object_id = 0;
1402         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1403
1404         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1405                 connector = radeon_get_connector_for_encoder_init(encoder);
1406         else
1407                 connector = radeon_get_connector_for_encoder(encoder);
1408
1409         if (connector) {
1410                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1411                 struct radeon_connector_atom_dig *dig_connector =
1412                         radeon_connector->con_priv;
1413
1414                 dp_clock = dig_connector->dp_clock;
1415                 dp_lane_count = dig_connector->dp_lane_count;
1416                 connector_object_id =
1417                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1418         }
1419
1420         memset(&args, 0, sizeof(args));
1421
1422         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1423                 return;
1424
1425         switch (frev) {
1426         case 1:
1427                 /* no params on frev 1 */
1428                 break;
1429         case 2:
1430                 switch (crev) {
1431                 case 1:
1432                 case 2:
1433                         args.v1.sDigEncoder.ucAction = action;
1434                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1435                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1436
1437                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1438                                 if (dp_clock == 270000)
1439                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1440                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1441                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1442                                 args.v1.sDigEncoder.ucLaneNum = 8;
1443                         else
1444                                 args.v1.sDigEncoder.ucLaneNum = 4;
1445                         break;
1446                 case 3:
1447                         args.v3.sExtEncoder.ucAction = action;
1448                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1449                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1450                         else
1451                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1452                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1453
1454                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1455                                 if (dp_clock == 270000)
1456                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1457                                 else if (dp_clock == 540000)
1458                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1459                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1460                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1461                                 args.v3.sExtEncoder.ucLaneNum = 8;
1462                         else
1463                                 args.v3.sExtEncoder.ucLaneNum = 4;
1464                         switch (ext_enum) {
1465                         case GRAPH_OBJECT_ENUM_ID1:
1466                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1467                                 break;
1468                         case GRAPH_OBJECT_ENUM_ID2:
1469                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1470                                 break;
1471                         case GRAPH_OBJECT_ENUM_ID3:
1472                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1473                                 break;
1474                         }
1475                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1476                         break;
1477                 default:
1478                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1479                         return;
1480                 }
1481                 break;
1482         default:
1483                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1484                 return;
1485         }
1486         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1487 }
1488
1489 static void
1490 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1491 {
1492         struct drm_device *dev = encoder->dev;
1493         struct radeon_device *rdev = dev->dev_private;
1494         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1495         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1496         ENABLE_YUV_PS_ALLOCATION args;
1497         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1498         uint32_t temp, reg;
1499
1500         memset(&args, 0, sizeof(args));
1501
1502         if (rdev->family >= CHIP_R600)
1503                 reg = R600_BIOS_3_SCRATCH;
1504         else
1505                 reg = RADEON_BIOS_3_SCRATCH;
1506
1507         /* XXX: fix up scratch reg handling */
1508         temp = RREG32(reg);
1509         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1510                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1511                              (radeon_crtc->crtc_id << 18)));
1512         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1513                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1514         else
1515                 WREG32(reg, 0);
1516
1517         if (enable)
1518                 args.ucEnable = ATOM_ENABLE;
1519         args.ucCRTC = radeon_crtc->crtc_id;
1520
1521         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1522
1523         WREG32(reg, temp);
1524 }
1525
1526 static void
1527 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1528 {
1529         struct drm_device *dev = encoder->dev;
1530         struct radeon_device *rdev = dev->dev_private;
1531         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1532         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1533         int index = 0;
1534
1535         memset(&args, 0, sizeof(args));
1536
1537         switch (radeon_encoder->encoder_id) {
1538         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1539         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1540                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1541                 break;
1542         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1543         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1544         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1545                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1546                 break;
1547         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1548                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1549                 break;
1550         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1551                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1552                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1553                 else
1554                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1555                 break;
1556         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1557         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1558                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1559                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1560                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1561                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1562                 else
1563                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1564                 break;
1565         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1566         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1567                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1568                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1569                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1570                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1571                 else
1572                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1573                 break;
1574         default:
1575                 return;
1576         }
1577
1578         switch (mode) {
1579         case DRM_MODE_DPMS_ON:
1580                 args.ucAction = ATOM_ENABLE;
1581                 /* workaround for DVOOutputControl on some RS690 systems */
1582                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1583                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1584                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1585                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1586                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1587                 } else
1588                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1589                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1590                         args.ucAction = ATOM_LCD_BLON;
1591                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1592                 }
1593                 break;
1594         case DRM_MODE_DPMS_STANDBY:
1595         case DRM_MODE_DPMS_SUSPEND:
1596         case DRM_MODE_DPMS_OFF:
1597                 args.ucAction = ATOM_DISABLE;
1598                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1599                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1600                         args.ucAction = ATOM_LCD_BLOFF;
1601                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1602                 }
1603                 break;
1604         }
1605 }
1606
1607 static void
1608 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1609 {
1610         struct drm_device *dev = encoder->dev;
1611         struct radeon_device *rdev = dev->dev_private;
1612         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1613         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1614         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1615         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1616         struct radeon_connector *radeon_connector = NULL;
1617         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1618
1619         if (connector) {
1620                 radeon_connector = to_radeon_connector(connector);
1621                 radeon_dig_connector = radeon_connector->con_priv;
1622         }
1623
1624         switch (mode) {
1625         case DRM_MODE_DPMS_ON:
1626                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1627                         if (!connector)
1628                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1629                         else
1630                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1631
1632                         /* setup and enable the encoder */
1633                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1634                         atombios_dig_encoder_setup(encoder,
1635                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1636                                                    dig->panel_mode);
1637                         if (ext_encoder) {
1638                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1639                                         atombios_external_encoder_setup(encoder, ext_encoder,
1640                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1641                         }
1642                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1643                 } else if (ASIC_IS_DCE4(rdev)) {
1644                         /* setup and enable the encoder */
1645                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1646                         /* enable the transmitter */
1647                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1648                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1649                 } else {
1650                         /* setup and enable the encoder and transmitter */
1651                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1652                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1653                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1654                         /* some early dce3.2 boards have a bug in their transmitter control table */
1655                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1656                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1657                 }
1658                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1659                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1660                                 atombios_set_edp_panel_power(connector,
1661                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1662                                 radeon_dig_connector->edp_on = true;
1663                         }
1664                         radeon_dp_link_train(encoder, connector);
1665                         if (ASIC_IS_DCE4(rdev))
1666                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1667                 }
1668                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1669                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1670                 break;
1671         case DRM_MODE_DPMS_STANDBY:
1672         case DRM_MODE_DPMS_SUSPEND:
1673         case DRM_MODE_DPMS_OFF:
1674                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1675                         /* disable the transmitter */
1676                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1677                 } else if (ASIC_IS_DCE4(rdev)) {
1678                         /* disable the transmitter */
1679                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1680                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1681                 } else {
1682                         /* disable the encoder and transmitter */
1683                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1684                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1685                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1686                 }
1687                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1688                         if (ASIC_IS_DCE4(rdev))
1689                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1690                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1691                                 atombios_set_edp_panel_power(connector,
1692                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1693                                 radeon_dig_connector->edp_on = false;
1694                         }
1695                 }
1696                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1697                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1698                 break;
1699         }
1700 }
1701
1702 static void
1703 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1704                              struct drm_encoder *ext_encoder,
1705                              int mode)
1706 {
1707         struct drm_device *dev = encoder->dev;
1708         struct radeon_device *rdev = dev->dev_private;
1709
1710         switch (mode) {
1711         case DRM_MODE_DPMS_ON:
1712         default:
1713                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1714                         atombios_external_encoder_setup(encoder, ext_encoder,
1715                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1716                         atombios_external_encoder_setup(encoder, ext_encoder,
1717                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1718                 } else
1719                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1720                 break;
1721         case DRM_MODE_DPMS_STANDBY:
1722         case DRM_MODE_DPMS_SUSPEND:
1723         case DRM_MODE_DPMS_OFF:
1724                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1725                         atombios_external_encoder_setup(encoder, ext_encoder,
1726                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1727                         atombios_external_encoder_setup(encoder, ext_encoder,
1728                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1729                 } else
1730                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1731                 break;
1732         }
1733 }
1734
1735 static void
1736 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1737 {
1738         struct drm_device *dev = encoder->dev;
1739         struct radeon_device *rdev = dev->dev_private;
1740         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1741         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1742
1743         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1744                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1745                   radeon_encoder->active_device);
1746         switch (radeon_encoder->encoder_id) {
1747         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1748         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1749         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1750         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1751         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1752         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1753         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1754         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1755                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1756                 break;
1757         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1758         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1759         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1760         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1761         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1762                 radeon_atom_encoder_dpms_dig(encoder, mode);
1763                 break;
1764         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1765                 if (ASIC_IS_DCE5(rdev)) {
1766                         switch (mode) {
1767                         case DRM_MODE_DPMS_ON:
1768                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1769                                 break;
1770                         case DRM_MODE_DPMS_STANDBY:
1771                         case DRM_MODE_DPMS_SUSPEND:
1772                         case DRM_MODE_DPMS_OFF:
1773                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1774                                 break;
1775                         }
1776                 } else if (ASIC_IS_DCE3(rdev))
1777                         radeon_atom_encoder_dpms_dig(encoder, mode);
1778                 else
1779                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1780                 break;
1781         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1782         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1783                 if (ASIC_IS_DCE5(rdev)) {
1784                         switch (mode) {
1785                         case DRM_MODE_DPMS_ON:
1786                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1787                                 break;
1788                         case DRM_MODE_DPMS_STANDBY:
1789                         case DRM_MODE_DPMS_SUSPEND:
1790                         case DRM_MODE_DPMS_OFF:
1791                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1792                                 break;
1793                         }
1794                 } else
1795                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1796                 break;
1797         default:
1798                 return;
1799         }
1800
1801         if (ext_encoder)
1802                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1803
1804         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1805
1806 }
1807
1808 union crtc_source_param {
1809         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1810         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1811 };
1812
1813 static void
1814 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1815 {
1816         struct drm_device *dev = encoder->dev;
1817         struct radeon_device *rdev = dev->dev_private;
1818         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1819         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1820         union crtc_source_param args;
1821         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1822         uint8_t frev, crev;
1823         struct radeon_encoder_atom_dig *dig;
1824
1825         memset(&args, 0, sizeof(args));
1826
1827         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1828                 return;
1829
1830         switch (frev) {
1831         case 1:
1832                 switch (crev) {
1833                 case 1:
1834                 default:
1835                         if (ASIC_IS_AVIVO(rdev))
1836                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1837                         else {
1838                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1839                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1840                                 } else {
1841                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1842                                 }
1843                         }
1844                         switch (radeon_encoder->encoder_id) {
1845                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1846                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1847                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1848                                 break;
1849                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1850                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1851                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1852                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1853                                 else
1854                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1855                                 break;
1856                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1857                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1858                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1859                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1860                                 break;
1861                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1862                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1863                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1864                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1865                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1866                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1867                                 else
1868                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1869                                 break;
1870                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1871                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1872                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1873                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1874                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1875                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1876                                 else
1877                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1878                                 break;
1879                         }
1880                         break;
1881                 case 2:
1882                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1883                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1884                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1885
1886                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1887                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1888                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1889                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1890                                 else
1891                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1892                         } else
1893                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1894                         switch (radeon_encoder->encoder_id) {
1895                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1896                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1897                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1898                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1899                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1900                                 dig = radeon_encoder->enc_priv;
1901                                 switch (dig->dig_encoder) {
1902                                 case 0:
1903                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1904                                         break;
1905                                 case 1:
1906                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1907                                         break;
1908                                 case 2:
1909                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1910                                         break;
1911                                 case 3:
1912                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1913                                         break;
1914                                 case 4:
1915                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1916                                         break;
1917                                 case 5:
1918                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1919                                         break;
1920                                 case 6:
1921                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1922                                         break;
1923                                 }
1924                                 break;
1925                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1926                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1927                                 break;
1928                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1929                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1930                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1931                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1932                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1933                                 else
1934                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1935                                 break;
1936                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1937                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1938                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1939                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1940                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1941                                 else
1942                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1943                                 break;
1944                         }
1945                         break;
1946                 }
1947                 break;
1948         default:
1949                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1950                 return;
1951         }
1952
1953         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1954
1955         /* update scratch regs with new routing */
1956         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1957 }
1958
1959 static void
1960 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1961                               struct drm_display_mode *mode)
1962 {
1963         struct drm_device *dev = encoder->dev;
1964         struct radeon_device *rdev = dev->dev_private;
1965         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1966         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1967
1968         /* Funky macbooks */
1969         if ((dev->pci_device == 0x71C5) &&
1970             (dev->pci_subvendor == 0x106b) &&
1971             (dev->pci_subdevice == 0x0080)) {
1972                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1973                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1974
1975                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1976                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1977
1978                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1979                 }
1980         }
1981
1982         /* set scaler clears this on some chips */
1983         if (ASIC_IS_AVIVO(rdev) &&
1984             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1985                 if (ASIC_IS_DCE8(rdev)) {
1986                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1987                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1988                                        CIK_INTERLEAVE_EN);
1989                         else
1990                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1991                 } else if (ASIC_IS_DCE4(rdev)) {
1992                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1993                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1994                                        EVERGREEN_INTERLEAVE_EN);
1995                         else
1996                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1997                 } else {
1998                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1999                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2000                                        AVIVO_D1MODE_INTERLEAVE_EN);
2001                         else
2002                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2003                 }
2004         }
2005 }
2006
2007 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2008 {
2009         struct drm_device *dev = encoder->dev;
2010         struct radeon_device *rdev = dev->dev_private;
2011         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2012         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2013         struct drm_encoder *test_encoder;
2014         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2015         uint32_t dig_enc_in_use = 0;
2016
2017         if (ASIC_IS_DCE6(rdev)) {
2018                 /* DCE6 */
2019                 switch (radeon_encoder->encoder_id) {
2020                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2021                         if (dig->linkb)
2022                                 return 1;
2023                         else
2024                                 return 0;
2025                         break;
2026                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2027                         if (dig->linkb)
2028                                 return 3;
2029                         else
2030                                 return 2;
2031                         break;
2032                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2033                         if (dig->linkb)
2034                                 return 5;
2035                         else
2036                                 return 4;
2037                         break;
2038                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2039                         return 6;
2040                         break;
2041                 }
2042         } else if (ASIC_IS_DCE4(rdev)) {
2043                 /* DCE4/5 */
2044                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2045                         /* ontario follows DCE4 */
2046                         if (rdev->family == CHIP_PALM) {
2047                                 if (dig->linkb)
2048                                         return 1;
2049                                 else
2050                                         return 0;
2051                         } else
2052                                 /* llano follows DCE3.2 */
2053                                 return radeon_crtc->crtc_id;
2054                 } else {
2055                         switch (radeon_encoder->encoder_id) {
2056                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2057                                 if (dig->linkb)
2058                                         return 1;
2059                                 else
2060                                         return 0;
2061                                 break;
2062                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2063                                 if (dig->linkb)
2064                                         return 3;
2065                                 else
2066                                         return 2;
2067                                 break;
2068                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2069                                 if (dig->linkb)
2070                                         return 5;
2071                                 else
2072                                         return 4;
2073                                 break;
2074                         }
2075                 }
2076         }
2077
2078         /* on DCE32 and encoder can driver any block so just crtc id */
2079         if (ASIC_IS_DCE32(rdev)) {
2080                 return radeon_crtc->crtc_id;
2081         }
2082
2083         /* on DCE3 - LVTMA can only be driven by DIGB */
2084         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2085                 struct radeon_encoder *radeon_test_encoder;
2086
2087                 if (encoder == test_encoder)
2088                         continue;
2089
2090                 if (!radeon_encoder_is_digital(test_encoder))
2091                         continue;
2092
2093                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2094                 dig = radeon_test_encoder->enc_priv;
2095
2096                 if (dig->dig_encoder >= 0)
2097                         dig_enc_in_use |= (1 << dig->dig_encoder);
2098         }
2099
2100         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2101                 if (dig_enc_in_use & 0x2)
2102                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2103                 return 1;
2104         }
2105         if (!(dig_enc_in_use & 1))
2106                 return 0;
2107         return 1;
2108 }
2109
2110 /* This only needs to be called once at startup */
2111 void
2112 radeon_atom_encoder_init(struct radeon_device *rdev)
2113 {
2114         struct drm_device *dev = rdev->ddev;
2115         struct drm_encoder *encoder;
2116
2117         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2118                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2119                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2120
2121                 switch (radeon_encoder->encoder_id) {
2122                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2123                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2124                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2125                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2126                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2127                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2128                         break;
2129                 default:
2130                         break;
2131                 }
2132
2133                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2134                         atombios_external_encoder_setup(encoder, ext_encoder,
2135                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2136         }
2137 }
2138
2139 static void
2140 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2141                              struct drm_display_mode *mode,
2142                              struct drm_display_mode *adjusted_mode)
2143 {
2144         struct drm_device *dev = encoder->dev;
2145         struct radeon_device *rdev = dev->dev_private;
2146         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2147
2148         radeon_encoder->pixel_clock = adjusted_mode->clock;
2149
2150         /* need to call this here rather than in prepare() since we need some crtc info */
2151         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2152
2153         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2154                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2155                         atombios_yuv_setup(encoder, true);
2156                 else
2157                         atombios_yuv_setup(encoder, false);
2158         }
2159
2160         switch (radeon_encoder->encoder_id) {
2161         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2162         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2164         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2165                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2166                 break;
2167         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2168         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2169         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2172                 /* handled in dpms */
2173                 break;
2174         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2175         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2176         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2177                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2178                 break;
2179         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2180         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2181         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2182         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2183                 atombios_dac_setup(encoder, ATOM_ENABLE);
2184                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2185                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2186                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2187                         else
2188                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2189                 }
2190                 break;
2191         }
2192
2193         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2194
2195         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2196                 if (rdev->asic->display.hdmi_enable)
2197                         radeon_hdmi_enable(rdev, encoder, true);
2198                 if (rdev->asic->display.hdmi_setmode)
2199                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2200         }
2201 }
2202
2203 static bool
2204 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2205 {
2206         struct drm_device *dev = encoder->dev;
2207         struct radeon_device *rdev = dev->dev_private;
2208         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2209         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2210
2211         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2212                                        ATOM_DEVICE_CV_SUPPORT |
2213                                        ATOM_DEVICE_CRT_SUPPORT)) {
2214                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2215                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2216                 uint8_t frev, crev;
2217
2218                 memset(&args, 0, sizeof(args));
2219
2220                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2221                         return false;
2222
2223                 args.sDacload.ucMisc = 0;
2224
2225                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2226                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2227                         args.sDacload.ucDacType = ATOM_DAC_A;
2228                 else
2229                         args.sDacload.ucDacType = ATOM_DAC_B;
2230
2231                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2232                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2233                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2234                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2235                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2236                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2237                         if (crev >= 3)
2238                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2239                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2240                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2241                         if (crev >= 3)
2242                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2243                 }
2244
2245                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2246
2247                 return true;
2248         } else
2249                 return false;
2250 }
2251
2252 static enum drm_connector_status
2253 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2254 {
2255         struct drm_device *dev = encoder->dev;
2256         struct radeon_device *rdev = dev->dev_private;
2257         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2258         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2259         uint32_t bios_0_scratch;
2260
2261         if (!atombios_dac_load_detect(encoder, connector)) {
2262                 DRM_DEBUG_KMS("detect returned false \n");
2263                 return connector_status_unknown;
2264         }
2265
2266         if (rdev->family >= CHIP_R600)
2267                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2268         else
2269                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2270
2271         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2272         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2273                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2274                         return connector_status_connected;
2275         }
2276         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2277                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2278                         return connector_status_connected;
2279         }
2280         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2281                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2282                         return connector_status_connected;
2283         }
2284         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2285                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2286                         return connector_status_connected; /* CTV */
2287                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2288                         return connector_status_connected; /* STV */
2289         }
2290         return connector_status_disconnected;
2291 }
2292
2293 static enum drm_connector_status
2294 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2295 {
2296         struct drm_device *dev = encoder->dev;
2297         struct radeon_device *rdev = dev->dev_private;
2298         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2299         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2300         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2301         u32 bios_0_scratch;
2302
2303         if (!ASIC_IS_DCE4(rdev))
2304                 return connector_status_unknown;
2305
2306         if (!ext_encoder)
2307                 return connector_status_unknown;
2308
2309         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2310                 return connector_status_unknown;
2311
2312         /* load detect on the dp bridge */
2313         atombios_external_encoder_setup(encoder, ext_encoder,
2314                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2315
2316         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2317
2318         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2319         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2320                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2321                         return connector_status_connected;
2322         }
2323         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2324                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2325                         return connector_status_connected;
2326         }
2327         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2328                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2329                         return connector_status_connected;
2330         }
2331         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2332                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2333                         return connector_status_connected; /* CTV */
2334                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2335                         return connector_status_connected; /* STV */
2336         }
2337         return connector_status_disconnected;
2338 }
2339
2340 void
2341 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2342 {
2343         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2344
2345         if (ext_encoder)
2346                 /* ddc_setup on the dp bridge */
2347                 atombios_external_encoder_setup(encoder, ext_encoder,
2348                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2349
2350 }
2351
2352 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2353 {
2354         struct radeon_device *rdev = encoder->dev->dev_private;
2355         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2356         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2357
2358         if ((radeon_encoder->active_device &
2359              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2360             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2361              ENCODER_OBJECT_ID_NONE)) {
2362                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2363                 if (dig) {
2364                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2365                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2366                                 if (rdev->family >= CHIP_R600)
2367                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2368                                 else
2369                                         /* RS600/690/740 have only 1 afmt block */
2370                                         dig->afmt = rdev->mode_info.afmt[0];
2371                         }
2372                 }
2373         }
2374
2375         radeon_atom_output_lock(encoder, true);
2376
2377         if (connector) {
2378                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2379
2380                 /* select the clock/data port if it uses a router */
2381                 if (radeon_connector->router.cd_valid)
2382                         radeon_router_select_cd_port(radeon_connector);
2383
2384                 /* turn eDP panel on for mode set */
2385                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2386                         atombios_set_edp_panel_power(connector,
2387                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2388         }
2389
2390         /* this is needed for the pll/ss setup to work correctly in some cases */
2391         atombios_set_encoder_crtc_source(encoder);
2392 }
2393
2394 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2395 {
2396         /* need to call this here as we need the crtc set up */
2397         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2398         radeon_atom_output_lock(encoder, false);
2399 }
2400
2401 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2402 {
2403         struct drm_device *dev = encoder->dev;
2404         struct radeon_device *rdev = dev->dev_private;
2405         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2406         struct radeon_encoder_atom_dig *dig;
2407
2408         /* check for pre-DCE3 cards with shared encoders;
2409          * can't really use the links individually, so don't disable
2410          * the encoder if it's in use by another connector
2411          */
2412         if (!ASIC_IS_DCE3(rdev)) {
2413                 struct drm_encoder *other_encoder;
2414                 struct radeon_encoder *other_radeon_encoder;
2415
2416                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2417                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2418                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2419                             drm_helper_encoder_in_use(other_encoder))
2420                                 goto disable_done;
2421                 }
2422         }
2423
2424         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2425
2426         switch (radeon_encoder->encoder_id) {
2427         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2428         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2429         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2430         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2431                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2432                 break;
2433         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2434         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2435         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2436         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2437         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2438                 /* handled in dpms */
2439                 break;
2440         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2441         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2442         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2443                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2444                 break;
2445         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2446         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2447         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2448         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2449                 atombios_dac_setup(encoder, ATOM_DISABLE);
2450                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2451                         atombios_tv_setup(encoder, ATOM_DISABLE);
2452                 break;
2453         }
2454
2455 disable_done:
2456         if (radeon_encoder_is_digital(encoder)) {
2457                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2458                         if (rdev->asic->display.hdmi_enable)
2459                                 radeon_hdmi_enable(rdev, encoder, false);
2460                 }
2461                 dig = radeon_encoder->enc_priv;
2462                 dig->dig_encoder = -1;
2463         }
2464         radeon_encoder->active_device = 0;
2465 }
2466
2467 /* these are handled by the primary encoders */
2468 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2469 {
2470
2471 }
2472
2473 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2474 {
2475
2476 }
2477
2478 static void
2479 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2480                          struct drm_display_mode *mode,
2481                          struct drm_display_mode *adjusted_mode)
2482 {
2483
2484 }
2485
2486 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2487 {
2488
2489 }
2490
2491 static void
2492 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2493 {
2494
2495 }
2496
2497 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2498                                        const struct drm_display_mode *mode,
2499                                        struct drm_display_mode *adjusted_mode)
2500 {
2501         return true;
2502 }
2503
2504 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2505         .dpms = radeon_atom_ext_dpms,
2506         .mode_fixup = radeon_atom_ext_mode_fixup,
2507         .prepare = radeon_atom_ext_prepare,
2508         .mode_set = radeon_atom_ext_mode_set,
2509         .commit = radeon_atom_ext_commit,
2510         .disable = radeon_atom_ext_disable,
2511         /* no detect for TMDS/LVDS yet */
2512 };
2513
2514 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2515         .dpms = radeon_atom_encoder_dpms,
2516         .mode_fixup = radeon_atom_mode_fixup,
2517         .prepare = radeon_atom_encoder_prepare,
2518         .mode_set = radeon_atom_encoder_mode_set,
2519         .commit = radeon_atom_encoder_commit,
2520         .disable = radeon_atom_encoder_disable,
2521         .detect = radeon_atom_dig_detect,
2522 };
2523
2524 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2525         .dpms = radeon_atom_encoder_dpms,
2526         .mode_fixup = radeon_atom_mode_fixup,
2527         .prepare = radeon_atom_encoder_prepare,
2528         .mode_set = radeon_atom_encoder_mode_set,
2529         .commit = radeon_atom_encoder_commit,
2530         .detect = radeon_atom_dac_detect,
2531 };
2532
2533 void radeon_enc_destroy(struct drm_encoder *encoder)
2534 {
2535         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2536         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2537                 radeon_atom_backlight_exit(radeon_encoder);
2538         drm_free(radeon_encoder->enc_priv, M_DRM);
2539         drm_encoder_cleanup(encoder);
2540         drm_free(radeon_encoder, M_DRM);
2541 }
2542
2543 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2544         .destroy = radeon_enc_destroy,
2545 };
2546
2547 static struct radeon_encoder_atom_dac *
2548 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2549 {
2550         struct drm_device *dev = radeon_encoder->base.dev;
2551         struct radeon_device *rdev = dev->dev_private;
2552         struct radeon_encoder_atom_dac *dac = kmalloc(sizeof(struct radeon_encoder_atom_dac),
2553                                                       M_DRM,
2554                                                       M_ZERO | M_WAITOK);
2555
2556         if (!dac)
2557                 return NULL;
2558
2559         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2560         return dac;
2561 }
2562
2563 static struct radeon_encoder_atom_dig *
2564 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2565 {
2566         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2567         struct radeon_encoder_atom_dig *dig = kmalloc(sizeof(struct radeon_encoder_atom_dig),
2568                                                       M_DRM,
2569                                                       M_ZERO | M_WAITOK);
2570
2571         if (!dig)
2572                 return NULL;
2573
2574         /* coherent mode by default */
2575         dig->coherent_mode = true;
2576         dig->dig_encoder = -1;
2577
2578         if (encoder_enum == 2)
2579                 dig->linkb = true;
2580         else
2581                 dig->linkb = false;
2582
2583         return dig;
2584 }
2585
2586 void
2587 radeon_add_atom_encoder(struct drm_device *dev,
2588                         uint32_t encoder_enum,
2589                         uint32_t supported_device,
2590                         u16 caps)
2591 {
2592         struct radeon_device *rdev = dev->dev_private;
2593         struct drm_encoder *encoder;
2594         struct radeon_encoder *radeon_encoder;
2595
2596         /* see if we already added it */
2597         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2598                 radeon_encoder = to_radeon_encoder(encoder);
2599                 if (radeon_encoder->encoder_enum == encoder_enum) {
2600                         radeon_encoder->devices |= supported_device;
2601                         return;
2602                 }
2603
2604         }
2605
2606         /* add a new one */
2607         radeon_encoder = kmalloc(sizeof(struct radeon_encoder),
2608                                  M_DRM, M_ZERO | M_WAITOK);
2609         if (!radeon_encoder)
2610                 return;
2611
2612         encoder = &radeon_encoder->base;
2613         switch (rdev->num_crtc) {
2614         case 1:
2615                 encoder->possible_crtcs = 0x1;
2616                 break;
2617         case 2:
2618         default:
2619                 encoder->possible_crtcs = 0x3;
2620                 break;
2621         case 4:
2622                 encoder->possible_crtcs = 0xf;
2623                 break;
2624         case 6:
2625                 encoder->possible_crtcs = 0x3f;
2626                 break;
2627         }
2628
2629         radeon_encoder->enc_priv = NULL;
2630
2631         radeon_encoder->encoder_enum = encoder_enum;
2632         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2633         radeon_encoder->devices = supported_device;
2634         radeon_encoder->rmx_type = RMX_OFF;
2635         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2636         radeon_encoder->is_ext_encoder = false;
2637         radeon_encoder->caps = caps;
2638
2639         switch (radeon_encoder->encoder_id) {
2640         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2641         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2642         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2643         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2644                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2645                         radeon_encoder->rmx_type = RMX_FULL;
2646                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2647                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2648                 } else {
2649                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2650                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2651                 }
2652                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2653                 break;
2654         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2655                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2656                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2657                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2658                 break;
2659         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2660         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2661         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2662                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2663                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2664                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2665                 break;
2666         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2667         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2668         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2669         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2670         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2671         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2672         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2673         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2674                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2675                         radeon_encoder->rmx_type = RMX_FULL;
2676                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2677                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2678                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2679                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2680                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2681                 } else {
2682                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2683                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2684                 }
2685                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2686                 break;
2687         case ENCODER_OBJECT_ID_SI170B:
2688         case ENCODER_OBJECT_ID_CH7303:
2689         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2690         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2691         case ENCODER_OBJECT_ID_TITFP513:
2692         case ENCODER_OBJECT_ID_VT1623:
2693         case ENCODER_OBJECT_ID_HDMI_SI1930:
2694         case ENCODER_OBJECT_ID_TRAVIS:
2695         case ENCODER_OBJECT_ID_NUTMEG:
2696                 /* these are handled by the primary encoders */
2697                 radeon_encoder->is_ext_encoder = true;
2698                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2699                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2700                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2701                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2702                 else
2703                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2704                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2705                 break;
2706         }
2707 }