sys/dev/drm/radeon/cayman_blit_shaders.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <drm/drmP.h>
  28
  29 /*
  30  * evergreen cards need to use the 3D engine to blit data which requires
  31  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
  32  * (which normally generates the 3D state) into the DRM, we opt to use
  33  * statically generated state tables.  The regsiter state and shaders
  34  * were hand generated to support blitting functionality.  See the 3D
  35  * driver or documentation for descriptions of the registers and
  36  * shader instructions.
  37  */
  38
  39 const u32 cayman_default_state[] =
  40 {
  41         0xc0066900,
  42         0x00000000,
  43         0x00000060, /* DB_RENDER_CONTROL */
  44         0x00000000, /* DB_COUNT_CONTROL */
  45         0x00000000, /* DB_DEPTH_VIEW */
  46         0x0000002a, /* DB_RENDER_OVERRIDE */
  47         0x00000000, /* DB_RENDER_OVERRIDE2 */
  48         0x00000000, /* DB_HTILE_DATA_BASE */
  49
  50         0xc0026900,
  51         0x0000000a,
  52         0x00000000, /* DB_STENCIL_CLEAR */
  53         0x00000000, /* DB_DEPTH_CLEAR */
  54
  55         0xc0036900,
  56         0x0000000f,
  57         0x00000000, /* DB_DEPTH_INFO */
  58         0x00000000, /* DB_Z_INFO */
  59         0x00000000, /* DB_STENCIL_INFO */
  60
  61         0xc0016900,
  62         0x00000080,
  63         0x00000000, /* PA_SC_WINDOW_OFFSET */
  64
  65         0xc00d6900,
  66         0x00000083,
  67         0x0000ffff, /* PA_SC_CLIPRECT_RULE */
  68         0x00000000, /* PA_SC_CLIPRECT_0_TL */
  69         0x20002000, /* PA_SC_CLIPRECT_0_BR */
  70         0x00000000,
  71         0x20002000,
  72         0x00000000,
  73         0x20002000,
  74         0x00000000,
  75         0x20002000,
  76         0xaaaaaaaa, /* PA_SC_EDGERULE */
  77         0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
  78         0x0000000f, /* CB_TARGET_MASK */
  79         0x0000000f, /* CB_SHADER_MASK */
  80
  81         0xc0226900,
  82         0x00000094,
  83         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
  84         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
  85         0x80000000,
  86         0x20002000,
  87         0x80000000,
  88         0x20002000,
  89         0x80000000,
  90         0x20002000,
  91         0x80000000,
  92         0x20002000,
  93         0x80000000,
  94         0x20002000,
  95         0x80000000,
  96         0x20002000,
  97         0x80000000,
  98         0x20002000,
  99         0x80000000,
 100         0x20002000,
 101         0x80000000,
 102         0x20002000,
 103         0x80000000,
 104         0x20002000,
 105         0x80000000,
 106         0x20002000,
 107         0x80000000,
 108         0x20002000,
 109         0x80000000,
 110         0x20002000,
 111         0x80000000,
 112         0x20002000,
 113         0x80000000,
 114         0x20002000,
 115         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 116         0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
 117
 118         0xc0016900,
 119         0x000000d4,
 120         0x00000000, /* SX_MISC */
 121
 122         0xc0026900,
 123         0x000000d9,
 124         0x00000000, /* CP_RINGID */
 125         0x00000000, /* CP_VMID */
 126
 127         0xc0096900,
 128         0x00000100,
 129         0x00ffffff, /* VGT_MAX_VTX_INDX */
 130         0x00000000, /* VGT_MIN_VTX_INDX */
 131         0x00000000, /* VGT_INDX_OFFSET */
 132         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 133         0x00000000, /* SX_ALPHA_TEST_CONTROL */
 134         0x00000000, /* CB_BLEND_RED */
 135         0x00000000, /* CB_BLEND_GREEN */
 136         0x00000000, /* CB_BLEND_BLUE */
 137         0x00000000, /* CB_BLEND_ALPHA */
 138
 139         0xc0016900,
 140         0x00000187,
 141         0x00000100, /* SPI_VS_OUT_ID_0 */
 142
 143         0xc0026900,
 144         0x00000191,
 145         0x00000100, /* SPI_PS_INPUT_CNTL_0 */
 146         0x00000101, /* SPI_PS_INPUT_CNTL_1 */
 147
 148         0xc0016900,
 149         0x000001b1,
 150         0x00000000, /* SPI_VS_OUT_CONFIG */
 151
 152         0xc0106900,
 153         0x000001b3,
 154         0x20000001, /* SPI_PS_IN_CONTROL_0 */
 155         0x00000000, /* SPI_PS_IN_CONTROL_1 */
 156         0x00000000, /* SPI_INTERP_CONTROL_0 */
 157         0x00000000, /* SPI_INPUT_Z */
 158         0x00000000, /* SPI_FOG_CNTL */
 159         0x00100000, /* SPI_BARYC_CNTL */
 160         0x00000000, /* SPI_PS_IN_CONTROL_2 */
 161         0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
 162         0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
 163         0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
 164         0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
 165         0x00000000, /* SPI_GPR_MGMT */
 166         0x00000000, /* SPI_LDS_MGMT */
 167         0x00000000, /* SPI_STACK_MGMT */
 168         0x00000000, /* SPI_WAVE_MGMT_1 */
 169         0x00000000, /* SPI_WAVE_MGMT_2 */
 170
 171         0xc0016900,
 172         0x000001e0,
 173         0x00000000, /* CB_BLEND0_CONTROL */
 174
 175         0xc00e6900,
 176         0x00000200,
 177         0x00000000, /* DB_DEPTH_CONTROL */
 178         0x00000000, /* DB_EQAA */
 179         0x00cc0010, /* CB_COLOR_CONTROL */
 180         0x00000210, /* DB_SHADER_CONTROL */
 181         0x00010000, /* PA_CL_CLIP_CNTL */
 182         0x00000004, /* PA_SU_SC_MODE_CNTL */
 183         0x00000100, /* PA_CL_VTE_CNTL */
 184         0x00000000, /* PA_CL_VS_OUT_CNTL */
 185         0x00000000, /* PA_CL_NANINF_CNTL */
 186         0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
 187         0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
 188         0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
 189         0x00000000, /*  */
 190         0x00000000, /*  */
 191
 192         0xc0026900,
 193         0x00000229,
 194         0x00000000, /* SQ_PGM_START_FS */
 195         0x00000000,
 196
 197         0xc0016900,
 198         0x0000023b,
 199         0x00000000, /* SQ_LDS_ALLOC_PS */
 200
 201         0xc0066900,
 202         0x00000240,
 203         0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
 204         0x00000000,
 205         0x00000000,
 206         0x00000000,
 207         0x00000000,
 208         0x00000000,
 209
 210         0xc0046900,
 211         0x00000247,
 212         0x00000000, /* SQ_GS_VERT_ITEMSIZE */
 213         0x00000000,
 214         0x00000000,
 215         0x00000000,
 216
 217         0xc0116900,
 218         0x00000280,
 219         0x00000000, /* PA_SU_POINT_SIZE */
 220         0x00000000, /* PA_SU_POINT_MINMAX */
 221         0x00000008, /* PA_SU_LINE_CNTL */
 222         0x00000000, /* PA_SC_LINE_STIPPLE */
 223         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 224         0x00000000, /* VGT_HOS_CNTL */
 225         0x00000000,
 226         0x00000000,
 227         0x00000000,
 228         0x00000000,
 229         0x00000000,
 230         0x00000000,
 231         0x00000000,
 232         0x00000000,
 233         0x00000000,
 234         0x00000000,
 235         0x00000000, /* VGT_GS_MODE */
 236
 237         0xc0026900,
 238         0x00000292,
 239         0x00000000, /* PA_SC_MODE_CNTL_0 */
 240         0x00000000, /* PA_SC_MODE_CNTL_1 */
 241
 242         0xc0016900,
 243         0x000002a1,
 244         0x00000000, /* VGT_PRIMITIVEID_EN */
 245
 246         0xc0016900,
 247         0x000002a5,
 248         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
 249
 250         0xc0026900,
 251         0x000002a8,
 252         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 253         0x00000000,
 254
 255         0xc0026900,
 256         0x000002ad,
 257         0x00000000, /* VGT_REUSE_OFF */
 258         0x00000000,
 259
 260         0xc0016900,
 261         0x000002d5,
 262         0x00000000, /* VGT_SHADER_STAGES_EN */
 263
 264         0xc0016900,
 265         0x000002dc,
 266         0x0000aa00, /* DB_ALPHA_TO_MASK */
 267
 268         0xc0066900,
 269         0x000002de,
 270         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 271         0x00000000,
 272         0x00000000,
 273         0x00000000,
 274         0x00000000,
 275         0x00000000,
 276
 277         0xc0026900,
 278         0x000002e5,
 279         0x00000000, /* VGT_STRMOUT_CONFIG */
 280         0x00000000,
 281
 282         0xc01b6900,
 283         0x000002f5,
 284         0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
 285         0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
 286         0x00000000, /* PA_SC_LINE_CNTL */
 287         0x00000000, /* PA_SC_AA_CONFIG */
 288         0x00000005, /* PA_SU_VTX_CNTL */
 289         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 290         0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
 291         0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
 292         0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
 293         0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
 294         0x00000000,
 295         0x00000000,
 296         0x00000000,
 297         0x00000000,
 298         0x00000000,
 299         0x00000000,
 300         0x00000000,
 301         0x00000000,
 302         0x00000000,
 303         0x00000000,
 304         0x00000000,
 305         0x00000000,
 306         0x00000000,
 307         0x00000000,
 308         0x00000000,
 309         0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
 310         0xffffffff,
 311
 312         0xc0026900,
 313         0x00000316,
 314         0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
 315         0x00000010, /*  */
 316 };
 317
 318 const u32 cayman_vs[] =
 319 {
 320         0x00000004,
 321         0x80400400,
 322         0x0000a03c,
 323         0x95000688,
 324         0x00004000,
 325         0x15000688,
 326         0x00000000,
 327         0x88000000,
 328         0x04000000,
 329         0x67961001,
 330 #ifdef __BIG_ENDIAN
 331         0x00020000,
 332 #else
 333         0x00000000,
 334 #endif
 335         0x00000000,
 336         0x04000000,
 337         0x67961000,
 338 #ifdef __BIG_ENDIAN
 339         0x00020008,
 340 #else
 341         0x00000008,
 342 #endif
 343         0x00000000,
 344 };
 345
 346 const u32 cayman_ps[] =
 347 {
 348         0x00000004,
 349         0xa00c0000,
 350         0x00000008,
 351         0x80400000,
 352         0x00000000,
 353         0x95000688,
 354         0x00000000,
 355         0x88000000,
 356         0x00380400,
 357         0x00146b10,
 358         0x00380000,
 359         0x20146b10,
 360         0x00380400,
 361         0x40146b00,
 362         0x80380000,
 363         0x60146b00,
 364         0x00000010,
 365         0x000d1000,
 366         0xb0800000,
 367         0x00000000,
 368 };
 369
 370 const u32 cayman_ps_size = DRM_ARRAY_SIZE(cayman_ps);
 371 const u32 cayman_vs_size = DRM_ARRAY_SIZE(cayman_vs);
 372 const u32 cayman_default_size = DRM_ARRAY_SIZE(cayman_default_state);