sys/dev/drm/radeon/r600_cp.c

   1 /*
   2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Dave Airlie <airlied@redhat.com>
  26  *     Alex Deucher <alexander.deucher@amd.com>
  27  *
  28  * ------------------------ This file is DEPRECATED! -------------------------
  29  *
  30  * $FreeBSD: head/sys/dev/drm2/radeon/r600_cp.c 254885 2013-08-25 19:37:15Z dumbbell $
  31  */
  32
  33 #include <sys/param.h>
  34 #include <sys/systm.h>
  35 #include <sys/linker.h>
  36 #include <sys/firmware.h>
  37
  38 #include <drm/drmP.h>
  39 #include <uapi_drm/radeon_drm.h>
  40 #include "radeon_drv.h"
  41 #include "r600_cp.h"
  42
  43 #define PFP_UCODE_SIZE 576
  44 #define PM4_UCODE_SIZE 1792
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47
  48 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  49 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  50
  51 #define R600_PTE_VALID     (1 << 0)
  52 #define R600_PTE_SYSTEM    (1 << 1)
  53 #define R600_PTE_SNOOPED   (1 << 2)
  54 #define R600_PTE_READABLE  (1 << 5)
  55 #define R600_PTE_WRITEABLE (1 << 6)
  56
  57 /* MAX values used for gfx init */
  58 #define R6XX_MAX_SH_GPRS           256
  59 #define R6XX_MAX_TEMP_GPRS         16
  60 #define R6XX_MAX_SH_THREADS        256
  61 #define R6XX_MAX_SH_STACK_ENTRIES  4096
  62 #define R6XX_MAX_BACKENDS          8
  63 #define R6XX_MAX_BACKENDS_MASK     0xff
  64 #define R6XX_MAX_SIMDS             8
  65 #define R6XX_MAX_SIMDS_MASK        0xff
  66 #define R6XX_MAX_PIPES             8
  67 #define R6XX_MAX_PIPES_MASK        0xff
  68
  69 #define R7XX_MAX_SH_GPRS           256
  70 #define R7XX_MAX_TEMP_GPRS         16
  71 #define R7XX_MAX_SH_THREADS        256
  72 #define R7XX_MAX_SH_STACK_ENTRIES  4096
  73 #define R7XX_MAX_BACKENDS          8
  74 #define R7XX_MAX_BACKENDS_MASK     0xff
  75 #define R7XX_MAX_SIMDS             16
  76 #define R7XX_MAX_SIMDS_MASK        0xffff
  77 #define R7XX_MAX_PIPES             8
  78 #define R7XX_MAX_PIPES_MASK        0xff
  79
  80 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
  81 {
  82         int i;
  83
  84         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
  85
  86         for (i = 0; i < dev_priv->usec_timeout; i++) {
  87                 int slots;
  88                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
  89                         slots = (RADEON_READ(R600_GRBM_STATUS)
  90                                  & R700_CMDFIFO_AVAIL_MASK);
  91                 else
  92                         slots = (RADEON_READ(R600_GRBM_STATUS)
  93                                  & R600_CMDFIFO_AVAIL_MASK);
  94                 if (slots >= entries)
  95                         return 0;
  96                 DRM_UDELAY(1);
  97         }
  98         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
  99                  RADEON_READ(R600_GRBM_STATUS),
 100                  RADEON_READ(R600_GRBM_STATUS2));
 101
 102         return -EBUSY;
 103 }
 104
 105 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
 106 {
 107         int i, ret;
 108
 109         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 110
 111         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 112                 ret = r600_do_wait_for_fifo(dev_priv, 8);
 113         else
 114                 ret = r600_do_wait_for_fifo(dev_priv, 16);
 115         if (ret)
 116                 return ret;
 117         for (i = 0; i < dev_priv->usec_timeout; i++) {
 118                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
 119                         return 0;
 120                 DRM_UDELAY(1);
 121         }
 122         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 123                  RADEON_READ(R600_GRBM_STATUS),
 124                  RADEON_READ(R600_GRBM_STATUS2));
 125
 126         return -EBUSY;
 127 }
 128
 129 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 130 {
 131         struct drm_sg_mem *entry = dev->sg;
 132 #ifdef __linux__
 133         int max_pages;
 134         int pages;
 135         int i;
 136 #endif
 137
 138         if (!entry)
 139                 return;
 140
 141         if (gart_info->bus_addr) {
 142 #ifdef __linux__
 143                 max_pages = (gart_info->table_size / sizeof(u64));
 144                 pages = (entry->pages <= max_pages)
 145                   ? entry->pages : max_pages;
 146
 147                 for (i = 0; i < pages; i++) {
 148                         if (!entry->busaddr[i])
 149                                 break;
 150                         pci_unmap_page(dev->pdev, entry->busaddr[i],
 151                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 152                 }
 153 #endif
 154                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 155                         gart_info->bus_addr = 0;
 156         }
 157 }
 158
 159 /* R600 has page table setup */
 160 int r600_page_table_init(struct drm_device *dev)
 161 {
 162         drm_radeon_private_t *dev_priv = dev->dev_private;
 163         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
 164         struct drm_local_map *map = &gart_info->mapping;
 165         struct drm_sg_mem *entry = dev->sg;
 166         int ret = 0;
 167         int i, j;
 168         int pages;
 169         u64 page_base;
 170         dma_addr_t entry_addr;
 171         int max_ati_pages, max_real_pages, gart_idx;
 172
 173         /* okay page table is available - lets rock */
 174         max_ati_pages = (gart_info->table_size / sizeof(u64));
 175         max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
 176
 177         pages = (entry->pages <= max_real_pages) ?
 178                 entry->pages : max_real_pages;
 179
 180         memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
 181
 182         gart_idx = 0;
 183         for (i = 0; i < pages; i++) {
 184 #ifdef __linux__
 185                 entry->busaddr[i] = pci_map_page(dev->pdev,
 186                                                  entry->pagelist[i], 0,
 187                                                  PAGE_SIZE,
 188                                                  PCI_DMA_BIDIRECTIONAL);
 189                 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
 190                         DRM_ERROR("unable to map PCIGART pages!\n");
 191                         r600_page_table_cleanup(dev, gart_info);
 192                         goto done;
 193                 }
 194 #endif
 195                 entry_addr = entry->busaddr[i];
 196                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 197                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
 198                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
 199                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
 200
 201                         DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
 202
 203                         gart_idx++;
 204
 205                         if ((i % 128) == 0)
 206                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
 207                                     i, (unsigned long long)page_base);
 208                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 209                 }
 210         }
 211         ret = 1;
 212 #ifdef __linux__
 213 done:
 214 #endif
 215         return ret;
 216 }
 217
 218 static void r600_vm_flush_gart_range(struct drm_device *dev)
 219 {
 220         drm_radeon_private_t *dev_priv = dev->dev_private;
 221         u32 resp, countdown = 1000;
 222         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 223         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 224         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
 225
 226         do {
 227                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
 228                 countdown--;
 229                 DRM_UDELAY(1);
 230         } while (((resp & 0xf0) == 0) && countdown);
 231 }
 232
 233 static void r600_vm_init(struct drm_device *dev)
 234 {
 235         drm_radeon_private_t *dev_priv = dev->dev_private;
 236         /* initialise the VM to use the page table we constructed up there */
 237         u32 vm_c0, i;
 238         u32 mc_rd_a;
 239         u32 vm_l2_cntl, vm_l2_cntl3;
 240         /* okay set up the PCIE aperture type thingo */
 241         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 242         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 243         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 244
 245         /* setup MC RD a */
 246         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
 247                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
 248                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
 249
 250         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
 251         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
 252
 253         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
 254         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
 255
 256         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
 257         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
 258
 259         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
 260         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
 261
 262         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
 263         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
 264
 265         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
 266         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
 267
 268         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
 269         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
 270
 271         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 272         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
 273         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 274
 275         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 276         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
 277                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
 278                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
 279         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 280
 281         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 282
 283         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 284
 285         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 286
 287         /* disable all other contexts */
 288         for (i = 1; i < 8; i++)
 289                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 290
 291         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 292         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 293         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 294
 295         r600_vm_flush_gart_range(dev);
 296 }
 297
 298 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
 299 {
 300         const char *chip_name;
 301         size_t pfp_req_size, me_req_size;
 302         char fw_name[30];
 303         int err;
 304
 305         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 306         case CHIP_R600:  chip_name = "R600";  break;
 307         case CHIP_RV610: chip_name = "RV610"; break;
 308         case CHIP_RV630: chip_name = "RV630"; break;
 309         case CHIP_RV620: chip_name = "RV620"; break;
 310         case CHIP_RV635: chip_name = "RV635"; break;
 311         case CHIP_RV670: chip_name = "RV670"; break;
 312         case CHIP_RS780:
 313         case CHIP_RS880: chip_name = "RS780"; break;
 314         case CHIP_RV770: chip_name = "RV770"; break;
 315         case CHIP_RV730:
 316         case CHIP_RV740: chip_name = "RV730"; break;
 317         case CHIP_RV710: chip_name = "RV710"; break;
 318         default:         panic("%s: Unsupported family %d", __func__, dev_priv->flags & RADEON_FAMILY_MASK);
 319         }
 320
 321         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 322                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
 323                 me_req_size = R700_PM4_UCODE_SIZE * 4;
 324         } else {
 325                 pfp_req_size = PFP_UCODE_SIZE * 4;
 326                 me_req_size = PM4_UCODE_SIZE * 12;
 327         }
 328
 329         DRM_INFO("Loading %s CP Microcode\n", chip_name);
 330         err = 0;
 331
 332         ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name);
 333         dev_priv->pfp_fw = firmware_get(fw_name);
 334         if (dev_priv->pfp_fw == NULL) {
 335                 err = -ENOENT;
 336                 goto out;
 337         }
 338         if (dev_priv->pfp_fw->datasize != pfp_req_size) {
 339                 DRM_ERROR(
 340                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
 341                        dev_priv->pfp_fw->datasize, fw_name);
 342                 err = -EINVAL;
 343                 goto out;
 344         }
 345
 346         ksnprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name);
 347         dev_priv->me_fw = firmware_get(fw_name);
 348         if (dev_priv->me_fw == NULL) {
 349                 err = -ENOENT;
 350                 goto out;
 351         }
 352         if (dev_priv->me_fw->datasize != me_req_size) {
 353                 DRM_ERROR(
 354                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
 355                        dev_priv->me_fw->datasize, fw_name);
 356                 err = -EINVAL;
 357         }
 358 out:
 359         if (err) {
 360                 if (err != -EINVAL)
 361                         DRM_ERROR(
 362                                "r600_cp: Failed to load firmware \"%s\"\n",
 363                                fw_name);
 364                 if (dev_priv->pfp_fw != NULL) {
 365                         firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD);
 366                         dev_priv->pfp_fw = NULL;
 367                 }
 368                 if (dev_priv->me_fw != NULL) {
 369                         firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD);
 370                         dev_priv->me_fw = NULL;
 371                 }
 372         }
 373         return err;
 374 }
 375
 376 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 377 {
 378         const __be32 *fw_data;
 379         int i;
 380
 381         if (!dev_priv->me_fw || !dev_priv->pfp_fw)
 382                 return;
 383
 384         r600_do_cp_stop(dev_priv);
 385
 386         RADEON_WRITE(R600_CP_RB_CNTL,
 387 #ifdef __BIG_ENDIAN
 388                      R600_BUF_SWAP_32BIT |
 389 #endif
 390                      R600_RB_NO_UPDATE |
 391                      R600_RB_BLKSZ(15) |
 392                      R600_RB_BUFSZ(3));
 393
 394         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 395         RADEON_READ(R600_GRBM_SOFT_RESET);
 396         DRM_MDELAY(15);
 397         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 398
 399         fw_data = (const __be32 *)dev_priv->me_fw->data;
 400         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 401         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
 402                 RADEON_WRITE(R600_CP_ME_RAM_DATA,
 403                              be32_to_cpup(fw_data++));
 404
 405         fw_data = (const __be32 *)dev_priv->pfp_fw->data;
 406         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 407         for (i = 0; i < PFP_UCODE_SIZE; i++)
 408                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
 409                              be32_to_cpup(fw_data++));
 410
 411         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 412         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 413         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 414
 415 }
 416
 417 static void r700_vm_init(struct drm_device *dev)
 418 {
 419         drm_radeon_private_t *dev_priv = dev->dev_private;
 420         /* initialise the VM to use the page table we constructed up there */
 421         u32 vm_c0, i;
 422         u32 mc_vm_md_l1;
 423         u32 vm_l2_cntl, vm_l2_cntl3;
 424         /* okay set up the PCIE aperture type thingo */
 425         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
 426         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 427         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 428
 429         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
 430             R700_ENABLE_L1_FRAGMENT_PROCESSING |
 431             R700_SYSTEM_ACCESS_MODE_IN_SYS |
 432             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 433             R700_EFFECTIVE_L1_TLB_SIZE(5) |
 434             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
 435
 436         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
 437         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
 438         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
 439         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
 440         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
 441         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
 442         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
 443
 444         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
 445         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
 446         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
 447
 448         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
 449         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
 450         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
 451
 452         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
 453
 454         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
 455
 456         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
 457
 458         /* disable all other contexts */
 459         for (i = 1; i < 8; i++)
 460                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
 461
 462         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
 463         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
 464         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
 465
 466         r600_vm_flush_gart_range(dev);
 467 }
 468
 469 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 470 {
 471         const __be32 *fw_data;
 472         int i;
 473
 474         if (!dev_priv->me_fw || !dev_priv->pfp_fw)
 475                 return;
 476
 477         r600_do_cp_stop(dev_priv);
 478
 479         RADEON_WRITE(R600_CP_RB_CNTL,
 480 #ifdef __BIG_ENDIAN
 481                      R600_BUF_SWAP_32BIT |
 482 #endif
 483                      R600_RB_NO_UPDATE |
 484                      R600_RB_BLKSZ(15) |
 485                      R600_RB_BUFSZ(3));
 486
 487         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
 488         RADEON_READ(R600_GRBM_SOFT_RESET);
 489         DRM_MDELAY(15);
 490         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 491
 492         fw_data = (const __be32 *)dev_priv->pfp_fw->data;
 493         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 494         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 495                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 496         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 497
 498         fw_data = (const __be32 *)dev_priv->me_fw->data;
 499         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 500         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 501                 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 502         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 503
 504         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 505         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 506         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
 507
 508 }
 509
 510 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
 511 {
 512         u32 tmp;
 513
 514         /* Start with assuming that writeback doesn't work */
 515         dev_priv->writeback_works = 0;
 516
 517         /* Writeback doesn't seem to work everywhere, test it here and possibly
 518          * enable it if it appears to work
 519          */
 520         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
 521
 522         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
 523
 524         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 525                 u32 val;
 526
 527                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
 528                 if (val == 0xdeadbeef)
 529                         break;
 530                 DRM_UDELAY(1);
 531         }
 532
 533         if (tmp < dev_priv->usec_timeout) {
 534                 dev_priv->writeback_works = 1;
 535                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 536         } else {
 537                 dev_priv->writeback_works = 0;
 538                 DRM_INFO("writeback test failed\n");
 539         }
 540         if (radeon_no_wb == 1) {
 541                 dev_priv->writeback_works = 0;
 542                 DRM_INFO("writeback forced off\n");
 543         }
 544
 545         if (!dev_priv->writeback_works) {
 546                 /* Disable writeback to avoid unnecessary bus master transfer */
 547                 RADEON_WRITE(R600_CP_RB_CNTL,
 548 #ifdef __BIG_ENDIAN
 549                              R600_BUF_SWAP_32BIT |
 550 #endif
 551                              RADEON_READ(R600_CP_RB_CNTL) |
 552                              R600_RB_NO_UPDATE);
 553                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
 554         }
 555 }
 556
 557 int r600_do_engine_reset(struct drm_device *dev)
 558 {
 559         drm_radeon_private_t *dev_priv = dev->dev_private;
 560         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
 561
 562         DRM_INFO("Resetting GPU\n");
 563
 564         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
 565         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
 566         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
 567
 568         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
 569         RADEON_READ(R600_GRBM_SOFT_RESET);
 570         DRM_UDELAY(50);
 571         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 572         RADEON_READ(R600_GRBM_SOFT_RESET);
 573
 574         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
 575         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
 576         RADEON_WRITE(R600_CP_RB_CNTL,
 577 #ifdef __BIG_ENDIAN
 578                      R600_BUF_SWAP_32BIT |
 579 #endif
 580                      R600_RB_RPTR_WR_ENA);
 581
 582         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
 583         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
 584         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
 585         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
 586
 587         /* Reset the CP ring */
 588         r600_do_cp_reset(dev_priv);
 589
 590         /* The CP is no longer running after an engine reset */
 591         dev_priv->cp_running = 0;
 592
 593         /* Reset any pending vertex, indirect buffers */
 594         radeon_freelist_reset(dev);
 595
 596         return 0;
 597
 598 }
 599
 600 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 601                                              u32 num_backends,
 602                                              u32 backend_disable_mask)
 603 {
 604         u32 backend_map = 0;
 605         u32 enabled_backends_mask;
 606         u32 enabled_backends_count;
 607         u32 cur_pipe;
 608         u32 swizzle_pipe[R6XX_MAX_PIPES];
 609         u32 cur_backend;
 610         u32 i;
 611
 612         if (num_tile_pipes > R6XX_MAX_PIPES)
 613                 num_tile_pipes = R6XX_MAX_PIPES;
 614         if (num_tile_pipes < 1)
 615                 num_tile_pipes = 1;
 616         if (num_backends > R6XX_MAX_BACKENDS)
 617                 num_backends = R6XX_MAX_BACKENDS;
 618         if (num_backends < 1)
 619                 num_backends = 1;
 620
 621         enabled_backends_mask = 0;
 622         enabled_backends_count = 0;
 623         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 624                 if (((backend_disable_mask >> i) & 1) == 0) {
 625                         enabled_backends_mask |= (1 << i);
 626                         ++enabled_backends_count;
 627                 }
 628                 if (enabled_backends_count == num_backends)
 629                         break;
 630         }
 631
 632         if (enabled_backends_count == 0) {
 633                 enabled_backends_mask = 1;
 634                 enabled_backends_count = 1;
 635         }
 636
 637         if (enabled_backends_count != num_backends)
 638                 num_backends = enabled_backends_count;
 639
 640         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 641         switch (num_tile_pipes) {
 642         case 1:
 643                 swizzle_pipe[0] = 0;
 644                 break;
 645         case 2:
 646                 swizzle_pipe[0] = 0;
 647                 swizzle_pipe[1] = 1;
 648                 break;
 649         case 3:
 650                 swizzle_pipe[0] = 0;
 651                 swizzle_pipe[1] = 1;
 652                 swizzle_pipe[2] = 2;
 653                 break;
 654         case 4:
 655                 swizzle_pipe[0] = 0;
 656                 swizzle_pipe[1] = 1;
 657                 swizzle_pipe[2] = 2;
 658                 swizzle_pipe[3] = 3;
 659                 break;
 660         case 5:
 661                 swizzle_pipe[0] = 0;
 662                 swizzle_pipe[1] = 1;
 663                 swizzle_pipe[2] = 2;
 664                 swizzle_pipe[3] = 3;
 665                 swizzle_pipe[4] = 4;
 666                 break;
 667         case 6:
 668                 swizzle_pipe[0] = 0;
 669                 swizzle_pipe[1] = 2;
 670                 swizzle_pipe[2] = 4;
 671                 swizzle_pipe[3] = 5;
 672                 swizzle_pipe[4] = 1;
 673                 swizzle_pipe[5] = 3;
 674                 break;
 675         case 7:
 676                 swizzle_pipe[0] = 0;
 677                 swizzle_pipe[1] = 2;
 678                 swizzle_pipe[2] = 4;
 679                 swizzle_pipe[3] = 6;
 680                 swizzle_pipe[4] = 1;
 681                 swizzle_pipe[5] = 3;
 682                 swizzle_pipe[6] = 5;
 683                 break;
 684         case 8:
 685                 swizzle_pipe[0] = 0;
 686                 swizzle_pipe[1] = 2;
 687                 swizzle_pipe[2] = 4;
 688                 swizzle_pipe[3] = 6;
 689                 swizzle_pipe[4] = 1;
 690                 swizzle_pipe[5] = 3;
 691                 swizzle_pipe[6] = 5;
 692                 swizzle_pipe[7] = 7;
 693                 break;
 694         }
 695
 696         cur_backend = 0;
 697         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 698                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 699                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 700
 701                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 702
 703                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 704         }
 705
 706         return backend_map;
 707 }
 708
 709 static int r600_count_pipe_bits(uint32_t val)
 710 {
 711         return hweight32(val);
 712 }
 713
 714 static void r600_gfx_init(struct drm_device *dev,
 715                           drm_radeon_private_t *dev_priv)
 716 {
 717         int i, j, num_qd_pipes;
 718         u32 sx_debug_1;
 719         u32 tc_cntl;
 720         u32 arb_pop;
 721         u32 num_gs_verts_per_thread;
 722         u32 vgt_gs_per_es;
 723         u32 gs_prim_buffer_depth = 0;
 724         u32 sq_ms_fifo_sizes;
 725         u32 sq_config;
 726         u32 sq_gpr_resource_mgmt_1 = 0;
 727         u32 sq_gpr_resource_mgmt_2 = 0;
 728         u32 sq_thread_resource_mgmt = 0;
 729         u32 sq_stack_resource_mgmt_1 = 0;
 730         u32 sq_stack_resource_mgmt_2 = 0;
 731         u32 hdp_host_path_cntl;
 732         u32 backend_map;
 733         u32 gb_tiling_config = 0;
 734         u32 cc_rb_backend_disable;
 735         u32 cc_gc_shader_pipe_config;
 736         u32 ramcfg;
 737
 738         /* setup chip specs */
 739         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 740         case CHIP_R600:
 741                 dev_priv->r600_max_pipes = 4;
 742                 dev_priv->r600_max_tile_pipes = 8;
 743                 dev_priv->r600_max_simds = 4;
 744                 dev_priv->r600_max_backends = 4;
 745                 dev_priv->r600_max_gprs = 256;
 746                 dev_priv->r600_max_threads = 192;
 747                 dev_priv->r600_max_stack_entries = 256;
 748                 dev_priv->r600_max_hw_contexts = 8;
 749                 dev_priv->r600_max_gs_threads = 16;
 750                 dev_priv->r600_sx_max_export_size = 128;
 751                 dev_priv->r600_sx_max_export_pos_size = 16;
 752                 dev_priv->r600_sx_max_export_smx_size = 128;
 753                 dev_priv->r600_sq_num_cf_insts = 2;
 754                 break;
 755         case CHIP_RV630:
 756         case CHIP_RV635:
 757                 dev_priv->r600_max_pipes = 2;
 758                 dev_priv->r600_max_tile_pipes = 2;
 759                 dev_priv->r600_max_simds = 3;
 760                 dev_priv->r600_max_backends = 1;
 761                 dev_priv->r600_max_gprs = 128;
 762                 dev_priv->r600_max_threads = 192;
 763                 dev_priv->r600_max_stack_entries = 128;
 764                 dev_priv->r600_max_hw_contexts = 8;
 765                 dev_priv->r600_max_gs_threads = 4;
 766                 dev_priv->r600_sx_max_export_size = 128;
 767                 dev_priv->r600_sx_max_export_pos_size = 16;
 768                 dev_priv->r600_sx_max_export_smx_size = 128;
 769                 dev_priv->r600_sq_num_cf_insts = 2;
 770                 break;
 771         case CHIP_RV610:
 772         case CHIP_RS780:
 773         case CHIP_RS880:
 774         case CHIP_RV620:
 775                 dev_priv->r600_max_pipes = 1;
 776                 dev_priv->r600_max_tile_pipes = 1;
 777                 dev_priv->r600_max_simds = 2;
 778                 dev_priv->r600_max_backends = 1;
 779                 dev_priv->r600_max_gprs = 128;
 780                 dev_priv->r600_max_threads = 192;
 781                 dev_priv->r600_max_stack_entries = 128;
 782                 dev_priv->r600_max_hw_contexts = 4;
 783                 dev_priv->r600_max_gs_threads = 4;
 784                 dev_priv->r600_sx_max_export_size = 128;
 785                 dev_priv->r600_sx_max_export_pos_size = 16;
 786                 dev_priv->r600_sx_max_export_smx_size = 128;
 787                 dev_priv->r600_sq_num_cf_insts = 1;
 788                 break;
 789         case CHIP_RV670:
 790                 dev_priv->r600_max_pipes = 4;
 791                 dev_priv->r600_max_tile_pipes = 4;
 792                 dev_priv->r600_max_simds = 4;
 793                 dev_priv->r600_max_backends = 4;
 794                 dev_priv->r600_max_gprs = 192;
 795                 dev_priv->r600_max_threads = 192;
 796                 dev_priv->r600_max_stack_entries = 256;
 797                 dev_priv->r600_max_hw_contexts = 8;
 798                 dev_priv->r600_max_gs_threads = 16;
 799                 dev_priv->r600_sx_max_export_size = 128;
 800                 dev_priv->r600_sx_max_export_pos_size = 16;
 801                 dev_priv->r600_sx_max_export_smx_size = 128;
 802                 dev_priv->r600_sq_num_cf_insts = 2;
 803                 break;
 804         default:
 805                 break;
 806         }
 807
 808         /* Initialize HDP */
 809         j = 0;
 810         for (i = 0; i < 32; i++) {
 811                 RADEON_WRITE((0x2c14 + j), 0x00000000);
 812                 RADEON_WRITE((0x2c18 + j), 0x00000000);
 813                 RADEON_WRITE((0x2c1c + j), 0x00000000);
 814                 RADEON_WRITE((0x2c20 + j), 0x00000000);
 815                 RADEON_WRITE((0x2c24 + j), 0x00000000);
 816                 j += 0x18;
 817         }
 818
 819         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
 820
 821         /* setup tiling, simd, pipe config */
 822         ramcfg = RADEON_READ(R600_RAMCFG);
 823
 824         switch (dev_priv->r600_max_tile_pipes) {
 825         case 1:
 826                 gb_tiling_config |= R600_PIPE_TILING(0);
 827                 break;
 828         case 2:
 829                 gb_tiling_config |= R600_PIPE_TILING(1);
 830                 break;
 831         case 4:
 832                 gb_tiling_config |= R600_PIPE_TILING(2);
 833                 break;
 834         case 8:
 835                 gb_tiling_config |= R600_PIPE_TILING(3);
 836                 break;
 837         default:
 838                 break;
 839         }
 840
 841         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
 842
 843         gb_tiling_config |= R600_GROUP_SIZE(0);
 844
 845         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
 846                 gb_tiling_config |= R600_ROW_TILING(3);
 847                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
 848         } else {
 849                 gb_tiling_config |=
 850                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 851                 gb_tiling_config |=
 852                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
 853         }
 854
 855         gb_tiling_config |= R600_BANK_SWAPS(1);
 856
 857         cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 858         cc_rb_backend_disable |=
 859                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
 860
 861         cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 862         cc_gc_shader_pipe_config |=
 863                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
 864         cc_gc_shader_pipe_config |=
 865                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
 866
 867         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
 868                                                         (R6XX_MAX_BACKENDS -
 869                                                          r600_count_pipe_bits((cc_rb_backend_disable &
 870                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
 871                                                         (cc_rb_backend_disable >> 16));
 872         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
 873
 874         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
 875         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 876         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
 877         if (gb_tiling_config & 0xc0) {
 878                 dev_priv->r600_group_size = 512;
 879         } else {
 880                 dev_priv->r600_group_size = 256;
 881         }
 882         dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
 883         if (gb_tiling_config & 0x30) {
 884                 dev_priv->r600_nbanks = 8;
 885         } else {
 886                 dev_priv->r600_nbanks = 4;
 887         }
 888
 889         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 890         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 891         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 892
 893         num_qd_pipes =
 894                 R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
 895         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
 896         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
 897
 898         /* set HW defaults for 3D engine */
 899         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
 900                                                 R600_ROQ_IB2_START(0x2b)));
 901
 902         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
 903                                               R600_ROQ_END(0x40)));
 904
 905         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
 906                                         R600_SYNC_GRADIENT |
 907                                         R600_SYNC_WALKER |
 908                                         R600_SYNC_ALIGNER));
 909
 910         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
 911                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
 912
 913         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
 914         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
 915         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
 916                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
 917         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
 918
 919         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 920             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
 921             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 922             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 923             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 924             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
 925                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
 926         else
 927                 RADEON_WRITE(R600_DB_DEBUG, 0);
 928
 929         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
 930                                           R600_DEPTH_FLUSH(16) |
 931                                           R600_DEPTH_PENDING_FREE(4) |
 932                                           R600_DEPTH_CACHELINE_FREE(16)));
 933         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
 934         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
 935
 936         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
 937         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
 938
 939         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
 940         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 941             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 942             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 943             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 944                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
 945                                     R600_FETCH_FIFO_HIWATER(0xa) |
 946                                     R600_DONE_FIFO_HIWATER(0xe0) |
 947                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
 948         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
 949                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
 950                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
 951                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
 952         }
 953         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 954
 955         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 956          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 957          */
 958         sq_config = RADEON_READ(R600_SQ_CONFIG);
 959         sq_config &= ~(R600_PS_PRIO(3) |
 960                        R600_VS_PRIO(3) |
 961                        R600_GS_PRIO(3) |
 962                        R600_ES_PRIO(3));
 963         sq_config |= (R600_DX9_CONSTS |
 964                       R600_VC_ENABLE |
 965                       R600_PS_PRIO(0) |
 966                       R600_VS_PRIO(1) |
 967                       R600_GS_PRIO(2) |
 968                       R600_ES_PRIO(3));
 969
 970         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
 971                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
 972                                           R600_NUM_VS_GPRS(124) |
 973                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
 974                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
 975                                           R600_NUM_ES_GPRS(0));
 976                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
 977                                            R600_NUM_VS_THREADS(48) |
 978                                            R600_NUM_GS_THREADS(4) |
 979                                            R600_NUM_ES_THREADS(4));
 980                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
 981                                             R600_NUM_VS_STACK_ENTRIES(128));
 982                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
 983                                             R600_NUM_ES_STACK_ENTRIES(0));
 984         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
 985                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
 986                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
 987                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
 988                 /* no vertex cache */
 989                 sq_config &= ~R600_VC_ENABLE;
 990
 991                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
 992                                           R600_NUM_VS_GPRS(44) |
 993                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
 994                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
 995                                           R600_NUM_ES_GPRS(17));
 996                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
 997                                            R600_NUM_VS_THREADS(78) |
 998                                            R600_NUM_GS_THREADS(4) |
 999                                            R600_NUM_ES_THREADS(31));
1000                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1001                                             R600_NUM_VS_STACK_ENTRIES(40));
1002                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1003                                             R600_NUM_ES_STACK_ENTRIES(16));
1004         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1005                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1006                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1007                                           R600_NUM_VS_GPRS(44) |
1008                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1009                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1010                                           R600_NUM_ES_GPRS(18));
1011                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1012                                            R600_NUM_VS_THREADS(78) |
1013                                            R600_NUM_GS_THREADS(4) |
1014                                            R600_NUM_ES_THREADS(31));
1015                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1016                                             R600_NUM_VS_STACK_ENTRIES(40));
1017                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1018                                             R600_NUM_ES_STACK_ENTRIES(16));
1019         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1020                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1021                                           R600_NUM_VS_GPRS(44) |
1022                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1023                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1024                                           R600_NUM_ES_GPRS(17));
1025                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1026                                            R600_NUM_VS_THREADS(78) |
1027                                            R600_NUM_GS_THREADS(4) |
1028                                            R600_NUM_ES_THREADS(31));
1029                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1030                                             R600_NUM_VS_STACK_ENTRIES(64));
1031                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1032                                             R600_NUM_ES_STACK_ENTRIES(64));
1033         }
1034
1035         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1036         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1037         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1038         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1039         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1040         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1041
1042         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1043             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1044             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1045             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1046                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1047         else
1048                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1049
1050         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1051                                                     R600_S0_Y(0x4) |
1052                                                     R600_S1_X(0x4) |
1053                                                     R600_S1_Y(0xc)));
1054         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1055                                                     R600_S0_Y(0xe) |
1056                                                     R600_S1_X(0x2) |
1057                                                     R600_S1_Y(0x2) |
1058                                                     R600_S2_X(0xa) |
1059                                                     R600_S2_Y(0x6) |
1060                                                     R600_S3_X(0x6) |
1061                                                     R600_S3_Y(0xa)));
1062         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1063                                                         R600_S0_Y(0xb) |
1064                                                         R600_S1_X(0x4) |
1065                                                         R600_S1_Y(0xc) |
1066                                                         R600_S2_X(0x1) |
1067                                                         R600_S2_Y(0x6) |
1068                                                         R600_S3_X(0xa) |
1069                                                         R600_S3_Y(0xe)));
1070         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1071                                                         R600_S4_Y(0x1) |
1072                                                         R600_S5_X(0x0) |
1073                                                         R600_S5_Y(0x0) |
1074                                                         R600_S6_X(0xb) |
1075                                                         R600_S6_Y(0x4) |
1076                                                         R600_S7_X(0x7) |
1077                                                         R600_S7_Y(0x8)));
1078
1079
1080         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1081         case CHIP_R600:
1082         case CHIP_RV630:
1083         case CHIP_RV635:
1084                 gs_prim_buffer_depth = 0;
1085                 break;
1086         case CHIP_RV610:
1087         case CHIP_RS780:
1088         case CHIP_RS880:
1089         case CHIP_RV620:
1090                 gs_prim_buffer_depth = 32;
1091                 break;
1092         case CHIP_RV670:
1093                 gs_prim_buffer_depth = 128;
1094                 break;
1095         default:
1096                 break;
1097         }
1098
1099         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1100         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1101         /* Max value for this is 256 */
1102         if (vgt_gs_per_es > 256)
1103                 vgt_gs_per_es = 256;
1104
1105         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1106         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1107         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1108         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1109
1110         /* more default values. 2D/3D driver should adjust as needed */
1111         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1112         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1113         RADEON_WRITE(R600_SX_MISC, 0);
1114         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1115         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1116         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1117         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1118         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1119         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1120
1121         /* clear render buffer base addresses */
1122         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1123         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1124         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1125         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1126         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1127         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1128         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1129         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1130
1131         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1132         case CHIP_RV610:
1133         case CHIP_RS780:
1134         case CHIP_RS880:
1135         case CHIP_RV620:
1136                 tc_cntl = R600_TC_L2_SIZE(8);
1137                 break;
1138         case CHIP_RV630:
1139         case CHIP_RV635:
1140                 tc_cntl = R600_TC_L2_SIZE(4);
1141                 break;
1142         case CHIP_R600:
1143                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1144                 break;
1145         default:
1146                 tc_cntl = R600_TC_L2_SIZE(0);
1147                 break;
1148         }
1149
1150         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1151
1152         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1153         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1154
1155         arb_pop = RADEON_READ(R600_ARB_POP);
1156         arb_pop |= R600_ENABLE_TC128;
1157         RADEON_WRITE(R600_ARB_POP, arb_pop);
1158
1159         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1160         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1161                                           R600_NUM_CLIP_SEQ(3)));
1162         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1163
1164 }
1165
1166 static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1167                                              u32 num_tile_pipes,
1168                                              u32 num_backends,
1169                                              u32 backend_disable_mask)
1170 {
1171         u32 backend_map = 0;
1172         u32 enabled_backends_mask;
1173         u32 enabled_backends_count;
1174         u32 cur_pipe;
1175         u32 swizzle_pipe[R7XX_MAX_PIPES];
1176         u32 cur_backend;
1177         u32 i;
1178         bool force_no_swizzle;
1179
1180         if (num_tile_pipes > R7XX_MAX_PIPES)
1181                 num_tile_pipes = R7XX_MAX_PIPES;
1182         if (num_tile_pipes < 1)
1183                 num_tile_pipes = 1;
1184         if (num_backends > R7XX_MAX_BACKENDS)
1185                 num_backends = R7XX_MAX_BACKENDS;
1186         if (num_backends < 1)
1187                 num_backends = 1;
1188
1189         enabled_backends_mask = 0;
1190         enabled_backends_count = 0;
1191         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1192                 if (((backend_disable_mask >> i) & 1) == 0) {
1193                         enabled_backends_mask |= (1 << i);
1194                         ++enabled_backends_count;
1195                 }
1196                 if (enabled_backends_count == num_backends)
1197                         break;
1198         }
1199
1200         if (enabled_backends_count == 0) {
1201                 enabled_backends_mask = 1;
1202                 enabled_backends_count = 1;
1203         }
1204
1205         if (enabled_backends_count != num_backends)
1206                 num_backends = enabled_backends_count;
1207
1208         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1209         case CHIP_RV770:
1210         case CHIP_RV730:
1211                 force_no_swizzle = false;
1212                 break;
1213         case CHIP_RV710:
1214         case CHIP_RV740:
1215         default:
1216                 force_no_swizzle = true;
1217                 break;
1218         }
1219
1220         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1221         switch (num_tile_pipes) {
1222         case 1:
1223                 swizzle_pipe[0] = 0;
1224                 break;
1225         case 2:
1226                 swizzle_pipe[0] = 0;
1227                 swizzle_pipe[1] = 1;
1228                 break;
1229         case 3:
1230                 if (force_no_swizzle) {
1231                         swizzle_pipe[0] = 0;
1232                         swizzle_pipe[1] = 1;
1233                         swizzle_pipe[2] = 2;
1234                 } else {
1235                         swizzle_pipe[0] = 0;
1236                         swizzle_pipe[1] = 2;
1237                         swizzle_pipe[2] = 1;
1238                 }
1239                 break;
1240         case 4:
1241                 if (force_no_swizzle) {
1242                         swizzle_pipe[0] = 0;
1243                         swizzle_pipe[1] = 1;
1244                         swizzle_pipe[2] = 2;
1245                         swizzle_pipe[3] = 3;
1246                 } else {
1247                         swizzle_pipe[0] = 0;
1248                         swizzle_pipe[1] = 2;
1249                         swizzle_pipe[2] = 3;
1250                         swizzle_pipe[3] = 1;
1251                 }
1252                 break;
1253         case 5:
1254                 if (force_no_swizzle) {
1255                         swizzle_pipe[0] = 0;
1256                         swizzle_pipe[1] = 1;
1257                         swizzle_pipe[2] = 2;
1258                         swizzle_pipe[3] = 3;
1259                         swizzle_pipe[4] = 4;
1260                 } else {
1261                         swizzle_pipe[0] = 0;
1262                         swizzle_pipe[1] = 2;
1263                         swizzle_pipe[2] = 4;
1264                         swizzle_pipe[3] = 1;
1265                         swizzle_pipe[4] = 3;
1266                 }
1267                 break;
1268         case 6:
1269                 if (force_no_swizzle) {
1270                         swizzle_pipe[0] = 0;
1271                         swizzle_pipe[1] = 1;
1272                         swizzle_pipe[2] = 2;
1273                         swizzle_pipe[3] = 3;
1274                         swizzle_pipe[4] = 4;
1275                         swizzle_pipe[5] = 5;
1276                 } else {
1277                         swizzle_pipe[0] = 0;
1278                         swizzle_pipe[1] = 2;
1279                         swizzle_pipe[2] = 4;
1280                         swizzle_pipe[3] = 5;
1281                         swizzle_pipe[4] = 3;
1282                         swizzle_pipe[5] = 1;
1283                 }
1284                 break;
1285         case 7:
1286                 if (force_no_swizzle) {
1287                         swizzle_pipe[0] = 0;
1288                         swizzle_pipe[1] = 1;
1289                         swizzle_pipe[2] = 2;
1290                         swizzle_pipe[3] = 3;
1291                         swizzle_pipe[4] = 4;
1292                         swizzle_pipe[5] = 5;
1293                         swizzle_pipe[6] = 6;
1294                 } else {
1295                         swizzle_pipe[0] = 0;
1296                         swizzle_pipe[1] = 2;
1297                         swizzle_pipe[2] = 4;
1298                         swizzle_pipe[3] = 6;
1299                         swizzle_pipe[4] = 3;
1300                         swizzle_pipe[5] = 1;
1301                         swizzle_pipe[6] = 5;
1302                 }
1303                 break;
1304         case 8:
1305                 if (force_no_swizzle) {
1306                         swizzle_pipe[0] = 0;
1307                         swizzle_pipe[1] = 1;
1308                         swizzle_pipe[2] = 2;
1309                         swizzle_pipe[3] = 3;
1310                         swizzle_pipe[4] = 4;
1311                         swizzle_pipe[5] = 5;
1312                         swizzle_pipe[6] = 6;
1313                         swizzle_pipe[7] = 7;
1314                 } else {
1315                         swizzle_pipe[0] = 0;
1316                         swizzle_pipe[1] = 2;
1317                         swizzle_pipe[2] = 4;
1318                         swizzle_pipe[3] = 6;
1319                         swizzle_pipe[4] = 3;
1320                         swizzle_pipe[5] = 1;
1321                         swizzle_pipe[6] = 7;
1322                         swizzle_pipe[7] = 5;
1323                 }
1324                 break;
1325         }
1326
1327         cur_backend = 0;
1328         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1329                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1330                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1331
1332                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1333
1334                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1335         }
1336
1337         return backend_map;
1338 }
1339
1340 static void r700_gfx_init(struct drm_device *dev,
1341                           drm_radeon_private_t *dev_priv)
1342 {
1343         int i, j, num_qd_pipes;
1344         u32 ta_aux_cntl;
1345         u32 sx_debug_1;
1346         u32 smx_dc_ctl0;
1347         u32 db_debug3;
1348         u32 num_gs_verts_per_thread;
1349         u32 vgt_gs_per_es;
1350         u32 gs_prim_buffer_depth = 0;
1351         u32 sq_ms_fifo_sizes;
1352         u32 sq_config;
1353         u32 sq_thread_resource_mgmt;
1354         u32 hdp_host_path_cntl;
1355         u32 sq_dyn_gpr_size_simd_ab_0;
1356         u32 backend_map;
1357         u32 gb_tiling_config = 0;
1358         u32 cc_rb_backend_disable;
1359         u32 cc_gc_shader_pipe_config;
1360         u32 mc_arb_ramcfg;
1361         u32 db_debug4;
1362
1363         /* setup chip specs */
1364         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1365         case CHIP_RV770:
1366                 dev_priv->r600_max_pipes = 4;
1367                 dev_priv->r600_max_tile_pipes = 8;
1368                 dev_priv->r600_max_simds = 10;
1369                 dev_priv->r600_max_backends = 4;
1370                 dev_priv->r600_max_gprs = 256;
1371                 dev_priv->r600_max_threads = 248;
1372                 dev_priv->r600_max_stack_entries = 512;
1373                 dev_priv->r600_max_hw_contexts = 8;
1374                 dev_priv->r600_max_gs_threads = 16 * 2;
1375                 dev_priv->r600_sx_max_export_size = 128;
1376                 dev_priv->r600_sx_max_export_pos_size = 16;
1377                 dev_priv->r600_sx_max_export_smx_size = 112;
1378                 dev_priv->r600_sq_num_cf_insts = 2;
1379
1380                 dev_priv->r700_sx_num_of_sets = 7;
1381                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1382                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1383                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1384                 break;
1385         case CHIP_RV730:
1386                 dev_priv->r600_max_pipes = 2;
1387                 dev_priv->r600_max_tile_pipes = 4;
1388                 dev_priv->r600_max_simds = 8;
1389                 dev_priv->r600_max_backends = 2;
1390                 dev_priv->r600_max_gprs = 128;
1391                 dev_priv->r600_max_threads = 248;
1392                 dev_priv->r600_max_stack_entries = 256;
1393                 dev_priv->r600_max_hw_contexts = 8;
1394                 dev_priv->r600_max_gs_threads = 16 * 2;
1395                 dev_priv->r600_sx_max_export_size = 256;
1396                 dev_priv->r600_sx_max_export_pos_size = 32;
1397                 dev_priv->r600_sx_max_export_smx_size = 224;
1398                 dev_priv->r600_sq_num_cf_insts = 2;
1399
1400                 dev_priv->r700_sx_num_of_sets = 7;
1401                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1402                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1403                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1404                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1405                         dev_priv->r600_sx_max_export_pos_size -= 16;
1406                         dev_priv->r600_sx_max_export_smx_size += 16;
1407                 }
1408                 break;
1409         case CHIP_RV710:
1410                 dev_priv->r600_max_pipes = 2;
1411                 dev_priv->r600_max_tile_pipes = 2;
1412                 dev_priv->r600_max_simds = 2;
1413                 dev_priv->r600_max_backends = 1;
1414                 dev_priv->r600_max_gprs = 256;
1415                 dev_priv->r600_max_threads = 192;
1416                 dev_priv->r600_max_stack_entries = 256;
1417                 dev_priv->r600_max_hw_contexts = 4;
1418                 dev_priv->r600_max_gs_threads = 8 * 2;
1419                 dev_priv->r600_sx_max_export_size = 128;
1420                 dev_priv->r600_sx_max_export_pos_size = 16;
1421                 dev_priv->r600_sx_max_export_smx_size = 112;
1422                 dev_priv->r600_sq_num_cf_insts = 1;
1423
1424                 dev_priv->r700_sx_num_of_sets = 7;
1425                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1426                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1427                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1428                 break;
1429         case CHIP_RV740:
1430                 dev_priv->r600_max_pipes = 4;
1431                 dev_priv->r600_max_tile_pipes = 4;
1432                 dev_priv->r600_max_simds = 8;
1433                 dev_priv->r600_max_backends = 4;
1434                 dev_priv->r600_max_gprs = 256;
1435                 dev_priv->r600_max_threads = 248;
1436                 dev_priv->r600_max_stack_entries = 512;
1437                 dev_priv->r600_max_hw_contexts = 8;
1438                 dev_priv->r600_max_gs_threads = 16 * 2;
1439                 dev_priv->r600_sx_max_export_size = 256;
1440                 dev_priv->r600_sx_max_export_pos_size = 32;
1441                 dev_priv->r600_sx_max_export_smx_size = 224;
1442                 dev_priv->r600_sq_num_cf_insts = 2;
1443
1444                 dev_priv->r700_sx_num_of_sets = 7;
1445                 dev_priv->r700_sc_prim_fifo_size = 0x100;
1446                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1447                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1448
1449                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1450                         dev_priv->r600_sx_max_export_pos_size -= 16;
1451                         dev_priv->r600_sx_max_export_smx_size += 16;
1452                 }
1453                 break;
1454         default:
1455                 break;
1456         }
1457
1458         /* Initialize HDP */
1459         j = 0;
1460         for (i = 0; i < 32; i++) {
1461                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1462                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1463                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1464                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1465                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1466                 j += 0x18;
1467         }
1468
1469         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1470
1471         /* setup tiling, simd, pipe config */
1472         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1473
1474         switch (dev_priv->r600_max_tile_pipes) {
1475         case 1:
1476                 gb_tiling_config |= R600_PIPE_TILING(0);
1477                 break;
1478         case 2:
1479                 gb_tiling_config |= R600_PIPE_TILING(1);
1480                 break;
1481         case 4:
1482                 gb_tiling_config |= R600_PIPE_TILING(2);
1483                 break;
1484         case 8:
1485                 gb_tiling_config |= R600_PIPE_TILING(3);
1486                 break;
1487         default:
1488                 break;
1489         }
1490
1491         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1492                 gb_tiling_config |= R600_BANK_TILING(1);
1493         else
1494                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1495
1496         gb_tiling_config |= R600_GROUP_SIZE(0);
1497
1498         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1499                 gb_tiling_config |= R600_ROW_TILING(3);
1500                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1501         } else {
1502                 gb_tiling_config |=
1503                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1504                 gb_tiling_config |=
1505                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1506         }
1507
1508         gb_tiling_config |= R600_BANK_SWAPS(1);
1509
1510         cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1511         cc_rb_backend_disable |=
1512                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1513
1514         cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1515         cc_gc_shader_pipe_config |=
1516                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1517         cc_gc_shader_pipe_config |=
1518                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1519
1520         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1521                 backend_map = 0x28;
1522         else
1523                 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1524                                                                 dev_priv->r600_max_tile_pipes,
1525                                                                 (R7XX_MAX_BACKENDS -
1526                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
1527                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
1528                                                                 (cc_rb_backend_disable >> 16));
1529         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1530
1531         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1532         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1533         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1534         if (gb_tiling_config & 0xc0) {
1535                 dev_priv->r600_group_size = 512;
1536         } else {
1537                 dev_priv->r600_group_size = 256;
1538         }
1539         dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1540         if (gb_tiling_config & 0x30) {
1541                 dev_priv->r600_nbanks = 8;
1542         } else {
1543                 dev_priv->r600_nbanks = 4;
1544         }
1545
1546         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1547         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1548         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1549
1550         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1551         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1552         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1553         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1554         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1555
1556         num_qd_pipes =
1557                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
1558         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1559         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1560
1561         /* set HW defaults for 3D engine */
1562         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1563                                                 R600_ROQ_IB2_START(0x2b)));
1564
1565         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1566
1567         ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);
1568         RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO);
1569
1570         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1571         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1572         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1573
1574         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1575         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1576         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1577         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1578
1579         if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1580                 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1581                                                   R700_GS_FLUSH_CTL(4) |
1582                                                   R700_ACK_FLUSH_CTL(3) |
1583                                                   R700_SYNC_FLUSH_CTL));
1584
1585         db_debug3 = RADEON_READ(R700_DB_DEBUG3);
1586         db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f);
1587         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1588         case CHIP_RV770:
1589         case CHIP_RV740:
1590                 db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f);
1591                 break;
1592         case CHIP_RV710:
1593         case CHIP_RV730:
1594         default:
1595                 db_debug3 |= R700_DB_CLK_OFF_DELAY(2);
1596                 break;
1597         }
1598         RADEON_WRITE(R700_DB_DEBUG3, db_debug3);
1599
1600         if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
1601                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1602                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1603                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1604         }
1605
1606         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1607                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1608                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1609
1610         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1611                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1612                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1613
1614         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1615
1616         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1617
1618         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1619
1620         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1621
1622         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1623
1624         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1625                             R600_DONE_FIFO_HIWATER(0xe0) |
1626                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1627         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1628         case CHIP_RV770:
1629         case CHIP_RV730:
1630         case CHIP_RV710:
1631                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1632                 break;
1633         case CHIP_RV740:
1634         default:
1635                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1636                 break;
1637         }
1638         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1639
1640         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1641          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1642          */
1643         sq_config = RADEON_READ(R600_SQ_CONFIG);
1644         sq_config &= ~(R600_PS_PRIO(3) |
1645                        R600_VS_PRIO(3) |
1646                        R600_GS_PRIO(3) |
1647                        R600_ES_PRIO(3));
1648         sq_config |= (R600_DX9_CONSTS |
1649                       R600_VC_ENABLE |
1650                       R600_EXPORT_SRC_C |
1651                       R600_PS_PRIO(0) |
1652                       R600_VS_PRIO(1) |
1653                       R600_GS_PRIO(2) |
1654                       R600_ES_PRIO(3));
1655         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1656                 /* no vertex cache */
1657                 sq_config &= ~R600_VC_ENABLE;
1658
1659         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1660
1661         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1662                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1663                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1664
1665         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1666                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1667
1668         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1669                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1670                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1671         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1672                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1673         else
1674                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1675         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1676
1677         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1678                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1679
1680         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1681                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1682
1683         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1684                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1685                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1686                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1687
1688         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1689         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1690         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1691         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1692         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1693         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1694         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1695         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1696
1697         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1698                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1699
1700         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1701                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1702                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1703         else
1704                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1705                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1706
1707         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1708         case CHIP_RV770:
1709         case CHIP_RV730:
1710         case CHIP_RV740:
1711                 gs_prim_buffer_depth = 384;
1712                 break;
1713         case CHIP_RV710:
1714                 gs_prim_buffer_depth = 128;
1715                 break;
1716         default:
1717                 break;
1718         }
1719
1720         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1721         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1722         /* Max value for this is 256 */
1723         if (vgt_gs_per_es > 256)
1724                 vgt_gs_per_es = 256;
1725
1726         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1727         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1728         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1729
1730         /* more default values. 2D/3D driver should adjust as needed */
1731         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1732         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1733         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1734         RADEON_WRITE(R600_SX_MISC, 0);
1735         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1736         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1737         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1738         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1739         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1740         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1741         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1742         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1743
1744         /* clear render buffer base addresses */
1745         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1746         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1747         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1748         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1749         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1750         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1751         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1752         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1753
1754         RADEON_WRITE(R700_TCP_CNTL, 0);
1755
1756         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1757         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1758
1759         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1760
1761         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1762                                           R600_NUM_CLIP_SEQ(3)));
1763
1764 }
1765
1766 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1767                                        drm_radeon_private_t *dev_priv,
1768                                        struct drm_file *file_priv)
1769 {
1770         struct drm_radeon_master_private *master_priv;
1771         u32 ring_start;
1772         u64 rptr_addr;
1773
1774         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1775                 r700_gfx_init(dev, dev_priv);
1776         else
1777                 r600_gfx_init(dev, dev_priv);
1778
1779         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1780         RADEON_READ(R600_GRBM_SOFT_RESET);
1781         DRM_MDELAY(15);
1782         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1783
1784
1785         /* Set ring buffer size */
1786 #ifdef __BIG_ENDIAN
1787         RADEON_WRITE(R600_CP_RB_CNTL,
1788                      R600_BUF_SWAP_32BIT |
1789                      R600_RB_NO_UPDATE |
1790                      (dev_priv->ring.rptr_update_l2qw << 8) |
1791                      dev_priv->ring.size_l2qw);
1792 #else
1793         RADEON_WRITE(R600_CP_RB_CNTL,
1794                      RADEON_RB_NO_UPDATE |
1795                      (dev_priv->ring.rptr_update_l2qw << 8) |
1796                      dev_priv->ring.size_l2qw);
1797 #endif
1798
1799         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0);
1800
1801         /* Set the write pointer delay */
1802         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1803
1804 #ifdef __BIG_ENDIAN
1805         RADEON_WRITE(R600_CP_RB_CNTL,
1806                      R600_BUF_SWAP_32BIT |
1807                      R600_RB_NO_UPDATE |
1808                      R600_RB_RPTR_WR_ENA |
1809                      (dev_priv->ring.rptr_update_l2qw << 8) |
1810                      dev_priv->ring.size_l2qw);
1811 #else
1812         RADEON_WRITE(R600_CP_RB_CNTL,
1813                      R600_RB_NO_UPDATE |
1814                      R600_RB_RPTR_WR_ENA |
1815                      (dev_priv->ring.rptr_update_l2qw << 8) |
1816                      dev_priv->ring.size_l2qw);
1817 #endif
1818
1819         /* Initialize the ring buffer's read and write pointers */
1820         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1821         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1822         SET_RING_HEAD(dev_priv, 0);
1823         dev_priv->ring.tail = 0;
1824
1825 #if __OS_HAS_AGP
1826         if (dev_priv->flags & RADEON_IS_AGP) {
1827                 rptr_addr = dev_priv->ring_rptr->offset
1828                         - dev->agp->base +
1829                         dev_priv->gart_vm_start;
1830         } else
1831 #endif
1832         {
1833                 rptr_addr = dev_priv->ring_rptr->offset
1834                         - ((unsigned long) dev->sg->vaddr)
1835                         + dev_priv->gart_vm_start;
1836         }
1837         RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
1838         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
1839
1840 #ifdef __BIG_ENDIAN
1841         RADEON_WRITE(R600_CP_RB_CNTL,
1842                      RADEON_BUF_SWAP_32BIT |
1843                      (dev_priv->ring.rptr_update_l2qw << 8) |
1844                      dev_priv->ring.size_l2qw);
1845 #else
1846         RADEON_WRITE(R600_CP_RB_CNTL,
1847                      (dev_priv->ring.rptr_update_l2qw << 8) |
1848                      dev_priv->ring.size_l2qw);
1849 #endif
1850
1851 #if __OS_HAS_AGP
1852         if (dev_priv->flags & RADEON_IS_AGP) {
1853                 /* XXX */
1854                 radeon_write_agp_base(dev_priv, dev->agp->base);
1855
1856                 /* XXX */
1857                 radeon_write_agp_location(dev_priv,
1858                              (((dev_priv->gart_vm_start - 1 +
1859                                 dev_priv->gart_size) & 0xffff0000) |
1860                               (dev_priv->gart_vm_start >> 16)));
1861
1862                 ring_start = (dev_priv->cp_ring->offset
1863                               - dev->agp->base
1864                               + dev_priv->gart_vm_start);
1865         } else
1866 #endif
1867                 ring_start = (dev_priv->cp_ring->offset
1868                               - (unsigned long)dev->sg->vaddr>
1869                               + dev_priv->gart_vm_start);
1870
1871         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1872
1873         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1874
1875         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1876
1877         /* Initialize the scratch register pointer.  This will cause
1878          * the scratch register values to be written out to memory
1879          * whenever they are updated.
1880          *
1881          * We simply put this behind the ring read pointer, this works
1882          * with PCI GART as well as (whatever kind of) AGP GART
1883          */
1884         {
1885                 u64 scratch_addr;
1886
1887                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
1888                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1889                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1890                 scratch_addr >>= 8;
1891                 scratch_addr &= 0xffffffff;
1892
1893                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1894         }
1895
1896         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1897
1898         /* Turn on bus mastering */
1899         radeon_enable_bm(dev_priv);
1900
1901         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1902         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1903
1904         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1905         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1906
1907         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1908         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1909
1910         /* reset sarea copies of these */
1911         master_priv = file_priv->masterp->driver_priv;
1912         if (master_priv->sarea_priv) {
1913                 master_priv->sarea_priv->last_frame = 0;
1914                 master_priv->sarea_priv->last_dispatch = 0;
1915                 master_priv->sarea_priv->last_clear = 0;
1916         }
1917
1918         r600_do_wait_for_idle(dev_priv);
1919
1920 }
1921
1922 int r600_do_cleanup_cp(struct drm_device *dev)
1923 {
1924         drm_radeon_private_t *dev_priv = dev->dev_private;
1925         DRM_DEBUG("\n");
1926
1927         /* Make sure interrupts are disabled here because the uninstall ioctl
1928          * may not have been called from userspace and after dev_private
1929          * is freed, it's too late.
1930          */
1931         if (dev->irq_enabled)
1932                 drm_irq_uninstall(dev);
1933
1934 #if __OS_HAS_AGP
1935         if (dev_priv->flags & RADEON_IS_AGP) {
1936                 if (dev_priv->cp_ring != NULL) {
1937                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1938                         dev_priv->cp_ring = NULL;
1939                 }
1940                 if (dev_priv->ring_rptr != NULL) {
1941                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1942                         dev_priv->ring_rptr = NULL;
1943                 }
1944                 if (dev->agp_buffer_map != NULL) {
1945                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1946                         dev->agp_buffer_map = NULL;
1947                 }
1948         } else
1949 #endif
1950         {
1951
1952                 if (dev_priv->gart_info.bus_addr)
1953                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1954
1955                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1956                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1957                         dev_priv->gart_info.addr = NULL;
1958                 }
1959         }
1960         /* only clear to the start of flags */
1961         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1962
1963         return 0;
1964 }
1965
1966 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1967                     struct drm_file *file_priv)
1968 {
1969         drm_radeon_private_t *dev_priv = dev->dev_private;
1970         struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
1971
1972         DRM_DEBUG("\n");
1973
1974         lockinit(&dev_priv->cs_mutex, "drm__radeon_private__cs_mutex", 0,
1975                  LK_CANRECURSE);
1976         r600_cs_legacy_init();
1977         /* if we require new memory map but we don't have it fail */
1978         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1979                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1980                 r600_do_cleanup_cp(dev);
1981                 return -EINVAL;
1982         }
1983
1984         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1985                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1986                 dev_priv->flags &= ~RADEON_IS_AGP;
1987                 /* The writeback test succeeds, but when writeback is enabled,
1988                  * the ring buffer read ptr update fails after first 128 bytes.
1989                  */
1990                 radeon_no_wb = 1;
1991         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1992                  && !init->is_pci) {
1993                 DRM_DEBUG("Restoring AGP flag\n");
1994                 dev_priv->flags |= RADEON_IS_AGP;
1995         }
1996
1997         dev_priv->usec_timeout = init->usec_timeout;
1998         if (dev_priv->usec_timeout < 1 ||
1999             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2000                 DRM_DEBUG("TIMEOUT problem!\n");
2001                 r600_do_cleanup_cp(dev);
2002                 return -EINVAL;
2003         }
2004
2005         /* Enable vblank on CRTC1 for older X servers
2006          */
2007         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
2008         dev_priv->do_boxes = 0;
2009         dev_priv->cp_mode = init->cp_mode;
2010
2011         /* We don't support anything other than bus-mastering ring mode,
2012          * but the ring can be in either AGP or PCI space for the ring
2013          * read pointer.
2014          */
2015         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
2016             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
2017                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
2018                 r600_do_cleanup_cp(dev);
2019                 return -EINVAL;
2020         }
2021
2022         switch (init->fb_bpp) {
2023         case 16:
2024                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2025                 break;
2026         case 32:
2027         default:
2028                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2029                 break;
2030         }
2031         dev_priv->front_offset = init->front_offset;
2032         dev_priv->front_pitch = init->front_pitch;
2033         dev_priv->back_offset = init->back_offset;
2034         dev_priv->back_pitch = init->back_pitch;
2035
2036         dev_priv->ring_offset = init->ring_offset;
2037         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2038         dev_priv->buffers_offset = init->buffers_offset;
2039         dev_priv->gart_textures_offset = init->gart_textures_offset;
2040
2041         master_priv->sarea = drm_getsarea(dev);
2042         if (!master_priv->sarea) {
2043                 DRM_ERROR("could not find sarea!\n");
2044                 r600_do_cleanup_cp(dev);
2045                 return -EINVAL;
2046         }
2047
2048         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
2049         if (!dev_priv->cp_ring) {
2050                 DRM_ERROR("could not find cp ring region!\n");
2051                 r600_do_cleanup_cp(dev);
2052                 return -EINVAL;
2053         }
2054         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
2055         if (!dev_priv->ring_rptr) {
2056                 DRM_ERROR("could not find ring read pointer!\n");
2057                 r600_do_cleanup_cp(dev);
2058                 return -EINVAL;
2059         }
2060         dev->agp_buffer_token = init->buffers_offset;
2061         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
2062         if (!dev->agp_buffer_map) {
2063                 DRM_ERROR("could not find dma buffer region!\n");
2064                 r600_do_cleanup_cp(dev);
2065                 return -EINVAL;
2066         }
2067
2068         if (init->gart_textures_offset) {
2069                 dev_priv->gart_textures =
2070                     drm_core_findmap(dev, init->gart_textures_offset);
2071                 if (!dev_priv->gart_textures) {
2072                         DRM_ERROR("could not find GART texture region!\n");
2073                         r600_do_cleanup_cp(dev);
2074                         return -EINVAL;
2075                 }
2076         }
2077
2078 #if __OS_HAS_AGP
2079         /* XXX */
2080         if (dev_priv->flags & RADEON_IS_AGP) {
2081                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
2082                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
2083                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
2084                 if (!dev_priv->cp_ring->handle ||
2085                     !dev_priv->ring_rptr->handle ||
2086                     !dev->agp_buffer_map->handle) {
2087                         DRM_ERROR("could not find ioremap agp regions!\n");
2088                         r600_do_cleanup_cp(dev);
2089                         return -EINVAL;
2090                 }
2091         } else
2092 #endif
2093         {
2094                 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2095                 dev_priv->ring_rptr->handle =
2096                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
2097                 dev->agp_buffer_map->handle =
2098                         (void *)(unsigned long)dev->agp_buffer_map->offset;
2099
2100                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2101                           dev_priv->cp_ring->handle);
2102                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2103                           dev_priv->ring_rptr->handle);
2104                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2105                           dev->agp_buffer_map->handle);
2106         }
2107
2108         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2109         dev_priv->fb_size =
2110                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2111                 - dev_priv->fb_location;
2112
2113         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2114                                         ((dev_priv->front_offset
2115                                           + dev_priv->fb_location) >> 10));
2116
2117         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2118                                        ((dev_priv->back_offset
2119                                          + dev_priv->fb_location) >> 10));
2120
2121         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2122                                         ((dev_priv->depth_offset
2123                                           + dev_priv->fb_location) >> 10));
2124
2125         dev_priv->gart_size = init->gart_size;
2126
2127         /* New let's set the memory map ... */
2128         if (dev_priv->new_memmap) {
2129                 u32 base = 0;
2130
2131                 DRM_INFO("Setting GART location based on new memory map\n");
2132
2133                 /* If using AGP, try to locate the AGP aperture at the same
2134                  * location in the card and on the bus, though we have to
2135                  * align it down.
2136                  */
2137 #if __OS_HAS_AGP
2138                 /* XXX */
2139                 if (dev_priv->flags & RADEON_IS_AGP) {
2140                         base = dev->agp->base;
2141                         /* Check if valid */
2142                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2143                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2144                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2145                                          dev->agp->base);
2146                                 base = 0;
2147                         }
2148                 }
2149 #endif
2150                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2151                 if (base == 0) {
2152                         base = dev_priv->fb_location + dev_priv->fb_size;
2153                         if (base < dev_priv->fb_location ||
2154                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2155                                 base = dev_priv->fb_location
2156                                         - dev_priv->gart_size;
2157                 }
2158                 dev_priv->gart_vm_start = base & 0xffc00000u;
2159                 if (dev_priv->gart_vm_start != base)
2160                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2161                                  base, dev_priv->gart_vm_start);
2162         }
2163
2164 #if __OS_HAS_AGP
2165         /* XXX */
2166         if (dev_priv->flags & RADEON_IS_AGP)
2167                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2168                                                  - dev->agp->base
2169                                                  + dev_priv->gart_vm_start);
2170         else
2171 #endif
2172                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2173                                                  - (unsigned long)dev->sg->vaddr
2174                                                  + dev_priv->gart_vm_start);
2175
2176         DRM_DEBUG("fb 0x%08x size %d\n",
2177                   (unsigned int) dev_priv->fb_location,
2178                   (unsigned int) dev_priv->fb_size);
2179         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2180         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2181                   (unsigned int) dev_priv->gart_vm_start);
2182         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2183                   dev_priv->gart_buffers_offset);
2184
2185         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2186         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2187                               + init->ring_size / sizeof(u32));
2188         dev_priv->ring.size = init->ring_size;
2189         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2190
2191         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2192         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2193
2194         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2195         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2196
2197         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2198
2199         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2200
2201 #if __OS_HAS_AGP
2202         if (dev_priv->flags & RADEON_IS_AGP) {
2203                 /* XXX turn off pcie gart */
2204         } else
2205 #endif
2206         {
2207                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2208                 /* if we have an offset set from userspace */
2209                 if (!dev_priv->pcigart_offset_set) {
2210                         DRM_ERROR("Need gart offset from userspace\n");
2211                         r600_do_cleanup_cp(dev);
2212                         return -EINVAL;
2213                 }
2214
2215                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2216
2217                 dev_priv->gart_info.bus_addr =
2218                         dev_priv->pcigart_offset + dev_priv->fb_location;
2219                 dev_priv->gart_info.mapping.offset =
2220                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2221                 dev_priv->gart_info.mapping.size =
2222                         dev_priv->gart_info.table_size;
2223
2224                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2225                 if (!dev_priv->gart_info.mapping.handle) {
2226                         DRM_ERROR("ioremap failed.\n");
2227                         r600_do_cleanup_cp(dev);
2228                         return -EINVAL;
2229                 }
2230
2231                 dev_priv->gart_info.addr =
2232                         dev_priv->gart_info.mapping.handle;
2233
2234                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2235                           dev_priv->gart_info.addr,
2236                           dev_priv->pcigart_offset);
2237
2238                 if (!r600_page_table_init(dev)) {
2239                         DRM_ERROR("Failed to init GART table\n");
2240                         r600_do_cleanup_cp(dev);
2241                         return -EINVAL;
2242                 }
2243
2244                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2245                         r700_vm_init(dev);
2246                 else
2247                         r600_vm_init(dev);
2248         }
2249
2250         if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2251                 int err = r600_cp_init_microcode(dev_priv);
2252                 if (err) {
2253                         DRM_ERROR("Failed to load firmware!\n");
2254                         r600_do_cleanup_cp(dev);
2255                         return err;
2256                 }
2257         }
2258         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2259                 r700_cp_load_microcode(dev_priv);
2260         else
2261                 r600_cp_load_microcode(dev_priv);
2262
2263         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2264
2265         dev_priv->last_buf = 0;
2266
2267         r600_do_engine_reset(dev);
2268         r600_test_writeback(dev_priv);
2269
2270         return 0;
2271 }
2272
2273 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2274 {
2275         drm_radeon_private_t *dev_priv = dev->dev_private;
2276
2277         DRM_DEBUG("\n");
2278         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2279                 r700_vm_init(dev);
2280                 r700_cp_load_microcode(dev_priv);
2281         } else {
2282                 r600_vm_init(dev);
2283                 r600_cp_load_microcode(dev_priv);
2284         }
2285         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2286         r600_do_engine_reset(dev);
2287
2288         return 0;
2289 }
2290
2291 /* Wait for the CP to go idle.
2292  */
2293 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2294 {
2295         RING_LOCALS;
2296         DRM_DEBUG("\n");
2297
2298         BEGIN_RING(5);
2299         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2300         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2301         /* wait for 3D idle clean */
2302         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2303         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2304         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2305
2306         ADVANCE_RING();
2307         COMMIT_RING();
2308
2309         return r600_do_wait_for_idle(dev_priv);
2310 }
2311
2312 /* Start the Command Processor.
2313  */
2314 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2315 {
2316         u32 cp_me;
2317         RING_LOCALS;
2318         DRM_DEBUG("\n");
2319
2320         BEGIN_RING(7);
2321         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2322         OUT_RING(0x00000001);
2323         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2324                 OUT_RING(0x00000003);
2325         else
2326                 OUT_RING(0x00000000);
2327         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2328         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2329         OUT_RING(0x00000000);
2330         OUT_RING(0x00000000);
2331         ADVANCE_RING();
2332         COMMIT_RING();
2333
2334         /* set the mux and reset the halt bit */
2335         cp_me = 0xff;
2336         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2337
2338         dev_priv->cp_running = 1;
2339
2340 }
2341
2342 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2343 {
2344         u32 cur_read_ptr;
2345         DRM_DEBUG("\n");
2346
2347         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2348         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2349         SET_RING_HEAD(dev_priv, cur_read_ptr);
2350         dev_priv->ring.tail = cur_read_ptr;
2351 }
2352
2353 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2354 {
2355         uint32_t cp_me;
2356
2357         DRM_DEBUG("\n");
2358
2359         cp_me = 0xff | R600_CP_ME_HALT;
2360
2361         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2362
2363         dev_priv->cp_running = 0;
2364 }
2365
2366 int r600_cp_dispatch_indirect(struct drm_device *dev,
2367                               struct drm_buf *buf, int start, int end)
2368 {
2369         drm_radeon_private_t *dev_priv = dev->dev_private;
2370         RING_LOCALS;
2371
2372         if (start != end) {
2373                 unsigned long offset = (dev_priv->gart_buffers_offset
2374                                         + buf->offset + start);
2375                 int dwords = (end - start + 3) / sizeof(u32);
2376
2377                 DRM_DEBUG("dwords:%d\n", dwords);
2378                 DRM_DEBUG("offset 0x%lx\n", offset);
2379
2380
2381                 /* Indirect buffer data must be a multiple of 16 dwords.
2382                  * pad the data with a Type-2 CP packet.
2383                  */
2384                 while (dwords & 0xf) {
2385                         u32 *data = (u32 *)
2386                             ((char *)dev->agp_buffer_map->handle
2387                              + buf->offset + start);
2388                         data[dwords++] = RADEON_CP_PACKET2;
2389                 }
2390
2391                 /* Fire off the indirect buffer */
2392                 BEGIN_RING(4);
2393                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2394                 OUT_RING((offset & 0xfffffffc));
2395                 OUT_RING((upper_32_bits(offset) & 0xff));
2396                 OUT_RING(dwords);
2397                 ADVANCE_RING();
2398         }
2399
2400         return 0;
2401 }
2402
2403 void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2404 {
2405         drm_radeon_private_t *dev_priv = dev->dev_private;
2406         struct drm_master *master = file_priv->masterp;
2407         struct drm_radeon_master_private *master_priv = master->driver_priv;
2408         drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2409         int nbox = sarea_priv->nbox;
2410         struct drm_clip_rect *pbox = sarea_priv->boxes;
2411         int i, cpp, src_pitch, dst_pitch;
2412         uint64_t src, dst;
2413         RING_LOCALS;
2414         DRM_DEBUG("\n");
2415
2416         if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2417                 cpp = 4;
2418         else
2419                 cpp = 2;
2420
2421         if (sarea_priv->pfCurrentPage == 0) {
2422                 src_pitch = dev_priv->back_pitch;
2423                 dst_pitch = dev_priv->front_pitch;
2424                 src = dev_priv->back_offset + dev_priv->fb_location;
2425                 dst = dev_priv->front_offset + dev_priv->fb_location;
2426         } else {
2427                 src_pitch = dev_priv->front_pitch;
2428                 dst_pitch = dev_priv->back_pitch;
2429                 src = dev_priv->front_offset + dev_priv->fb_location;
2430                 dst = dev_priv->back_offset + dev_priv->fb_location;
2431         }
2432
2433         if (r600_prepare_blit_copy(dev, file_priv)) {
2434                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2435                 return;
2436         }
2437         for (i = 0; i < nbox; i++) {
2438                 int x = pbox[i].x1;
2439                 int y = pbox[i].y1;
2440                 int w = pbox[i].x2 - x;
2441                 int h = pbox[i].y2 - y;
2442
2443                 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2444
2445                 r600_blit_swap(dev,
2446                                src, dst,
2447                                x, y, x, y, w, h,
2448                                src_pitch, dst_pitch, cpp);
2449         }
2450         r600_done_blit_copy(dev);
2451
2452         /* Increment the frame counter.  The client-side 3D driver must
2453          * throttle the framerate by waiting for this value before
2454          * performing the swapbuffer ioctl.
2455          */
2456         sarea_priv->last_frame++;
2457
2458         BEGIN_RING(3);
2459         R600_FRAME_AGE(sarea_priv->last_frame);
2460         ADVANCE_RING();
2461 }
2462
2463 int r600_cp_dispatch_texture(struct drm_device *dev,
2464                              struct drm_file *file_priv,
2465                              drm_radeon_texture_t *tex,
2466                              drm_radeon_tex_image_t *image)
2467 {
2468         drm_radeon_private_t *dev_priv = dev->dev_private;
2469         struct drm_buf *buf;
2470         u32 *buffer;
2471         const u8 __user *data;
2472         int size, pass_size;
2473         u64 src_offset, dst_offset;
2474
2475         if (!radeon_check_offset(dev_priv, tex->offset)) {
2476                 DRM_ERROR("Invalid destination offset\n");
2477                 return -EINVAL;
2478         }
2479
2480         /* this might fail for zero-sized uploads - are those illegal? */
2481         if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2482                 DRM_ERROR("Invalid final destination offset\n");
2483                 return -EINVAL;
2484         }
2485
2486         size = tex->height * tex->pitch;
2487
2488         if (size == 0)
2489                 return 0;
2490
2491         dst_offset = tex->offset;
2492
2493         if (r600_prepare_blit_copy(dev, file_priv)) {
2494                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2495                 return -EAGAIN;
2496         }
2497         do {
2498                 data = (const u8 __user *)image->data;
2499                 pass_size = size;
2500
2501                 buf = radeon_freelist_get(dev);
2502                 if (!buf) {
2503                         DRM_DEBUG("EAGAIN\n");
2504                         if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2505                                 return -EFAULT;
2506                         return -EAGAIN;
2507                 }
2508
2509                 if (pass_size > buf->total)
2510                         pass_size = buf->total;
2511
2512                 /* Dispatch the indirect buffer.
2513                  */
2514                 buffer =
2515                     (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2516
2517                 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2518                         DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2519                         return -EFAULT;
2520                 }
2521
2522                 buf->file_priv = file_priv;
2523                 buf->used = pass_size;
2524                 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2525
2526                 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2527
2528                 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2529
2530                 /* Update the input parameters for next time */
2531                 image->data = (const u8 __user *)image->data + pass_size;
2532                 dst_offset += pass_size;
2533                 size -= pass_size;
2534         } while (size > 0);
2535         r600_done_blit_copy(dev);
2536
2537         return 0;
2538 }
2539
2540 /*
2541  * Legacy cs ioctl
2542  */
2543 static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2544 {
2545         /* FIXME: check if wrap affect last reported wrap & sequence */
2546         radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2547         if (!radeon->cs_id_scnt) {
2548                 /* increment wrap counter */
2549                 radeon->cs_id_wcnt += 0x01000000;
2550                 /* valid sequence counter start at 1 */
2551                 radeon->cs_id_scnt = 1;
2552         }
2553         return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2554 }
2555
2556 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2557 {
2558         RING_LOCALS;
2559
2560         *id = radeon_cs_id_get(dev_priv);
2561
2562         /* SCRATCH 2 */
2563         BEGIN_RING(3);
2564         R600_CLEAR_AGE(*id);
2565         ADVANCE_RING();
2566         COMMIT_RING();
2567 }
2568
2569 static int r600_ib_get(struct drm_device *dev,
2570                         struct drm_file *fpriv,
2571                         struct drm_buf **buffer)
2572 {
2573         struct drm_buf *buf;
2574
2575         *buffer = NULL;
2576         buf = radeon_freelist_get(dev);
2577         if (!buf) {
2578                 return -EBUSY;
2579         }
2580         buf->file_priv = fpriv;
2581         *buffer = buf;
2582         return 0;
2583 }
2584
2585 static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2586                         struct drm_file *fpriv, int l, int r)
2587 {
2588         drm_radeon_private_t *dev_priv = dev->dev_private;
2589
2590         if (buf) {
2591                 if (!r)
2592                         r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2593                 radeon_cp_discard_buffer(dev, fpriv->masterp, buf);
2594                 COMMIT_RING();
2595         }
2596 }
2597
2598 int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2599 {
2600         struct drm_radeon_private *dev_priv = dev->dev_private;
2601         struct drm_radeon_cs *cs = data;
2602         struct drm_buf *buf;
2603         unsigned family;
2604         int l, r = 0;
2605         u32 *ib, cs_id = 0;
2606
2607         if (dev_priv == NULL) {
2608                 DRM_ERROR("called with no initialization\n");
2609                 return -EINVAL;
2610         }
2611         family = dev_priv->flags & RADEON_FAMILY_MASK;
2612         if (family < CHIP_R600) {
2613                 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2614                 return -EINVAL;
2615         }
2616         lockmgr(&dev_priv->cs_mutex, LK_EXCLUSIVE);
2617         /* get ib */
2618         l = 0;
2619         r = r600_ib_get(dev, fpriv, &buf);
2620         if (r) {
2621                 DRM_ERROR("ib_get failed\n");
2622                 goto out;
2623         }
2624         ib = (u32 *)((uintptr_t)dev->agp_buffer_map->handle + buf->offset);
2625         /* now parse command stream */
2626         r = r600_cs_legacy(dev, data,  fpriv, family, ib, &l);
2627         if (r) {
2628                 goto out;
2629         }
2630
2631 out:
2632         r600_ib_free(dev, buf, fpriv, l, r);
2633         /* emit cs id sequence */
2634         r600_cs_id_emit(dev_priv, &cs_id);
2635         cs->cs_id = cs_id;
2636         lockmgr(&dev_priv->cs_mutex, LK_RELEASE);
2637         return r;
2638 }
2639
2640 void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2641 {
2642         struct drm_radeon_private *dev_priv = dev->dev_private;
2643
2644         *npipes = dev_priv->r600_npipes;
2645         *nbanks = dev_priv->r600_nbanks;
2646         *group_size = dev_priv->r600_group_size;
2647 }