drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / radeon_kms.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  *
28  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_kms.c 254885 2013-08-25 19:37:15Z dumbbell $
29  */
30
31 #include <drm/drmP.h>
32 #include "radeon.h"
33 #include <uapi_drm/radeon_drm.h>
34 #include "radeon_asic.h"
35 #include "radeon_kms.h"
36
37 /**
38  * radeon_driver_unload_kms - Main unload function for KMS.
39  *
40  * @dev: drm dev pointer
41  *
42  * This is the main unload function for KMS (all asics).
43  * It calls radeon_modeset_fini() to tear down the
44  * displays, and radeon_device_fini() to tear down
45  * the rest of the device (CP, writeback, etc.).
46  * Returns 0 on success.
47  */
48 int radeon_driver_unload_kms(struct drm_device *dev)
49 {
50         struct radeon_device *rdev = dev->dev_private;
51
52         if (rdev == NULL)
53                 return 0;
54         if (rdev->rmmio == NULL)
55                 goto done_free;
56         radeon_acpi_fini(rdev);
57         radeon_modeset_fini(rdev);
58         radeon_device_fini(rdev);
59
60 done_free:
61         drm_free(rdev, M_DRM);
62         dev->dev_private = NULL;
63         return 0;
64 }
65
66 /**
67  * radeon_driver_load_kms - Main load function for KMS.
68  *
69  * @dev: drm dev pointer
70  * @flags: device flags
71  *
72  * This is the main load function for KMS (all asics).
73  * It calls radeon_device_init() to set up the non-display
74  * parts of the chip (asic init, CP, writeback, etc.), and
75  * radeon_modeset_init() to set up the display parts
76  * (crtcs, encoders, hotplug detect, etc.).
77  * Returns 0 on success, error on failure.
78  */
79 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
80 {
81         struct radeon_device *rdev;
82         int r, acpi_status;
83
84         rdev = kmalloc(sizeof(struct radeon_device), M_DRM,
85                        M_ZERO | M_WAITOK);
86         if (rdev == NULL) {
87                 return -ENOMEM;
88         }
89         dev->dev_private = (void *)rdev;
90
91         /* update BUS flag */
92         if (drm_device_is_agp(dev)) {
93                 DRM_INFO("RADEON_IS_AGP\n");
94                 flags |= RADEON_IS_AGP;
95         } else if (drm_device_is_pcie(dev)) {
96                 DRM_INFO("RADEON_IS_PCIE\n");
97                 flags |= RADEON_IS_PCIE;
98         } else {
99                 DRM_INFO("RADEON_IS_PCI\n");
100                 flags |= RADEON_IS_PCI;
101         }
102
103         /* radeon_device_init should report only fatal error
104          * like memory allocation failure or iomapping failure,
105          * or memory manager initialization failure, it must
106          * properly initialize the GPU MC controller and permit
107          * VRAM allocation
108          */
109         r = radeon_device_init(rdev, dev, flags);
110         if (r) {
111                 dev_err(dev->dev, "Fatal error during GPU init\n");
112                 goto out;
113         }
114
115         /* Again modeset_init should fail only on fatal error
116          * otherwise it should provide enough functionalities
117          * for shadowfb to run
118          */
119         r = radeon_modeset_init(rdev);
120         if (r)
121                 dev_err(dev->dev, "Fatal error during modeset init\n");
122
123         /* Call ACPI methods: require modeset init
124          * but failure is not fatal
125          */
126         if (!r) {
127                 acpi_status = radeon_acpi_init(rdev);
128                 if (acpi_status)
129                 dev_dbg(dev->dev,
130                                 "Error during ACPI methods call\n");
131         }
132
133 out:
134         if (r)
135                 radeon_driver_unload_kms(dev);
136         return r;
137 }
138
139 /**
140  * radeon_set_filp_rights - Set filp right.
141  *
142  * @dev: drm dev pointer
143  * @owner: drm file
144  * @applier: drm file
145  * @value: value
146  *
147  * Sets the filp rights for the device (all asics).
148  */
149 static void radeon_set_filp_rights(struct drm_device *dev,
150                                    struct drm_file **owner,
151                                    struct drm_file *applier,
152                                    uint32_t *value)
153 {
154         DRM_LOCK(dev);
155         if (*value == 1) {
156                 /* wants rights */
157                 if (!*owner)
158                         *owner = applier;
159         } else if (*value == 0) {
160                 /* revokes rights */
161                 if (*owner == applier)
162                         *owner = NULL;
163         }
164         *value = *owner == applier ? 1 : 0;
165         DRM_UNLOCK(dev);
166 }
167
168 /*
169  * Userspace get information ioctl
170  */
171 /**
172  * radeon_info_ioctl - answer a device specific request.
173  *
174  * @rdev: radeon device pointer
175  * @data: request object
176  * @filp: drm filp
177  *
178  * This function is used to pass device specific parameters to the userspace
179  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
180  * etc. (all asics).
181  * Returns 0 on success, -EINVAL on failure.
182  */
183 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
184 {
185         struct radeon_device *rdev = dev->dev_private;
186         struct drm_radeon_info *info = data;
187         struct radeon_mode_info *minfo = &rdev->mode_info;
188         uint32_t *value, value_tmp, *value_ptr, value_size;
189         uint64_t value64;
190         struct drm_crtc *crtc;
191         int i, found;
192
193         value_ptr = (uint32_t *)((unsigned long)info->value);
194         value = &value_tmp;
195         value_size = sizeof(uint32_t);
196
197         switch (info->request) {
198         case RADEON_INFO_DEVICE_ID:
199                 *value = dev->pci_device;
200                 break;
201         case RADEON_INFO_NUM_GB_PIPES:
202                 *value = rdev->num_gb_pipes;
203                 break;
204         case RADEON_INFO_NUM_Z_PIPES:
205                 *value = rdev->num_z_pipes;
206                 break;
207         case RADEON_INFO_ACCEL_WORKING:
208                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
209                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
210                         *value = false;
211                 else
212                         *value = rdev->accel_working;
213                 break;
214         case RADEON_INFO_CRTC_FROM_ID:
215                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
216                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
217                         return -EFAULT;
218                 }
219                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
220                         crtc = (struct drm_crtc *)minfo->crtcs[i];
221                         if (crtc && crtc->base.id == *value) {
222                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
223                                 *value = radeon_crtc->crtc_id;
224                                 found = 1;
225                                 break;
226                         }
227                 }
228                 if (!found) {
229                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
230                         return -EINVAL;
231                 }
232                 break;
233         case RADEON_INFO_ACCEL_WORKING2:
234                 *value = rdev->accel_working;
235                 break;
236         case RADEON_INFO_TILING_CONFIG:
237                 if (rdev->family >= CHIP_BONAIRE)
238                         *value = rdev->config.cik.tile_config;
239                 else if (rdev->family >= CHIP_TAHITI)
240                         *value = rdev->config.si.tile_config;
241                 else if (rdev->family >= CHIP_CAYMAN)
242                         *value = rdev->config.cayman.tile_config;
243                 else if (rdev->family >= CHIP_CEDAR)
244                         *value = rdev->config.evergreen.tile_config;
245                 else if (rdev->family >= CHIP_RV770)
246                         *value = rdev->config.rv770.tile_config;
247                 else if (rdev->family >= CHIP_R600)
248                         *value = rdev->config.r600.tile_config;
249                 else {
250                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
251                         return -EINVAL;
252                 }
253                 break;
254         case RADEON_INFO_WANT_HYPERZ:
255                 /* The "value" here is both an input and output parameter.
256                  * If the input value is 1, filp requests hyper-z access.
257                  * If the input value is 0, filp revokes its hyper-z access.
258                  *
259                  * When returning, the value is 1 if filp owns hyper-z access,
260                  * 0 otherwise. */
261                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
262                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
263                         return -EFAULT;
264                 }
265                 if (*value >= 2) {
266                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
267                         return -EINVAL;
268                 }
269                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
270                 break;
271         case RADEON_INFO_WANT_CMASK:
272                 /* The same logic as Hyper-Z. */
273                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
274                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
275                         return -EFAULT;
276                 }
277                 if (*value >= 2) {
278                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
279                         return -EINVAL;
280                 }
281                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
282                 break;
283         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
284                 /* return clock value in KHz */
285                 if (rdev->asic->get_xclk)
286                         *value = radeon_get_xclk(rdev) * 10;
287                 else
288                         *value = rdev->clock.spll.reference_freq * 10;
289                 break;
290         case RADEON_INFO_NUM_BACKENDS:
291                 if (rdev->family >= CHIP_BONAIRE)
292                         *value = rdev->config.cik.max_backends_per_se *
293                                 rdev->config.cik.max_shader_engines;
294                 else if (rdev->family >= CHIP_TAHITI)
295                         *value = rdev->config.si.max_backends_per_se *
296                                 rdev->config.si.max_shader_engines;
297                 else if (rdev->family >= CHIP_CAYMAN)
298                         *value = rdev->config.cayman.max_backends_per_se *
299                                 rdev->config.cayman.max_shader_engines;
300                 else if (rdev->family >= CHIP_CEDAR)
301                         *value = rdev->config.evergreen.max_backends;
302                 else if (rdev->family >= CHIP_RV770)
303                         *value = rdev->config.rv770.max_backends;
304                 else if (rdev->family >= CHIP_R600)
305                         *value = rdev->config.r600.max_backends;
306                 else {
307                         return -EINVAL;
308                 }
309                 break;
310         case RADEON_INFO_NUM_TILE_PIPES:
311                 if (rdev->family >= CHIP_BONAIRE)
312                         *value = rdev->config.cik.max_tile_pipes;
313                 else if (rdev->family >= CHIP_TAHITI)
314                         *value = rdev->config.si.max_tile_pipes;
315                 else if (rdev->family >= CHIP_CAYMAN)
316                         *value = rdev->config.cayman.max_tile_pipes;
317                 else if (rdev->family >= CHIP_CEDAR)
318                         *value = rdev->config.evergreen.max_tile_pipes;
319                 else if (rdev->family >= CHIP_RV770)
320                         *value = rdev->config.rv770.max_tile_pipes;
321                 else if (rdev->family >= CHIP_R600)
322                         *value = rdev->config.r600.max_tile_pipes;
323                 else {
324                         return -EINVAL;
325                 }
326                 break;
327         case RADEON_INFO_FUSION_GART_WORKING:
328                 *value = 1;
329                 break;
330         case RADEON_INFO_BACKEND_MAP:
331                 if (rdev->family >= CHIP_BONAIRE)
332                         return -EINVAL;
333                 else if (rdev->family >= CHIP_TAHITI)
334                         *value = rdev->config.si.backend_map;
335                 else if (rdev->family >= CHIP_CAYMAN)
336                         *value = rdev->config.cayman.backend_map;
337                 else if (rdev->family >= CHIP_CEDAR)
338                         *value = rdev->config.evergreen.backend_map;
339                 else if (rdev->family >= CHIP_RV770)
340                         *value = rdev->config.rv770.backend_map;
341                 else if (rdev->family >= CHIP_R600)
342                         *value = rdev->config.r600.backend_map;
343                 else {
344                         return -EINVAL;
345                 }
346                 break;
347         case RADEON_INFO_VA_START:
348                 /* this is where we report if vm is supported or not */
349                 if (rdev->family < CHIP_CAYMAN)
350                         return -EINVAL;
351                 *value = RADEON_VA_RESERVED_SIZE;
352                 break;
353         case RADEON_INFO_IB_VM_MAX_SIZE:
354                 /* this is where we report if vm is supported or not */
355                 if (rdev->family < CHIP_CAYMAN)
356                         return -EINVAL;
357                 *value = RADEON_IB_VM_MAX_SIZE;
358                 break;
359         case RADEON_INFO_MAX_PIPES:
360                 if (rdev->family >= CHIP_BONAIRE)
361                         *value = rdev->config.cik.max_cu_per_sh;
362                 else if (rdev->family >= CHIP_TAHITI)
363                         *value = rdev->config.si.max_cu_per_sh;
364                 else if (rdev->family >= CHIP_CAYMAN)
365                         *value = rdev->config.cayman.max_pipes_per_simd;
366                 else if (rdev->family >= CHIP_CEDAR)
367                         *value = rdev->config.evergreen.max_pipes;
368                 else if (rdev->family >= CHIP_RV770)
369                         *value = rdev->config.rv770.max_pipes;
370                 else if (rdev->family >= CHIP_R600)
371                         *value = rdev->config.r600.max_pipes;
372                 else {
373                         return -EINVAL;
374                 }
375                 break;
376         case RADEON_INFO_TIMESTAMP:
377                 if (rdev->family < CHIP_R600) {
378                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
379                         return -EINVAL;
380                 }
381                 value = (uint32_t*)&value64;
382                 value_size = sizeof(uint64_t);
383                 value64 = radeon_get_gpu_clock_counter(rdev);
384                 break;
385         case RADEON_INFO_MAX_SE:
386                 if (rdev->family >= CHIP_BONAIRE)
387                         *value = rdev->config.cik.max_shader_engines;
388                 else if (rdev->family >= CHIP_TAHITI)
389                         *value = rdev->config.si.max_shader_engines;
390                 else if (rdev->family >= CHIP_CAYMAN)
391                         *value = rdev->config.cayman.max_shader_engines;
392                 else if (rdev->family >= CHIP_CEDAR)
393                         *value = rdev->config.evergreen.num_ses;
394                 else
395                         *value = 1;
396                 break;
397         case RADEON_INFO_MAX_SH_PER_SE:
398                 if (rdev->family >= CHIP_BONAIRE)
399                         *value = rdev->config.cik.max_sh_per_se;
400                 else if (rdev->family >= CHIP_TAHITI)
401                         *value = rdev->config.si.max_sh_per_se;
402                 else
403                         return -EINVAL;
404                 break;
405         case RADEON_INFO_FASTFB_WORKING:
406                 *value = rdev->fastfb_working;
407                 break;
408         case RADEON_INFO_RING_WORKING:
409                 if (DRM_COPY_FROM_USER(value, value_ptr, sizeof(uint32_t))) {
410                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
411                         return -EFAULT;
412                 }
413                 switch (*value) {
414                 case RADEON_CS_RING_GFX:
415                 case RADEON_CS_RING_COMPUTE:
416                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
417                         break;
418                 case RADEON_CS_RING_DMA:
419                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
420                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
421                         break;
422                 case RADEON_CS_RING_UVD:
423                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
424                         break;
425                 default:
426                         return -EINVAL;
427                 }
428                 break;
429         case RADEON_INFO_SI_TILE_MODE_ARRAY:
430                 if (rdev->family >= CHIP_BONAIRE) {
431                         value = rdev->config.cik.tile_mode_array;
432                         value_size = sizeof(uint32_t)*32;
433                 } else if (rdev->family >= CHIP_TAHITI) {
434                         value = rdev->config.si.tile_mode_array;
435                         value_size = sizeof(uint32_t)*32;
436                 } else {
437                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
438                         return -EINVAL;
439                 }
440                 break;
441         default:
442                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
443                 return -EINVAL;
444         }
445         if (DRM_COPY_TO_USER(value_ptr, (char*)value, value_size)) {
446                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
447                 return -EFAULT;
448         }
449         return 0;
450 }
451
452
453 /*
454  * Outdated mess for old drm with Xorg being in charge (void function now).
455  */
456 /**
457  * radeon_driver_firstopen_kms - drm callback for first open
458  *
459  * @dev: drm dev pointer
460  *
461  * Nothing to be done for KMS (all asics).
462  * Returns 0 on success.
463  */
464 int radeon_driver_firstopen_kms(struct drm_device *dev)
465 {
466         return 0;
467 }
468
469 /**
470  * radeon_driver_firstopen_kms - drm callback for last close
471  *
472  * @dev: drm dev pointer
473  *
474  * Switch vga switcheroo state after last close (all asics).
475  */
476 void radeon_driver_lastclose_kms(struct drm_device *dev)
477 {
478 #ifdef DUMBBELL_WIP
479         vga_switcheroo_process_delayed_switch();
480 #endif /* DUMBBELL_WIP */
481 }
482
483 /**
484  * radeon_driver_open_kms - drm callback for open
485  *
486  * @dev: drm dev pointer
487  * @file_priv: drm file
488  *
489  * On device open, init vm on cayman+ (all asics).
490  * Returns 0 on success, error on failure.
491  */
492 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
493 {
494         struct radeon_device *rdev = dev->dev_private;
495
496         file_priv->driver_priv = NULL;
497
498         /* new gpu have virtual address space support */
499         if (rdev->family >= CHIP_CAYMAN) {
500                 struct radeon_fpriv *fpriv;
501                 struct radeon_bo_va *bo_va;
502                 int r;
503
504                 fpriv = kmalloc(sizeof(*fpriv), M_DRM,
505                                 M_ZERO | M_WAITOK);
506                 if (unlikely(!fpriv)) {
507                         return -ENOMEM;
508                 }
509
510                 radeon_vm_init(rdev, &fpriv->vm);
511
512                 /* map the ib pool buffer read only into
513                  * virtual address space */
514                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
515                                          rdev->ring_tmp_bo.bo);
516                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
517                                           RADEON_VM_PAGE_READABLE |
518                                           RADEON_VM_PAGE_SNOOPED);
519                 if (r) {
520                         radeon_vm_fini(rdev, &fpriv->vm);
521                         drm_free(fpriv, M_DRM);
522                         return r;
523                 }
524
525                 file_priv->driver_priv = fpriv;
526         }
527         return 0;
528 }
529
530 /**
531  * radeon_driver_postclose_kms - drm callback for post close
532  *
533  * @dev: drm dev pointer
534  * @file_priv: drm file
535  *
536  * On device post close, tear down vm on cayman+ (all asics).
537  */
538 void radeon_driver_postclose_kms(struct drm_device *dev,
539                                  struct drm_file *file_priv)
540 {
541         struct radeon_device *rdev = dev->dev_private;
542
543         /* new gpu have virtual address space support */
544         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
545                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
546                 struct radeon_bo_va *bo_va;
547                 int r;
548
549                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
550                 if (!r) {
551                         bo_va = radeon_vm_bo_find(&fpriv->vm,
552                                                   rdev->ring_tmp_bo.bo);
553                         if (bo_va)
554                                 radeon_vm_bo_rmv(rdev, bo_va);
555                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
556                 }
557
558                 radeon_vm_fini(rdev, &fpriv->vm);
559                 drm_free(fpriv, M_DRM);
560                 file_priv->driver_priv = NULL;
561         }
562 }
563
564 /**
565  * radeon_driver_preclose_kms - drm callback for pre close
566  *
567  * @dev: drm dev pointer
568  * @file_priv: drm file
569  *
570  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
571  * (all asics).
572  */
573 void radeon_driver_preclose_kms(struct drm_device *dev,
574                                 struct drm_file *file_priv)
575 {
576         struct radeon_device *rdev = dev->dev_private;
577         if (rdev->hyperz_filp == file_priv)
578                 rdev->hyperz_filp = NULL;
579         if (rdev->cmask_filp == file_priv)
580                 rdev->cmask_filp = NULL;
581         radeon_uvd_free_handles(rdev, file_priv);
582 }
583
584 /*
585  * VBlank related functions.
586  */
587 /**
588  * radeon_get_vblank_counter_kms - get frame count
589  *
590  * @dev: drm dev pointer
591  * @crtc: crtc to get the frame count from
592  *
593  * Gets the frame count on the requested crtc (all asics).
594  * Returns frame count on success, -EINVAL on failure.
595  */
596 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
597 {
598         struct radeon_device *rdev = dev->dev_private;
599
600         if (crtc < 0 || crtc >= rdev->num_crtc) {
601                 DRM_ERROR("Invalid crtc %d\n", crtc);
602                 return -EINVAL;
603         }
604
605         return radeon_get_vblank_counter(rdev, crtc);
606 }
607
608 /**
609  * radeon_enable_vblank_kms - enable vblank interrupt
610  *
611  * @dev: drm dev pointer
612  * @crtc: crtc to enable vblank interrupt for
613  *
614  * Enable the interrupt on the requested crtc (all asics).
615  * Returns 0 on success, -EINVAL on failure.
616  */
617 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
618 {
619         struct radeon_device *rdev = dev->dev_private;
620         int r;
621
622         if (crtc < 0 || crtc >= rdev->num_crtc) {
623                 DRM_ERROR("Invalid crtc %d\n", crtc);
624                 return -EINVAL;
625         }
626
627         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
628         rdev->irq.crtc_vblank_int[crtc] = true;
629         r = radeon_irq_set(rdev);
630         lockmgr(&rdev->irq.lock, LK_RELEASE);
631         return r;
632 }
633
634 /**
635  * radeon_disable_vblank_kms - disable vblank interrupt
636  *
637  * @dev: drm dev pointer
638  * @crtc: crtc to disable vblank interrupt for
639  *
640  * Disable the interrupt on the requested crtc (all asics).
641  */
642 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
643 {
644         struct radeon_device *rdev = dev->dev_private;
645
646         if (crtc < 0 || crtc >= rdev->num_crtc) {
647                 DRM_ERROR("Invalid crtc %d\n", crtc);
648                 return;
649         }
650
651         lockmgr(&rdev->irq.lock, LK_EXCLUSIVE);
652         rdev->irq.crtc_vblank_int[crtc] = false;
653         radeon_irq_set(rdev);
654         lockmgr(&rdev->irq.lock, LK_RELEASE);
655 }
656
657 /**
658  * radeon_get_vblank_timestamp_kms - get vblank timestamp
659  *
660  * @dev: drm dev pointer
661  * @crtc: crtc to get the timestamp for
662  * @max_error: max error
663  * @vblank_time: time value
664  * @flags: flags passed to the driver
665  *
666  * Gets the timestamp on the requested crtc based on the
667  * scanout position.  (all asics).
668  * Returns postive status flags on success, negative error on failure.
669  */
670 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
671                                     int *max_error,
672                                     struct timeval *vblank_time,
673                                     unsigned flags)
674 {
675         struct drm_crtc *drmcrtc;
676         struct radeon_device *rdev = dev->dev_private;
677
678         if (crtc < 0 || crtc >= dev->num_crtcs) {
679                 DRM_ERROR("Invalid crtc %d\n", crtc);
680                 return -EINVAL;
681         }
682
683         /* Get associated drm_crtc: */
684         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
685
686         /* Helper routine in DRM core does all the work: */
687         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
688                                                      vblank_time, flags,
689                                                      drmcrtc);
690 }
691
692 /*
693  * IOCTL.
694  */
695 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
696                          struct drm_file *file_priv)
697 {
698         /* Not valid in KMS. */
699         return -EINVAL;
700 }
701
702 #define KMS_INVALID_IOCTL(name)                                         \
703 static int                                                              \
704 name(struct drm_device *dev, void *data, struct drm_file *file_priv)    \
705 {                                                                       \
706         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
707         return -EINVAL;                                                 \
708 }
709
710 /*
711  * All these ioctls are invalid in kms world.
712  */
713 KMS_INVALID_IOCTL(radeon_cp_init_kms)
714 KMS_INVALID_IOCTL(radeon_cp_start_kms)
715 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
716 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
717 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
718 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
719 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
720 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
721 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
722 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
723 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
724 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
725 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
726 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
727 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
728 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
729 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
730 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
731 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
732 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
733 KMS_INVALID_IOCTL(radeon_mem_free_kms)
734 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
735 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
736 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
737 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
738 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
739 KMS_INVALID_IOCTL(radeon_surface_free_kms)
740
741
742 struct drm_ioctl_desc radeon_ioctls_kms[] = {
743         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
744         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
745         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
746         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
747         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
748         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
749         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
750         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
751         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
752         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
753         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
754         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
755         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
756         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
757         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
758         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
759         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
760         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
761         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
762         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
763         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
764         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
765         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
766         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
767         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
768         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
769         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
770         /* KMS */
771         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
772         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
773         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
774         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
775         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
776         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
777         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
778         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
779         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
780         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
781         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
782         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
783         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
784 };
785 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);