drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / radeon_object.c
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  *
32  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_object.c 254885 2013-08-25 19:37:15Z dumbbell $
33  */
34
35 #include <drm/drmP.h>
36 #include <uapi_drm/radeon_drm.h>
37 #include "radeon.h"
38 #ifdef DUMBBELL_WIP
39 #include "radeon_trace.h"
40 #endif /* DUMBBELL_WIP */
41 #include <linux/io.h>
42
43
44 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45
46 /*
47  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
48  * function are calling it.
49  */
50
51 static void radeon_bo_clear_va(struct radeon_bo *bo)
52 {
53         struct radeon_bo_va *bo_va, *tmp;
54
55         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
56                 /* remove from all vm address space */
57                 radeon_vm_bo_rmv(bo->rdev, bo_va);
58         }
59 }
60
61 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
62 {
63         struct radeon_bo *bo;
64
65         bo = container_of(tbo, struct radeon_bo, tbo);
66         spin_lock(&bo->rdev->gem.mutex);
67         list_del_init(&bo->list);
68         spin_unlock(&bo->rdev->gem.mutex);
69         radeon_bo_clear_surface_reg(bo);
70         radeon_bo_clear_va(bo);
71         drm_gem_object_release(&bo->gem_base);
72         drm_free(bo, M_DRM);
73 }
74
75 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
76 {
77         if (bo->destroy == &radeon_ttm_bo_destroy)
78                 return true;
79         return false;
80 }
81
82 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
83 {
84         u32 c = 0;
85
86         rbo->placement.fpfn = 0;
87         rbo->placement.lpfn = 0;
88         rbo->placement.placement = rbo->placements;
89         rbo->placement.busy_placement = rbo->placements;
90         if (domain & RADEON_GEM_DOMAIN_VRAM)
91                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
92                                         TTM_PL_FLAG_VRAM;
93         if (domain & RADEON_GEM_DOMAIN_GTT) {
94                 if (rbo->rdev->flags & RADEON_IS_AGP) {
95                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
96                 } else {
97                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
98                 }
99         }
100         if (domain & RADEON_GEM_DOMAIN_CPU) {
101                 if (rbo->rdev->flags & RADEON_IS_AGP) {
102                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
103                 } else {
104                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
105                 }
106         }
107         if (!c)
108                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
109         rbo->placement.num_placement = c;
110         rbo->placement.num_busy_placement = c;
111 }
112
113 int radeon_bo_create(struct radeon_device *rdev,
114                      unsigned long size, int byte_align, bool kernel, u32 domain,
115                      struct sg_table *sg, struct radeon_bo **bo_ptr)
116 {
117         struct radeon_bo *bo;
118         enum ttm_bo_type type;
119         unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
120         size_t acc_size;
121         int r;
122
123         size = roundup2(size, PAGE_SIZE);
124
125         if (kernel) {
126                 type = ttm_bo_type_kernel;
127         } else if (sg) {
128                 type = ttm_bo_type_sg;
129         } else {
130                 type = ttm_bo_type_device;
131         }
132         *bo_ptr = NULL;
133
134         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
135                                        sizeof(struct radeon_bo));
136
137         bo = kmalloc(sizeof(struct radeon_bo), M_DRM,
138                      M_ZERO | M_WAITOK);
139         if (bo == NULL)
140                 return -ENOMEM;
141         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
142         if (unlikely(r)) {
143                 drm_free(bo, M_DRM);
144                 return r;
145         }
146         bo->rdev = rdev;
147         bo->surface_reg = -1;
148         INIT_LIST_HEAD(&bo->list);
149         INIT_LIST_HEAD(&bo->va);
150         radeon_ttm_placement_from_domain(bo, domain);
151         /* Kernel allocation are uninterruptible */
152         lockmgr(&rdev->pm.mclk_lock, LK_SHARED);
153         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
154                         &bo->placement, page_align, !kernel, NULL,
155                         acc_size, sg, &radeon_ttm_bo_destroy);
156         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE);
157         if (unlikely(r != 0)) {
158                 return r;
159         }
160         *bo_ptr = bo;
161
162 #ifdef DUMBBELL_WIP
163         trace_radeon_bo_create(bo);
164 #endif /* DUMBBELL_WIP */
165
166         return 0;
167 }
168
169 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
170 {
171         bool is_iomem;
172         int r;
173
174         if (bo->kptr) {
175                 if (ptr) {
176                         *ptr = bo->kptr;
177                 }
178                 return 0;
179         }
180         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
181         if (r) {
182                 return r;
183         }
184         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
185         if (ptr) {
186                 *ptr = bo->kptr;
187         }
188         radeon_bo_check_tiling(bo, 0, 0);
189         return 0;
190 }
191
192 void radeon_bo_kunmap(struct radeon_bo *bo)
193 {
194         if (bo->kptr == NULL)
195                 return;
196         bo->kptr = NULL;
197         radeon_bo_check_tiling(bo, 0, 0);
198         ttm_bo_kunmap(&bo->kmap);
199 }
200
201 void radeon_bo_unref(struct radeon_bo **bo)
202 {
203         struct ttm_buffer_object *tbo;
204         struct radeon_device *rdev;
205         struct radeon_bo *rbo;
206
207         if ((rbo = *bo) == NULL)
208                 return;
209         *bo = NULL;
210         rdev = rbo->rdev;
211         tbo = &rbo->tbo;
212         lockmgr(&rdev->pm.mclk_lock, LK_SHARED);
213         ttm_bo_unref(&tbo);
214         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE);
215 }
216
217 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
218                              u64 *gpu_addr)
219 {
220         int r, i;
221
222         if (bo->pin_count) {
223                 bo->pin_count++;
224                 if (gpu_addr)
225                         *gpu_addr = radeon_bo_gpu_offset(bo);
226
227                 if (max_offset != 0) {
228                         u64 domain_start;
229
230                         if (domain == RADEON_GEM_DOMAIN_VRAM)
231                                 domain_start = bo->rdev->mc.vram_start;
232                         else
233                                 domain_start = bo->rdev->mc.gtt_start;
234                         if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) {
235                                 DRM_ERROR("radeon_bo_pin_restricted: "
236                                     "max_offset(%ju) < "
237                                     "(radeon_bo_gpu_offset(%ju) - "
238                                     "domain_start(%ju)",
239                                     (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo),
240                                     (uintmax_t)domain_start);
241                         }
242                 }
243
244                 return 0;
245         }
246         radeon_ttm_placement_from_domain(bo, domain);
247         if (domain == RADEON_GEM_DOMAIN_VRAM) {
248                 /* force to pin into visible video ram */
249                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
250         }
251         if (max_offset) {
252                 u64 lpfn = max_offset >> PAGE_SHIFT;
253
254                 if (!bo->placement.lpfn)
255                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
256
257                 if (lpfn < bo->placement.lpfn)
258                         bo->placement.lpfn = lpfn;
259         }
260         for (i = 0; i < bo->placement.num_placement; i++)
261                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
262         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
263         if (likely(r == 0)) {
264                 bo->pin_count = 1;
265                 if (gpu_addr != NULL)
266                         *gpu_addr = radeon_bo_gpu_offset(bo);
267         }
268         if (unlikely(r != 0))
269                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
270         return r;
271 }
272
273 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
274 {
275         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
276 }
277
278 int radeon_bo_unpin(struct radeon_bo *bo)
279 {
280         int r, i;
281
282         if (!bo->pin_count) {
283                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
284                 return 0;
285         }
286         bo->pin_count--;
287         if (bo->pin_count)
288                 return 0;
289         for (i = 0; i < bo->placement.num_placement; i++)
290                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
291         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
292         if (unlikely(r != 0))
293                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
294         return r;
295 }
296
297 int radeon_bo_evict_vram(struct radeon_device *rdev)
298 {
299         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
300         if (0 && (rdev->flags & RADEON_IS_IGP)) {
301                 if (rdev->mc.igp_sideport_enabled == false)
302                         /* Useless to evict on IGP chips */
303                         return 0;
304         }
305         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
306 }
307
308 void radeon_bo_force_delete(struct radeon_device *rdev)
309 {
310         struct radeon_bo *bo, *n;
311
312         if (list_empty(&rdev->gem.objects)) {
313                 return;
314         }
315         dev_err(rdev->dev, "Userspace still has active objects !\n");
316         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
317                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
318                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
319                         *((unsigned long *)&bo->gem_base.refcount));
320                 spin_lock(&bo->rdev->gem.mutex);
321                 list_del_init(&bo->list);
322                 spin_unlock(&bo->rdev->gem.mutex);
323                 /* this should unref the ttm bo */
324                 drm_gem_object_unreference(&bo->gem_base);
325         }
326 }
327
328 int radeon_bo_init(struct radeon_device *rdev)
329 {
330         /* Add an MTRR for the VRAM */
331         if (!rdev->fastfb_working) {
332                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, rdev->mc.aper_size);
333         }
334         DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n",
335                 (uintmax_t)rdev->mc.mc_vram_size >> 20,
336                 (uintmax_t)rdev->mc.aper_size >> 20);
337         DRM_INFO("RAM width %dbits %cDR\n",
338                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
339         return radeon_ttm_init(rdev);
340 }
341
342 void radeon_bo_fini(struct radeon_device *rdev)
343 {
344         radeon_ttm_fini(rdev);
345         arch_phys_wc_del(rdev->mc.vram_mtrr);
346 }
347
348 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
349                                 struct list_head *head)
350 {
351         if (lobj->written) {
352                 list_add(&lobj->tv.head, head);
353         } else {
354                 list_add_tail(&lobj->tv.head, head);
355         }
356 }
357
358 int radeon_bo_list_validate(struct list_head *head, int ring)
359 {
360         struct radeon_bo_list *lobj;
361         struct radeon_bo *bo;
362         u32 domain;
363         int r;
364
365         r = ttm_eu_reserve_buffers(head);
366         if (unlikely(r != 0)) {
367                 return r;
368         }
369         list_for_each_entry(lobj, head, tv.head) {
370                 bo = lobj->bo;
371                 if (!bo->pin_count) {
372                         domain = lobj->domain;
373                         
374                 retry:
375                         radeon_ttm_placement_from_domain(bo, domain);
376                         if (ring == R600_RING_TYPE_UVD_INDEX)
377                                 radeon_uvd_force_into_uvd_segment(bo);
378                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
379                                                 true, false);
380                         if (unlikely(r)) {
381                                 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
382                                         domain = lobj->alt_domain;
383                                         goto retry;
384                                 }
385                                 return r;
386                         }
387                 }
388                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
389                 lobj->tiling_flags = bo->tiling_flags;
390         }
391         return 0;
392 }
393
394 #ifdef DUMBBELL_WIP
395 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
396                              struct vm_area_struct *vma)
397 {
398         return ttm_fbdev_mmap(vma, &bo->tbo);
399 }
400 #endif /* DUMBBELL_WIP */
401
402 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
403 {
404         struct radeon_device *rdev = bo->rdev;
405         struct radeon_surface_reg *reg;
406         struct radeon_bo *old_object;
407         int steal;
408         int i;
409
410         KASSERT(radeon_bo_is_reserved(bo),
411             ("radeon_bo_get_surface_reg: radeon_bo is not reserved"));
412
413         if (!bo->tiling_flags)
414                 return 0;
415
416         if (bo->surface_reg >= 0) {
417                 reg = &rdev->surface_regs[bo->surface_reg];
418                 i = bo->surface_reg;
419                 goto out;
420         }
421
422         steal = -1;
423         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
424
425                 reg = &rdev->surface_regs[i];
426                 if (!reg->bo)
427                         break;
428
429                 old_object = reg->bo;
430                 if (old_object->pin_count == 0)
431                         steal = i;
432         }
433
434         /* if we are all out */
435         if (i == RADEON_GEM_MAX_SURFACES) {
436                 if (steal == -1)
437                         return -ENOMEM;
438                 /* find someone with a surface reg and nuke their BO */
439                 reg = &rdev->surface_regs[steal];
440                 old_object = reg->bo;
441                 /* blow away the mapping */
442                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
443                 ttm_bo_unmap_virtual(&old_object->tbo);
444                 old_object->surface_reg = -1;
445                 i = steal;
446         }
447
448         bo->surface_reg = i;
449         reg->bo = bo;
450
451 out:
452         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
453                                bo->tbo.mem.start << PAGE_SHIFT,
454                                bo->tbo.num_pages << PAGE_SHIFT);
455         return 0;
456 }
457
458 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
459 {
460         struct radeon_device *rdev = bo->rdev;
461         struct radeon_surface_reg *reg;
462
463         if (bo->surface_reg == -1)
464                 return;
465
466         reg = &rdev->surface_regs[bo->surface_reg];
467         radeon_clear_surface_reg(rdev, bo->surface_reg);
468
469         reg->bo = NULL;
470         bo->surface_reg = -1;
471 }
472
473 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
474                                 uint32_t tiling_flags, uint32_t pitch)
475 {
476         struct radeon_device *rdev = bo->rdev;
477         int r;
478
479         if (rdev->family >= CHIP_CEDAR) {
480                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
481
482                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
483                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
484                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
485                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
486                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
487                 switch (bankw) {
488                 case 0:
489                 case 1:
490                 case 2:
491                 case 4:
492                 case 8:
493                         break;
494                 default:
495                         return -EINVAL;
496                 }
497                 switch (bankh) {
498                 case 0:
499                 case 1:
500                 case 2:
501                 case 4:
502                 case 8:
503                         break;
504                 default:
505                         return -EINVAL;
506                 }
507                 switch (mtaspect) {
508                 case 0:
509                 case 1:
510                 case 2:
511                 case 4:
512                 case 8:
513                         break;
514                 default:
515                         return -EINVAL;
516                 }
517                 if (tilesplit > 6) {
518                         return -EINVAL;
519                 }
520                 if (stilesplit > 6) {
521                         return -EINVAL;
522                 }
523         }
524         r = radeon_bo_reserve(bo, false);
525         if (unlikely(r != 0))
526                 return r;
527         bo->tiling_flags = tiling_flags;
528         bo->pitch = pitch;
529         radeon_bo_unreserve(bo);
530         return 0;
531 }
532
533 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
534                                 uint32_t *tiling_flags,
535                                 uint32_t *pitch)
536 {
537         KASSERT(radeon_bo_is_reserved(bo),
538             ("radeon_bo_get_tiling_flags: radeon_bo is not reserved"));
539         if (tiling_flags)
540                 *tiling_flags = bo->tiling_flags;
541         if (pitch)
542                 *pitch = bo->pitch;
543 }
544
545 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
546                                 bool force_drop)
547 {
548         KASSERT((radeon_bo_is_reserved(bo) || force_drop),
549             ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop"));
550
551         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
552                 return 0;
553
554         if (force_drop) {
555                 radeon_bo_clear_surface_reg(bo);
556                 return 0;
557         }
558
559         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
560                 if (!has_moved)
561                         return 0;
562
563                 if (bo->surface_reg >= 0)
564                         radeon_bo_clear_surface_reg(bo);
565                 return 0;
566         }
567
568         if ((bo->surface_reg >= 0) && !has_moved)
569                 return 0;
570
571         return radeon_bo_get_surface_reg(bo);
572 }
573
574 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
575                            struct ttm_mem_reg *mem)
576 {
577         struct radeon_bo *rbo;
578         if (!radeon_ttm_bo_is_radeon_bo(bo))
579                 return;
580         rbo = container_of(bo, struct radeon_bo, tbo);
581         radeon_bo_check_tiling(rbo, 0, 1);
582         radeon_vm_bo_invalidate(rbo->rdev, rbo);
583 }
584
585 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
586 {
587         struct radeon_device *rdev;
588         struct radeon_bo *rbo;
589         unsigned long offset, size;
590         int r;
591
592         if (!radeon_ttm_bo_is_radeon_bo(bo))
593                 return 0;
594         rbo = container_of(bo, struct radeon_bo, tbo);
595         radeon_bo_check_tiling(rbo, 0, 0);
596         rdev = rbo->rdev;
597         if (bo->mem.mem_type == TTM_PL_VRAM) {
598                 size = bo->mem.num_pages << PAGE_SHIFT;
599                 offset = bo->mem.start << PAGE_SHIFT;
600                 if ((offset + size) > rdev->mc.visible_vram_size) {
601                         /* hurrah the memory is not visible ! */
602                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
603                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
604                         r = ttm_bo_validate(bo, &rbo->placement, false, false);
605                         if (unlikely(r != 0))
606                                 return r;
607                         offset = bo->mem.start << PAGE_SHIFT;
608                         /* this should not happen */
609                         if ((offset + size) > rdev->mc.visible_vram_size)
610                                 return -EINVAL;
611                 }
612         }
613         return 0;
614 }
615
616 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
617 {
618         int r;
619
620         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
621         if (unlikely(r != 0))
622                 return r;
623         lockmgr(&bo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
624         if (mem_type)
625                 *mem_type = bo->tbo.mem.mem_type;
626         if (bo->tbo.sync_obj)
627                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
628         lockmgr(&bo->tbo.bdev->fence_lock, LK_RELEASE);
629         ttm_bo_unreserve(&bo->tbo);
630         return r;
631 }
632
633
634 /**
635  * radeon_bo_reserve - reserve bo
636  * @bo:         bo structure
637  * @no_intr:    don't return -ERESTARTSYS on pending signal
638  *
639  * Returns:
640  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
641  * a signal. Release all buffer reservations and return to user-space.
642  */
643 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
644 {
645         int r;
646
647         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
648         if (unlikely(r != 0)) {
649                 if (r != -ERESTARTSYS)
650                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
651                 return r;
652         }
653         return 0;
654 }