sys/dev/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *
  28  * $FreeBSD: head/sys/dev/drm2/radeon/rv770.c 254885 2013-08-25 19:37:15Z dumbbell $
  29  */
  30
  31 #include <drm/drmP.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include <uapi_drm/radeon_drm.h>
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  44
  45 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  46 {
  47         unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  48         int r;
  49
  50         /* RV740 uses evergreen uvd clk programming */
  51         if (rdev->family == CHIP_RV740)
  52                 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
  53
  54         /* bypass vclk and dclk with bclk */
  55         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  56                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  57                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  58
  59         if (!vclk || !dclk) {
  60                 /* keep the Bypass mode, put PLL to sleep */
  61                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  62                 return 0;
  63         }
  64
  65         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
  66                                           43663, 0x03FFFFFE, 1, 30, ~0,
  67                                           &fb_div, &vclk_div, &dclk_div);
  68         if (r)
  69                 return r;
  70
  71         fb_div |= 1;
  72         vclk_div -= 1;
  73         dclk_div -= 1;
  74
  75         /* set UPLL_FB_DIV to 0x50000 */
  76         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
  77
  78         /* deassert UPLL_RESET and UPLL_SLEEP */
  79         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
  80
  81         /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
  82         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  83         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
  84
  85         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  86         if (r)
  87                 return r;
  88
  89         /* assert PLL_RESET */
  90         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  91
  92         /* set the required FB_DIV, REF_DIV, Post divder values */
  93         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
  94         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  95                  UPLL_SW_HILEN(vclk_div >> 1) |
  96                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
  97                  UPLL_SW_HILEN2(dclk_div >> 1) |
  98                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
  99                  ~UPLL_SW_MASK);
 100
 101         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
 102                  ~UPLL_FB_DIV_MASK);
 103
 104         /* give the PLL some time to settle */
 105         DRM_MDELAY(15);
 106
 107         /* deassert PLL_RESET */
 108         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 109
 110         DRM_MDELAY(15);
 111
 112         /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
 113         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 114         WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
 115
 116         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 117         if (r)
 118                 return r;
 119
 120         /* switch VCLK and DCLK selection */
 121         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 122                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 123                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 124
 125         DRM_MDELAY(100);
 126
 127         return 0;
 128 }
 129
 130 static const u32 r7xx_golden_registers[] =
 131 {
 132         0x8d00, 0xffffffff, 0x0e0e0074,
 133         0x8d04, 0xffffffff, 0x013a2b34,
 134         0x9508, 0xffffffff, 0x00000002,
 135         0x8b20, 0xffffffff, 0,
 136         0x88c4, 0xffffffff, 0x000000c2,
 137         0x28350, 0xffffffff, 0,
 138         0x9058, 0xffffffff, 0x0fffc40f,
 139         0x240c, 0xffffffff, 0x00000380,
 140         0x733c, 0xffffffff, 0x00000002,
 141         0x2650, 0x00040000, 0,
 142         0x20bc, 0x00040000, 0,
 143         0x7300, 0xffffffff, 0x001000f0
 144 };
 145
 146 static const u32 r7xx_golden_dyn_gpr_registers[] =
 147 {
 148         0x8db0, 0xffffffff, 0x98989898,
 149         0x8db4, 0xffffffff, 0x98989898,
 150         0x8db8, 0xffffffff, 0x98989898,
 151         0x8dbc, 0xffffffff, 0x98989898,
 152         0x8dc0, 0xffffffff, 0x98989898,
 153         0x8dc4, 0xffffffff, 0x98989898,
 154         0x8dc8, 0xffffffff, 0x98989898,
 155         0x8dcc, 0xffffffff, 0x98989898,
 156         0x88c4, 0xffffffff, 0x00000082
 157 };
 158
 159 static const u32 rv770_golden_registers[] =
 160 {
 161         0x562c, 0xffffffff, 0,
 162         0x3f90, 0xffffffff, 0,
 163         0x9148, 0xffffffff, 0,
 164         0x3f94, 0xffffffff, 0,
 165         0x914c, 0xffffffff, 0,
 166         0x9698, 0x18000000, 0x18000000
 167 };
 168
 169 static const u32 rv770ce_golden_registers[] =
 170 {
 171         0x562c, 0xffffffff, 0,
 172         0x3f90, 0xffffffff, 0x00cc0000,
 173         0x9148, 0xffffffff, 0x00cc0000,
 174         0x3f94, 0xffffffff, 0x00cc0000,
 175         0x914c, 0xffffffff, 0x00cc0000,
 176         0x9b7c, 0xffffffff, 0x00fa0000,
 177         0x3f8c, 0xffffffff, 0x00fa0000,
 178         0x9698, 0x18000000, 0x18000000
 179 };
 180
 181 static const u32 rv770_mgcg_init[] =
 182 {
 183         0x8bcc, 0xffffffff, 0x130300f9,
 184         0x5448, 0xffffffff, 0x100,
 185         0x55e4, 0xffffffff, 0x100,
 186         0x160c, 0xffffffff, 0x100,
 187         0x5644, 0xffffffff, 0x100,
 188         0xc164, 0xffffffff, 0x100,
 189         0x8a18, 0xffffffff, 0x100,
 190         0x897c, 0xffffffff, 0x8000100,
 191         0x8b28, 0xffffffff, 0x3c000100,
 192         0x9144, 0xffffffff, 0x100,
 193         0x9a1c, 0xffffffff, 0x10000,
 194         0x9a50, 0xffffffff, 0x100,
 195         0x9a1c, 0xffffffff, 0x10001,
 196         0x9a50, 0xffffffff, 0x100,
 197         0x9a1c, 0xffffffff, 0x10002,
 198         0x9a50, 0xffffffff, 0x100,
 199         0x9a1c, 0xffffffff, 0x10003,
 200         0x9a50, 0xffffffff, 0x100,
 201         0x9a1c, 0xffffffff, 0x0,
 202         0x9870, 0xffffffff, 0x100,
 203         0x8d58, 0xffffffff, 0x100,
 204         0x9500, 0xffffffff, 0x0,
 205         0x9510, 0xffffffff, 0x100,
 206         0x9500, 0xffffffff, 0x1,
 207         0x9510, 0xffffffff, 0x100,
 208         0x9500, 0xffffffff, 0x2,
 209         0x9510, 0xffffffff, 0x100,
 210         0x9500, 0xffffffff, 0x3,
 211         0x9510, 0xffffffff, 0x100,
 212         0x9500, 0xffffffff, 0x4,
 213         0x9510, 0xffffffff, 0x100,
 214         0x9500, 0xffffffff, 0x5,
 215         0x9510, 0xffffffff, 0x100,
 216         0x9500, 0xffffffff, 0x6,
 217         0x9510, 0xffffffff, 0x100,
 218         0x9500, 0xffffffff, 0x7,
 219         0x9510, 0xffffffff, 0x100,
 220         0x9500, 0xffffffff, 0x8,
 221         0x9510, 0xffffffff, 0x100,
 222         0x9500, 0xffffffff, 0x9,
 223         0x9510, 0xffffffff, 0x100,
 224         0x9500, 0xffffffff, 0x8000,
 225         0x9490, 0xffffffff, 0x0,
 226         0x949c, 0xffffffff, 0x100,
 227         0x9490, 0xffffffff, 0x1,
 228         0x949c, 0xffffffff, 0x100,
 229         0x9490, 0xffffffff, 0x2,
 230         0x949c, 0xffffffff, 0x100,
 231         0x9490, 0xffffffff, 0x3,
 232         0x949c, 0xffffffff, 0x100,
 233         0x9490, 0xffffffff, 0x4,
 234         0x949c, 0xffffffff, 0x100,
 235         0x9490, 0xffffffff, 0x5,
 236         0x949c, 0xffffffff, 0x100,
 237         0x9490, 0xffffffff, 0x6,
 238         0x949c, 0xffffffff, 0x100,
 239         0x9490, 0xffffffff, 0x7,
 240         0x949c, 0xffffffff, 0x100,
 241         0x9490, 0xffffffff, 0x8,
 242         0x949c, 0xffffffff, 0x100,
 243         0x9490, 0xffffffff, 0x9,
 244         0x949c, 0xffffffff, 0x100,
 245         0x9490, 0xffffffff, 0x8000,
 246         0x9604, 0xffffffff, 0x0,
 247         0x9654, 0xffffffff, 0x100,
 248         0x9604, 0xffffffff, 0x1,
 249         0x9654, 0xffffffff, 0x100,
 250         0x9604, 0xffffffff, 0x2,
 251         0x9654, 0xffffffff, 0x100,
 252         0x9604, 0xffffffff, 0x3,
 253         0x9654, 0xffffffff, 0x100,
 254         0x9604, 0xffffffff, 0x4,
 255         0x9654, 0xffffffff, 0x100,
 256         0x9604, 0xffffffff, 0x5,
 257         0x9654, 0xffffffff, 0x100,
 258         0x9604, 0xffffffff, 0x6,
 259         0x9654, 0xffffffff, 0x100,
 260         0x9604, 0xffffffff, 0x7,
 261         0x9654, 0xffffffff, 0x100,
 262         0x9604, 0xffffffff, 0x8,
 263         0x9654, 0xffffffff, 0x100,
 264         0x9604, 0xffffffff, 0x9,
 265         0x9654, 0xffffffff, 0x100,
 266         0x9604, 0xffffffff, 0x80000000,
 267         0x9030, 0xffffffff, 0x100,
 268         0x9034, 0xffffffff, 0x100,
 269         0x9038, 0xffffffff, 0x100,
 270         0x903c, 0xffffffff, 0x100,
 271         0x9040, 0xffffffff, 0x100,
 272         0xa200, 0xffffffff, 0x100,
 273         0xa204, 0xffffffff, 0x100,
 274         0xa208, 0xffffffff, 0x100,
 275         0xa20c, 0xffffffff, 0x100,
 276         0x971c, 0xffffffff, 0x100,
 277         0x915c, 0xffffffff, 0x00020001,
 278         0x9160, 0xffffffff, 0x00040003,
 279         0x916c, 0xffffffff, 0x00060005,
 280         0x9170, 0xffffffff, 0x00080007,
 281         0x9174, 0xffffffff, 0x000a0009,
 282         0x9178, 0xffffffff, 0x000c000b,
 283         0x917c, 0xffffffff, 0x000e000d,
 284         0x9180, 0xffffffff, 0x0010000f,
 285         0x918c, 0xffffffff, 0x00120011,
 286         0x9190, 0xffffffff, 0x00140013,
 287         0x9194, 0xffffffff, 0x00020001,
 288         0x9198, 0xffffffff, 0x00040003,
 289         0x919c, 0xffffffff, 0x00060005,
 290         0x91a8, 0xffffffff, 0x00080007,
 291         0x91ac, 0xffffffff, 0x000a0009,
 292         0x91b0, 0xffffffff, 0x000c000b,
 293         0x91b4, 0xffffffff, 0x000e000d,
 294         0x91b8, 0xffffffff, 0x0010000f,
 295         0x91c4, 0xffffffff, 0x00120011,
 296         0x91c8, 0xffffffff, 0x00140013,
 297         0x91cc, 0xffffffff, 0x00020001,
 298         0x91d0, 0xffffffff, 0x00040003,
 299         0x91d4, 0xffffffff, 0x00060005,
 300         0x91e0, 0xffffffff, 0x00080007,
 301         0x91e4, 0xffffffff, 0x000a0009,
 302         0x91e8, 0xffffffff, 0x000c000b,
 303         0x91ec, 0xffffffff, 0x00020001,
 304         0x91f0, 0xffffffff, 0x00040003,
 305         0x91f4, 0xffffffff, 0x00060005,
 306         0x9200, 0xffffffff, 0x00080007,
 307         0x9204, 0xffffffff, 0x000a0009,
 308         0x9208, 0xffffffff, 0x000c000b,
 309         0x920c, 0xffffffff, 0x000e000d,
 310         0x9210, 0xffffffff, 0x0010000f,
 311         0x921c, 0xffffffff, 0x00120011,
 312         0x9220, 0xffffffff, 0x00140013,
 313         0x9224, 0xffffffff, 0x00020001,
 314         0x9228, 0xffffffff, 0x00040003,
 315         0x922c, 0xffffffff, 0x00060005,
 316         0x9238, 0xffffffff, 0x00080007,
 317         0x923c, 0xffffffff, 0x000a0009,
 318         0x9240, 0xffffffff, 0x000c000b,
 319         0x9244, 0xffffffff, 0x000e000d,
 320         0x9248, 0xffffffff, 0x0010000f,
 321         0x9254, 0xffffffff, 0x00120011,
 322         0x9258, 0xffffffff, 0x00140013,
 323         0x925c, 0xffffffff, 0x00020001,
 324         0x9260, 0xffffffff, 0x00040003,
 325         0x9264, 0xffffffff, 0x00060005,
 326         0x9270, 0xffffffff, 0x00080007,
 327         0x9274, 0xffffffff, 0x000a0009,
 328         0x9278, 0xffffffff, 0x000c000b,
 329         0x927c, 0xffffffff, 0x000e000d,
 330         0x9280, 0xffffffff, 0x0010000f,
 331         0x928c, 0xffffffff, 0x00120011,
 332         0x9290, 0xffffffff, 0x00140013,
 333         0x9294, 0xffffffff, 0x00020001,
 334         0x929c, 0xffffffff, 0x00040003,
 335         0x92a0, 0xffffffff, 0x00060005,
 336         0x92a4, 0xffffffff, 0x00080007
 337 };
 338
 339 static const u32 rv710_golden_registers[] =
 340 {
 341         0x3f90, 0x00ff0000, 0x00fc0000,
 342         0x9148, 0x00ff0000, 0x00fc0000,
 343         0x3f94, 0x00ff0000, 0x00fc0000,
 344         0x914c, 0x00ff0000, 0x00fc0000,
 345         0xb4c, 0x00000020, 0x00000020,
 346         0xa180, 0xffffffff, 0x00003f3f
 347 };
 348
 349 static const u32 rv710_mgcg_init[] =
 350 {
 351         0x8bcc, 0xffffffff, 0x13030040,
 352         0x5448, 0xffffffff, 0x100,
 353         0x55e4, 0xffffffff, 0x100,
 354         0x160c, 0xffffffff, 0x100,
 355         0x5644, 0xffffffff, 0x100,
 356         0xc164, 0xffffffff, 0x100,
 357         0x8a18, 0xffffffff, 0x100,
 358         0x897c, 0xffffffff, 0x8000100,
 359         0x8b28, 0xffffffff, 0x3c000100,
 360         0x9144, 0xffffffff, 0x100,
 361         0x9a1c, 0xffffffff, 0x10000,
 362         0x9a50, 0xffffffff, 0x100,
 363         0x9a1c, 0xffffffff, 0x0,
 364         0x9870, 0xffffffff, 0x100,
 365         0x8d58, 0xffffffff, 0x100,
 366         0x9500, 0xffffffff, 0x0,
 367         0x9510, 0xffffffff, 0x100,
 368         0x9500, 0xffffffff, 0x1,
 369         0x9510, 0xffffffff, 0x100,
 370         0x9500, 0xffffffff, 0x8000,
 371         0x9490, 0xffffffff, 0x0,
 372         0x949c, 0xffffffff, 0x100,
 373         0x9490, 0xffffffff, 0x1,
 374         0x949c, 0xffffffff, 0x100,
 375         0x9490, 0xffffffff, 0x8000,
 376         0x9604, 0xffffffff, 0x0,
 377         0x9654, 0xffffffff, 0x100,
 378         0x9604, 0xffffffff, 0x1,
 379         0x9654, 0xffffffff, 0x100,
 380         0x9604, 0xffffffff, 0x80000000,
 381         0x9030, 0xffffffff, 0x100,
 382         0x9034, 0xffffffff, 0x100,
 383         0x9038, 0xffffffff, 0x100,
 384         0x903c, 0xffffffff, 0x100,
 385         0x9040, 0xffffffff, 0x100,
 386         0xa200, 0xffffffff, 0x100,
 387         0xa204, 0xffffffff, 0x100,
 388         0xa208, 0xffffffff, 0x100,
 389         0xa20c, 0xffffffff, 0x100,
 390         0x971c, 0xffffffff, 0x100,
 391         0x915c, 0xffffffff, 0x00020001,
 392         0x9174, 0xffffffff, 0x00000003,
 393         0x9178, 0xffffffff, 0x00050001,
 394         0x917c, 0xffffffff, 0x00030002,
 395         0x918c, 0xffffffff, 0x00000004,
 396         0x9190, 0xffffffff, 0x00070006,
 397         0x9194, 0xffffffff, 0x00050001,
 398         0x9198, 0xffffffff, 0x00030002,
 399         0x91a8, 0xffffffff, 0x00000004,
 400         0x91ac, 0xffffffff, 0x00070006,
 401         0x91e8, 0xffffffff, 0x00000001,
 402         0x9294, 0xffffffff, 0x00000001,
 403         0x929c, 0xffffffff, 0x00000002,
 404         0x92a0, 0xffffffff, 0x00040003,
 405         0x9150, 0xffffffff, 0x4d940000
 406 };
 407
 408 static const u32 rv730_golden_registers[] =
 409 {
 410         0x3f90, 0x00ff0000, 0x00f00000,
 411         0x9148, 0x00ff0000, 0x00f00000,
 412         0x3f94, 0x00ff0000, 0x00f00000,
 413         0x914c, 0x00ff0000, 0x00f00000,
 414         0x900c, 0xffffffff, 0x003b033f,
 415         0xb4c, 0x00000020, 0x00000020,
 416         0xa180, 0xffffffff, 0x00003f3f
 417 };
 418
 419 static const u32 rv730_mgcg_init[] =
 420 {
 421         0x8bcc, 0xffffffff, 0x130300f9,
 422         0x5448, 0xffffffff, 0x100,
 423         0x55e4, 0xffffffff, 0x100,
 424         0x160c, 0xffffffff, 0x100,
 425         0x5644, 0xffffffff, 0x100,
 426         0xc164, 0xffffffff, 0x100,
 427         0x8a18, 0xffffffff, 0x100,
 428         0x897c, 0xffffffff, 0x8000100,
 429         0x8b28, 0xffffffff, 0x3c000100,
 430         0x9144, 0xffffffff, 0x100,
 431         0x9a1c, 0xffffffff, 0x10000,
 432         0x9a50, 0xffffffff, 0x100,
 433         0x9a1c, 0xffffffff, 0x10001,
 434         0x9a50, 0xffffffff, 0x100,
 435         0x9a1c, 0xffffffff, 0x0,
 436         0x9870, 0xffffffff, 0x100,
 437         0x8d58, 0xffffffff, 0x100,
 438         0x9500, 0xffffffff, 0x0,
 439         0x9510, 0xffffffff, 0x100,
 440         0x9500, 0xffffffff, 0x1,
 441         0x9510, 0xffffffff, 0x100,
 442         0x9500, 0xffffffff, 0x2,
 443         0x9510, 0xffffffff, 0x100,
 444         0x9500, 0xffffffff, 0x3,
 445         0x9510, 0xffffffff, 0x100,
 446         0x9500, 0xffffffff, 0x4,
 447         0x9510, 0xffffffff, 0x100,
 448         0x9500, 0xffffffff, 0x5,
 449         0x9510, 0xffffffff, 0x100,
 450         0x9500, 0xffffffff, 0x6,
 451         0x9510, 0xffffffff, 0x100,
 452         0x9500, 0xffffffff, 0x7,
 453         0x9510, 0xffffffff, 0x100,
 454         0x9500, 0xffffffff, 0x8000,
 455         0x9490, 0xffffffff, 0x0,
 456         0x949c, 0xffffffff, 0x100,
 457         0x9490, 0xffffffff, 0x1,
 458         0x949c, 0xffffffff, 0x100,
 459         0x9490, 0xffffffff, 0x2,
 460         0x949c, 0xffffffff, 0x100,
 461         0x9490, 0xffffffff, 0x3,
 462         0x949c, 0xffffffff, 0x100,
 463         0x9490, 0xffffffff, 0x4,
 464         0x949c, 0xffffffff, 0x100,
 465         0x9490, 0xffffffff, 0x5,
 466         0x949c, 0xffffffff, 0x100,
 467         0x9490, 0xffffffff, 0x6,
 468         0x949c, 0xffffffff, 0x100,
 469         0x9490, 0xffffffff, 0x7,
 470         0x949c, 0xffffffff, 0x100,
 471         0x9490, 0xffffffff, 0x8000,
 472         0x9604, 0xffffffff, 0x0,
 473         0x9654, 0xffffffff, 0x100,
 474         0x9604, 0xffffffff, 0x1,
 475         0x9654, 0xffffffff, 0x100,
 476         0x9604, 0xffffffff, 0x2,
 477         0x9654, 0xffffffff, 0x100,
 478         0x9604, 0xffffffff, 0x3,
 479         0x9654, 0xffffffff, 0x100,
 480         0x9604, 0xffffffff, 0x4,
 481         0x9654, 0xffffffff, 0x100,
 482         0x9604, 0xffffffff, 0x5,
 483         0x9654, 0xffffffff, 0x100,
 484         0x9604, 0xffffffff, 0x6,
 485         0x9654, 0xffffffff, 0x100,
 486         0x9604, 0xffffffff, 0x7,
 487         0x9654, 0xffffffff, 0x100,
 488         0x9604, 0xffffffff, 0x80000000,
 489         0x9030, 0xffffffff, 0x100,
 490         0x9034, 0xffffffff, 0x100,
 491         0x9038, 0xffffffff, 0x100,
 492         0x903c, 0xffffffff, 0x100,
 493         0x9040, 0xffffffff, 0x100,
 494         0xa200, 0xffffffff, 0x100,
 495         0xa204, 0xffffffff, 0x100,
 496         0xa208, 0xffffffff, 0x100,
 497         0xa20c, 0xffffffff, 0x100,
 498         0x971c, 0xffffffff, 0x100,
 499         0x915c, 0xffffffff, 0x00020001,
 500         0x916c, 0xffffffff, 0x00040003,
 501         0x9170, 0xffffffff, 0x00000005,
 502         0x9178, 0xffffffff, 0x00050001,
 503         0x917c, 0xffffffff, 0x00030002,
 504         0x918c, 0xffffffff, 0x00000004,
 505         0x9190, 0xffffffff, 0x00070006,
 506         0x9194, 0xffffffff, 0x00050001,
 507         0x9198, 0xffffffff, 0x00030002,
 508         0x91a8, 0xffffffff, 0x00000004,
 509         0x91ac, 0xffffffff, 0x00070006,
 510         0x91b0, 0xffffffff, 0x00050001,
 511         0x91b4, 0xffffffff, 0x00030002,
 512         0x91c4, 0xffffffff, 0x00000004,
 513         0x91c8, 0xffffffff, 0x00070006,
 514         0x91cc, 0xffffffff, 0x00050001,
 515         0x91d0, 0xffffffff, 0x00030002,
 516         0x91e0, 0xffffffff, 0x00000004,
 517         0x91e4, 0xffffffff, 0x00070006,
 518         0x91e8, 0xffffffff, 0x00000001,
 519         0x91ec, 0xffffffff, 0x00050001,
 520         0x91f0, 0xffffffff, 0x00030002,
 521         0x9200, 0xffffffff, 0x00000004,
 522         0x9204, 0xffffffff, 0x00070006,
 523         0x9208, 0xffffffff, 0x00050001,
 524         0x920c, 0xffffffff, 0x00030002,
 525         0x921c, 0xffffffff, 0x00000004,
 526         0x9220, 0xffffffff, 0x00070006,
 527         0x9224, 0xffffffff, 0x00050001,
 528         0x9228, 0xffffffff, 0x00030002,
 529         0x9238, 0xffffffff, 0x00000004,
 530         0x923c, 0xffffffff, 0x00070006,
 531         0x9240, 0xffffffff, 0x00050001,
 532         0x9244, 0xffffffff, 0x00030002,
 533         0x9254, 0xffffffff, 0x00000004,
 534         0x9258, 0xffffffff, 0x00070006,
 535         0x9294, 0xffffffff, 0x00000001,
 536         0x929c, 0xffffffff, 0x00000002,
 537         0x92a0, 0xffffffff, 0x00040003,
 538         0x92a4, 0xffffffff, 0x00000005
 539 };
 540
 541 static const u32 rv740_golden_registers[] =
 542 {
 543         0x88c4, 0xffffffff, 0x00000082,
 544         0x28a50, 0xfffffffc, 0x00000004,
 545         0x2650, 0x00040000, 0,
 546         0x20bc, 0x00040000, 0,
 547         0x733c, 0xffffffff, 0x00000002,
 548         0x7300, 0xffffffff, 0x001000f0,
 549         0x3f90, 0x00ff0000, 0,
 550         0x9148, 0x00ff0000, 0,
 551         0x3f94, 0x00ff0000, 0,
 552         0x914c, 0x00ff0000, 0,
 553         0x240c, 0xffffffff, 0x00000380,
 554         0x8a14, 0x00000007, 0x00000007,
 555         0x8b24, 0xffffffff, 0x00ff0fff,
 556         0x28a4c, 0xffffffff, 0x00004000,
 557         0xa180, 0xffffffff, 0x00003f3f,
 558         0x8d00, 0xffffffff, 0x0e0e003a,
 559         0x8d04, 0xffffffff, 0x013a0e2a,
 560         0x8c00, 0xffffffff, 0xe400000f,
 561         0x8db0, 0xffffffff, 0x98989898,
 562         0x8db4, 0xffffffff, 0x98989898,
 563         0x8db8, 0xffffffff, 0x98989898,
 564         0x8dbc, 0xffffffff, 0x98989898,
 565         0x8dc0, 0xffffffff, 0x98989898,
 566         0x8dc4, 0xffffffff, 0x98989898,
 567         0x8dc8, 0xffffffff, 0x98989898,
 568         0x8dcc, 0xffffffff, 0x98989898,
 569         0x9058, 0xffffffff, 0x0fffc40f,
 570         0x900c, 0xffffffff, 0x003b033f,
 571         0x28350, 0xffffffff, 0,
 572         0x8cf0, 0x1fffffff, 0x08e00420,
 573         0x9508, 0xffffffff, 0x00000002,
 574         0x88c4, 0xffffffff, 0x000000c2,
 575         0x9698, 0x18000000, 0x18000000
 576 };
 577
 578 static const u32 rv740_mgcg_init[] =
 579 {
 580         0x8bcc, 0xffffffff, 0x13030100,
 581         0x5448, 0xffffffff, 0x100,
 582         0x55e4, 0xffffffff, 0x100,
 583         0x160c, 0xffffffff, 0x100,
 584         0x5644, 0xffffffff, 0x100,
 585         0xc164, 0xffffffff, 0x100,
 586         0x8a18, 0xffffffff, 0x100,
 587         0x897c, 0xffffffff, 0x100,
 588         0x8b28, 0xffffffff, 0x100,
 589         0x9144, 0xffffffff, 0x100,
 590         0x9a1c, 0xffffffff, 0x10000,
 591         0x9a50, 0xffffffff, 0x100,
 592         0x9a1c, 0xffffffff, 0x10001,
 593         0x9a50, 0xffffffff, 0x100,
 594         0x9a1c, 0xffffffff, 0x10002,
 595         0x9a50, 0xffffffff, 0x100,
 596         0x9a1c, 0xffffffff, 0x10003,
 597         0x9a50, 0xffffffff, 0x100,
 598         0x9a1c, 0xffffffff, 0x0,
 599         0x9870, 0xffffffff, 0x100,
 600         0x8d58, 0xffffffff, 0x100,
 601         0x9500, 0xffffffff, 0x0,
 602         0x9510, 0xffffffff, 0x100,
 603         0x9500, 0xffffffff, 0x1,
 604         0x9510, 0xffffffff, 0x100,
 605         0x9500, 0xffffffff, 0x2,
 606         0x9510, 0xffffffff, 0x100,
 607         0x9500, 0xffffffff, 0x3,
 608         0x9510, 0xffffffff, 0x100,
 609         0x9500, 0xffffffff, 0x4,
 610         0x9510, 0xffffffff, 0x100,
 611         0x9500, 0xffffffff, 0x5,
 612         0x9510, 0xffffffff, 0x100,
 613         0x9500, 0xffffffff, 0x6,
 614         0x9510, 0xffffffff, 0x100,
 615         0x9500, 0xffffffff, 0x7,
 616         0x9510, 0xffffffff, 0x100,
 617         0x9500, 0xffffffff, 0x8000,
 618         0x9490, 0xffffffff, 0x0,
 619         0x949c, 0xffffffff, 0x100,
 620         0x9490, 0xffffffff, 0x1,
 621         0x949c, 0xffffffff, 0x100,
 622         0x9490, 0xffffffff, 0x2,
 623         0x949c, 0xffffffff, 0x100,
 624         0x9490, 0xffffffff, 0x3,
 625         0x949c, 0xffffffff, 0x100,
 626         0x9490, 0xffffffff, 0x4,
 627         0x949c, 0xffffffff, 0x100,
 628         0x9490, 0xffffffff, 0x5,
 629         0x949c, 0xffffffff, 0x100,
 630         0x9490, 0xffffffff, 0x6,
 631         0x949c, 0xffffffff, 0x100,
 632         0x9490, 0xffffffff, 0x7,
 633         0x949c, 0xffffffff, 0x100,
 634         0x9490, 0xffffffff, 0x8000,
 635         0x9604, 0xffffffff, 0x0,
 636         0x9654, 0xffffffff, 0x100,
 637         0x9604, 0xffffffff, 0x1,
 638         0x9654, 0xffffffff, 0x100,
 639         0x9604, 0xffffffff, 0x2,
 640         0x9654, 0xffffffff, 0x100,
 641         0x9604, 0xffffffff, 0x3,
 642         0x9654, 0xffffffff, 0x100,
 643         0x9604, 0xffffffff, 0x4,
 644         0x9654, 0xffffffff, 0x100,
 645         0x9604, 0xffffffff, 0x5,
 646         0x9654, 0xffffffff, 0x100,
 647         0x9604, 0xffffffff, 0x6,
 648         0x9654, 0xffffffff, 0x100,
 649         0x9604, 0xffffffff, 0x7,
 650         0x9654, 0xffffffff, 0x100,
 651         0x9604, 0xffffffff, 0x80000000,
 652         0x9030, 0xffffffff, 0x100,
 653         0x9034, 0xffffffff, 0x100,
 654         0x9038, 0xffffffff, 0x100,
 655         0x903c, 0xffffffff, 0x100,
 656         0x9040, 0xffffffff, 0x100,
 657         0xa200, 0xffffffff, 0x100,
 658         0xa204, 0xffffffff, 0x100,
 659         0xa208, 0xffffffff, 0x100,
 660         0xa20c, 0xffffffff, 0x100,
 661         0x971c, 0xffffffff, 0x100,
 662         0x915c, 0xffffffff, 0x00020001,
 663         0x9160, 0xffffffff, 0x00040003,
 664         0x916c, 0xffffffff, 0x00060005,
 665         0x9170, 0xffffffff, 0x00080007,
 666         0x9174, 0xffffffff, 0x000a0009,
 667         0x9178, 0xffffffff, 0x000c000b,
 668         0x917c, 0xffffffff, 0x000e000d,
 669         0x9180, 0xffffffff, 0x0010000f,
 670         0x918c, 0xffffffff, 0x00120011,
 671         0x9190, 0xffffffff, 0x00140013,
 672         0x9194, 0xffffffff, 0x00020001,
 673         0x9198, 0xffffffff, 0x00040003,
 674         0x919c, 0xffffffff, 0x00060005,
 675         0x91a8, 0xffffffff, 0x00080007,
 676         0x91ac, 0xffffffff, 0x000a0009,
 677         0x91b0, 0xffffffff, 0x000c000b,
 678         0x91b4, 0xffffffff, 0x000e000d,
 679         0x91b8, 0xffffffff, 0x0010000f,
 680         0x91c4, 0xffffffff, 0x00120011,
 681         0x91c8, 0xffffffff, 0x00140013,
 682         0x91cc, 0xffffffff, 0x00020001,
 683         0x91d0, 0xffffffff, 0x00040003,
 684         0x91d4, 0xffffffff, 0x00060005,
 685         0x91e0, 0xffffffff, 0x00080007,
 686         0x91e4, 0xffffffff, 0x000a0009,
 687         0x91e8, 0xffffffff, 0x000c000b,
 688         0x91ec, 0xffffffff, 0x00020001,
 689         0x91f0, 0xffffffff, 0x00040003,
 690         0x91f4, 0xffffffff, 0x00060005,
 691         0x9200, 0xffffffff, 0x00080007,
 692         0x9204, 0xffffffff, 0x000a0009,
 693         0x9208, 0xffffffff, 0x000c000b,
 694         0x920c, 0xffffffff, 0x000e000d,
 695         0x9210, 0xffffffff, 0x0010000f,
 696         0x921c, 0xffffffff, 0x00120011,
 697         0x9220, 0xffffffff, 0x00140013,
 698         0x9224, 0xffffffff, 0x00020001,
 699         0x9228, 0xffffffff, 0x00040003,
 700         0x922c, 0xffffffff, 0x00060005,
 701         0x9238, 0xffffffff, 0x00080007,
 702         0x923c, 0xffffffff, 0x000a0009,
 703         0x9240, 0xffffffff, 0x000c000b,
 704         0x9244, 0xffffffff, 0x000e000d,
 705         0x9248, 0xffffffff, 0x0010000f,
 706         0x9254, 0xffffffff, 0x00120011,
 707         0x9258, 0xffffffff, 0x00140013,
 708         0x9294, 0xffffffff, 0x00020001,
 709         0x929c, 0xffffffff, 0x00040003,
 710         0x92a0, 0xffffffff, 0x00060005,
 711         0x92a4, 0xffffffff, 0x00080007
 712 };
 713
 714 static void rv770_init_golden_registers(struct radeon_device *rdev)
 715 {
 716         switch (rdev->family) {
 717         case CHIP_RV770:
 718                 radeon_program_register_sequence(rdev,
 719                                                  r7xx_golden_registers,
 720                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 721                 radeon_program_register_sequence(rdev,
 722                                                  r7xx_golden_dyn_gpr_registers,
 723                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 724                 if (rdev->ddev->pci_device == 0x994e)
 725                         radeon_program_register_sequence(rdev,
 726                                                          rv770ce_golden_registers,
 727                                                          (const u32)ARRAY_SIZE(rv770ce_golden_registers));
 728                 else
 729                         radeon_program_register_sequence(rdev,
 730                                                          rv770_golden_registers,
 731                                                          (const u32)ARRAY_SIZE(rv770_golden_registers));
 732                 radeon_program_register_sequence(rdev,
 733                                                  rv770_mgcg_init,
 734                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 735                 break;
 736         case CHIP_RV730:
 737                 radeon_program_register_sequence(rdev,
 738                                                  r7xx_golden_registers,
 739                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 740                 radeon_program_register_sequence(rdev,
 741                                                  r7xx_golden_dyn_gpr_registers,
 742                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 743                 radeon_program_register_sequence(rdev,
 744                                                  rv730_golden_registers,
 745                                                  (const u32)ARRAY_SIZE(rv730_golden_registers));
 746                 radeon_program_register_sequence(rdev,
 747                                                  rv730_mgcg_init,
 748                                                  (const u32)ARRAY_SIZE(rv730_mgcg_init));
 749                 break;
 750         case CHIP_RV710:
 751                 radeon_program_register_sequence(rdev,
 752                                                  r7xx_golden_registers,
 753                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 754                 radeon_program_register_sequence(rdev,
 755                                                  r7xx_golden_dyn_gpr_registers,
 756                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 757                 radeon_program_register_sequence(rdev,
 758                                                  rv710_golden_registers,
 759                                                  (const u32)ARRAY_SIZE(rv710_golden_registers));
 760                 radeon_program_register_sequence(rdev,
 761                                                  rv710_mgcg_init,
 762                                                  (const u32)ARRAY_SIZE(rv710_mgcg_init));
 763                 break;
 764         case CHIP_RV740:
 765                 radeon_program_register_sequence(rdev,
 766                                                  rv740_golden_registers,
 767                                                  (const u32)ARRAY_SIZE(rv740_golden_registers));
 768                 radeon_program_register_sequence(rdev,
 769                                                  rv740_mgcg_init,
 770                                                  (const u32)ARRAY_SIZE(rv740_mgcg_init));
 771                 break;
 772         default:
 773                 break;
 774         }
 775 }
 776
 777 #define PCIE_BUS_CLK                10000
 778 #define TCLK                        (PCIE_BUS_CLK / 10)
 779
 780 /**
 781  * rv770_get_xclk - get the xclk
 782  *
 783  * @rdev: radeon_device pointer
 784  *
 785  * Returns the reference clock used by the gfx engine
 786  * (r7xx-cayman).
 787  */
 788 u32 rv770_get_xclk(struct radeon_device *rdev)
 789 {
 790         u32 reference_clock = rdev->clock.spll.reference_freq;
 791         u32 tmp = RREG32(CG_CLKPIN_CNTL);
 792
 793         if (tmp & MUX_TCLK_TO_XCLK)
 794                 return TCLK;
 795
 796         if (tmp & XTALIN_DIVIDE)
 797                 return reference_clock / 4;
 798
 799         return reference_clock;
 800 }
 801
 802 int rv770_uvd_resume(struct radeon_device *rdev)
 803 {
 804         uint64_t addr;
 805         uint32_t chip_id, size;
 806         int r;
 807
 808         r = radeon_uvd_resume(rdev);
 809         if (r)
 810                 return r;
 811
 812         /* programm the VCPU memory controller bits 0-27 */
 813         addr = rdev->uvd.gpu_addr >> 3;
 814         size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->datasize + 4) >> 3;
 815         WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
 816         WREG32(UVD_VCPU_CACHE_SIZE0, size);
 817
 818         addr += size;
 819         size = RADEON_UVD_STACK_SIZE >> 3;
 820         WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
 821         WREG32(UVD_VCPU_CACHE_SIZE1, size);
 822
 823         addr += size;
 824         size = RADEON_UVD_HEAP_SIZE >> 3;
 825         WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
 826         WREG32(UVD_VCPU_CACHE_SIZE2, size);
 827
 828         /* bits 28-31 */
 829         addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
 830         WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 831
 832         /* bits 32-39 */
 833         addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
 834         WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 835
 836         /* tell firmware which hardware it is running on */
 837         switch (rdev->family) {
 838         default:
 839                 return -EINVAL;
 840         case CHIP_RV710:
 841                 chip_id = 0x01000005;
 842                 break;
 843         case CHIP_RV730:
 844                 chip_id = 0x01000006;
 845                 break;
 846         case CHIP_RV740:
 847                 chip_id = 0x01000007;
 848                 break;
 849         case CHIP_CYPRESS:
 850         case CHIP_HEMLOCK:
 851                 chip_id = 0x01000008;
 852                 break;
 853         case CHIP_JUNIPER:
 854                 chip_id = 0x01000009;
 855                 break;
 856         case CHIP_REDWOOD:
 857                 chip_id = 0x0100000a;
 858                 break;
 859         case CHIP_CEDAR:
 860                 chip_id = 0x0100000b;
 861                 break;
 862         case CHIP_SUMO:
 863         case CHIP_SUMO2:
 864                 chip_id = 0x0100000c;
 865                 break;
 866         case CHIP_PALM:
 867                 chip_id = 0x0100000e;
 868                 break;
 869         case CHIP_CAYMAN:
 870                 chip_id = 0x0100000f;
 871                 break;
 872         case CHIP_BARTS:
 873                 chip_id = 0x01000010;
 874                 break;
 875         case CHIP_TURKS:
 876                 chip_id = 0x01000011;
 877                 break;
 878         case CHIP_CAICOS:
 879                 chip_id = 0x01000012;
 880                 break;
 881         case CHIP_TAHITI:
 882                 chip_id = 0x01000014;
 883                 break;
 884         case CHIP_VERDE:
 885                 chip_id = 0x01000015;
 886                 break;
 887         case CHIP_PITCAIRN:
 888                 chip_id = 0x01000016;
 889                 break;
 890         case CHIP_ARUBA:
 891                 chip_id = 0x01000017;
 892                 break;
 893         }
 894         WREG32(UVD_VCPU_CHIP_ID, chip_id);
 895
 896         return 0;
 897 }
 898
 899 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 900 {
 901         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 902         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 903         int i;
 904
 905         /* Lock the graphics update lock */
 906         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 907         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 908
 909         /* update the scanout addresses */
 910         if (radeon_crtc->crtc_id) {
 911                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 912                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 913         } else {
 914                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 915                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 916         }
 917         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 918                (u32)crtc_base);
 919         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 920                (u32)crtc_base);
 921
 922         /* Wait for update_pending to go high. */
 923         for (i = 0; i < rdev->usec_timeout; i++) {
 924                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 925                         break;
 926                 DRM_UDELAY(1);
 927         }
 928         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 929
 930         /* Unlock the lock, so double-buffering can take place inside vblank */
 931         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 932         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 933
 934         /* Return current update_pending status: */
 935         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 936 }
 937
 938 /* get temperature in millidegrees */
 939 int rv770_get_temp(struct radeon_device *rdev)
 940 {
 941         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 942                 ASIC_T_SHIFT;
 943         int actual_temp;
 944
 945         if (temp & 0x400)
 946                 actual_temp = -256;
 947         else if (temp & 0x200)
 948                 actual_temp = 255;
 949         else if (temp & 0x100) {
 950                 actual_temp = temp & 0x1ff;
 951                 actual_temp |= ~0x1ff;
 952         } else
 953                 actual_temp = temp & 0xff;
 954
 955         return (actual_temp * 1000) / 2;
 956 }
 957
 958 void rv770_pm_misc(struct radeon_device *rdev)
 959 {
 960         int req_ps_idx = rdev->pm.requested_power_state_index;
 961         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 962         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 963         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 964
 965         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 966                 /* 0xff01 is a flag rather then an actual voltage */
 967                 if (voltage->voltage == 0xff01)
 968                         return;
 969                 if (voltage->voltage != rdev->pm.current_vddc) {
 970                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 971                         rdev->pm.current_vddc = voltage->voltage;
 972                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 973                 }
 974         }
 975 }
 976
 977 /*
 978  * GART
 979  */
 980 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
 981 {
 982         u32 tmp;
 983         int r, i;
 984
 985         if (rdev->gart.robj == NULL) {
 986                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 987                 return -EINVAL;
 988         }
 989         r = radeon_gart_table_vram_pin(rdev);
 990         if (r)
 991                 return r;
 992         radeon_gart_restore(rdev);
 993         /* Setup L2 cache */
 994         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 995                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 996                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 997         WREG32(VM_L2_CNTL2, 0);
 998         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 999         /* Setup TLB control */
1000         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1001                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1002                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1003                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1004         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1005         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1006         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1007         if (rdev->family == CHIP_RV740)
1008                 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1009         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1010         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1011         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1012         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1013         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1014         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1015         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1016         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1017                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1018         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1019                         (u32)(rdev->dummy_page.addr >> 12));
1020         for (i = 1; i < 7; i++)
1021                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1022
1023         r600_pcie_gart_tlb_flush(rdev);
1024         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1025                  (unsigned)(rdev->mc.gtt_size >> 20),
1026                  (unsigned long long)rdev->gart.table_addr);
1027         rdev->gart.ready = true;
1028         return 0;
1029 }
1030
1031 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
1032 {
1033         u32 tmp;
1034         int i;
1035
1036         /* Disable all tables */
1037         for (i = 0; i < 7; i++)
1038                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1039
1040         /* Setup L2 cache */
1041         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1042                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1043         WREG32(VM_L2_CNTL2, 0);
1044         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1045         /* Setup TLB control */
1046         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1047         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1048         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1049         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1050         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1051         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1052         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1053         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1054         radeon_gart_table_vram_unpin(rdev);
1055 }
1056
1057 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
1058 {
1059         radeon_gart_fini(rdev);
1060         rv770_pcie_gart_disable(rdev);
1061         radeon_gart_table_vram_free(rdev);
1062 }
1063
1064
1065 static void rv770_agp_enable(struct radeon_device *rdev)
1066 {
1067         u32 tmp;
1068         int i;
1069
1070         /* Setup L2 cache */
1071         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1072                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1073                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1074         WREG32(VM_L2_CNTL2, 0);
1075         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1076         /* Setup TLB control */
1077         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1078                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1079                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1080                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1081         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1082         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1083         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1084         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1085         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1086         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1087         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1088         for (i = 0; i < 7; i++)
1089                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1090 }
1091
1092 static void rv770_mc_program(struct radeon_device *rdev)
1093 {
1094         struct rv515_mc_save save;
1095         u32 tmp;
1096         int i, j;
1097
1098         /* Initialize HDP */
1099         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1100                 WREG32((0x2c14 + j), 0x00000000);
1101                 WREG32((0x2c18 + j), 0x00000000);
1102                 WREG32((0x2c1c + j), 0x00000000);
1103                 WREG32((0x2c20 + j), 0x00000000);
1104                 WREG32((0x2c24 + j), 0x00000000);
1105         }
1106         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
1107          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1108          */
1109         tmp = RREG32(HDP_DEBUG1);
1110
1111         rv515_mc_stop(rdev, &save);
1112         if (r600_mc_wait_for_idle(rdev)) {
1113                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1114         }
1115         /* Lockout access through VGA aperture*/
1116         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1117         /* Update configuration */
1118         if (rdev->flags & RADEON_IS_AGP) {
1119                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1120                         /* VRAM before AGP */
1121                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1122                                 rdev->mc.vram_start >> 12);
1123                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1124                                 rdev->mc.gtt_end >> 12);
1125                 } else {
1126                         /* VRAM after AGP */
1127                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1128                                 rdev->mc.gtt_start >> 12);
1129                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1130                                 rdev->mc.vram_end >> 12);
1131                 }
1132         } else {
1133                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1134                         rdev->mc.vram_start >> 12);
1135                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1136                         rdev->mc.vram_end >> 12);
1137         }
1138         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1139         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1140         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1141         WREG32(MC_VM_FB_LOCATION, tmp);
1142         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1143         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1144         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1145         if (rdev->flags & RADEON_IS_AGP) {
1146                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1147                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1148                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1149         } else {
1150                 WREG32(MC_VM_AGP_BASE, 0);
1151                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1152                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1153         }
1154         if (r600_mc_wait_for_idle(rdev)) {
1155                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1156         }
1157         rv515_mc_resume(rdev, &save);
1158         /* we need to own VRAM, so turn off the VGA renderer here
1159          * to stop it overwriting our objects */
1160         rv515_vga_render_disable(rdev);
1161 }
1162
1163
1164 /*
1165  * CP.
1166  */
1167 void r700_cp_stop(struct radeon_device *rdev)
1168 {
1169         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1170         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1171         WREG32(SCRATCH_UMSK, 0);
1172         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1173 }
1174
1175 static int rv770_cp_load_microcode(struct radeon_device *rdev)
1176 {
1177         const __be32 *fw_data;
1178         int i;
1179
1180         if (!rdev->me_fw || !rdev->pfp_fw)
1181                 return -EINVAL;
1182
1183         r700_cp_stop(rdev);
1184         WREG32(CP_RB_CNTL,
1185 #ifdef __BIG_ENDIAN
1186                BUF_SWAP_32BIT |
1187 #endif
1188                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1189
1190         /* Reset cp */
1191         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1192         RREG32(GRBM_SOFT_RESET);
1193         DRM_MDELAY(15);
1194         WREG32(GRBM_SOFT_RESET, 0);
1195
1196         fw_data = (const __be32 *)rdev->pfp_fw->data;
1197         WREG32(CP_PFP_UCODE_ADDR, 0);
1198         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1199                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1200         WREG32(CP_PFP_UCODE_ADDR, 0);
1201
1202         fw_data = (const __be32 *)rdev->me_fw->data;
1203         WREG32(CP_ME_RAM_WADDR, 0);
1204         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1205                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1206
1207         WREG32(CP_PFP_UCODE_ADDR, 0);
1208         WREG32(CP_ME_RAM_WADDR, 0);
1209         WREG32(CP_ME_RAM_RADDR, 0);
1210         return 0;
1211 }
1212
1213 void r700_cp_fini(struct radeon_device *rdev)
1214 {
1215         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1216         r700_cp_stop(rdev);
1217         radeon_ring_fini(rdev, ring);
1218         radeon_scratch_free(rdev, ring->rptr_save_reg);
1219 }
1220
1221 /*
1222  * Core functions
1223  */
1224 static void rv770_gpu_init(struct radeon_device *rdev)
1225 {
1226         int i, j, num_qd_pipes;
1227         u32 ta_aux_cntl;
1228         u32 sx_debug_1;
1229         u32 smx_dc_ctl0;
1230         u32 db_debug3;
1231         u32 num_gs_verts_per_thread;
1232         u32 vgt_gs_per_es;
1233         u32 gs_prim_buffer_depth = 0;
1234         u32 sq_ms_fifo_sizes;
1235         u32 sq_config;
1236         u32 sq_thread_resource_mgmt;
1237         u32 hdp_host_path_cntl;
1238         u32 sq_dyn_gpr_size_simd_ab_0;
1239         u32 gb_tiling_config = 0;
1240         u32 cc_rb_backend_disable = 0;
1241         u32 cc_gc_shader_pipe_config = 0;
1242         u32 mc_arb_ramcfg;
1243         u32 db_debug4, tmp;
1244         u32 inactive_pipes, shader_pipe_config;
1245         u32 disabled_rb_mask;
1246         unsigned active_number;
1247
1248         /* setup chip specs */
1249         rdev->config.rv770.tiling_group_size = 256;
1250         switch (rdev->family) {
1251         case CHIP_RV770:
1252                 rdev->config.rv770.max_pipes = 4;
1253                 rdev->config.rv770.max_tile_pipes = 8;
1254                 rdev->config.rv770.max_simds = 10;
1255                 rdev->config.rv770.max_backends = 4;
1256                 rdev->config.rv770.max_gprs = 256;
1257                 rdev->config.rv770.max_threads = 248;
1258                 rdev->config.rv770.max_stack_entries = 512;
1259                 rdev->config.rv770.max_hw_contexts = 8;
1260                 rdev->config.rv770.max_gs_threads = 16 * 2;
1261                 rdev->config.rv770.sx_max_export_size = 128;
1262                 rdev->config.rv770.sx_max_export_pos_size = 16;
1263                 rdev->config.rv770.sx_max_export_smx_size = 112;
1264                 rdev->config.rv770.sq_num_cf_insts = 2;
1265
1266                 rdev->config.rv770.sx_num_of_sets = 7;
1267                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1268                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1269                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1270                 break;
1271         case CHIP_RV730:
1272                 rdev->config.rv770.max_pipes = 2;
1273                 rdev->config.rv770.max_tile_pipes = 4;
1274                 rdev->config.rv770.max_simds = 8;
1275                 rdev->config.rv770.max_backends = 2;
1276                 rdev->config.rv770.max_gprs = 128;
1277                 rdev->config.rv770.max_threads = 248;
1278                 rdev->config.rv770.max_stack_entries = 256;
1279                 rdev->config.rv770.max_hw_contexts = 8;
1280                 rdev->config.rv770.max_gs_threads = 16 * 2;
1281                 rdev->config.rv770.sx_max_export_size = 256;
1282                 rdev->config.rv770.sx_max_export_pos_size = 32;
1283                 rdev->config.rv770.sx_max_export_smx_size = 224;
1284                 rdev->config.rv770.sq_num_cf_insts = 2;
1285
1286                 rdev->config.rv770.sx_num_of_sets = 7;
1287                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1288                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1289                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1290                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1291                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1292                         rdev->config.rv770.sx_max_export_smx_size += 16;
1293                 }
1294                 break;
1295         case CHIP_RV710:
1296                 rdev->config.rv770.max_pipes = 2;
1297                 rdev->config.rv770.max_tile_pipes = 2;
1298                 rdev->config.rv770.max_simds = 2;
1299                 rdev->config.rv770.max_backends = 1;
1300                 rdev->config.rv770.max_gprs = 256;
1301                 rdev->config.rv770.max_threads = 192;
1302                 rdev->config.rv770.max_stack_entries = 256;
1303                 rdev->config.rv770.max_hw_contexts = 4;
1304                 rdev->config.rv770.max_gs_threads = 8 * 2;
1305                 rdev->config.rv770.sx_max_export_size = 128;
1306                 rdev->config.rv770.sx_max_export_pos_size = 16;
1307                 rdev->config.rv770.sx_max_export_smx_size = 112;
1308                 rdev->config.rv770.sq_num_cf_insts = 1;
1309
1310                 rdev->config.rv770.sx_num_of_sets = 7;
1311                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1312                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1313                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1314                 break;
1315         case CHIP_RV740:
1316                 rdev->config.rv770.max_pipes = 4;
1317                 rdev->config.rv770.max_tile_pipes = 4;
1318                 rdev->config.rv770.max_simds = 8;
1319                 rdev->config.rv770.max_backends = 4;
1320                 rdev->config.rv770.max_gprs = 256;
1321                 rdev->config.rv770.max_threads = 248;
1322                 rdev->config.rv770.max_stack_entries = 512;
1323                 rdev->config.rv770.max_hw_contexts = 8;
1324                 rdev->config.rv770.max_gs_threads = 16 * 2;
1325                 rdev->config.rv770.sx_max_export_size = 256;
1326                 rdev->config.rv770.sx_max_export_pos_size = 32;
1327                 rdev->config.rv770.sx_max_export_smx_size = 224;
1328                 rdev->config.rv770.sq_num_cf_insts = 2;
1329
1330                 rdev->config.rv770.sx_num_of_sets = 7;
1331                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1332                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1333                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1334
1335                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1336                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1337                         rdev->config.rv770.sx_max_export_smx_size += 16;
1338                 }
1339                 break;
1340         default:
1341                 break;
1342         }
1343
1344         /* Initialize HDP */
1345         j = 0;
1346         for (i = 0; i < 32; i++) {
1347                 WREG32((0x2c14 + j), 0x00000000);
1348                 WREG32((0x2c18 + j), 0x00000000);
1349                 WREG32((0x2c1c + j), 0x00000000);
1350                 WREG32((0x2c20 + j), 0x00000000);
1351                 WREG32((0x2c24 + j), 0x00000000);
1352                 j += 0x18;
1353         }
1354
1355         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1356
1357         /* setup tiling, simd, pipe config */
1358         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1359
1360         shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1361         inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1362         for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1363                 if (!(inactive_pipes & tmp)) {
1364                         active_number++;
1365                 }
1366                 tmp <<= 1;
1367         }
1368         if (active_number == 1) {
1369                 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1370         } else {
1371                 WREG32(SPI_CONFIG_CNTL, 0);
1372         }
1373
1374         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1375         tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
1376         if (tmp < rdev->config.rv770.max_backends) {
1377                 rdev->config.rv770.max_backends = tmp;
1378         }
1379
1380         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1381         tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
1382         if (tmp < rdev->config.rv770.max_pipes) {
1383                 rdev->config.rv770.max_pipes = tmp;
1384         }
1385         tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1386         if (tmp < rdev->config.rv770.max_simds) {
1387                 rdev->config.rv770.max_simds = tmp;
1388         }
1389
1390         switch (rdev->config.rv770.max_tile_pipes) {
1391         case 1:
1392         default:
1393                 gb_tiling_config = PIPE_TILING(0);
1394                 break;
1395         case 2:
1396                 gb_tiling_config = PIPE_TILING(1);
1397                 break;
1398         case 4:
1399                 gb_tiling_config = PIPE_TILING(2);
1400                 break;
1401         case 8:
1402                 gb_tiling_config = PIPE_TILING(3);
1403                 break;
1404         }
1405         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1406
1407         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1408         tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1409         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1410                                         R7XX_MAX_BACKENDS, disabled_rb_mask);
1411         gb_tiling_config |= tmp << 16;
1412         rdev->config.rv770.backend_map = tmp;
1413
1414         if (rdev->family == CHIP_RV770)
1415                 gb_tiling_config |= BANK_TILING(1);
1416         else {
1417                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1418                         gb_tiling_config |= BANK_TILING(1);
1419                 else
1420                         gb_tiling_config |= BANK_TILING(0);
1421         }
1422         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1423         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1424         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1425                 gb_tiling_config |= ROW_TILING(3);
1426                 gb_tiling_config |= SAMPLE_SPLIT(3);
1427         } else {
1428                 gb_tiling_config |=
1429                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1430                 gb_tiling_config |=
1431                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1432         }
1433
1434         gb_tiling_config |= BANK_SWAPS(1);
1435         rdev->config.rv770.tile_config = gb_tiling_config;
1436
1437         WREG32(GB_TILING_CONFIG, gb_tiling_config);
1438         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1439         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1440         WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1441         WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1442         if (rdev->family == CHIP_RV730) {
1443                 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1444                 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1445                 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1446         }
1447
1448         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1449         WREG32(CGTS_TCC_DISABLE, 0);
1450         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1451         WREG32(CGTS_USER_TCC_DISABLE, 0);
1452
1453
1454         num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1455         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1456         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1457
1458         /* set HW defaults for 3D engine */
1459         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1460                                      ROQ_IB2_START(0x2b)));
1461
1462         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1463
1464         ta_aux_cntl = RREG32(TA_CNTL_AUX);
1465         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1466
1467         sx_debug_1 = RREG32(SX_DEBUG_1);
1468         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1469         WREG32(SX_DEBUG_1, sx_debug_1);
1470
1471         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1472         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1473         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1474         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1475
1476         if (rdev->family != CHIP_RV740)
1477                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1478                                        GS_FLUSH_CTL(4) |
1479                                        ACK_FLUSH_CTL(3) |
1480                                        SYNC_FLUSH_CTL));
1481
1482         if (rdev->family != CHIP_RV770)
1483                 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1484
1485         db_debug3 = RREG32(DB_DEBUG3);
1486         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1487         switch (rdev->family) {
1488         case CHIP_RV770:
1489         case CHIP_RV740:
1490                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1491                 break;
1492         case CHIP_RV710:
1493         case CHIP_RV730:
1494         default:
1495                 db_debug3 |= DB_CLK_OFF_DELAY(2);
1496                 break;
1497         }
1498         WREG32(DB_DEBUG3, db_debug3);
1499
1500         if (rdev->family != CHIP_RV770) {
1501                 db_debug4 = RREG32(DB_DEBUG4);
1502                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1503                 WREG32(DB_DEBUG4, db_debug4);
1504         }
1505
1506         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1507                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1508                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1509
1510         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1511                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1512                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1513
1514         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1515
1516         WREG32(VGT_NUM_INSTANCES, 1);
1517
1518         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1519
1520         WREG32(CP_PERFMON_CNTL, 0);
1521
1522         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1523                             DONE_FIFO_HIWATER(0xe0) |
1524                             ALU_UPDATE_FIFO_HIWATER(0x8));
1525         switch (rdev->family) {
1526         case CHIP_RV770:
1527         case CHIP_RV730:
1528         case CHIP_RV710:
1529                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1530                 break;
1531         case CHIP_RV740:
1532         default:
1533                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1534                 break;
1535         }
1536         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1537
1538         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1539          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1540          */
1541         sq_config = RREG32(SQ_CONFIG);
1542         sq_config &= ~(PS_PRIO(3) |
1543                        VS_PRIO(3) |
1544                        GS_PRIO(3) |
1545                        ES_PRIO(3));
1546         sq_config |= (DX9_CONSTS |
1547                       VC_ENABLE |
1548                       EXPORT_SRC_C |
1549                       PS_PRIO(0) |
1550                       VS_PRIO(1) |
1551                       GS_PRIO(2) |
1552                       ES_PRIO(3));
1553         if (rdev->family == CHIP_RV710)
1554                 /* no vertex cache */
1555                 sq_config &= ~VC_ENABLE;
1556
1557         WREG32(SQ_CONFIG, sq_config);
1558
1559         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1560                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1561                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1562
1563         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1564                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1565
1566         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1567                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1568                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1569         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1570                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1571         else
1572                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1573         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1574
1575         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1576                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1577
1578         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1579                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1580
1581         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1582                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1583                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1584                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1585
1586         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1587         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1588         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1589         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1590         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1591         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1592         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1593         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1594
1595         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1596                                           FORCE_EOV_MAX_REZ_CNT(255)));
1597
1598         if (rdev->family == CHIP_RV710)
1599                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1600                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1601         else
1602                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1603                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1604
1605         switch (rdev->family) {
1606         case CHIP_RV770:
1607         case CHIP_RV730:
1608         case CHIP_RV740:
1609                 gs_prim_buffer_depth = 384;
1610                 break;
1611         case CHIP_RV710:
1612                 gs_prim_buffer_depth = 128;
1613                 break;
1614         default:
1615                 break;
1616         }
1617
1618         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1619         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1620         /* Max value for this is 256 */
1621         if (vgt_gs_per_es > 256)
1622                 vgt_gs_per_es = 256;
1623
1624         WREG32(VGT_ES_PER_GS, 128);
1625         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1626         WREG32(VGT_GS_PER_VS, 2);
1627
1628         /* more default values. 2D/3D driver should adjust as needed */
1629         WREG32(VGT_GS_VERTEX_REUSE, 16);
1630         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1631         WREG32(VGT_STRMOUT_EN, 0);
1632         WREG32(SX_MISC, 0);
1633         WREG32(PA_SC_MODE_CNTL, 0);
1634         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1635         WREG32(PA_SC_AA_CONFIG, 0);
1636         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1637         WREG32(PA_SC_LINE_STIPPLE, 0);
1638         WREG32(SPI_INPUT_Z, 0);
1639         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1640         WREG32(CB_COLOR7_FRAG, 0);
1641
1642         /* clear render buffer base addresses */
1643         WREG32(CB_COLOR0_BASE, 0);
1644         WREG32(CB_COLOR1_BASE, 0);
1645         WREG32(CB_COLOR2_BASE, 0);
1646         WREG32(CB_COLOR3_BASE, 0);
1647         WREG32(CB_COLOR4_BASE, 0);
1648         WREG32(CB_COLOR5_BASE, 0);
1649         WREG32(CB_COLOR6_BASE, 0);
1650         WREG32(CB_COLOR7_BASE, 0);
1651
1652         WREG32(TCP_CNTL, 0);
1653
1654         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1655         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1656
1657         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1658
1659         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1660                                           NUM_CLIP_SEQ(3)));
1661         WREG32(VC_ENHANCE, 0);
1662 }
1663
1664 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1665 {
1666         u64 size_bf, size_af;
1667
1668         if (mc->mc_vram_size > 0xE0000000) {
1669                 /* leave room for at least 512M GTT */
1670                 dev_warn(rdev->dev, "limiting VRAM\n");
1671                 mc->real_vram_size = 0xE0000000;
1672                 mc->mc_vram_size = 0xE0000000;
1673         }
1674         if (rdev->flags & RADEON_IS_AGP) {
1675                 size_bf = mc->gtt_start;
1676                 size_af = mc->mc_mask - mc->gtt_end;
1677                 if (size_bf > size_af) {
1678                         if (mc->mc_vram_size > size_bf) {
1679                                 dev_warn(rdev->dev, "limiting VRAM\n");
1680                                 mc->real_vram_size = size_bf;
1681                                 mc->mc_vram_size = size_bf;
1682                         }
1683                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1684                 } else {
1685                         if (mc->mc_vram_size > size_af) {
1686                                 dev_warn(rdev->dev, "limiting VRAM\n");
1687                                 mc->real_vram_size = size_af;
1688                                 mc->mc_vram_size = size_af;
1689                         }
1690                         mc->vram_start = mc->gtt_end + 1;
1691                 }
1692                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1693                 dev_info(rdev->dev, "VRAM: %juM 0x%08jX - 0x%08jX (%juM used)\n",
1694                                 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
1695                                 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
1696         } else {
1697                 radeon_vram_location(rdev, &rdev->mc, 0);
1698                 rdev->mc.gtt_base_align = 0;
1699                 radeon_gtt_location(rdev, mc);
1700         }
1701 }
1702
1703 static int rv770_mc_init(struct radeon_device *rdev)
1704 {
1705         u32 tmp;
1706         int chansize, numchan;
1707
1708         /* Get VRAM informations */
1709         rdev->mc.vram_is_ddr = true;
1710         tmp = RREG32(MC_ARB_RAMCFG);
1711         if (tmp & CHANSIZE_OVERRIDE) {
1712                 chansize = 16;
1713         } else if (tmp & CHANSIZE_MASK) {
1714                 chansize = 64;
1715         } else {
1716                 chansize = 32;
1717         }
1718         tmp = RREG32(MC_SHARED_CHMAP);
1719         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1720         case 0:
1721         default:
1722                 numchan = 1;
1723                 break;
1724         case 1:
1725                 numchan = 2;
1726                 break;
1727         case 2:
1728                 numchan = 4;
1729                 break;
1730         case 3:
1731                 numchan = 8;
1732                 break;
1733         }
1734         rdev->mc.vram_width = numchan * chansize;
1735         /* Could aper size report 0 ? */
1736         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1737         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1738         /* Setup GPU memory space */
1739         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1740         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1741         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1742         r700_vram_gtt_location(rdev, &rdev->mc);
1743         radeon_update_bandwidth_info(rdev);
1744
1745         return 0;
1746 }
1747
1748 /**
1749  * rv770_copy_dma - copy pages using the DMA engine
1750  *
1751  * @rdev: radeon_device pointer
1752  * @src_offset: src GPU address
1753  * @dst_offset: dst GPU address
1754  * @num_gpu_pages: number of GPU pages to xfer
1755  * @fence: radeon fence object
1756  *
1757  * Copy GPU paging using the DMA engine (r7xx).
1758  * Used by the radeon ttm implementation to move pages if
1759  * registered as the asic copy callback.
1760  */
1761 int rv770_copy_dma(struct radeon_device *rdev,
1762                   uint64_t src_offset, uint64_t dst_offset,
1763                   unsigned num_gpu_pages,
1764                   struct radeon_fence **fence)
1765 {
1766         struct radeon_semaphore *sem = NULL;
1767         int ring_index = rdev->asic->copy.dma_ring_index;
1768         struct radeon_ring *ring = &rdev->ring[ring_index];
1769         u32 size_in_dw, cur_size_in_dw;
1770         int i, num_loops;
1771         int r = 0;
1772
1773         r = radeon_semaphore_create(rdev, &sem);
1774         if (r) {
1775                 DRM_ERROR("radeon: moving bo (%d).\n", r);
1776                 return r;
1777         }
1778
1779         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
1780         num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
1781         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
1782         if (r) {
1783                 DRM_ERROR("radeon: moving bo (%d).\n", r);
1784                 radeon_semaphore_free(rdev, &sem, NULL);
1785                 return r;
1786         }
1787
1788         if (radeon_fence_need_sync(*fence, ring->idx)) {
1789                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
1790                                             ring->idx);
1791                 radeon_fence_note_sync(*fence, ring->idx);
1792         } else {
1793                 radeon_semaphore_free(rdev, &sem, NULL);
1794         }
1795
1796         for (i = 0; i < num_loops; i++) {
1797                 cur_size_in_dw = size_in_dw;
1798                 if (cur_size_in_dw > 0xFFFF)
1799                         cur_size_in_dw = 0xFFFF;
1800                 size_in_dw -= cur_size_in_dw;
1801                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
1802                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
1803                 radeon_ring_write(ring, src_offset & 0xfffffffc);
1804                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
1805                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
1806                 src_offset += cur_size_in_dw * 4;
1807                 dst_offset += cur_size_in_dw * 4;
1808         }
1809
1810         r = radeon_fence_emit(rdev, fence, ring->idx);
1811         if (r) {
1812                 radeon_ring_unlock_undo(rdev, ring);
1813                 return r;
1814         }
1815
1816         radeon_ring_unlock_commit(rdev, ring);
1817         radeon_semaphore_free(rdev, &sem, *fence);
1818
1819         return r;
1820 }
1821
1822 static int rv770_startup(struct radeon_device *rdev)
1823 {
1824         struct radeon_ring *ring;
1825         int r;
1826
1827         /* enable pcie gen2 link */
1828         rv770_pcie_gen2_enable(rdev);
1829
1830         rv770_mc_program(rdev);
1831
1832         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1833                 r = r600_init_microcode(rdev);
1834                 if (r) {
1835                         DRM_ERROR("Failed to load firmware!\n");
1836                         return r;
1837                 }
1838         }
1839
1840         r = r600_vram_scratch_init(rdev);
1841         if (r)
1842                 return r;
1843
1844         if (rdev->flags & RADEON_IS_AGP) {
1845                 rv770_agp_enable(rdev);
1846         } else {
1847                 r = rv770_pcie_gart_enable(rdev);
1848                 if (r)
1849                         return r;
1850         }
1851
1852         rv770_gpu_init(rdev);
1853         r = r600_blit_init(rdev);
1854         if (r) {
1855                 r600_blit_fini(rdev);
1856                 rdev->asic->copy.copy = NULL;
1857                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1858         }
1859
1860         /* allocate wb buffer */
1861         r = radeon_wb_init(rdev);
1862         if (r)
1863                 return r;
1864
1865         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1866         if (r) {
1867                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1868                 return r;
1869         }
1870
1871         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1872         if (r) {
1873                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1874                 return r;
1875         }
1876
1877         r = rv770_uvd_resume(rdev);
1878         if (!r) {
1879                 r = radeon_fence_driver_start_ring(rdev,
1880                                                    R600_RING_TYPE_UVD_INDEX);
1881                 if (r)
1882                         dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1883         }
1884
1885         if (r)
1886                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1887
1888         /* Enable IRQ */
1889         if (!rdev->irq.installed) {
1890                 r = radeon_irq_kms_init(rdev);
1891                 if (r)
1892                         return r;
1893         }
1894
1895         r = r600_irq_init(rdev);
1896         if (r) {
1897                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1898                 radeon_irq_kms_fini(rdev);
1899                 return r;
1900         }
1901         r600_irq_set(rdev);
1902
1903         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1904         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1905                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
1906                              0, 0xfffff, RADEON_CP_PACKET2);
1907         if (r)
1908                 return r;
1909
1910         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1911         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1912                              DMA_RB_RPTR, DMA_RB_WPTR,
1913                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1914         if (r)
1915                 return r;
1916
1917         r = rv770_cp_load_microcode(rdev);
1918         if (r)
1919                 return r;
1920         r = r600_cp_resume(rdev);
1921         if (r)
1922                 return r;
1923
1924         r = r600_dma_resume(rdev);
1925         if (r)
1926                 return r;
1927
1928         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1929         if (ring->ring_size) {
1930                 r = radeon_ring_init(rdev, ring, ring->ring_size,
1931                                      R600_WB_UVD_RPTR_OFFSET,
1932                                      UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1933                                      0, 0xfffff, RADEON_CP_PACKET2);
1934                 if (!r)
1935                         r = r600_uvd_init(rdev);
1936
1937                 if (r)
1938                         DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1939         }
1940
1941         r = radeon_ib_pool_init(rdev);
1942         if (r) {
1943                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1944                 return r;
1945         }
1946
1947         r = r600_audio_init(rdev);
1948         if (r) {
1949                 DRM_ERROR("radeon: audio init failed\n");
1950                 return r;
1951         }
1952
1953         return 0;
1954 }
1955
1956 int rv770_resume(struct radeon_device *rdev)
1957 {
1958         int r;
1959
1960         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1961          * posting will perform necessary task to bring back GPU into good
1962          * shape.
1963          */
1964         /* post card */
1965         atom_asic_init(rdev->mode_info.atom_context);
1966
1967         /* init golden registers */
1968         rv770_init_golden_registers(rdev);
1969
1970         rdev->accel_working = true;
1971         r = rv770_startup(rdev);
1972         if (r) {
1973                 DRM_ERROR("r600 startup failed on resume\n");
1974                 rdev->accel_working = false;
1975                 return r;
1976         }
1977
1978         return r;
1979
1980 }
1981
1982 int rv770_suspend(struct radeon_device *rdev)
1983 {
1984         r600_audio_fini(rdev);
1985         r600_uvd_stop(rdev);
1986         radeon_uvd_suspend(rdev);
1987         r700_cp_stop(rdev);
1988         r600_dma_stop(rdev);
1989         r600_irq_suspend(rdev);
1990         radeon_wb_disable(rdev);
1991         rv770_pcie_gart_disable(rdev);
1992
1993         return 0;
1994 }
1995
1996 /* Plan is to move initialization in that function and use
1997  * helper function so that radeon_device_init pretty much
1998  * do nothing more than calling asic specific function. This
1999  * should also allow to remove a bunch of callback function
2000  * like vram_info.
2001  */
2002 int rv770_init(struct radeon_device *rdev)
2003 {
2004         int r;
2005
2006         /* Read BIOS */
2007         if (!radeon_get_bios(rdev)) {
2008                 if (ASIC_IS_AVIVO(rdev))
2009                         return -EINVAL;
2010         }
2011         /* Must be an ATOMBIOS */
2012         if (!rdev->is_atom_bios) {
2013                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2014                 return -EINVAL;
2015         }
2016         r = radeon_atombios_init(rdev);
2017         if (r)
2018                 return r;
2019         /* Post card if necessary */
2020         if (!radeon_card_posted(rdev)) {
2021                 if (!rdev->bios) {
2022                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2023                         return -EINVAL;
2024                 }
2025                 DRM_INFO("GPU not posted. posting now...\n");
2026                 atom_asic_init(rdev->mode_info.atom_context);
2027         }
2028         /* init golden registers */
2029         rv770_init_golden_registers(rdev);
2030         /* Initialize scratch registers */
2031         r600_scratch_init(rdev);
2032         /* Initialize surface registers */
2033         radeon_surface_init(rdev);
2034         /* Initialize clocks */
2035         radeon_get_clock_info(rdev->ddev);
2036         /* Fence driver */
2037         r = radeon_fence_driver_init(rdev);
2038         if (r)
2039                 return r;
2040         /* initialize AGP */
2041         if (rdev->flags & RADEON_IS_AGP) {
2042                 r = radeon_agp_init(rdev);
2043                 if (r)
2044                         radeon_agp_disable(rdev);
2045         }
2046         r = rv770_mc_init(rdev);
2047         if (r)
2048                 return r;
2049         /* Memory manager */
2050         r = radeon_bo_init(rdev);
2051         if (r)
2052                 return r;
2053
2054         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2055         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2056
2057         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2058         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2059
2060         r = radeon_uvd_init(rdev);
2061         if (!r) {
2062                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2063                 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
2064                                4096);
2065         }
2066
2067         rdev->ih.ring_obj = NULL;
2068         r600_ih_ring_init(rdev, 64 * 1024);
2069
2070         r = r600_pcie_gart_init(rdev);
2071         if (r)
2072                 return r;
2073
2074         rdev->accel_working = true;
2075         r = rv770_startup(rdev);
2076         if (r) {
2077                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2078                 r700_cp_fini(rdev);
2079                 r600_dma_fini(rdev);
2080                 r600_irq_fini(rdev);
2081                 radeon_wb_fini(rdev);
2082                 radeon_ib_pool_fini(rdev);
2083                 radeon_irq_kms_fini(rdev);
2084                 rv770_pcie_gart_fini(rdev);
2085                 rdev->accel_working = false;
2086         }
2087
2088         return 0;
2089 }
2090
2091 void rv770_fini(struct radeon_device *rdev)
2092 {
2093         r600_blit_fini(rdev);
2094         r700_cp_fini(rdev);
2095         r600_dma_fini(rdev);
2096         r600_irq_fini(rdev);
2097         radeon_wb_fini(rdev);
2098         radeon_ib_pool_fini(rdev);
2099         radeon_irq_kms_fini(rdev);
2100         rv770_pcie_gart_fini(rdev);
2101         r600_uvd_stop(rdev);
2102         radeon_uvd_fini(rdev);
2103         r600_vram_scratch_fini(rdev);
2104         radeon_gem_fini(rdev);
2105         radeon_fence_driver_fini(rdev);
2106         radeon_agp_fini(rdev);
2107         radeon_bo_fini(rdev);
2108         radeon_atombios_fini(rdev);
2109         r600_fini_microcode(rdev);
2110         drm_free(rdev->bios, M_DRM);
2111         rdev->bios = NULL;
2112 }
2113
2114 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
2115 {
2116         u32 link_width_cntl, lanes, speed_cntl, tmp;
2117         u16 link_cntl2;
2118         u32 mask;
2119         int ret;
2120
2121         if (radeon_pcie_gen2 == 0)
2122                 return;
2123
2124         if (rdev->flags & RADEON_IS_IGP)
2125                 return;
2126
2127         if (!(rdev->flags & RADEON_IS_PCIE))
2128                 return;
2129
2130         /* x2 cards have a special sequence */
2131         if (ASIC_IS_X2(rdev))
2132                 return;
2133
2134         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
2135         if (ret != 0)
2136                 return;
2137
2138         if (!(mask & DRM_PCIE_SPEED_50))
2139                 return;
2140
2141         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
2142
2143         /* advertise upconfig capability */
2144         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2145         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2146         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2147         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2148         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2149                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2150                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2151                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
2152                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2153                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2154                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2155         } else {
2156                 link_width_cntl |= LC_UPCONFIGURE_DIS;
2157                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2158         }
2159
2160         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2161         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2162             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2163
2164                 tmp = RREG32(0x541c);
2165                 WREG32(0x541c, tmp | 0x8);
2166                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2167                 link_cntl2 = RREG16(0x4088);
2168                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2169                 link_cntl2 |= 0x2;
2170                 WREG16(0x4088, link_cntl2);
2171                 WREG32(MM_CFGREGS_CNTL, 0);
2172
2173                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2174                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2175                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2176
2177                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2178                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2179                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2180
2181                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2182                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2183                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2184
2185                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2186                 speed_cntl |= LC_GEN2_EN_STRAP;
2187                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2188
2189         } else {
2190                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2191                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2192                 if (1)
2193                         link_width_cntl |= LC_UPCONFIGURE_DIS;
2194                 else
2195                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2196                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2197         }
2198 }