drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / sumo_dpm.h
1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __SUMO_DPM_H__
24 #define __SUMO_DPM_H__
25
26 #include "atom.h"
27
28 #define SUMO_MAX_HARDWARE_POWERLEVELS 5
29 #define SUMO_PM_NUMBER_OF_TC 15
30
31 struct sumo_pl {
32         u32 sclk;
33         u32 vddc_index;
34         u32 ds_divider_index;
35         u32 ss_divider_index;
36         u32 allow_gnb_slow;
37         u32 sclk_dpm_tdp_limit;
38 };
39
40 /* used for the flags field */
41 #define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)
42 #define SUMO_POWERSTATE_FLAGS_BOOST_STATE       (1 << 1)
43
44 struct sumo_ps {
45         struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
46         u32 num_levels;
47         /* flags */
48         u32 flags;
49 };
50
51 #define NUMBER_OF_M3ARB_PARAM_SETS 10
52 #define SUMO_MAX_NUMBER_VOLTAGES    4
53
54 struct sumo_disp_clock_voltage_mapping_table {
55         u32 num_max_voltage_levels;
56         u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];
57 };
58
59 struct sumo_vid_mapping_entry {
60         u16 vid_2bit;
61         u16 vid_7bit;
62 };
63
64 struct sumo_vid_mapping_table {
65         u32 num_entries;
66         struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];
67 };
68
69 struct sumo_sclk_voltage_mapping_entry {
70         u32 sclk_frequency;
71         u16 vid_2bit;
72         u16 rsv;
73 };
74
75 struct sumo_sclk_voltage_mapping_table {
76         u32 num_max_dpm_entries;
77         struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];
78 };
79
80 struct sumo_sys_info {
81         u32 bootup_sclk;
82         u32 min_sclk;
83         u32 bootup_uma_clk;
84         u16 bootup_nb_voltage_index;
85         u8 htc_tmp_lmt;
86         u8 htc_hyst_lmt;
87         struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
88         struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;
89         struct sumo_vid_mapping_table vid_mapping_table;
90         u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];
91         u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];
92         u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];
93         u32 sclk_dpm_boost_margin;
94         u32 sclk_dpm_throttle_margin;
95         u32 sclk_dpm_tdp_limit_pg;
96         u32 gnb_tdp_limit;
97         u32 sclk_dpm_tdp_limit_boost;
98         u32 boost_sclk;
99         u32 boost_vid_2bit;
100         bool enable_boost;
101 };
102
103 struct sumo_power_info {
104         u32 asi;
105         u32 pasi;
106         u32 bsp;
107         u32 bsu;
108         u32 pbsp;
109         u32 pbsu;
110         u32 dsp;
111         u32 psp;
112         u32 thermal_auto_throttling;
113         u32 uvd_m3_arbiter;
114         u32 fw_version;
115         struct sumo_sys_info sys_info;
116         struct sumo_pl acpi_pl;
117         struct sumo_pl boot_pl;
118         struct sumo_pl boost_pl;
119         bool disable_gfx_power_gating_in_uvd;
120         bool driver_nbps_policy_disable;
121         bool enable_alt_vddnb;
122         bool enable_dynamic_m3_arbiter;
123         bool enable_gfx_clock_gating;
124         bool enable_gfx_power_gating;
125         bool enable_mg_clock_gating;
126         bool enable_sclk_ds;
127         bool enable_auto_thermal_throttling;
128         bool enable_dynamic_patch_ps;
129         bool enable_dpm;
130         bool enable_boost;
131         struct radeon_ps current_rps;
132         struct sumo_ps current_ps;
133         struct radeon_ps requested_rps;
134         struct sumo_ps requested_ps;
135 };
136
137 #define SUMO_UTC_DFLT_00                     0x48
138 #define SUMO_UTC_DFLT_01                     0x44
139 #define SUMO_UTC_DFLT_02                     0x44
140 #define SUMO_UTC_DFLT_03                     0x44
141 #define SUMO_UTC_DFLT_04                     0x44
142 #define SUMO_UTC_DFLT_05                     0x44
143 #define SUMO_UTC_DFLT_06                     0x44
144 #define SUMO_UTC_DFLT_07                     0x44
145 #define SUMO_UTC_DFLT_08                     0x44
146 #define SUMO_UTC_DFLT_09                     0x44
147 #define SUMO_UTC_DFLT_10                     0x44
148 #define SUMO_UTC_DFLT_11                     0x44
149 #define SUMO_UTC_DFLT_12                     0x44
150 #define SUMO_UTC_DFLT_13                     0x44
151 #define SUMO_UTC_DFLT_14                     0x44
152
153 #define SUMO_DTC_DFLT_00                     0x48
154 #define SUMO_DTC_DFLT_01                     0x44
155 #define SUMO_DTC_DFLT_02                     0x44
156 #define SUMO_DTC_DFLT_03                     0x44
157 #define SUMO_DTC_DFLT_04                     0x44
158 #define SUMO_DTC_DFLT_05                     0x44
159 #define SUMO_DTC_DFLT_06                     0x44
160 #define SUMO_DTC_DFLT_07                     0x44
161 #define SUMO_DTC_DFLT_08                     0x44
162 #define SUMO_DTC_DFLT_09                     0x44
163 #define SUMO_DTC_DFLT_10                     0x44
164 #define SUMO_DTC_DFLT_11                     0x44
165 #define SUMO_DTC_DFLT_12                     0x44
166 #define SUMO_DTC_DFLT_13                     0x44
167 #define SUMO_DTC_DFLT_14                     0x44
168
169 #define SUMO_AH_DFLT               5
170
171 #define SUMO_R_DFLT0               70
172 #define SUMO_R_DFLT1               70
173 #define SUMO_R_DFLT2               70
174 #define SUMO_R_DFLT3               70
175 #define SUMO_R_DFLT4               100
176
177 #define SUMO_L_DFLT0               0
178 #define SUMO_L_DFLT1               20
179 #define SUMO_L_DFLT2               20
180 #define SUMO_L_DFLT3               20
181 #define SUMO_L_DFLT4               20
182 #define SUMO_VRC_DFLT              0x30033
183 #define SUMO_MGCGTTLOCAL0_DFLT     0
184 #define SUMO_MGCGTTLOCAL1_DFLT     0
185 #define SUMO_GICST_DFLT            19
186 #define SUMO_SST_DFLT              8
187 #define SUMO_VOLTAGEDROPT_DFLT     1
188 #define SUMO_GFXPOWERGATINGT_DFLT  100
189
190 /* sumo_dpm.c */
191 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);
192 void sumo_program_vc(struct radeon_device *rdev, u32 vrc);
193 void sumo_clear_vc(struct radeon_device *rdev);
194 void sumo_program_sstp(struct radeon_device *rdev);
195 void sumo_take_smu_control(struct radeon_device *rdev, bool enable);
196 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
197                                                struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
198                                                ATOM_AVAILABLE_SCLK_LIST *table);
199 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
200                                       struct sumo_vid_mapping_table *vid_mapping_table,
201                                       ATOM_AVAILABLE_SCLK_LIST *table);
202 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
203                               struct sumo_vid_mapping_table *vid_mapping_table,
204                               u32 vid_2bit);
205 u32 sumo_get_sleep_divider_from_id(u32 id);
206 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
207                                          u32 sclk,
208                                          u32 min_sclk_in_sr);
209
210 /* sumo_smc.c */
211 void sumo_initialize_m3_arb(struct radeon_device *rdev);
212 void sumo_smu_pg_init(struct radeon_device *rdev);
213 void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);
214 void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
215                                       bool powersaving, bool force_nbps1);
216 void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);
217 void sumo_enable_boost_timer(struct radeon_device *rdev);
218 u32 sumo_get_running_fw_version(struct radeon_device *rdev);
219
220 #endif