drm/radeon: Sync to Linux 3.11
[dragonfly.git] / sys / dev / drm / radeon / trinity_dpm.h
1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __TRINITY_DPM_H__
24 #define __TRINITY_DPM_H__
25
26 #include "sumo_dpm.h"
27
28 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)
29
30 struct trinity_pl {
31         u32 sclk;
32         u8 vddc_index;
33         u8 ds_divider_index;
34         u8 ss_divider_index;
35         u8 allow_gnb_slow;
36         u8 force_nbp_state;
37         u8 display_wm;
38         u8 vce_wm;
39 };
40
41 #define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH  (1 << 0)
42 #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1)
43 #define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW  (1 << 2)
44
45 #define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE    (1 << 0)
46
47 struct trinity_ps {
48         u32 num_levels;
49         struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
50
51         u32 nbps_flags;
52         u32 bapm_flags;
53
54         u8 Dpm0PgNbPsLo;
55         u8 Dpm0PgNbPsHi;
56         u8 DpmXNbPsLo;
57         u8 DpmXNbPsHi;
58
59         u32 vclk_low_divider;
60         u32 vclk_high_divider;
61         u32 dclk_low_divider;
62         u32 dclk_high_divider;
63 };
64
65 #define TRINITY_NUM_NBPSTATES   4
66
67 struct trinity_uvd_clock_table_entry
68 {
69         u32 vclk;
70         u32 dclk;
71         u8 vclk_did;
72         u8 dclk_did;
73         u8 rsv[2];
74 };
75
76 struct trinity_sys_info {
77         u32 bootup_uma_clk;
78         u32 bootup_sclk;
79         u32 min_sclk;
80         u32 dentist_vco_freq;
81         u32 nb_dpm_enable;
82         u32 nbp_mclk[TRINITY_NUM_NBPSTATES];
83         u32 nbp_nclk[TRINITY_NUM_NBPSTATES];
84         u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES];
85         u16 bootup_nb_voltage_index;
86         u8 htc_tmp_lmt;
87         u8 htc_hyst_lmt;
88         struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
89         struct sumo_vid_mapping_table vid_mapping_table;
90         u32 uma_channel_number;
91         struct trinity_uvd_clock_table_entry uvd_clock_table_entries[4];
92 };
93
94 struct trinity_power_info {
95         u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
96         u32 dpm_interval;
97         u32 thermal_auto_throttling;
98         struct trinity_sys_info sys_info;
99         struct trinity_pl boot_pl;
100         u32 min_sclk_did;
101         bool enable_nbps_policy;
102         bool voltage_drop_in_dce;
103         bool override_dynamic_mgpg;
104         bool enable_gfx_clock_gating;
105         bool enable_gfx_power_gating;
106         bool enable_mg_clock_gating;
107         bool enable_gfx_dynamic_mgpg;
108         bool enable_auto_thermal_throttling;
109         bool enable_dpm;
110         bool enable_sclk_ds;
111         bool uvd_dpm;
112         struct radeon_ps current_rps;
113         struct trinity_ps current_ps;
114         struct radeon_ps requested_rps;
115         struct trinity_ps requested_ps;
116 };
117
118 #define TRINITY_AT_DFLT            30
119
120 /* trinity_smc.c */
121 int trinity_dpm_config(struct radeon_device *rdev, bool enable);
122 int trinity_uvd_dpm_config(struct radeon_device *rdev);
123 int trinity_dpm_force_state(struct radeon_device *rdev, u32 n);
124 int trinity_dpm_n_levels_disabled(struct radeon_device *rdev, u32 n);
125 int trinity_dpm_no_forced_level(struct radeon_device *rdev);
126 int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev,
127                                           bool enable);
128 int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev);
129 void trinity_acquire_mutex(struct radeon_device *rdev);
130 void trinity_release_mutex(struct radeon_device *rdev);
131
132 #endif