sys/dev/drm/radeon/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   2 /*
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel D�zer <michel@daenzer.net>
  31  *
  32  * ------------------------ This file is DEPRECATED! -------------------------
  33  *
  34  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_irq.c 254885 2013-08-25 19:37:15Z dumbbell $
  35  */
  36
  37 #include <drm/drmP.h>
  38 #include <uapi_drm/radeon_drm.h>
  39 #include "radeon_drv.h"
  40
  41 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
  42 {
  43         drm_radeon_private_t *dev_priv = dev->dev_private;
  44
  45         if (state)
  46                 dev_priv->irq_enable_reg |= mask;
  47         else
  48                 dev_priv->irq_enable_reg &= ~mask;
  49
  50         if (dev->irq_enabled)
  51                 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  52 }
  53
  54 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
  55 {
  56         drm_radeon_private_t *dev_priv = dev->dev_private;
  57
  58         if (state)
  59                 dev_priv->r500_disp_irq_reg |= mask;
  60         else
  61                 dev_priv->r500_disp_irq_reg &= ~mask;
  62
  63         if (dev->irq_enabled)
  64                 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  65 }
  66
  67 int radeon_enable_vblank(struct drm_device *dev, int crtc)
  68 {
  69         drm_radeon_private_t *dev_priv = dev->dev_private;
  70
  71         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
  72                 switch (crtc) {
  73                 case 0:
  74                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
  75                         break;
  76                 case 1:
  77                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
  78                         break;
  79                 default:
  80                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  81                                   crtc);
  82                         return -EINVAL;
  83                 }
  84         } else {
  85                 switch (crtc) {
  86                 case 0:
  87                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
  88                         break;
  89                 case 1:
  90                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
  91                         break;
  92                 default:
  93                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
  94                                   crtc);
  95                         return -EINVAL;
  96                 }
  97         }
  98
  99         return 0;
 100 }
 101
 102 void radeon_disable_vblank(struct drm_device *dev, int crtc)
 103 {
 104         drm_radeon_private_t *dev_priv = dev->dev_private;
 105
 106         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 107                 switch (crtc) {
 108                 case 0:
 109                         r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
 110                         break;
 111                 case 1:
 112                         r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
 113                         break;
 114                 default:
 115                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 116                                   crtc);
 117                         break;
 118                 }
 119         } else {
 120                 switch (crtc) {
 121                 case 0:
 122                         radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
 123                         break;
 124                 case 1:
 125                         radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
 126                         break;
 127                 default:
 128                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
 129                                   crtc);
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
 136 {
 137         u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
 138         u32 irq_mask = RADEON_SW_INT_TEST;
 139
 140         *r500_disp_int = 0;
 141         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 142                 /* vbl interrupts in a different place */
 143
 144                 if (irqs & R500_DISPLAY_INT_STATUS) {
 145                         /* if a display interrupt */
 146                         u32 disp_irq;
 147
 148                         disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
 149
 150                         *r500_disp_int = disp_irq;
 151                         if (disp_irq & R500_D1_VBLANK_INTERRUPT)
 152                                 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 153                         if (disp_irq & R500_D2_VBLANK_INTERRUPT)
 154                                 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
 155                 }
 156                 irq_mask |= R500_DISPLAY_INT_STATUS;
 157         } else
 158                 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
 159
 160         irqs &= irq_mask;
 161
 162         if (irqs)
 163                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
 164
 165         return irqs;
 166 }
 167
 168 /* Interrupts - Used for device synchronization and flushing in the
 169  * following circumstances:
 170  *
 171  * - Exclusive FB access with hw idle:
 172  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
 173  *
 174  * - Frame throttling, NV_fence:
 175  *    - Drop marker irq's into command stream ahead of time.
 176  *    - Wait on irq's with lock *not held*
 177  *    - Check each for termination condition
 178  *
 179  * - Internally in cp_getbuffer, etc:
 180  *    - as above, but wait with lock held???
 181  *
 182  * NOTE: These functions are misleadingly named -- the irq's aren't
 183  * tied to dma at all, this is just a hangover from dri prehistory.
 184  */
 185
 186 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
 187 {
 188         struct drm_device *dev = (struct drm_device *) arg;
 189         drm_radeon_private_t *dev_priv =
 190             (drm_radeon_private_t *) dev->dev_private;
 191         u32 stat;
 192         u32 r500_disp_int;
 193
 194         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 195                 return IRQ_NONE;
 196
 197         /* Only consider the bits we're interested in - others could be used
 198          * outside the DRM
 199          */
 200         stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
 201         if (!stat)
 202                 return IRQ_NONE;
 203
 204         stat &= dev_priv->irq_enable_reg;
 205
 206         /* SW interrupt */
 207         if (stat & RADEON_SW_INT_TEST)
 208                 DRM_WAKEUP(&dev_priv->swi_queue);
 209
 210         /* VBLANK interrupt */
 211         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 212                 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
 213                         drm_handle_vblank(dev, 0);
 214                 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
 215                         drm_handle_vblank(dev, 1);
 216         } else {
 217                 if (stat & RADEON_CRTC_VBLANK_STAT)
 218                         drm_handle_vblank(dev, 0);
 219                 if (stat & RADEON_CRTC2_VBLANK_STAT)
 220                         drm_handle_vblank(dev, 1);
 221         }
 222         return IRQ_HANDLED;
 223 }
 224
 225 static int radeon_emit_irq(struct drm_device * dev)
 226 {
 227         drm_radeon_private_t *dev_priv = dev->dev_private;
 228         unsigned int ret;
 229         RING_LOCALS;
 230
 231         atomic_inc(&dev_priv->swi_emitted);
 232         ret = atomic_read(&dev_priv->swi_emitted);
 233
 234         BEGIN_RING(4);
 235         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 236         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 237         ADVANCE_RING();
 238         COMMIT_RING();
 239
 240         return ret;
 241 }
 242
 243 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
 244 {
 245         drm_radeon_private_t *dev_priv =
 246             (drm_radeon_private_t *) dev->dev_private;
 247         int ret = 0;
 248
 249         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 250                 return 0;
 251
 252         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 253
 254         DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
 255                     RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 256
 257         return ret;
 258 }
 259
 260 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
 261 {
 262         drm_radeon_private_t *dev_priv = dev->dev_private;
 263
 264         if (!dev_priv) {
 265                 DRM_ERROR("called with no initialization\n");
 266                 return -EINVAL;
 267         }
 268
 269         if (crtc < 0 || crtc > 1) {
 270                 DRM_ERROR("Invalid crtc %d\n", crtc);
 271                 return -EINVAL;
 272         }
 273
 274         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
 275                 if (crtc == 0)
 276                         return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
 277                 else
 278                         return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
 279         } else {
 280                 if (crtc == 0)
 281                         return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
 282                 else
 283                         return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
 284         }
 285 }
 286
 287 /* Needs the lock as it touches the ring.
 288  */
 289 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
 290 {
 291         drm_radeon_private_t *dev_priv = dev->dev_private;
 292         drm_radeon_irq_emit_t *emit = data;
 293         int result;
 294
 295         if (!dev_priv) {
 296                 DRM_ERROR("called with no initialization\n");
 297                 return -EINVAL;
 298         }
 299
 300         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 301                 return -EINVAL;
 302
 303         LOCK_TEST_WITH_RETURN(dev, file_priv);
 304
 305         result = radeon_emit_irq(dev);
 306
 307         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 308                 DRM_ERROR("copy_to_user\n");
 309                 return -EFAULT;
 310         }
 311
 312         return 0;
 313 }
 314
 315 /* Doesn't need the hardware lock.
 316  */
 317 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
 318 {
 319         drm_radeon_private_t *dev_priv = dev->dev_private;
 320         drm_radeon_irq_wait_t *irqwait = data;
 321
 322         if (!dev_priv) {
 323                 DRM_ERROR("called with no initialization\n");
 324                 return -EINVAL;
 325         }
 326
 327         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 328                 return -EINVAL;
 329
 330         return radeon_wait_irq(dev, irqwait->irq_seq);
 331 }
 332
 333 /* drm_dma.h hooks
 334 */
 335 void radeon_driver_irq_preinstall(struct drm_device * dev)
 336 {
 337         drm_radeon_private_t *dev_priv =
 338             (drm_radeon_private_t *) dev->dev_private;
 339         u32 dummy;
 340
 341         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 342                 return;
 343
 344         /* Disable *all* interrupts */
 345         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 346                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 347         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 348
 349         /* Clear bits if they're already high */
 350         radeon_acknowledge_irqs(dev_priv, &dummy);
 351 }
 352
 353 int radeon_driver_irq_postinstall(struct drm_device *dev)
 354 {
 355         drm_radeon_private_t *dev_priv =
 356             (drm_radeon_private_t *) dev->dev_private;
 357
 358         atomic_set(&dev_priv->swi_emitted, 0);
 359         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
 360
 361         dev->max_vblank_count = 0x001fffff;
 362
 363         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 364                 return 0;
 365
 366         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 367
 368         return 0;
 369 }
 370
 371 void radeon_driver_irq_uninstall(struct drm_device * dev)
 372 {
 373         drm_radeon_private_t *dev_priv =
 374             (drm_radeon_private_t *) dev->dev_private;
 375         if (!dev_priv)
 376                 return;
 377
 378         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 379                 return;
 380
 381         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
 382                 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
 383         /* Disable *all* interrupts */
 384         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 385 }
 386
 387
 388 int radeon_vblank_crtc_get(struct drm_device *dev)
 389 {
 390         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 391
 392         return dev_priv->vblank_crtc;
 393 }
 394
 395 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
 396 {
 397         drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
 398         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 399                 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
 400                 return -EINVAL;
 401         }
 402         dev_priv->vblank_crtc = (unsigned int)value;
 403         return 0;
 404 }