2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
270 u_int32_t cpu_apic_versions[MAXCPU];
272 extern int64_t tsc_offsets[];
274 extern u_long ebda_addr;
276 #ifdef SMP /* APIC-IO */
277 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
281 * APIC ID logical/physical mapping structures.
282 * We oversize these to simplify boot-time config.
284 int cpu_num_to_apic_id[NAPICID];
285 int apic_id_to_logical[NAPICID];
287 /* AP uses this during bootstrap. Do not staticize. */
291 /* Hotwire a 0->4MB V==P mapping */
292 extern pt_entry_t *KPTphys;
295 * SMP page table page. Setup by locore to point to a page table
296 * page from which we allocate per-cpu privatespace areas io_apics,
300 #define IO_MAPPING_START_INDEX \
301 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
303 extern pt_entry_t *SMPpt;
305 struct pcb stoppcbs[MAXCPU];
307 static basetable_entry basetable_entry_types[] =
309 {0, 20, "Processor"},
317 * Local data and functions.
320 static u_int boot_address;
321 static u_int base_memory;
322 static int mp_finish;
323 static int mp_finish_lapic;
325 static void mp_enable(u_int boot_addr);
327 static int mptable_iterate_entries(const mpcth_t,
328 mptable_iter_func, void *);
329 static int mptable_search(void);
330 static int mptable_search_sig(u_int32_t target, int count);
331 static int mptable_hyperthread_fixup(cpumask_t, int);
332 static int mptable_map(struct mptable_pos *);
333 static void mptable_unmap(struct mptable_pos *);
334 static void mptable_bus_info_alloc(const mpcth_t,
335 struct mptable_bus_info *);
336 static void mptable_bus_info_free(struct mptable_bus_info *);
338 static int mptable_lapic_probe(struct lapic_enumerator *);
339 static void mptable_lapic_enumerate(struct lapic_enumerator *);
340 static void mptable_lapic_default(void);
342 static int mptable_ioapic_probe(struct ioapic_enumerator *);
343 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
345 static int start_all_aps(u_int boot_addr);
346 static void install_ap_tramp(u_int boot_addr);
347 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
348 static int smitest(void);
350 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
351 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
352 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
353 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
357 static vm_paddr_t mptable_fps_phyaddr;
358 static int mptable_use_default;
359 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
360 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
361 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
362 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
365 * Calculate usable address in base memory for AP trampoline code.
368 mp_bootaddress(u_int basemem)
370 POSTCODE(MP_BOOTADDRESS_POST);
372 base_memory = basemem;
374 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
375 if ((base_memory - boot_address) < bootMP_size)
376 boot_address -= 4096; /* not enough, lower by 4k */
385 struct mptable_pos mpt;
388 KKASSERT(mptable_fps_phyaddr == 0);
390 mptable_fps_phyaddr = mptable_search();
391 if (mptable_fps_phyaddr == 0)
394 error = mptable_map(&mpt);
396 mptable_fps_phyaddr = 0;
400 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
401 kprintf("MPTABLE: use default configuration\n");
402 mptable_use_default = 1;
404 if (mpt.mp_fps->mpfb2 & 0x80)
409 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
412 * Look for an Intel MP spec table (ie, SMP capable hardware).
421 * Make sure our SMPpt[] page table is big enough to hold all the
424 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
426 POSTCODE(MP_PROBE_POST);
428 /* see if EBDA exists */
429 if (ebda_addr != 0) {
430 /* search first 1K of EBDA */
431 target = (u_int32_t)ebda_addr;
432 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
435 /* last 1K of base memory, effective 'top of base' passed in */
436 target = (u_int32_t)(base_memory - 0x400);
437 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
441 /* search the BIOS */
442 target = (u_int32_t)BIOS_BASE;
443 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
446 /* search the extended BIOS */
447 target = (u_int32_t)BIOS_BASE2;
448 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
456 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
458 int count, total_size;
459 const void *position;
461 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
462 total_size = cth->base_table_length - sizeof(struct MPCTH);
463 position = (const uint8_t *)cth + sizeof(struct MPCTH);
464 count = cth->entry_count;
469 KKASSERT(total_size >= 0);
470 if (total_size == 0) {
471 kprintf("invalid base MP table, "
472 "entry count and length mismatch\n");
476 type = *(const uint8_t *)position;
478 case 0: /* processor_entry */
479 case 1: /* bus_entry */
480 case 2: /* io_apic_entry */
481 case 3: /* int_entry */
482 case 4: /* int_entry */
485 kprintf("unknown base MP table entry type %d\n", type);
489 if (total_size < basetable_entry_types[type].length) {
490 kprintf("invalid base MP table length, "
491 "does not contain all entries\n");
494 total_size -= basetable_entry_types[type].length;
496 error = func(arg, position, type);
500 position = (const uint8_t *)position +
501 basetable_entry_types[type].length;
508 * Startup the SMP processors.
513 POSTCODE(MP_START_POST);
514 mp_enable(boot_address);
519 * Print various information about the SMP system hardware and setup.
526 POSTCODE(MP_ANNOUNCE_POST);
528 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
529 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
530 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
531 for (x = 1; x <= mp_naps; ++x) {
532 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
533 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
537 kprintf(" Warning: APIC I/O disabled\n");
541 * AP cpu's call this to sync up protected mode.
543 * WARNING! We must ensure that the cpu is sufficiently initialized to
544 * be able to use to the FP for our optimized bzero/bcopy code before
545 * we enter more mainstream C code.
547 * WARNING! %fs is not set up on entry. This routine sets up %fs.
553 int x, myid = bootAP;
555 struct mdglobaldata *md;
556 struct privatespace *ps;
558 ps = &CPU_prvspace[myid];
560 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
561 gdt_segs[GPROC0_SEL].ssd_base =
562 (int) &ps->mdglobaldata.gd_common_tss;
563 ps->mdglobaldata.mi.gd_prvspace = ps;
565 for (x = 0; x < NGDT; x++) {
566 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
569 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
570 r_gdt.rd_base = (int) &gdt[myid * NGDT];
571 lgdt(&r_gdt); /* does magic intra-segment return */
576 mdcpu->gd_currentldt = _default_ldt;
578 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
579 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
581 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
583 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
584 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
585 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
586 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
587 md->gd_common_tssd = *md->gd_tss_gdt;
591 * Set to a known state:
592 * Set by mpboot.s: CR0_PG, CR0_PE
593 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
596 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
598 pmap_set_opt(); /* PSE/4MB pages, etc */
600 /* set up CPU registers and state */
603 /* set up FPU state on the AP */
604 npxinit(__INITIAL_NPXCW__);
606 /* set up SSE registers */
610 /*******************************************************************
611 * local functions and data
615 * start the SMP system
618 mp_enable(u_int boot_addr)
620 POSTCODE(MP_ENABLE_POST);
624 /* Initialize BSP's local APIC */
627 /* start each Application Processor */
628 start_all_aps(boot_addr);
634 MachIntrABI.finalize();
639 * look for the MP spec signature
642 /* string defined by the Intel MP Spec as identifying the MP table */
643 #define MP_SIG 0x5f504d5f /* _MP_ */
644 #define NEXT(X) ((X) += 4)
646 mptable_search_sig(u_int32_t target, int count)
652 KKASSERT(target != 0);
654 map_size = count * sizeof(u_int32_t);
655 addr = pmap_mapdev((vm_paddr_t)target, map_size);
658 for (x = 0; x < count; NEXT(x)) {
659 if (addr[x] == MP_SIG) {
660 /* make array index a byte index */
661 ret = target + (x * sizeof(u_int32_t));
666 pmap_unmapdev((vm_offset_t)addr, map_size);
670 static int processor_entry (const struct PROCENTRY *entry, int cpu);
673 * Check if we should perform a hyperthreading "fix-up" to
674 * enumerate any logical CPU's that aren't already listed
677 * XXX: We assume that all of the physical CPUs in the
678 * system have the same number of logical CPUs.
680 * XXX: We assume that APIC ID's are allocated such that
681 * the APIC ID's for a physical processor are aligned
682 * with the number of logical CPU's in the processor.
685 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
687 int i, id, lcpus_max, logical_cpus;
689 if ((cpu_feature & CPUID_HTT) == 0)
692 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
696 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
698 * INSTRUCTION SET REFERENCE, A-M (#253666)
699 * Page 3-181, Table 3-20
700 * "The nearest power-of-2 integer that is not smaller
701 * than EBX[23:16] is the number of unique initial APIC
702 * IDs reserved for addressing different logical
703 * processors in a physical package."
706 if ((1 << i) >= lcpus_max) {
713 KKASSERT(cpu_count != 0);
714 if (cpu_count == lcpus_max) {
715 /* We have nothing to fix */
717 } else if (cpu_count == 1) {
718 /* XXX this may be incorrect */
719 logical_cpus = lcpus_max;
724 * Calculate the distances between two nearest
725 * APIC IDs. If all such distances are same,
726 * then it is the number of missing cpus that
727 * we are going to fill later.
729 dist = cur = prev = -1;
730 for (id = 0; id < MAXCPU; ++id) {
731 if ((id_mask & CPUMASK(id)) == 0)
736 int new_dist = cur - prev;
742 * Make sure that all distances
743 * between two nearest APIC IDs
746 if (dist != new_dist)
754 /* Must be power of 2 */
755 if (dist & (dist - 1))
758 /* Can't exceed CPU package capacity */
759 if (dist > lcpus_max)
760 logical_cpus = lcpus_max;
766 * For each APIC ID of a CPU that is set in the mask,
767 * scan the other candidate APIC ID's for this
768 * physical processor. If any of those ID's are
769 * already in the table, then kill the fixup.
771 for (id = 0; id < MAXCPU; id++) {
772 if ((id_mask & CPUMASK(id)) == 0)
774 /* First, make sure we are on a logical_cpus boundary. */
775 if (id % logical_cpus != 0)
777 for (i = id + 1; i < id + logical_cpus; i++)
778 if ((id_mask & CPUMASK(i)) != 0)
785 mptable_map(struct mptable_pos *mpt)
789 vm_size_t cth_mapsz = 0;
791 KKASSERT(mptable_fps_phyaddr != 0);
793 bzero(mpt, sizeof(*mpt));
795 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
798 * Map configuration table header to get
799 * the base table size
801 cth = pmap_mapdev(fps->pap, sizeof(*cth));
802 cth_mapsz = cth->base_table_length;
803 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
805 if (cth_mapsz < sizeof(*cth)) {
806 kprintf("invalid base MP table length %d\n",
808 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
815 cth = pmap_mapdev(fps->pap, cth_mapsz);
820 mpt->mp_cth_mapsz = cth_mapsz;
826 mptable_unmap(struct mptable_pos *mpt)
828 if (mpt->mp_cth != NULL) {
829 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
831 mpt->mp_cth_mapsz = 0;
833 if (mpt->mp_fps != NULL) {
834 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
840 mp_set_cpuids(int cpu_id, int apic_id)
842 CPU_TO_ID(cpu_id) = apic_id;
843 ID_TO_CPU(apic_id) = cpu_id;
847 processor_entry(const struct PROCENTRY *entry, int cpu)
851 /* check for usability */
852 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
855 /* check for BSP flag */
856 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
857 mp_set_cpuids(0, entry->apic_id);
858 return 0; /* its already been counted */
861 /* add another AP to list, if less than max number of CPUs */
862 else if (cpu < MAXCPU) {
863 mp_set_cpuids(cpu, entry->apic_id);
871 ioapic_map(vm_paddr_t pa)
873 KKASSERT(pa < 0x100000000LL);
874 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
878 * start each AP in our list
881 start_all_aps(u_int boot_addr)
889 u_long mpbioswarmvec;
890 struct mdglobaldata *gd;
891 struct privatespace *ps;
895 POSTCODE(START_ALL_APS_POST);
897 /* install the AP 1st level boot code */
898 install_ap_tramp(boot_addr);
901 /* save the current value of the warm-start vector */
902 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
903 outb(CMOS_REG, BIOS_RESET);
904 mpbiosreason = inb(CMOS_DATA);
906 /* setup a vector to our boot code */
907 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
908 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
909 outb(CMOS_REG, BIOS_RESET);
910 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
913 * If we have a TSC we can figure out the SMI interrupt rate.
914 * The SMI does not necessarily use a constant rate. Spend
915 * up to 250ms trying to figure it out.
918 if (cpu_feature & CPUID_TSC) {
919 set_apic_timer(275000);
920 smilast = read_apic_timer();
921 for (x = 0; x < 20 && read_apic_timer(); ++x) {
922 smicount = smitest();
923 if (smibest == 0 || smilast - smicount < smibest)
924 smibest = smilast - smicount;
927 if (smibest > 250000)
930 smibest = smibest * (int64_t)1000000 /
931 get_apic_timer_frequency();
935 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
936 1000000 / smibest, smibest);
939 /* set up temporary P==V mapping for AP boot */
940 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
941 kptbase = (uintptr_t)(void *)KPTphys;
942 for (x = 0; x < NKPT; x++) {
943 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
944 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
949 for (x = 1; x <= mp_naps; ++x) {
951 /* This is a bit verbose, it will go away soon. */
953 /* first page of AP's private space */
954 pg = x * i386_btop(sizeof(struct privatespace));
956 /* allocate new private data page(s) */
957 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
958 MDGLOBALDATA_BASEALLOC_SIZE);
959 /* wire it into the private page table page */
960 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
961 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
962 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
964 pg += MDGLOBALDATA_BASEALLOC_PAGES;
966 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
967 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
968 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
969 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
971 /* allocate and set up an idle stack data page */
972 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
973 for (i = 0; i < UPAGES; i++) {
974 SMPpt[pg + 4 + i] = (pt_entry_t)
975 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
978 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
979 bzero(gd, sizeof(*gd));
980 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
982 /* prime data page for it to use */
983 mi_gdinit(&gd->mi, x);
985 gd->gd_CMAP1 = &SMPpt[pg + 0];
986 gd->gd_CMAP2 = &SMPpt[pg + 1];
987 gd->gd_CMAP3 = &SMPpt[pg + 2];
988 gd->gd_PMAP1 = &SMPpt[pg + 3];
989 gd->gd_CADDR1 = ps->CPAGE1;
990 gd->gd_CADDR2 = ps->CPAGE2;
991 gd->gd_CADDR3 = ps->CPAGE3;
992 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
995 * Per-cpu pmap for get_ptbase().
997 gd->gd_GDADDR1= (unsigned *)
998 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
999 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
1001 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
1002 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
1005 * Setup the AP boot stack
1007 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
1010 /* attempt to start the Application Processor */
1011 CHECK_INIT(99); /* setup checkpoints */
1012 if (!start_ap(gd, boot_addr, smibest)) {
1013 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1014 CHECK_PRINT("trace"); /* show checkpoints */
1015 /* better panic as the AP may be running loose */
1016 kprintf("panic y/n? [y] ");
1017 if (cngetc() != 'n')
1020 CHECK_PRINT("trace"); /* show checkpoints */
1022 /* record its version info */
1023 cpu_apic_versions[x] = cpu_apic_versions[0];
1026 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
1029 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
1030 for (shift = 0; (1 << shift) <= ncpus; ++shift)
1033 ncpus2_shift = shift;
1034 ncpus2 = 1 << shift;
1035 ncpus2_mask = ncpus2 - 1;
1037 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
1038 if ((1 << shift) < ncpus)
1040 ncpus_fit = 1 << shift;
1041 ncpus_fit_mask = ncpus_fit - 1;
1043 /* build our map of 'other' CPUs */
1044 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1045 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1046 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1048 /* fill in our (BSP) APIC version */
1049 cpu_apic_versions[0] = lapic.version;
1051 /* restore the warmstart vector */
1052 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1053 outb(CMOS_REG, BIOS_RESET);
1054 outb(CMOS_DATA, mpbiosreason);
1057 * NOTE! The idlestack for the BSP was setup by locore. Finish
1058 * up, clean out the P==V mapping we did earlier.
1060 for (x = 0; x < NKPT; x++)
1065 * Wait all APs to finish initializing LAPIC
1067 mp_finish_lapic = 1;
1069 kprintf("SMP: Waiting APs LAPIC initialization\n");
1070 if (cpu_feature & CPUID_TSC)
1071 tsc0_offset = rdtsc();
1074 while (smp_lapic_mask != smp_startup_mask) {
1076 if (cpu_feature & CPUID_TSC)
1077 tsc0_offset = rdtsc();
1079 while (try_mplock() == 0)
1082 /* number of APs actually started */
1087 * load the 1st level AP boot code into base memory.
1090 /* targets for relocation */
1091 extern void bigJump(void);
1092 extern void bootCodeSeg(void);
1093 extern void bootDataSeg(void);
1094 extern void MPentry(void);
1095 extern u_int MP_GDT;
1096 extern u_int mp_gdtbase;
1099 install_ap_tramp(u_int boot_addr)
1102 int size = *(int *) ((u_long) & bootMP_size);
1103 u_char *src = (u_char *) ((u_long) bootMP);
1104 u_char *dst = (u_char *) boot_addr + KERNBASE;
1105 u_int boot_base = (u_int) bootMP;
1110 POSTCODE(INSTALL_AP_TRAMP_POST);
1112 for (x = 0; x < size; ++x)
1116 * modify addresses in code we just moved to basemem. unfortunately we
1117 * need fairly detailed info about mpboot.s for this to work. changes
1118 * to mpboot.s might require changes here.
1121 /* boot code is located in KERNEL space */
1122 dst = (u_char *) boot_addr + KERNBASE;
1124 /* modify the lgdt arg */
1125 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1126 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1128 /* modify the ljmp target for MPentry() */
1129 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1130 *dst32 = ((u_int) MPentry - KERNBASE);
1132 /* modify the target for boot code segment */
1133 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1134 dst8 = (u_int8_t *) (dst16 + 1);
1135 *dst16 = (u_int) boot_addr & 0xffff;
1136 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1138 /* modify the target for boot data segment */
1139 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1140 dst8 = (u_int8_t *) (dst16 + 1);
1141 *dst16 = (u_int) boot_addr & 0xffff;
1142 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1147 * This function starts the AP (application processor) identified
1148 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1149 * to accomplish this. This is necessary because of the nuances
1150 * of the different hardware we might encounter. It ain't pretty,
1151 * but it seems to work.
1153 * NOTE: eventually an AP gets to ap_init(), which is called just
1154 * before the AP goes into the LWKT scheduler's idle loop.
1157 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
1161 u_long icr_lo, icr_hi;
1163 POSTCODE(START_AP_POST);
1165 /* get the PHYSICAL APIC ID# */
1166 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
1168 /* calculate the vector */
1169 vector = (boot_addr >> 12) & 0xff;
1171 /* We don't want anything interfering */
1174 /* Make sure the target cpu sees everything */
1178 * Try to detect when a SMI has occurred, wait up to 200ms.
1180 * If a SMI occurs during an AP reset but before we issue
1181 * the STARTUP command, the AP may brick. To work around
1182 * this problem we hold off doing the AP startup until
1183 * after we have detected the SMI. Hopefully another SMI
1184 * will not occur before we finish the AP startup.
1186 * Retries don't seem to help. SMIs have a window of opportunity
1187 * and if USB->legacy keyboard emulation is enabled in the BIOS
1188 * the interrupt rate can be quite high.
1190 * NOTE: Don't worry about the L1 cache load, it might bloat
1191 * ldelta a little but ndelta will be so huge when the SMI
1192 * occurs the detection logic will still work fine.
1195 set_apic_timer(200000);
1200 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1201 * and running the target CPU. OR this INIT IPI might be latched (P5
1202 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1205 * see apic/apicreg.h for icr bit definitions.
1207 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
1211 * Setup the address for the target AP. We can setup
1212 * icr_hi once and then just trigger operations with
1215 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1216 icr_hi |= (physical_cpu << 24);
1217 icr_lo = lapic.icr_lo & 0xfff00000;
1218 lapic.icr_hi = icr_hi;
1221 * Do an INIT IPI: assert RESET
1223 * Use edge triggered mode to assert INIT
1225 lapic.icr_lo = icr_lo | 0x0000c500;
1226 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1230 * The spec calls for a 10ms delay but we may have to use a
1231 * MUCH lower delay to avoid bricking an AP due to a fast SMI
1232 * interrupt. We have other loops here too and dividing by 2
1233 * doesn't seem to be enough even after subtracting 350us,
1234 * so we divide by 4.
1236 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
1237 * interrupt was detected we use the full 10ms.
1241 else if (smibest < 150 * 4 + 350)
1243 else if ((smibest - 350) / 4 < 10000)
1244 u_sleep((smibest - 350) / 4);
1249 * Do an INIT IPI: deassert RESET
1251 * Use level triggered mode to deassert. It is unclear
1252 * why we need to do this.
1254 lapic.icr_lo = icr_lo | 0x00008500;
1255 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1257 u_sleep(150); /* wait 150us */
1260 * Next we do a STARTUP IPI: the previous INIT IPI might still be
1261 * latched, (P5 bug) this 1st STARTUP would then terminate
1262 * immediately, and the previously started INIT IPI would continue. OR
1263 * the previous INIT IPI has already run. and this STARTUP IPI will
1264 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1267 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1268 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1270 u_sleep(200); /* wait ~200uS */
1273 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1274 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1275 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1276 * recognized after hardware RESET or INIT IPI.
1278 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1279 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1282 /* Resume normal operation */
1285 /* wait for it to start, see ap_init() */
1286 set_apic_timer(5000000);/* == 5 seconds */
1287 while (read_apic_timer()) {
1288 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
1289 return 1; /* return SUCCESS */
1292 return 0; /* return FAILURE */
1307 while (read_apic_timer()) {
1309 for (count = 0; count < 100; ++count)
1310 ntsc = rdtsc(); /* force loop to occur */
1312 ndelta = ntsc - ltsc;
1313 if (ldelta > ndelta)
1315 if (ndelta > ldelta * 2)
1318 ldelta = ntsc - ltsc;
1321 return(read_apic_timer());
1325 * Lazy flush the TLB on all other CPU's. DEPRECATED.
1327 * If for some reason we were unable to start all cpus we cannot safely
1328 * use broadcast IPIs.
1331 static cpumask_t smp_invltlb_req;
1332 #define SMP_INVLTLB_DEBUG
1338 struct mdglobaldata *md = mdcpu;
1339 #ifdef SMP_INVLTLB_DEBUG
1344 crit_enter_gd(&md->mi);
1345 md->gd_invltlb_ret = 0;
1346 ++md->mi.gd_cnt.v_smpinvltlb;
1347 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1348 #ifdef SMP_INVLTLB_DEBUG
1351 if (smp_startup_mask == smp_active_mask) {
1352 all_but_self_ipi(XINVLTLB_OFFSET);
1354 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
1355 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1358 #ifdef SMP_INVLTLB_DEBUG
1360 kprintf("smp_invltlb: ipi sent\n");
1362 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
1363 (smp_active_mask & ~md->mi.gd_cpumask)) {
1366 #ifdef SMP_INVLTLB_DEBUG
1368 if (++count == 400000000) {
1369 print_backtrace(-1);
1370 kprintf("smp_invltlb: endless loop %08lx %08lx, "
1371 "rflags %016lx retry",
1372 (long)md->gd_invltlb_ret,
1373 (long)smp_invltlb_req,
1374 (long)read_eflags());
1375 __asm __volatile ("sti");
1378 lwkt_process_ipiq();
1380 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
1381 ~md->mi.gd_cpumask &
1384 kprintf("bcpu %d\n", bcpu);
1385 xgd = globaldata_find(bcpu);
1386 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
1395 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1396 crit_exit_gd(&md->mi);
1403 * Called from Xinvltlb assembly with interrupts disabled. We didn't
1404 * bother to bump the critical section count or nested interrupt count
1405 * so only do very low level operations here.
1408 smp_invltlb_intr(void)
1410 struct mdglobaldata *md = mdcpu;
1411 struct mdglobaldata *omd;
1415 mask = smp_invltlb_req;
1419 cpu = BSFCPUMASK(mask);
1420 mask &= ~CPUMASK(cpu);
1421 omd = (struct mdglobaldata *)globaldata_find(cpu);
1422 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
1429 * When called the executing CPU will send an IPI to all other CPUs
1430 * requesting that they halt execution.
1432 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1434 * - Signals all CPUs in map to stop.
1435 * - Waits for each to stop.
1442 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1443 * from executing at same time.
1446 stop_cpus(cpumask_t map)
1448 map &= smp_active_mask;
1450 /* send the Xcpustop IPI to all CPUs in map */
1451 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1453 while ((stopped_cpus & map) != map)
1461 * Called by a CPU to restart stopped CPUs.
1463 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1465 * - Signals all CPUs in map to restart.
1466 * - Waits for each to restart.
1474 restart_cpus(cpumask_t map)
1476 /* signal other cpus to restart */
1477 started_cpus = map & smp_active_mask;
1479 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
1486 * This is called once the mpboot code has gotten us properly relocated
1487 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1488 * and when it returns the scheduler will call the real cpu_idle() main
1489 * loop for the idlethread. Interrupts are disabled on entry and should
1490 * remain disabled at return.
1498 * Adjust smp_startup_mask to signal the BSP that we have started
1499 * up successfully. Note that we do not yet hold the BGL. The BSP
1500 * is waiting for our signal.
1502 * We can't set our bit in smp_active_mask yet because we are holding
1503 * interrupts physically disabled and remote cpus could deadlock
1504 * trying to send us an IPI.
1506 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
1510 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1511 * non-zero, then get the MP lock.
1513 * Note: We are in a critical section.
1515 * Note: we are the idle thread, we can only spin.
1517 * Note: The load fence is memory volatile and prevents the compiler
1518 * from improperly caching mp_finish_lapic, and the cpu from improperly
1521 while (mp_finish_lapic == 0)
1523 while (try_mplock() == 0)
1526 if (cpu_feature & CPUID_TSC) {
1528 * The BSP is constantly updating tsc0_offset, figure out
1529 * the relative difference to synchronize ktrdump.
1531 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1534 /* BSP may have changed PTD while we're waiting for the lock */
1537 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1541 /* Build our map of 'other' CPUs. */
1542 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1544 /* A quick check from sanity claus */
1545 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
1546 if (mycpu->gd_cpuid != apic_id) {
1547 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1548 kprintf("SMP: apic_id = %d\n", apic_id);
1549 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1550 panic("cpuid mismatch! boom!!");
1553 /* Initialize AP's local APIC for irq's */
1556 /* LAPIC initialization is done */
1557 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1560 /* Let BSP move onto the next initialization stage */
1564 * Interlock for finalization. Wait until mp_finish is non-zero,
1565 * then get the MP lock.
1567 * Note: We are in a critical section.
1569 * Note: we are the idle thread, we can only spin.
1571 * Note: The load fence is memory volatile and prevents the compiler
1572 * from improperly caching mp_finish, and the cpu from improperly
1575 while (mp_finish == 0)
1577 while (try_mplock() == 0)
1580 /* BSP may have changed PTD while we're waiting for the lock */
1583 /* Set memory range attributes for this CPU to match the BSP */
1584 mem_range_AP_init();
1587 * Once we go active we must process any IPIQ messages that may
1588 * have been queued, because no actual IPI will occur until we
1589 * set our bit in the smp_active_mask. If we don't the IPI
1590 * message interlock could be left set which would also prevent
1593 * The idle loop doesn't expect the BGL to be held and while
1594 * lwkt_switch() normally cleans things up this is a special case
1595 * because we returning almost directly into the idle loop.
1597 * The idle thread is never placed on the runq, make sure
1598 * nothing we've done put it there.
1600 KKASSERT(get_mplock_count(curthread) == 1);
1601 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1604 * Enable interrupts here. idle_restore will also do it, but
1605 * doing it here lets us clean up any strays that got posted to
1606 * the CPU during the AP boot while we are still in a critical
1609 __asm __volatile("sti; pause; pause"::);
1610 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1612 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1613 lwkt_process_ipiq();
1616 * Releasing the mp lock lets the BSP finish up the SMP init
1619 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1623 * Get SMP fully working before we start initializing devices.
1631 kprintf("Finish MP startup\n");
1633 while (smp_active_mask != smp_startup_mask)
1635 while (try_mplock() == 0)
1638 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1641 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1644 cpu_send_ipiq(int dcpu)
1646 if (CPUMASK(dcpu) & smp_active_mask)
1647 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1650 #if 0 /* single_apic_ipi_passive() not working yet */
1652 * Returns 0 on failure, 1 on success
1655 cpu_send_ipiq_passive(int dcpu)
1658 if (CPUMASK(dcpu) & smp_active_mask) {
1659 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1660 APIC_DELMODE_FIXED);
1667 mptable_bus_info_callback(void *xarg, const void *pos, int type)
1669 struct mptable_bus_info *bus_info = xarg;
1670 const struct BUSENTRY *ent;
1671 struct mptable_bus *bus;
1677 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
1678 if (bus->mb_id == ent->bus_id) {
1679 kprintf("mptable_bus_info_alloc: duplicated bus id "
1680 "(%d)\n", bus->mb_id);
1686 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
1687 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1688 bus->mb_type = MPTABLE_BUS_PCI;
1689 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
1690 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1691 bus->mb_type = MPTABLE_BUS_ISA;
1695 bus->mb_id = ent->bus_id;
1696 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
1702 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
1706 bzero(bus_info, sizeof(*bus_info));
1707 TAILQ_INIT(&bus_info->mbi_list);
1709 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
1711 mptable_bus_info_free(bus_info);
1715 mptable_bus_info_free(struct mptable_bus_info *bus_info)
1717 struct mptable_bus *bus;
1719 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
1720 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
1725 struct mptable_lapic_cbarg1 {
1728 u_int ht_apicid_mask;
1732 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
1734 const struct PROCENTRY *ent;
1735 struct mptable_lapic_cbarg1 *arg = xarg;
1741 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1745 if (ent->apic_id < 32) {
1746 arg->ht_apicid_mask |= 1 << ent->apic_id;
1747 } else if (arg->ht_fixup) {
1748 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
1754 struct mptable_lapic_cbarg2 {
1761 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
1763 const struct PROCENTRY *ent;
1764 struct mptable_lapic_cbarg2 *arg = xarg;
1770 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1771 KKASSERT(!arg->found_bsp);
1775 if (processor_entry(ent, arg->cpu))
1778 if (arg->logical_cpus) {
1779 struct PROCENTRY proc;
1783 * Create fake mptable processor entries
1784 * and feed them to processor_entry() to
1785 * enumerate the logical CPUs.
1787 bzero(&proc, sizeof(proc));
1789 proc.cpu_flags = PROCENTRY_FLAG_EN;
1790 proc.apic_id = ent->apic_id;
1792 for (i = 1; i < arg->logical_cpus; i++) {
1794 processor_entry(&proc, arg->cpu);
1802 mptable_lapic_default(void)
1804 int ap_apicid, bsp_apicid;
1806 mp_naps = 1; /* exclude BSP */
1808 /* Map local apic before the id field is accessed */
1809 lapic_map(DEFAULT_APIC_BASE);
1811 bsp_apicid = APIC_ID(lapic.id);
1812 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
1815 mp_set_cpuids(0, bsp_apicid);
1816 /* one and only AP */
1817 mp_set_cpuids(1, ap_apicid);
1823 * ID_TO_CPU(N), APIC ID to logical CPU table
1824 * CPU_TO_ID(N), logical CPU to APIC ID table
1827 mptable_lapic_enumerate(struct lapic_enumerator *e)
1829 struct mptable_pos mpt;
1830 struct mptable_lapic_cbarg1 arg1;
1831 struct mptable_lapic_cbarg2 arg2;
1833 int error, logical_cpus = 0;
1834 vm_offset_t lapic_addr;
1836 if (mptable_use_default) {
1837 mptable_lapic_default();
1841 error = mptable_map(&mpt);
1843 panic("mptable_lapic_enumerate mptable_map failed\n");
1844 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1848 /* Save local apic address */
1849 lapic_addr = (vm_offset_t)cth->apic_address;
1850 KKASSERT(lapic_addr != 0);
1853 * Find out how many CPUs do we have
1855 bzero(&arg1, sizeof(arg1));
1856 arg1.ht_fixup = 1; /* Apply ht fixup by default */
1858 error = mptable_iterate_entries(cth,
1859 mptable_lapic_pass1_callback, &arg1);
1861 panic("mptable_iterate_entries(lapic_pass1) failed\n");
1862 KKASSERT(arg1.cpu_count != 0);
1864 /* See if we need to fixup HT logical CPUs. */
1865 if (arg1.ht_fixup) {
1866 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
1868 if (logical_cpus != 0)
1869 arg1.cpu_count *= logical_cpus;
1871 mp_naps = arg1.cpu_count;
1873 /* Qualify the numbers again, after possible HT fixup */
1874 if (mp_naps > MAXCPU) {
1875 kprintf("Warning: only using %d of %d available CPUs!\n",
1880 --mp_naps; /* subtract the BSP */
1883 * Link logical CPU id to local apic id
1885 bzero(&arg2, sizeof(arg2));
1887 arg2.logical_cpus = logical_cpus;
1889 error = mptable_iterate_entries(cth,
1890 mptable_lapic_pass2_callback, &arg2);
1892 panic("mptable_iterate_entries(lapic_pass2) failed\n");
1893 KKASSERT(arg2.found_bsp);
1895 /* Map local apic */
1896 lapic_map(lapic_addr);
1898 mptable_unmap(&mpt);
1901 struct mptable_lapic_probe_cbarg {
1907 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
1909 const struct PROCENTRY *ent;
1910 struct mptable_lapic_probe_cbarg *arg = xarg;
1916 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1920 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1921 if (arg->found_bsp) {
1922 kprintf("more than one BSP in base MP table\n");
1931 mptable_lapic_probe(struct lapic_enumerator *e)
1933 struct mptable_pos mpt;
1934 struct mptable_lapic_probe_cbarg arg;
1938 if (mptable_fps_phyaddr == 0)
1941 if (mptable_use_default)
1944 error = mptable_map(&mpt);
1947 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1952 if (cth->apic_address == 0)
1955 bzero(&arg, sizeof(arg));
1956 error = mptable_iterate_entries(cth,
1957 mptable_lapic_probe_callback, &arg);
1959 if (arg.cpu_count == 0) {
1960 kprintf("MP table contains no processor entries\n");
1962 } else if (!arg.found_bsp) {
1963 kprintf("MP table does not contains BSP entry\n");
1968 mptable_unmap(&mpt);
1972 static struct lapic_enumerator mptable_lapic_enumerator = {
1973 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
1974 .lapic_probe = mptable_lapic_probe,
1975 .lapic_enumerate = mptable_lapic_enumerate
1979 mptable_lapic_enum_register(void)
1981 lapic_enumerator_register(&mptable_lapic_enumerator);
1983 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
1984 mptable_lapic_enum_register, 0);
1987 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
1989 const struct IOAPICENTRY *ent;
1990 struct mptable_ioapic *nioapic, *ioapic;
1996 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
1999 if (ent->apic_address == 0) {
2000 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
2004 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2005 if (ioapic->mio_apic_id == ent->apic_id) {
2006 kprintf("mptable_ioapic_create_list: duplicated "
2007 "apic id %d\n", ioapic->mio_apic_id);
2010 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
2011 kprintf("mptable_ioapic_create_list: overlapped "
2012 "IOAPIC addr 0x%08x", ioapic->mio_addr);
2017 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2018 nioapic->mio_apic_id = ent->apic_id;
2019 nioapic->mio_addr = (uint32_t)ent->apic_address;
2022 * Create IOAPIC list in ascending order of APIC ID
2024 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
2025 mptable_ioapic_list, mio_link) {
2026 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
2027 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
2028 ioapic, nioapic, mio_link);
2033 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
2039 mptable_ioapic_create_list(void)
2041 struct mptable_ioapic *ioapic;
2042 struct mptable_pos mpt;
2045 if (mptable_fps_phyaddr == 0)
2048 if (mptable_use_default) {
2049 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2050 ioapic->mio_idx = 0;
2051 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
2052 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
2054 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
2058 error = mptable_map(&mpt);
2060 panic("mptable_ioapic_create_list: mptable_map failed\n");
2061 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2063 error = mptable_iterate_entries(mpt.mp_cth,
2064 mptable_ioapic_list_callback, NULL);
2066 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
2067 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
2068 kfree(ioapic, M_DEVBUF);
2074 * Assign index number for each IOAPIC
2077 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2078 ioapic->mio_idx = idx;
2082 mptable_unmap(&mpt);
2084 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
2085 mptable_ioapic_create_list, 0);
2088 mptable_pci_int_callback(void *xarg, const void *pos, int type)
2090 const struct mptable_bus_info *bus_info = xarg;
2091 const struct mptable_ioapic *ioapic;
2092 const struct mptable_bus *bus;
2093 struct mptable_pci_int *pci_int;
2094 const struct INTENTRY *ent;
2095 int pci_pin, pci_dev;
2101 if (ent->int_type != 0)
2104 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2105 if (bus->mb_type == MPTABLE_BUS_PCI &&
2106 bus->mb_id == ent->src_bus_id)
2112 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2113 if (ioapic->mio_apic_id == ent->dst_apic_id)
2116 if (ioapic == NULL) {
2117 kprintf("MPTABLE: warning PCI int dst apic id %d "
2118 "does not exist\n", ent->dst_apic_id);
2122 pci_pin = ent->src_bus_irq & 0x3;
2123 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
2125 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2126 if (pci_int->mpci_bus == ent->src_bus_id &&
2127 pci_int->mpci_dev == pci_dev &&
2128 pci_int->mpci_pin == pci_pin) {
2129 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
2130 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
2131 kprintf("MPTABLE: warning duplicated "
2132 "PCI int entry for "
2133 "bus %d, dev %d, pin %d\n",
2139 kprintf("mptable_pci_int_register: "
2140 "conflict PCI int entry for "
2141 "bus %d, dev %d, pin %d, "
2142 "IOAPIC %d.%d -> %d.%d\n",
2146 pci_int->mpci_ioapic_idx,
2147 pci_int->mpci_ioapic_pin,
2155 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
2157 pci_int->mpci_bus = ent->src_bus_id;
2158 pci_int->mpci_dev = pci_dev;
2159 pci_int->mpci_pin = pci_pin;
2160 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
2161 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
2163 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
2169 mptable_pci_int_register(void)
2171 struct mptable_bus_info bus_info;
2172 const struct mptable_bus *bus;
2173 struct mptable_pci_int *pci_int;
2174 struct mptable_pos mpt;
2175 int error, force_pci0, npcibus;
2178 if (mptable_fps_phyaddr == 0)
2181 if (mptable_use_default)
2184 if (TAILQ_EMPTY(&mptable_ioapic_list))
2187 error = mptable_map(&mpt);
2189 panic("mptable_pci_int_register: mptable_map failed\n");
2190 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2194 mptable_bus_info_alloc(cth, &bus_info);
2195 if (TAILQ_EMPTY(&bus_info.mbi_list))
2200 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
2201 if (bus->mb_type == MPTABLE_BUS_PCI)
2205 mptable_bus_info_free(&bus_info);
2207 } else if (npcibus == 1) {
2211 error = mptable_iterate_entries(cth,
2212 mptable_pci_int_callback, &bus_info);
2214 mptable_bus_info_free(&bus_info);
2217 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
2218 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
2219 kfree(pci_int, M_DEVBUF);
2225 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
2226 pci_int->mpci_bus = 0;
2229 mptable_unmap(&mpt);
2231 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2232 mptable_pci_int_register, 0);
2234 struct mptable_ioapic_probe_cbarg {
2235 const struct mptable_bus_info *bus_info;
2239 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
2241 struct mptable_ioapic_probe_cbarg *arg = xarg;
2242 const struct mptable_ioapic *ioapic;
2243 const struct mptable_bus *bus;
2244 const struct INTENTRY *ent;
2250 if (ent->int_type != 0)
2253 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2254 if (bus->mb_type == MPTABLE_BUS_ISA &&
2255 bus->mb_id == ent->src_bus_id)
2261 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2262 if (ioapic->mio_apic_id == ent->dst_apic_id)
2265 if (ioapic == NULL) {
2266 kprintf("MPTABLE: warning ISA int dst apic id %d "
2267 "does not exist\n", ent->dst_apic_id);
2271 /* XXX magic number */
2272 if (ent->src_bus_irq >= 16) {
2273 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
2281 mptable_ioapic_probe(struct ioapic_enumerator *e)
2283 struct mptable_ioapic_probe_cbarg arg;
2284 struct mptable_bus_info bus_info;
2285 struct mptable_pos mpt;
2289 if (mptable_fps_phyaddr == 0)
2292 if (mptable_use_default)
2295 if (TAILQ_EMPTY(&mptable_ioapic_list))
2298 error = mptable_map(&mpt);
2300 panic("mptable_ioapic_probe: mptable_map failed\n");
2301 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2305 mptable_bus_info_alloc(cth, &bus_info);
2307 bzero(&arg, sizeof(arg));
2308 arg.bus_info = &bus_info;
2310 error = mptable_iterate_entries(cth,
2311 mptable_ioapic_probe_callback, &arg);
2313 mptable_bus_info_free(&bus_info);
2314 mptable_unmap(&mpt);
2319 struct mptable_ioapic_int_cbarg {
2320 const struct mptable_bus_info *bus_info;
2325 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
2327 struct mptable_ioapic_int_cbarg *arg = xarg;
2328 const struct mptable_ioapic *ioapic;
2329 const struct mptable_bus *bus;
2330 const struct INTENTRY *ent;
2339 if (ent->int_type != 0)
2342 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2343 if (bus->mb_type == MPTABLE_BUS_ISA &&
2344 bus->mb_id == ent->src_bus_id)
2350 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2351 if (ioapic->mio_apic_id == ent->dst_apic_id)
2354 if (ioapic == NULL) {
2355 kprintf("MPTABLE: warning ISA int dst apic id %d "
2356 "does not exist\n", ent->dst_apic_id);
2360 if (ent->dst_apic_int >= ioapic->mio_npin) {
2361 panic("mptable_ioapic_enumerate: invalid I/O APIC "
2362 "pin %d, should be < %d",
2363 ent->dst_apic_int, ioapic->mio_npin);
2365 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
2367 if (ent->src_bus_irq != gsi) {
2369 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
2370 ent->src_bus_irq, gsi);
2372 ioapic_intsrc(ent->src_bus_irq, gsi,
2373 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2379 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
2381 struct mptable_bus_info bus_info;
2382 struct mptable_ioapic *ioapic;
2383 struct mptable_pos mpt;
2387 KKASSERT(mptable_fps_phyaddr != 0);
2388 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
2390 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2391 const struct mptable_ioapic *prev_ioapic;
2395 addr = ioapic_map(ioapic->mio_addr);
2397 ver = ioapic_read(addr, IOAPIC_VER);
2398 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
2399 >> MAXREDIRSHIFT) + 1;
2401 prev_ioapic = TAILQ_PREV(ioapic,
2402 mptable_ioapic_list, mio_link);
2403 if (prev_ioapic == NULL) {
2404 ioapic->mio_gsi_base = 0;
2406 ioapic->mio_gsi_base =
2407 prev_ioapic->mio_gsi_base +
2408 prev_ioapic->mio_npin;
2410 ioapic_add(addr, ioapic->mio_gsi_base,
2414 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
2415 "apic id %d, idx %d, gsi base %d, npin %d\n",
2417 ioapic->mio_apic_id,
2419 ioapic->mio_gsi_base,
2424 if (mptable_use_default) {
2426 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
2427 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2431 error = mptable_map(&mpt);
2433 panic("mptable_ioapic_probe: mptable_map failed\n");
2434 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2438 mptable_bus_info_alloc(cth, &bus_info);
2440 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
2442 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
2443 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2445 struct mptable_ioapic_int_cbarg arg;
2447 bzero(&arg, sizeof(arg));
2448 arg.bus_info = &bus_info;
2450 error = mptable_iterate_entries(cth,
2451 mptable_ioapic_int_callback, &arg);
2453 panic("mptable_ioapic_int failed\n");
2455 if (arg.ioapic_nint == 0) {
2457 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
2460 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
2461 INTR_POLARITY_HIGH);
2465 mptable_bus_info_free(&bus_info);
2467 mptable_unmap(&mpt);
2470 static struct ioapic_enumerator mptable_ioapic_enumerator = {
2471 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
2472 .ioapic_probe = mptable_ioapic_probe,
2473 .ioapic_enumerate = mptable_ioapic_enumerate
2477 mptable_ioapic_enum_register(void)
2479 ioapic_enumerator_register(&mptable_ioapic_enumerator);
2481 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2482 mptable_ioapic_enum_register, 0);
2485 mptable_pci_int_dump(void)
2487 const struct mptable_pci_int *pci_int;
2489 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2490 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
2493 pci_int->mpci_pin + 'A',
2494 pci_int->mpci_ioapic_idx,
2495 pci_int->mpci_ioapic_pin);
2500 mptable_pci_int_route(int bus, int dev, int pin, int intline)
2502 const struct mptable_pci_int *pci_int;
2506 --pin; /* zero based */
2508 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2509 if (pci_int->mpci_bus == bus &&
2510 pci_int->mpci_dev == dev &&
2511 pci_int->mpci_pin == pin)
2514 if (pci_int != NULL) {
2517 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
2518 pci_int->mpci_ioapic_pin);
2520 irq = ioapic_abi_find_gsi(gsi,
2521 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2527 kprintf("MPTABLE: fixed interrupt routing "
2528 "for %d:%d INT%c\n", bus, dev, pin + 'A');
2531 irq = ioapic_abi_find_irq(intline,
2532 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2535 if (irq >= 0 && bootverbose) {
2536 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
2537 bus, dev, pin + 'A', irq);