2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/mpapic.h>
61 #include <machine/psl.h>
62 #include <machine/segments.h>
63 #include <machine/tss.h>
64 #include <machine/specialreg.h>
65 #include <machine/globaldata.h>
66 #include <machine/pmap_inval.h>
68 #include <machine/md_var.h> /* setidt() */
69 #include <machine_base/icu/icu.h> /* IPIs */
70 #include <machine/intr_machdep.h> /* IPIs */
72 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
74 #define WARMBOOT_TARGET 0
75 #define WARMBOOT_OFF (KERNBASE + 0x0467)
76 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78 #define BIOS_BASE (0xf0000)
79 #define BIOS_BASE2 (0xe0000)
80 #define BIOS_SIZE (0x10000)
81 #define BIOS_COUNT (BIOS_SIZE/4)
83 #define CMOS_REG (0x70)
84 #define CMOS_DATA (0x71)
85 #define BIOS_RESET (0x0f)
86 #define BIOS_WARM (0x0a)
88 #define PROCENTRY_FLAG_EN 0x01
89 #define PROCENTRY_FLAG_BP 0x02
90 #define IOAPICENTRY_FLAG_EN 0x01
93 /* MP Floating Pointer Structure */
94 typedef struct MPFPS {
107 /* MP Configuration Table Header */
108 typedef struct MPCTH {
110 u_short base_table_length;
114 u_char product_id[12];
115 void *oem_table_pointer;
116 u_short oem_table_size;
119 u_short extended_table_length;
120 u_char extended_table_checksum;
125 typedef struct PROCENTRY {
130 u_long cpu_signature;
131 u_long feature_flags;
136 typedef struct BUSENTRY {
142 typedef struct IOAPICENTRY {
148 } *io_apic_entry_ptr;
150 typedef struct INTENTRY {
160 /* descriptions of MP basetable entries */
161 typedef struct BASETABLE_ENTRY {
170 vm_size_t mp_cth_mapsz;
173 #define MPTABLE_POS_USE_DEFAULT(mpt) \
174 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
178 int mb_type; /* MPTABLE_BUS_ */
179 TAILQ_ENTRY(mptable_bus) mb_link;
182 #define MPTABLE_BUS_ISA 0
183 #define MPTABLE_BUS_PCI 1
185 struct mptable_bus_info {
186 TAILQ_HEAD(, mptable_bus) mbi_list;
189 struct mptable_pci_int {
196 TAILQ_ENTRY(mptable_pci_int) mpci_link;
199 struct mptable_ioapic {
205 TAILQ_ENTRY(mptable_ioapic) mio_link;
208 typedef int (*mptable_iter_func)(void *, const void *, int);
211 * this code MUST be enabled here and in mpboot.s.
212 * it follows the very early stages of AP boot by placing values in CMOS ram.
213 * it NORMALLY will never be needed and thus the primitive method for enabling.
216 #if defined(CHECK_POINTS)
217 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
218 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
220 #define CHECK_INIT(D); \
221 CHECK_WRITE(0x34, (D)); \
222 CHECK_WRITE(0x35, (D)); \
223 CHECK_WRITE(0x36, (D)); \
224 CHECK_WRITE(0x37, (D)); \
225 CHECK_WRITE(0x38, (D)); \
226 CHECK_WRITE(0x39, (D));
228 #define CHECK_PRINT(S); \
229 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
238 #else /* CHECK_POINTS */
240 #define CHECK_INIT(D)
241 #define CHECK_PRINT(S)
243 #endif /* CHECK_POINTS */
246 * Values to send to the POST hardware.
248 #define MP_BOOTADDRESS_POST 0x10
249 #define MP_PROBE_POST 0x11
250 #define MPTABLE_PASS1_POST 0x12
252 #define MP_START_POST 0x13
253 #define MP_ENABLE_POST 0x14
254 #define MPTABLE_PASS2_POST 0x15
256 #define START_ALL_APS_POST 0x16
257 #define INSTALL_AP_TRAMP_POST 0x17
258 #define START_AP_POST 0x18
260 #define MP_ANNOUNCE_POST 0x19
262 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
263 int current_postcode;
265 /** XXX FIXME: what system files declare these??? */
266 extern struct region_descriptor r_gdt, r_idt;
268 int mp_naps; /* # of Applications processors */
269 #ifdef SMP /* APIC-IO */
270 static int mp_nbusses; /* # of busses */
271 int mp_napics; /* # of IO APICs */
272 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
273 u_int32_t *io_apic_versions;
277 u_int32_t cpu_apic_versions[MAXCPU];
279 extern int64_t tsc_offsets[];
281 extern u_long ebda_addr;
283 #ifdef SMP /* APIC-IO */
284 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
288 * APIC ID logical/physical mapping structures.
289 * We oversize these to simplify boot-time config.
291 int cpu_num_to_apic_id[NAPICID];
292 #ifdef SMP /* APIC-IO */
293 int io_num_to_apic_id[NAPICID];
295 int apic_id_to_logical[NAPICID];
297 /* AP uses this during bootstrap. Do not staticize. */
301 /* Hotwire a 0->4MB V==P mapping */
302 extern pt_entry_t *KPTphys;
305 * SMP page table page. Setup by locore to point to a page table
306 * page from which we allocate per-cpu privatespace areas io_apics,
310 #define IO_MAPPING_START_INDEX \
311 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
313 extern pt_entry_t *SMPpt;
314 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
316 struct pcb stoppcbs[MAXCPU];
318 static basetable_entry basetable_entry_types[] =
320 {0, 20, "Processor"},
328 * Local data and functions.
331 static u_int boot_address;
332 static u_int base_memory;
333 static int mp_finish;
334 static int mp_finish_lapic;
336 static void mp_enable(u_int boot_addr);
338 static int mptable_iterate_entries(const mpcth_t,
339 mptable_iter_func, void *);
340 static int mptable_search(void);
341 static int mptable_search_sig(u_int32_t target, int count);
342 static int mptable_hyperthread_fixup(cpumask_t, int);
343 static int mptable_map(struct mptable_pos *);
344 static void mptable_unmap(struct mptable_pos *);
345 static void mptable_bus_info_alloc(const mpcth_t,
346 struct mptable_bus_info *);
347 static void mptable_bus_info_free(struct mptable_bus_info *);
349 static int mptable_lapic_probe(struct lapic_enumerator *);
350 static void mptable_lapic_enumerate(struct lapic_enumerator *);
351 static void mptable_lapic_default(void);
353 static int mptable_ioapic_probe(struct ioapic_enumerator *);
354 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
356 #ifdef SMP /* APIC-IO */
357 static int apic_int_is_bus_type(int intr, int bus_type);
359 static int start_all_aps(u_int boot_addr);
360 static void install_ap_tramp(u_int boot_addr);
361 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
362 static int smitest(void);
364 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
365 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
366 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
367 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
371 static vm_paddr_t mptable_fps_phyaddr;
372 static int mptable_use_default;
373 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
374 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
375 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
376 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
379 * Calculate usable address in base memory for AP trampoline code.
382 mp_bootaddress(u_int basemem)
384 POSTCODE(MP_BOOTADDRESS_POST);
386 base_memory = basemem;
388 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
389 if ((base_memory - boot_address) < bootMP_size)
390 boot_address -= 4096; /* not enough, lower by 4k */
399 struct mptable_pos mpt;
402 KKASSERT(mptable_fps_phyaddr == 0);
404 mptable_fps_phyaddr = mptable_search();
405 if (mptable_fps_phyaddr == 0)
408 error = mptable_map(&mpt);
410 mptable_fps_phyaddr = 0;
414 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
415 kprintf("MPTABLE: use default configuration\n");
416 mptable_use_default = 1;
418 if (mpt.mp_fps->mpfb2 & 0x80)
423 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
426 * Look for an Intel MP spec table (ie, SMP capable hardware).
435 * Make sure our SMPpt[] page table is big enough to hold all the
438 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
440 POSTCODE(MP_PROBE_POST);
442 /* see if EBDA exists */
443 if (ebda_addr != 0) {
444 /* search first 1K of EBDA */
445 target = (u_int32_t)ebda_addr;
446 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
449 /* last 1K of base memory, effective 'top of base' passed in */
450 target = (u_int32_t)(base_memory - 0x400);
451 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
455 /* search the BIOS */
456 target = (u_int32_t)BIOS_BASE;
457 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
460 /* search the extended BIOS */
461 target = (u_int32_t)BIOS_BASE2;
462 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
470 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
472 int count, total_size;
473 const void *position;
475 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
476 total_size = cth->base_table_length - sizeof(struct MPCTH);
477 position = (const uint8_t *)cth + sizeof(struct MPCTH);
478 count = cth->entry_count;
483 KKASSERT(total_size >= 0);
484 if (total_size == 0) {
485 kprintf("invalid base MP table, "
486 "entry count and length mismatch\n");
490 type = *(const uint8_t *)position;
492 case 0: /* processor_entry */
493 case 1: /* bus_entry */
494 case 2: /* io_apic_entry */
495 case 3: /* int_entry */
496 case 4: /* int_entry */
499 kprintf("unknown base MP table entry type %d\n", type);
503 if (total_size < basetable_entry_types[type].length) {
504 kprintf("invalid base MP table length, "
505 "does not contain all entries\n");
508 total_size -= basetable_entry_types[type].length;
510 error = func(arg, position, type);
514 position = (const uint8_t *)position +
515 basetable_entry_types[type].length;
522 * Startup the SMP processors.
527 POSTCODE(MP_START_POST);
528 mp_enable(boot_address);
533 * Print various information about the SMP system hardware and setup.
540 POSTCODE(MP_ANNOUNCE_POST);
542 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
543 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
544 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
545 for (x = 1; x <= mp_naps; ++x) {
546 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
547 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
551 kprintf(" Warning: APIC I/O disabled\n");
555 * AP cpu's call this to sync up protected mode.
557 * WARNING! We must ensure that the cpu is sufficiently initialized to
558 * be able to use to the FP for our optimized bzero/bcopy code before
559 * we enter more mainstream C code.
561 * WARNING! %fs is not set up on entry. This routine sets up %fs.
567 int x, myid = bootAP;
569 struct mdglobaldata *md;
570 struct privatespace *ps;
572 ps = &CPU_prvspace[myid];
574 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
575 gdt_segs[GPROC0_SEL].ssd_base =
576 (int) &ps->mdglobaldata.gd_common_tss;
577 ps->mdglobaldata.mi.gd_prvspace = ps;
579 for (x = 0; x < NGDT; x++) {
580 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
583 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
584 r_gdt.rd_base = (int) &gdt[myid * NGDT];
585 lgdt(&r_gdt); /* does magic intra-segment return */
590 mdcpu->gd_currentldt = _default_ldt;
592 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
593 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
595 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
597 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
598 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
599 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
600 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
601 md->gd_common_tssd = *md->gd_tss_gdt;
605 * Set to a known state:
606 * Set by mpboot.s: CR0_PG, CR0_PE
607 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
610 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
612 pmap_set_opt(); /* PSE/4MB pages, etc */
614 /* set up CPU registers and state */
617 /* set up FPU state on the AP */
618 npxinit(__INITIAL_NPXCW__);
620 /* set up SSE registers */
624 /*******************************************************************
625 * local functions and data
629 * start the SMP system
632 mp_enable(u_int boot_addr)
634 POSTCODE(MP_ENABLE_POST);
638 /* Initialize BSP's local APIC */
641 /* start each Application Processor */
642 start_all_aps(boot_addr);
648 MachIntrABI.finalize();
653 * look for the MP spec signature
656 /* string defined by the Intel MP Spec as identifying the MP table */
657 #define MP_SIG 0x5f504d5f /* _MP_ */
658 #define NEXT(X) ((X) += 4)
660 mptable_search_sig(u_int32_t target, int count)
666 KKASSERT(target != 0);
668 map_size = count * sizeof(u_int32_t);
669 addr = pmap_mapdev((vm_paddr_t)target, map_size);
672 for (x = 0; x < count; NEXT(x)) {
673 if (addr[x] == MP_SIG) {
674 /* make array index a byte index */
675 ret = target + (x * sizeof(u_int32_t));
680 pmap_unmapdev((vm_offset_t)addr, map_size);
685 typedef struct BUSDATA {
687 enum busTypes bus_type;
690 typedef struct INTDATA {
700 typedef struct BUSTYPENAME {
706 static bus_datum *bus_data;
708 /* the IO INT data, one entry per possible APIC INTerrupt */
709 static io_int *io_apic_ints;
712 static int processor_entry (const struct PROCENTRY *entry, int cpu);
715 * Check if we should perform a hyperthreading "fix-up" to
716 * enumerate any logical CPU's that aren't already listed
719 * XXX: We assume that all of the physical CPUs in the
720 * system have the same number of logical CPUs.
722 * XXX: We assume that APIC ID's are allocated such that
723 * the APIC ID's for a physical processor are aligned
724 * with the number of logical CPU's in the processor.
727 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
729 int i, id, lcpus_max, logical_cpus;
731 if ((cpu_feature & CPUID_HTT) == 0)
734 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
738 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
740 * INSTRUCTION SET REFERENCE, A-M (#253666)
741 * Page 3-181, Table 3-20
742 * "The nearest power-of-2 integer that is not smaller
743 * than EBX[23:16] is the number of unique initial APIC
744 * IDs reserved for addressing different logical
745 * processors in a physical package."
748 if ((1 << i) >= lcpus_max) {
755 KKASSERT(cpu_count != 0);
756 if (cpu_count == lcpus_max) {
757 /* We have nothing to fix */
759 } else if (cpu_count == 1) {
760 /* XXX this may be incorrect */
761 logical_cpus = lcpus_max;
766 * Calculate the distances between two nearest
767 * APIC IDs. If all such distances are same,
768 * then it is the number of missing cpus that
769 * we are going to fill later.
771 dist = cur = prev = -1;
772 for (id = 0; id < MAXCPU; ++id) {
773 if ((id_mask & CPUMASK(id)) == 0)
778 int new_dist = cur - prev;
784 * Make sure that all distances
785 * between two nearest APIC IDs
788 if (dist != new_dist)
796 /* Must be power of 2 */
797 if (dist & (dist - 1))
800 /* Can't exceed CPU package capacity */
801 if (dist > lcpus_max)
802 logical_cpus = lcpus_max;
808 * For each APIC ID of a CPU that is set in the mask,
809 * scan the other candidate APIC ID's for this
810 * physical processor. If any of those ID's are
811 * already in the table, then kill the fixup.
813 for (id = 0; id < MAXCPU; id++) {
814 if ((id_mask & CPUMASK(id)) == 0)
816 /* First, make sure we are on a logical_cpus boundary. */
817 if (id % logical_cpus != 0)
819 for (i = id + 1; i < id + logical_cpus; i++)
820 if ((id_mask & CPUMASK(i)) != 0)
827 mptable_map(struct mptable_pos *mpt)
831 vm_size_t cth_mapsz = 0;
833 KKASSERT(mptable_fps_phyaddr != 0);
835 bzero(mpt, sizeof(*mpt));
837 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
840 * Map configuration table header to get
841 * the base table size
843 cth = pmap_mapdev(fps->pap, sizeof(*cth));
844 cth_mapsz = cth->base_table_length;
845 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
847 if (cth_mapsz < sizeof(*cth)) {
848 kprintf("invalid base MP table length %d\n",
850 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
857 cth = pmap_mapdev(fps->pap, cth_mapsz);
862 mpt->mp_cth_mapsz = cth_mapsz;
868 mptable_unmap(struct mptable_pos *mpt)
870 if (mpt->mp_cth != NULL) {
871 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
873 mpt->mp_cth_mapsz = 0;
875 if (mpt->mp_fps != NULL) {
876 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
882 assign_apic_irq(int apic, int intpin, int irq)
886 if (int_to_apicintpin[irq].ioapic != -1)
887 panic("assign_apic_irq: inconsistent table");
889 int_to_apicintpin[irq].ioapic = apic;
890 int_to_apicintpin[irq].int_pin = intpin;
891 int_to_apicintpin[irq].apic_address = ioapic[apic];
892 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
894 for (x = 0; x < nintrs; x++) {
895 if ((io_apic_ints[x].int_type == 0 ||
896 io_apic_ints[x].int_type == 3) &&
897 io_apic_ints[x].int_vector == 0xff &&
898 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
899 io_apic_ints[x].dst_apic_int == intpin)
900 io_apic_ints[x].int_vector = irq;
905 revoke_apic_irq(int irq)
911 if (int_to_apicintpin[irq].ioapic == -1)
912 panic("revoke_apic_irq: inconsistent table");
914 oldapic = int_to_apicintpin[irq].ioapic;
915 oldintpin = int_to_apicintpin[irq].int_pin;
917 int_to_apicintpin[irq].ioapic = -1;
918 int_to_apicintpin[irq].int_pin = 0;
919 int_to_apicintpin[irq].apic_address = NULL;
920 int_to_apicintpin[irq].redirindex = 0;
922 for (x = 0; x < nintrs; x++) {
923 if ((io_apic_ints[x].int_type == 0 ||
924 io_apic_ints[x].int_type == 3) &&
925 io_apic_ints[x].int_vector != 0xff &&
926 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
927 io_apic_ints[x].dst_apic_int == oldintpin)
928 io_apic_ints[x].int_vector = 0xff;
933 mp_set_cpuids(int cpu_id, int apic_id)
935 CPU_TO_ID(cpu_id) = apic_id;
936 ID_TO_CPU(apic_id) = cpu_id;
938 if (apic_id > lapic_id_max)
939 lapic_id_max = apic_id;
943 processor_entry(const struct PROCENTRY *entry, int cpu)
947 /* check for usability */
948 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
951 /* check for BSP flag */
952 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
953 mp_set_cpuids(0, entry->apic_id);
954 return 0; /* its already been counted */
957 /* add another AP to list, if less than max number of CPUs */
958 else if (cpu < MAXCPU) {
959 mp_set_cpuids(cpu, entry->apic_id);
967 apic_int_is_bus_type(int intr, int bus_type)
971 for (bus = 0; bus < mp_nbusses; ++bus)
972 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
973 && ((int) bus_data[bus].bus_type == bus_type))
980 * Given a traditional ISA INT mask, return an APIC mask.
983 isa_apic_mask(u_int isa_mask)
988 #if defined(SKIP_IRQ15_REDIRECT)
989 if (isa_mask == (1 << 15)) {
990 kprintf("skipping ISA IRQ15 redirect\n");
993 #endif /* SKIP_IRQ15_REDIRECT */
995 isa_irq = ffs(isa_mask); /* find its bit position */
996 if (isa_irq == 0) /* doesn't exist */
998 --isa_irq; /* make it zero based */
1000 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1004 return (1 << apic_pin); /* convert pin# to a mask */
1008 * Determine which APIC pin an ISA/EISA INT is attached to.
1010 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1011 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1012 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1013 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1015 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1017 isa_apic_irq(int isa_irq)
1021 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1022 if (INTTYPE(intr) == 0) { /* standard INT */
1023 if (SRCBUSIRQ(intr) == isa_irq) {
1024 if (apic_int_is_bus_type(intr, ISA) ||
1025 apic_int_is_bus_type(intr, EISA)) {
1026 if (INTIRQ(intr) == 0xff)
1027 return -1; /* unassigned */
1028 return INTIRQ(intr); /* found */
1033 return -1; /* NOT found */
1038 * Determine which APIC pin a PCI INT is attached to.
1040 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1041 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1042 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1044 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1048 --pciInt; /* zero based */
1050 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1051 if ((INTTYPE(intr) == 0) /* standard INT */
1052 && (SRCBUSID(intr) == pciBus)
1053 && (SRCBUSDEVICE(intr) == pciDevice)
1054 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1055 if (apic_int_is_bus_type(intr, PCI)) {
1056 if (INTIRQ(intr) == 0xff) {
1057 kprintf("IOAPIC: pci_apic_irq() "
1059 return -1; /* unassigned */
1061 return INTIRQ(intr); /* exact match */
1066 return -1; /* NOT found */
1070 next_apic_irq(int irq)
1077 for (intr = 0; intr < nintrs; intr++) {
1078 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1080 bus = SRCBUSID(intr);
1081 bustype = apic_bus_type(bus);
1082 if (bustype != ISA &&
1088 if (intr >= nintrs) {
1091 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1092 if (INTTYPE(ointr) != 0)
1094 if (bus != SRCBUSID(ointr))
1096 if (bustype == PCI) {
1097 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1099 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1102 if (bustype == ISA || bustype == EISA) {
1103 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1106 if (INTPIN(intr) == INTPIN(ointr))
1110 if (ointr >= nintrs) {
1113 return INTIRQ(ointr);
1126 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1129 * Exactly what this means is unclear at this point. It is a solution
1130 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1131 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1132 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1136 undirect_isa_irq(int rirq)
1140 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1141 /** FIXME: tickle the MB redirector chip */
1145 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1152 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1155 undirect_pci_irq(int rirq)
1159 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1161 /** FIXME: tickle the MB redirector chip */
1165 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1173 * given a bus ID, return:
1174 * the bus type if found
1178 apic_bus_type(int id)
1182 for (x = 0; x < mp_nbusses; ++x)
1183 if (bus_data[x].bus_id == id)
1184 return bus_data[x].bus_type;
1190 * given a LOGICAL APIC# and pin#, return:
1191 * the associated src bus ID if found
1195 apic_src_bus_id(int apic, int pin)
1199 /* search each of the possible INTerrupt sources */
1200 for (x = 0; x < nintrs; ++x)
1201 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1202 (pin == io_apic_ints[x].dst_apic_int))
1203 return (io_apic_ints[x].src_bus_id);
1205 return -1; /* NOT found */
1209 * given a LOGICAL APIC# and pin#, return:
1210 * the associated src bus IRQ if found
1214 apic_src_bus_irq(int apic, int pin)
1218 for (x = 0; x < nintrs; x++)
1219 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1220 (pin == io_apic_ints[x].dst_apic_int))
1221 return (io_apic_ints[x].src_bus_irq);
1223 return -1; /* NOT found */
1228 * given a LOGICAL APIC# and pin#, return:
1229 * the associated INTerrupt type if found
1233 apic_int_type(int apic, int pin)
1237 /* search each of the possible INTerrupt sources */
1238 for (x = 0; x < nintrs; ++x) {
1239 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1240 (pin == io_apic_ints[x].dst_apic_int))
1241 return (io_apic_ints[x].int_type);
1243 return -1; /* NOT found */
1247 * Return the IRQ associated with an APIC pin
1250 apic_irq(int apic, int pin)
1255 for (x = 0; x < nintrs; ++x) {
1256 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1257 (pin == io_apic_ints[x].dst_apic_int)) {
1258 res = io_apic_ints[x].int_vector;
1261 if (apic != int_to_apicintpin[res].ioapic)
1262 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1263 if (pin != int_to_apicintpin[res].int_pin)
1264 panic("apic_irq inconsistent table (2)");
1273 * given a LOGICAL APIC# and pin#, return:
1274 * the associated trigger mode if found
1278 apic_trigger(int apic, int pin)
1282 /* search each of the possible INTerrupt sources */
1283 for (x = 0; x < nintrs; ++x)
1284 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1285 (pin == io_apic_ints[x].dst_apic_int))
1286 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1288 return -1; /* NOT found */
1293 * given a LOGICAL APIC# and pin#, return:
1294 * the associated 'active' level if found
1298 apic_polarity(int apic, int pin)
1302 /* search each of the possible INTerrupt sources */
1303 for (x = 0; x < nintrs; ++x)
1304 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1305 (pin == io_apic_ints[x].dst_apic_int))
1306 return (io_apic_ints[x].int_flags & 0x03);
1308 return -1; /* NOT found */
1312 * Map a physical memory address representing I/O into KVA. The I/O
1313 * block is assumed not to cross a page boundary.
1316 ioapic_map(vm_paddr_t pa)
1322 KKASSERT(pa < 0x100000000LL);
1324 pgeflag = 0; /* not used for SMP yet */
1327 * If the requested physical address has already been incidently
1328 * mapped, just use the existing mapping. Otherwise create a new
1331 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
1332 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
1333 ((vm_offset_t)pa & PG_FRAME)) {
1337 if (i == SMPpt_alloc_index) {
1338 if (i == NPTEPG - 2) {
1339 panic("permanent_io_mapping: We ran out of space"
1342 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
1343 ((vm_offset_t)pa & PG_FRAME));
1344 ++SMPpt_alloc_index;
1346 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
1347 ((vm_offset_t)pa & PAGE_MASK);
1348 return ((void *)vaddr);
1352 * start each AP in our list
1355 start_all_aps(u_int boot_addr)
1362 u_char mpbiosreason;
1363 u_long mpbioswarmvec;
1364 struct mdglobaldata *gd;
1365 struct privatespace *ps;
1369 POSTCODE(START_ALL_APS_POST);
1371 /* install the AP 1st level boot code */
1372 install_ap_tramp(boot_addr);
1375 /* save the current value of the warm-start vector */
1376 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
1377 outb(CMOS_REG, BIOS_RESET);
1378 mpbiosreason = inb(CMOS_DATA);
1380 /* setup a vector to our boot code */
1381 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1382 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1383 outb(CMOS_REG, BIOS_RESET);
1384 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1387 * If we have a TSC we can figure out the SMI interrupt rate.
1388 * The SMI does not necessarily use a constant rate. Spend
1389 * up to 250ms trying to figure it out.
1392 if (cpu_feature & CPUID_TSC) {
1393 set_apic_timer(275000);
1394 smilast = read_apic_timer();
1395 for (x = 0; x < 20 && read_apic_timer(); ++x) {
1396 smicount = smitest();
1397 if (smibest == 0 || smilast - smicount < smibest)
1398 smibest = smilast - smicount;
1401 if (smibest > 250000)
1404 smibest = smibest * (int64_t)1000000 /
1405 get_apic_timer_frequency();
1409 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
1410 1000000 / smibest, smibest);
1413 /* set up temporary P==V mapping for AP boot */
1414 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
1415 kptbase = (uintptr_t)(void *)KPTphys;
1416 for (x = 0; x < NKPT; x++) {
1417 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
1418 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
1423 for (x = 1; x <= mp_naps; ++x) {
1425 /* This is a bit verbose, it will go away soon. */
1427 /* first page of AP's private space */
1428 pg = x * i386_btop(sizeof(struct privatespace));
1430 /* allocate new private data page(s) */
1431 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
1432 MDGLOBALDATA_BASEALLOC_SIZE);
1433 /* wire it into the private page table page */
1434 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
1435 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
1436 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
1438 pg += MDGLOBALDATA_BASEALLOC_PAGES;
1440 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
1441 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
1442 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
1443 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
1445 /* allocate and set up an idle stack data page */
1446 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
1447 for (i = 0; i < UPAGES; i++) {
1448 SMPpt[pg + 4 + i] = (pt_entry_t)
1449 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
1452 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
1453 bzero(gd, sizeof(*gd));
1454 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
1456 /* prime data page for it to use */
1457 mi_gdinit(&gd->mi, x);
1459 gd->gd_CMAP1 = &SMPpt[pg + 0];
1460 gd->gd_CMAP2 = &SMPpt[pg + 1];
1461 gd->gd_CMAP3 = &SMPpt[pg + 2];
1462 gd->gd_PMAP1 = &SMPpt[pg + 3];
1463 gd->gd_CADDR1 = ps->CPAGE1;
1464 gd->gd_CADDR2 = ps->CPAGE2;
1465 gd->gd_CADDR3 = ps->CPAGE3;
1466 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
1469 * Per-cpu pmap for get_ptbase().
1471 gd->gd_GDADDR1= (unsigned *)
1472 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
1473 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
1475 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
1476 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
1479 * Setup the AP boot stack
1481 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
1484 /* attempt to start the Application Processor */
1485 CHECK_INIT(99); /* setup checkpoints */
1486 if (!start_ap(gd, boot_addr, smibest)) {
1487 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1488 CHECK_PRINT("trace"); /* show checkpoints */
1489 /* better panic as the AP may be running loose */
1490 kprintf("panic y/n? [y] ");
1491 if (cngetc() != 'n')
1494 CHECK_PRINT("trace"); /* show checkpoints */
1496 /* record its version info */
1497 cpu_apic_versions[x] = cpu_apic_versions[0];
1500 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
1503 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
1504 for (shift = 0; (1 << shift) <= ncpus; ++shift)
1507 ncpus2_shift = shift;
1508 ncpus2 = 1 << shift;
1509 ncpus2_mask = ncpus2 - 1;
1511 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
1512 if ((1 << shift) < ncpus)
1514 ncpus_fit = 1 << shift;
1515 ncpus_fit_mask = ncpus_fit - 1;
1517 /* build our map of 'other' CPUs */
1518 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1519 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1520 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1522 /* fill in our (BSP) APIC version */
1523 cpu_apic_versions[0] = lapic.version;
1525 /* restore the warmstart vector */
1526 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1527 outb(CMOS_REG, BIOS_RESET);
1528 outb(CMOS_DATA, mpbiosreason);
1531 * NOTE! The idlestack for the BSP was setup by locore. Finish
1532 * up, clean out the P==V mapping we did earlier.
1534 for (x = 0; x < NKPT; x++)
1539 * Wait all APs to finish initializing LAPIC
1541 mp_finish_lapic = 1;
1543 kprintf("SMP: Waiting APs LAPIC initialization\n");
1544 if (cpu_feature & CPUID_TSC)
1545 tsc0_offset = rdtsc();
1548 while (smp_lapic_mask != smp_startup_mask) {
1550 if (cpu_feature & CPUID_TSC)
1551 tsc0_offset = rdtsc();
1553 while (try_mplock() == 0)
1556 /* number of APs actually started */
1561 * load the 1st level AP boot code into base memory.
1564 /* targets for relocation */
1565 extern void bigJump(void);
1566 extern void bootCodeSeg(void);
1567 extern void bootDataSeg(void);
1568 extern void MPentry(void);
1569 extern u_int MP_GDT;
1570 extern u_int mp_gdtbase;
1573 install_ap_tramp(u_int boot_addr)
1576 int size = *(int *) ((u_long) & bootMP_size);
1577 u_char *src = (u_char *) ((u_long) bootMP);
1578 u_char *dst = (u_char *) boot_addr + KERNBASE;
1579 u_int boot_base = (u_int) bootMP;
1584 POSTCODE(INSTALL_AP_TRAMP_POST);
1586 for (x = 0; x < size; ++x)
1590 * modify addresses in code we just moved to basemem. unfortunately we
1591 * need fairly detailed info about mpboot.s for this to work. changes
1592 * to mpboot.s might require changes here.
1595 /* boot code is located in KERNEL space */
1596 dst = (u_char *) boot_addr + KERNBASE;
1598 /* modify the lgdt arg */
1599 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1600 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1602 /* modify the ljmp target for MPentry() */
1603 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1604 *dst32 = ((u_int) MPentry - KERNBASE);
1606 /* modify the target for boot code segment */
1607 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1608 dst8 = (u_int8_t *) (dst16 + 1);
1609 *dst16 = (u_int) boot_addr & 0xffff;
1610 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1612 /* modify the target for boot data segment */
1613 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1614 dst8 = (u_int8_t *) (dst16 + 1);
1615 *dst16 = (u_int) boot_addr & 0xffff;
1616 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1621 * This function starts the AP (application processor) identified
1622 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1623 * to accomplish this. This is necessary because of the nuances
1624 * of the different hardware we might encounter. It ain't pretty,
1625 * but it seems to work.
1627 * NOTE: eventually an AP gets to ap_init(), which is called just
1628 * before the AP goes into the LWKT scheduler's idle loop.
1631 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
1635 u_long icr_lo, icr_hi;
1637 POSTCODE(START_AP_POST);
1639 /* get the PHYSICAL APIC ID# */
1640 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
1642 /* calculate the vector */
1643 vector = (boot_addr >> 12) & 0xff;
1645 /* We don't want anything interfering */
1648 /* Make sure the target cpu sees everything */
1652 * Try to detect when a SMI has occurred, wait up to 200ms.
1654 * If a SMI occurs during an AP reset but before we issue
1655 * the STARTUP command, the AP may brick. To work around
1656 * this problem we hold off doing the AP startup until
1657 * after we have detected the SMI. Hopefully another SMI
1658 * will not occur before we finish the AP startup.
1660 * Retries don't seem to help. SMIs have a window of opportunity
1661 * and if USB->legacy keyboard emulation is enabled in the BIOS
1662 * the interrupt rate can be quite high.
1664 * NOTE: Don't worry about the L1 cache load, it might bloat
1665 * ldelta a little but ndelta will be so huge when the SMI
1666 * occurs the detection logic will still work fine.
1669 set_apic_timer(200000);
1674 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1675 * and running the target CPU. OR this INIT IPI might be latched (P5
1676 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1679 * see apic/apicreg.h for icr bit definitions.
1681 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
1685 * Setup the address for the target AP. We can setup
1686 * icr_hi once and then just trigger operations with
1689 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1690 icr_hi |= (physical_cpu << 24);
1691 icr_lo = lapic.icr_lo & 0xfff00000;
1692 lapic.icr_hi = icr_hi;
1695 * Do an INIT IPI: assert RESET
1697 * Use edge triggered mode to assert INIT
1699 lapic.icr_lo = icr_lo | 0x0000c500;
1700 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1704 * The spec calls for a 10ms delay but we may have to use a
1705 * MUCH lower delay to avoid bricking an AP due to a fast SMI
1706 * interrupt. We have other loops here too and dividing by 2
1707 * doesn't seem to be enough even after subtracting 350us,
1708 * so we divide by 4.
1710 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
1711 * interrupt was detected we use the full 10ms.
1715 else if (smibest < 150 * 4 + 350)
1717 else if ((smibest - 350) / 4 < 10000)
1718 u_sleep((smibest - 350) / 4);
1723 * Do an INIT IPI: deassert RESET
1725 * Use level triggered mode to deassert. It is unclear
1726 * why we need to do this.
1728 lapic.icr_lo = icr_lo | 0x00008500;
1729 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1731 u_sleep(150); /* wait 150us */
1734 * Next we do a STARTUP IPI: the previous INIT IPI might still be
1735 * latched, (P5 bug) this 1st STARTUP would then terminate
1736 * immediately, and the previously started INIT IPI would continue. OR
1737 * the previous INIT IPI has already run. and this STARTUP IPI will
1738 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1741 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1742 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1744 u_sleep(200); /* wait ~200uS */
1747 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1748 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1749 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1750 * recognized after hardware RESET or INIT IPI.
1752 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1753 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1756 /* Resume normal operation */
1759 /* wait for it to start, see ap_init() */
1760 set_apic_timer(5000000);/* == 5 seconds */
1761 while (read_apic_timer()) {
1762 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
1763 return 1; /* return SUCCESS */
1766 return 0; /* return FAILURE */
1781 while (read_apic_timer()) {
1783 for (count = 0; count < 100; ++count)
1784 ntsc = rdtsc(); /* force loop to occur */
1786 ndelta = ntsc - ltsc;
1787 if (ldelta > ndelta)
1789 if (ndelta > ldelta * 2)
1792 ldelta = ntsc - ltsc;
1795 return(read_apic_timer());
1799 * Lazy flush the TLB on all other CPU's. DEPRECATED.
1801 * If for some reason we were unable to start all cpus we cannot safely
1802 * use broadcast IPIs.
1805 static cpumask_t smp_invltlb_req;
1806 #define SMP_INVLTLB_DEBUG
1812 struct mdglobaldata *md = mdcpu;
1813 #ifdef SMP_INVLTLB_DEBUG
1818 crit_enter_gd(&md->mi);
1819 md->gd_invltlb_ret = 0;
1820 ++md->mi.gd_cnt.v_smpinvltlb;
1821 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1822 #ifdef SMP_INVLTLB_DEBUG
1825 if (smp_startup_mask == smp_active_mask) {
1826 all_but_self_ipi(XINVLTLB_OFFSET);
1828 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
1829 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1832 #ifdef SMP_INVLTLB_DEBUG
1834 kprintf("smp_invltlb: ipi sent\n");
1836 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
1837 (smp_active_mask & ~md->mi.gd_cpumask)) {
1840 #ifdef SMP_INVLTLB_DEBUG
1842 if (++count == 400000000) {
1843 print_backtrace(-1);
1844 kprintf("smp_invltlb: endless loop %08lx %08lx, "
1845 "rflags %016lx retry",
1846 (long)md->gd_invltlb_ret,
1847 (long)smp_invltlb_req,
1848 (long)read_eflags());
1849 __asm __volatile ("sti");
1852 lwkt_process_ipiq();
1854 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
1855 ~md->mi.gd_cpumask &
1858 kprintf("bcpu %d\n", bcpu);
1859 xgd = globaldata_find(bcpu);
1860 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
1869 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1870 crit_exit_gd(&md->mi);
1877 * Called from Xinvltlb assembly with interrupts disabled. We didn't
1878 * bother to bump the critical section count or nested interrupt count
1879 * so only do very low level operations here.
1882 smp_invltlb_intr(void)
1884 struct mdglobaldata *md = mdcpu;
1885 struct mdglobaldata *omd;
1889 mask = smp_invltlb_req;
1893 cpu = BSFCPUMASK(mask);
1894 mask &= ~CPUMASK(cpu);
1895 omd = (struct mdglobaldata *)globaldata_find(cpu);
1896 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
1903 * When called the executing CPU will send an IPI to all other CPUs
1904 * requesting that they halt execution.
1906 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1908 * - Signals all CPUs in map to stop.
1909 * - Waits for each to stop.
1916 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1917 * from executing at same time.
1920 stop_cpus(cpumask_t map)
1922 map &= smp_active_mask;
1924 /* send the Xcpustop IPI to all CPUs in map */
1925 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1927 while ((stopped_cpus & map) != map)
1935 * Called by a CPU to restart stopped CPUs.
1937 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1939 * - Signals all CPUs in map to restart.
1940 * - Waits for each to restart.
1948 restart_cpus(cpumask_t map)
1950 /* signal other cpus to restart */
1951 started_cpus = map & smp_active_mask;
1953 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
1960 * This is called once the mpboot code has gotten us properly relocated
1961 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1962 * and when it returns the scheduler will call the real cpu_idle() main
1963 * loop for the idlethread. Interrupts are disabled on entry and should
1964 * remain disabled at return.
1972 * Adjust smp_startup_mask to signal the BSP that we have started
1973 * up successfully. Note that we do not yet hold the BGL. The BSP
1974 * is waiting for our signal.
1976 * We can't set our bit in smp_active_mask yet because we are holding
1977 * interrupts physically disabled and remote cpus could deadlock
1978 * trying to send us an IPI.
1980 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
1984 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1985 * non-zero, then get the MP lock.
1987 * Note: We are in a critical section.
1989 * Note: we are the idle thread, we can only spin.
1991 * Note: The load fence is memory volatile and prevents the compiler
1992 * from improperly caching mp_finish_lapic, and the cpu from improperly
1995 while (mp_finish_lapic == 0)
1997 while (try_mplock() == 0)
2000 if (cpu_feature & CPUID_TSC) {
2002 * The BSP is constantly updating tsc0_offset, figure out
2003 * the relative difference to synchronize ktrdump.
2005 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2008 /* BSP may have changed PTD while we're waiting for the lock */
2011 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2015 /* Build our map of 'other' CPUs. */
2016 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2018 /* A quick check from sanity claus */
2019 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2020 if (mycpu->gd_cpuid != apic_id) {
2021 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2022 kprintf("SMP: apic_id = %d\n", apic_id);
2023 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2024 panic("cpuid mismatch! boom!!");
2027 /* Initialize AP's local APIC for irq's */
2030 /* LAPIC initialization is done */
2031 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
2034 /* Let BSP move onto the next initialization stage */
2038 * Interlock for finalization. Wait until mp_finish is non-zero,
2039 * then get the MP lock.
2041 * Note: We are in a critical section.
2043 * Note: we are the idle thread, we can only spin.
2045 * Note: The load fence is memory volatile and prevents the compiler
2046 * from improperly caching mp_finish, and the cpu from improperly
2049 while (mp_finish == 0)
2051 while (try_mplock() == 0)
2054 /* BSP may have changed PTD while we're waiting for the lock */
2057 /* Set memory range attributes for this CPU to match the BSP */
2058 mem_range_AP_init();
2061 * Once we go active we must process any IPIQ messages that may
2062 * have been queued, because no actual IPI will occur until we
2063 * set our bit in the smp_active_mask. If we don't the IPI
2064 * message interlock could be left set which would also prevent
2067 * The idle loop doesn't expect the BGL to be held and while
2068 * lwkt_switch() normally cleans things up this is a special case
2069 * because we returning almost directly into the idle loop.
2071 * The idle thread is never placed on the runq, make sure
2072 * nothing we've done put it there.
2074 KKASSERT(get_mplock_count(curthread) == 1);
2075 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2078 * Enable interrupts here. idle_restore will also do it, but
2079 * doing it here lets us clean up any strays that got posted to
2080 * the CPU during the AP boot while we are still in a critical
2083 __asm __volatile("sti; pause; pause"::);
2084 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2086 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2087 lwkt_process_ipiq();
2090 * Releasing the mp lock lets the BSP finish up the SMP init
2093 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2097 * Get SMP fully working before we start initializing devices.
2105 kprintf("Finish MP startup\n");
2107 while (smp_active_mask != smp_startup_mask)
2109 while (try_mplock() == 0)
2112 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2115 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2118 cpu_send_ipiq(int dcpu)
2120 if (CPUMASK(dcpu) & smp_active_mask)
2121 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2124 #if 0 /* single_apic_ipi_passive() not working yet */
2126 * Returns 0 on failure, 1 on success
2129 cpu_send_ipiq_passive(int dcpu)
2132 if (CPUMASK(dcpu) & smp_active_mask) {
2133 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2134 APIC_DELMODE_FIXED);
2141 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2143 struct mptable_bus_info *bus_info = xarg;
2144 const struct BUSENTRY *ent;
2145 struct mptable_bus *bus;
2151 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2152 if (bus->mb_id == ent->bus_id) {
2153 kprintf("mptable_bus_info_alloc: duplicated bus id "
2154 "(%d)\n", bus->mb_id);
2160 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2161 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2162 bus->mb_type = MPTABLE_BUS_PCI;
2163 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2164 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2165 bus->mb_type = MPTABLE_BUS_ISA;
2169 bus->mb_id = ent->bus_id;
2170 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2176 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2180 bzero(bus_info, sizeof(*bus_info));
2181 TAILQ_INIT(&bus_info->mbi_list);
2183 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2185 mptable_bus_info_free(bus_info);
2189 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2191 struct mptable_bus *bus;
2193 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2194 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2199 struct mptable_lapic_cbarg1 {
2202 u_int ht_apicid_mask;
2206 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2208 const struct PROCENTRY *ent;
2209 struct mptable_lapic_cbarg1 *arg = xarg;
2215 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2219 if (ent->apic_id < 32) {
2220 arg->ht_apicid_mask |= 1 << ent->apic_id;
2221 } else if (arg->ht_fixup) {
2222 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2228 struct mptable_lapic_cbarg2 {
2235 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2237 const struct PROCENTRY *ent;
2238 struct mptable_lapic_cbarg2 *arg = xarg;
2244 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2245 KKASSERT(!arg->found_bsp);
2249 if (processor_entry(ent, arg->cpu))
2252 if (arg->logical_cpus) {
2253 struct PROCENTRY proc;
2257 * Create fake mptable processor entries
2258 * and feed them to processor_entry() to
2259 * enumerate the logical CPUs.
2261 bzero(&proc, sizeof(proc));
2263 proc.cpu_flags = PROCENTRY_FLAG_EN;
2264 proc.apic_id = ent->apic_id;
2266 for (i = 1; i < arg->logical_cpus; i++) {
2268 processor_entry(&proc, arg->cpu);
2276 mptable_lapic_default(void)
2278 int ap_apicid, bsp_apicid;
2280 mp_naps = 1; /* exclude BSP */
2282 /* Map local apic before the id field is accessed */
2283 lapic_map(DEFAULT_APIC_BASE);
2285 bsp_apicid = APIC_ID(lapic.id);
2286 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2289 mp_set_cpuids(0, bsp_apicid);
2290 /* one and only AP */
2291 mp_set_cpuids(1, ap_apicid);
2297 * ID_TO_CPU(N), APIC ID to logical CPU table
2298 * CPU_TO_ID(N), logical CPU to APIC ID table
2301 mptable_lapic_enumerate(struct lapic_enumerator *e)
2303 struct mptable_pos mpt;
2304 struct mptable_lapic_cbarg1 arg1;
2305 struct mptable_lapic_cbarg2 arg2;
2307 int error, logical_cpus = 0;
2308 vm_offset_t lapic_addr;
2310 if (mptable_use_default) {
2311 mptable_lapic_default();
2315 error = mptable_map(&mpt);
2317 panic("mptable_lapic_enumerate mptable_map failed\n");
2318 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2322 /* Save local apic address */
2323 lapic_addr = (vm_offset_t)cth->apic_address;
2324 KKASSERT(lapic_addr != 0);
2327 * Find out how many CPUs do we have
2329 bzero(&arg1, sizeof(arg1));
2330 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2332 error = mptable_iterate_entries(cth,
2333 mptable_lapic_pass1_callback, &arg1);
2335 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2336 KKASSERT(arg1.cpu_count != 0);
2338 /* See if we need to fixup HT logical CPUs. */
2339 if (arg1.ht_fixup) {
2340 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
2342 if (logical_cpus != 0)
2343 arg1.cpu_count *= logical_cpus;
2345 mp_naps = arg1.cpu_count;
2347 /* Qualify the numbers again, after possible HT fixup */
2348 if (mp_naps > MAXCPU) {
2349 kprintf("Warning: only using %d of %d available CPUs!\n",
2354 --mp_naps; /* subtract the BSP */
2357 * Link logical CPU id to local apic id
2359 bzero(&arg2, sizeof(arg2));
2361 arg2.logical_cpus = logical_cpus;
2363 error = mptable_iterate_entries(cth,
2364 mptable_lapic_pass2_callback, &arg2);
2366 panic("mptable_iterate_entries(lapic_pass2) failed\n");
2367 KKASSERT(arg2.found_bsp);
2369 /* Map local apic */
2370 lapic_map(lapic_addr);
2372 mptable_unmap(&mpt);
2375 struct mptable_lapic_probe_cbarg {
2381 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
2383 const struct PROCENTRY *ent;
2384 struct mptable_lapic_probe_cbarg *arg = xarg;
2390 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2394 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2395 if (arg->found_bsp) {
2396 kprintf("more than one BSP in base MP table\n");
2405 mptable_lapic_probe(struct lapic_enumerator *e)
2407 struct mptable_pos mpt;
2408 struct mptable_lapic_probe_cbarg arg;
2412 if (mptable_fps_phyaddr == 0)
2415 if (mptable_use_default)
2418 error = mptable_map(&mpt);
2421 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2426 if (cth->apic_address == 0)
2429 bzero(&arg, sizeof(arg));
2430 error = mptable_iterate_entries(cth,
2431 mptable_lapic_probe_callback, &arg);
2433 if (arg.cpu_count == 0) {
2434 kprintf("MP table contains no processor entries\n");
2436 } else if (!arg.found_bsp) {
2437 kprintf("MP table does not contains BSP entry\n");
2442 mptable_unmap(&mpt);
2446 static struct lapic_enumerator mptable_lapic_enumerator = {
2447 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2448 .lapic_probe = mptable_lapic_probe,
2449 .lapic_enumerate = mptable_lapic_enumerate
2453 mptable_lapic_enum_register(void)
2455 lapic_enumerator_register(&mptable_lapic_enumerator);
2457 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2458 mptable_lapic_enum_register, 0);
2461 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
2463 const struct IOAPICENTRY *ent;
2464 struct mptable_ioapic *nioapic, *ioapic;
2470 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
2473 if (ent->apic_address == 0) {
2474 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
2478 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2479 if (ioapic->mio_apic_id == ent->apic_id) {
2480 kprintf("mptable_ioapic_create_list: duplicated "
2481 "apic id %d\n", ioapic->mio_apic_id);
2484 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
2485 kprintf("mptable_ioapic_create_list: overlapped "
2486 "IOAPIC addr 0x%08x", ioapic->mio_addr);
2491 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2492 nioapic->mio_apic_id = ent->apic_id;
2493 nioapic->mio_addr = (uint32_t)ent->apic_address;
2496 * Create IOAPIC list in ascending order of APIC ID
2498 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
2499 mptable_ioapic_list, mio_link) {
2500 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
2501 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
2502 ioapic, nioapic, mio_link);
2507 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
2513 mptable_ioapic_create_list(void)
2515 struct mptable_ioapic *ioapic;
2516 struct mptable_pos mpt;
2519 if (mptable_fps_phyaddr == 0)
2522 if (mptable_use_default) {
2523 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2524 ioapic->mio_idx = 0;
2525 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
2526 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
2528 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
2532 error = mptable_map(&mpt);
2534 panic("mptable_ioapic_create_list: mptable_map failed\n");
2535 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2537 error = mptable_iterate_entries(mpt.mp_cth,
2538 mptable_ioapic_list_callback, NULL);
2540 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
2541 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
2542 kfree(ioapic, M_DEVBUF);
2548 * Assign index number for each IOAPIC
2551 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2552 ioapic->mio_idx = idx;
2556 mptable_unmap(&mpt);
2558 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
2559 mptable_ioapic_create_list, 0);
2562 mptable_pci_int_callback(void *xarg, const void *pos, int type)
2564 const struct mptable_bus_info *bus_info = xarg;
2565 const struct mptable_ioapic *ioapic;
2566 const struct mptable_bus *bus;
2567 struct mptable_pci_int *pci_int;
2568 const struct INTENTRY *ent;
2569 int pci_pin, pci_dev;
2575 if (ent->int_type != 0)
2578 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2579 if (bus->mb_type == MPTABLE_BUS_PCI &&
2580 bus->mb_id == ent->src_bus_id)
2586 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2587 if (ioapic->mio_apic_id == ent->dst_apic_id)
2590 if (ioapic == NULL) {
2591 kprintf("MPTABLE: warning PCI int dst apic id %d "
2592 "does not exist\n", ent->dst_apic_id);
2596 pci_pin = ent->src_bus_irq & 0x3;
2597 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
2599 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2600 if (pci_int->mpci_bus == ent->src_bus_id &&
2601 pci_int->mpci_dev == pci_dev &&
2602 pci_int->mpci_pin == pci_pin) {
2603 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
2604 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
2605 kprintf("MPTABLE: warning duplicated "
2606 "PCI int entry for "
2607 "bus %d, dev %d, pin %d\n",
2613 kprintf("mptable_pci_int_register: "
2614 "conflict PCI int entry for "
2615 "bus %d, dev %d, pin %d, "
2616 "IOAPIC %d.%d -> %d.%d\n",
2620 pci_int->mpci_ioapic_idx,
2621 pci_int->mpci_ioapic_pin,
2629 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
2631 pci_int->mpci_bus = ent->src_bus_id;
2632 pci_int->mpci_dev = pci_dev;
2633 pci_int->mpci_pin = pci_pin;
2634 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
2635 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
2637 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
2643 mptable_pci_int_register(void)
2645 struct mptable_bus_info bus_info;
2646 const struct mptable_bus *bus;
2647 struct mptable_pci_int *pci_int;
2648 struct mptable_pos mpt;
2649 int error, force_pci0, npcibus;
2652 if (mptable_fps_phyaddr == 0)
2655 if (mptable_use_default)
2658 if (TAILQ_EMPTY(&mptable_ioapic_list))
2661 error = mptable_map(&mpt);
2663 panic("mptable_pci_int_register: mptable_map failed\n");
2664 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2668 mptable_bus_info_alloc(cth, &bus_info);
2669 if (TAILQ_EMPTY(&bus_info.mbi_list))
2674 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
2675 if (bus->mb_type == MPTABLE_BUS_PCI)
2679 mptable_bus_info_free(&bus_info);
2681 } else if (npcibus == 1) {
2685 error = mptable_iterate_entries(cth,
2686 mptable_pci_int_callback, &bus_info);
2688 mptable_bus_info_free(&bus_info);
2691 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
2692 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
2693 kfree(pci_int, M_DEVBUF);
2699 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
2700 pci_int->mpci_bus = 0;
2703 mptable_unmap(&mpt);
2705 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2706 mptable_pci_int_register, 0);
2708 struct mptable_ioapic_probe_cbarg {
2709 const struct mptable_bus_info *bus_info;
2713 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
2715 struct mptable_ioapic_probe_cbarg *arg = xarg;
2716 const struct mptable_ioapic *ioapic;
2717 const struct mptable_bus *bus;
2718 const struct INTENTRY *ent;
2724 if (ent->int_type != 0)
2727 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2728 if (bus->mb_type == MPTABLE_BUS_ISA &&
2729 bus->mb_id == ent->src_bus_id)
2735 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2736 if (ioapic->mio_apic_id == ent->dst_apic_id)
2739 if (ioapic == NULL) {
2740 kprintf("MPTABLE: warning ISA int dst apic id %d "
2741 "does not exist\n", ent->dst_apic_id);
2745 /* XXX magic number */
2746 if (ent->src_bus_irq >= 16) {
2747 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
2755 mptable_ioapic_probe(struct ioapic_enumerator *e)
2757 struct mptable_ioapic_probe_cbarg arg;
2758 struct mptable_bus_info bus_info;
2759 struct mptable_pos mpt;
2763 if (mptable_fps_phyaddr == 0)
2766 if (mptable_use_default)
2769 if (TAILQ_EMPTY(&mptable_ioapic_list))
2772 error = mptable_map(&mpt);
2774 panic("mptable_ioapic_probe: mptable_map failed\n");
2775 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2779 mptable_bus_info_alloc(cth, &bus_info);
2781 bzero(&arg, sizeof(arg));
2782 arg.bus_info = &bus_info;
2784 error = mptable_iterate_entries(cth,
2785 mptable_ioapic_probe_callback, &arg);
2787 mptable_bus_info_free(&bus_info);
2788 mptable_unmap(&mpt);
2793 struct mptable_ioapic_int_cbarg {
2794 const struct mptable_bus_info *bus_info;
2799 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
2801 struct mptable_ioapic_int_cbarg *arg = xarg;
2802 const struct mptable_ioapic *ioapic;
2803 const struct mptable_bus *bus;
2804 const struct INTENTRY *ent;
2813 if (ent->int_type != 0)
2816 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2817 if (bus->mb_type == MPTABLE_BUS_ISA &&
2818 bus->mb_id == ent->src_bus_id)
2824 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2825 if (ioapic->mio_apic_id == ent->dst_apic_id)
2828 if (ioapic == NULL) {
2829 kprintf("MPTABLE: warning ISA int dst apic id %d "
2830 "does not exist\n", ent->dst_apic_id);
2834 if (ent->dst_apic_int >= ioapic->mio_npin) {
2835 panic("mptable_ioapic_enumerate: invalid I/O APIC "
2836 "pin %d, should be < %d",
2837 ent->dst_apic_int, ioapic->mio_npin);
2839 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
2841 if (ent->src_bus_irq != gsi) {
2843 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
2844 ent->src_bus_irq, gsi);
2846 ioapic_intsrc(ent->src_bus_irq, gsi,
2847 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2853 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
2855 struct mptable_bus_info bus_info;
2856 struct mptable_ioapic *ioapic;
2857 struct mptable_pos mpt;
2861 KKASSERT(mptable_fps_phyaddr != 0);
2862 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
2864 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2865 const struct mptable_ioapic *prev_ioapic;
2869 addr = ioapic_map(ioapic->mio_addr);
2871 ver = ioapic_read(addr, IOAPIC_VER);
2872 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
2873 >> MAXREDIRSHIFT) + 1;
2875 prev_ioapic = TAILQ_PREV(ioapic,
2876 mptable_ioapic_list, mio_link);
2877 if (prev_ioapic == NULL) {
2878 ioapic->mio_gsi_base = 0;
2880 ioapic->mio_gsi_base =
2881 prev_ioapic->mio_gsi_base +
2882 prev_ioapic->mio_npin;
2884 ioapic_add(addr, ioapic->mio_gsi_base,
2888 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
2889 "apic id %d, idx %d, gsi base %d, npin %d\n",
2891 ioapic->mio_apic_id,
2893 ioapic->mio_gsi_base,
2898 if (mptable_use_default) {
2900 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
2901 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2905 error = mptable_map(&mpt);
2907 panic("mptable_ioapic_probe: mptable_map failed\n");
2908 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2912 mptable_bus_info_alloc(cth, &bus_info);
2914 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
2916 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
2917 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2919 struct mptable_ioapic_int_cbarg arg;
2921 bzero(&arg, sizeof(arg));
2922 arg.bus_info = &bus_info;
2924 error = mptable_iterate_entries(cth,
2925 mptable_ioapic_int_callback, &arg);
2927 panic("mptable_ioapic_int failed\n");
2929 if (arg.ioapic_nint == 0) {
2931 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
2934 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
2935 INTR_POLARITY_HIGH);
2939 mptable_bus_info_free(&bus_info);
2941 mptable_unmap(&mpt);
2944 static struct ioapic_enumerator mptable_ioapic_enumerator = {
2945 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
2946 .ioapic_probe = mptable_ioapic_probe,
2947 .ioapic_enumerate = mptable_ioapic_enumerate
2951 mptable_ioapic_enum_register(void)
2953 ioapic_enumerator_register(&mptable_ioapic_enumerator);
2955 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2956 mptable_ioapic_enum_register, 0);
2959 mptable_pci_int_dump(void)
2961 const struct mptable_pci_int *pci_int;
2963 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2964 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
2967 pci_int->mpci_pin + 'A',
2968 pci_int->mpci_ioapic_idx,
2969 pci_int->mpci_ioapic_pin);
2974 mptable_pci_int_route(int bus, int dev, int pin, int intline)
2976 const struct mptable_pci_int *pci_int;
2980 --pin; /* zero based */
2982 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2983 if (pci_int->mpci_bus == bus &&
2984 pci_int->mpci_dev == dev &&
2985 pci_int->mpci_pin == pin)
2988 if (pci_int != NULL) {
2991 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
2992 pci_int->mpci_ioapic_pin);
2994 irq = ioapic_abi_find_gsi(gsi,
2995 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
3001 kprintf("MPTABLE: fixed interrupt routing "
3002 "for %d:%d INT%c\n", bus, dev, pin + 'A');
3005 irq = ioapic_abi_find_irq(intline,
3006 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
3009 if (irq >= 0 && bootverbose) {
3010 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
3011 bus, dev, pin + 'A', irq);