2 * Copyright (c) 1990 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * This code is derived from software contributed to Berkeley by
7 * William Jolitz and Don Ahn.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
38 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
53 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
58 #include <sys/eventhandler.h>
60 #include <sys/kernel.h>
62 #include <sys/sysctl.h>
64 #include <sys/systimer.h>
65 #include <sys/globaldata.h>
66 #include <sys/thread2.h>
67 #include <sys/systimer.h>
68 #include <sys/machintr.h>
69 #include <sys/interrupt.h>
71 #include <machine/clock.h>
72 #include <machine/cputypes.h>
73 #include <machine/frame.h>
74 #include <machine/ipl.h>
75 #include <machine/limits.h>
76 #include <machine/md_var.h>
77 #include <machine/psl.h>
78 #include <machine/segments.h>
79 #include <machine/smp.h>
80 #include <machine/specialreg.h>
81 #include <machine/intr_machdep.h>
83 #include <machine_base/apic/ioapic.h>
84 #include <machine_base/apic/ioapic_abi.h>
85 #include <machine_base/icu/icu.h>
86 #include <bus/isa/isa.h>
87 #include <bus/isa/rtc.h>
88 #include <machine_base/isa/timerreg.h>
90 static void i8254_restore(void);
91 static void resettodr_on_shutdown(void *arg __unused);
94 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
95 * can use a simple formula for leap years.
97 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
98 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
101 #define TIMER_FREQ 1193182
104 static uint8_t i8254_walltimer_sel;
105 static uint16_t i8254_walltimer_cntr;
107 int adjkerntz; /* local offset from GMT in seconds */
108 int disable_rtc_set; /* disable resettodr() if != 0 */
110 int64_t tsc_frequency;
112 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
114 enum tstate { RELEASED, ACQUIRED };
115 enum tstate timer0_state;
116 enum tstate timer1_state;
117 enum tstate timer2_state;
119 static int beeping = 0;
120 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
121 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
122 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
123 static int rtc_loaded;
125 static int i8254_cputimer_div;
127 static int i8254_nointr;
128 static int i8254_intr_disable = 1;
129 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
131 static struct callout sysbeepstop_ch;
133 static sysclock_t i8254_cputimer_count(void);
134 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
135 static void i8254_cputimer_destruct(struct cputimer *cputimer);
137 static struct cputimer i8254_cputimer = {
138 SLIST_ENTRY_INITIALIZER,
142 i8254_cputimer_count,
143 cputimer_default_fromhz,
144 cputimer_default_fromus,
145 i8254_cputimer_construct,
146 i8254_cputimer_destruct,
151 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
152 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
153 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
155 static struct cputimer_intr i8254_cputimer_intr = {
157 .reload = i8254_intr_reload,
158 .enable = cputimer_intr_default_enable,
159 .config = i8254_intr_config,
160 .restart = cputimer_intr_default_restart,
161 .pmfixup = cputimer_intr_default_pmfixup,
162 .initclock = i8254_intr_initclock,
163 .next = SLIST_ENTRY_INITIALIZER,
165 .type = CPUTIMER_INTR_8254,
166 .prio = CPUTIMER_INTR_PRIO_8254,
167 .caps = CPUTIMER_INTR_CAP_PS
171 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
172 * counting as of this interrupt. We use timer1 in free-running mode (not
173 * generating any interrupts) as our main counter. Each cpu has timeouts
176 * This code is INTR_MPSAFE and may be called without the BGL held.
179 clkintr(void *dummy, void *frame_arg)
181 static sysclock_t sysclock_count; /* NOTE! Must be static */
182 struct globaldata *gd = mycpu;
183 struct globaldata *gscan;
187 * SWSTROBE mode is a one-shot, the timer is no longer running
192 * XXX the dispatcher needs work. right now we call systimer_intr()
193 * directly or via IPI for any cpu with systimers queued, which is
194 * usually *ALL* of them. We need to use the LAPIC timer for this.
196 sysclock_count = sys_cputimer->count();
197 for (n = 0; n < ncpus; ++n) {
198 gscan = globaldata_find(n);
199 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
202 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
205 systimer_intr(&sysclock_count, 0, frame_arg);
215 acquire_timer2(int mode)
217 if (timer2_state != RELEASED)
219 timer2_state = ACQUIRED;
222 * This access to the timer registers is as atomic as possible
223 * because it is a single instruction. We could do better if we
226 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
233 if (timer2_state != ACQUIRED)
235 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
236 timer2_state = RELEASED;
244 DB_SHOW_COMMAND(rtc, rtc)
246 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
247 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
248 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
249 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
254 * Return the current cpu timer count as a 32 bit integer.
258 i8254_cputimer_count(void)
260 static __uint16_t cputimer_last;
265 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
266 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
267 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
268 count = -count; /* -> countup */
269 if (count < cputimer_last) /* rollover */
270 i8254_cputimer.base += 0x00010000;
271 ret = i8254_cputimer.base | count;
272 cputimer_last = count;
278 * This function is called whenever the system timebase changes, allowing
279 * us to calculate what is needed to convert a system timebase tick
280 * into an 8254 tick for the interrupt timer. If we can convert to a
281 * simple shift, multiplication, or division, we do so. Otherwise 64
282 * bit arithmatic is required every time the interrupt timer is reloaded.
285 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
291 * Will a simple divide do the trick?
293 div = (timer->freq + (cti->freq / 2)) / cti->freq;
294 freq = cti->freq * div;
296 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
297 i8254_cputimer_div = div;
299 i8254_cputimer_div = 0;
303 * Reload for the next timeout. It is possible for the reload value
304 * to be 0 or negative, indicating that an immediate timer interrupt
305 * is desired. For now make the minimum 2 ticks.
307 * We may have to convert from the system timebase to the 8254 timebase.
310 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
314 if (i8254_cputimer_div)
315 reload /= i8254_cputimer_div;
317 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
323 if (timer0_running) {
324 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
325 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
326 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
327 if (reload < count) {
328 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
329 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
330 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
335 reload = 0; /* full count */
336 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
337 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
338 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
344 * DELAY(usec) - Spin for the specified number of microseconds.
345 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
346 * but do a thread switch in the loop
348 * Relies on timer 1 counting down from (cputimer_freq / hz)
349 * Note: timer had better have been programmed before this is first used!
352 DODELAY(int n, int doswitch)
354 int delta, prev_tick, tick, ticks_left;
359 static int state = 0;
363 for (n1 = 1; n1 <= 10000000; n1 *= 10)
368 kprintf("DELAY(%d)...", n);
371 * Guard against the timer being uninitialized if we are called
372 * early for console i/o.
374 if (timer0_state == RELEASED)
378 * Read the counter first, so that the rest of the setup overhead is
379 * counted. Then calculate the number of hardware timer ticks
380 * required, rounding up to be sure we delay at least the requested
381 * number of microseconds.
383 prev_tick = sys_cputimer->count();
384 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
390 while (ticks_left > 0) {
391 tick = sys_cputimer->count();
395 delta = tick - prev_tick;
400 if (doswitch && ticks_left > 0)
406 kprintf(" %d calls to getit() at %d usec each\n",
407 getit_calls, (n + 5) / getit_calls);
412 * DELAY() never switches.
421 * Returns non-zero if the specified time period has elapsed. Call
422 * first with last_clock set to 0.
425 CHECKTIMEOUT(TOTALDELAY *tdd)
430 if (tdd->started == 0) {
431 if (timer0_state == RELEASED)
433 tdd->last_clock = sys_cputimer->count();
437 delta = sys_cputimer->count() - tdd->last_clock;
438 us = (u_int64_t)delta * (u_int64_t)1000000 /
439 (u_int64_t)sys_cputimer->freq;
440 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
443 return (tdd->us < 0);
448 * DRIVERSLEEP() does not switch if called with a spinlock held or
449 * from a hard interrupt.
452 DRIVERSLEEP(int usec)
454 globaldata_t gd = mycpu;
456 if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
464 sysbeepstop(void *chan)
466 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
472 sysbeep(int pitch, int period)
474 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
476 if (sysbeep_enable == 0)
479 * Nobody else is using timer2, we do not need the clock lock
481 outb(TIMER_CNTR2, pitch);
482 outb(TIMER_CNTR2, (pitch>>8));
484 /* enable counter2 output to speaker */
485 outb(IO_PPI, inb(IO_PPI) | 3);
487 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
493 * RTC support routines
504 val = inb(IO_RTC + 1);
511 writertc(u_char reg, u_char val)
517 outb(IO_RTC + 1, val);
518 inb(0x84); /* XXX work around wrong order in rtcin() */
525 return(bcd2bin(rtcin(port)));
529 calibrate_clocks(void)
532 u_int count, prev_count, tot_count;
533 int sec, start_sec, timeout;
536 kprintf("Calibrating clock(s) ... ");
537 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
541 /* Read the mc146818A seconds counter. */
543 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
544 sec = rtcin(RTC_SEC);
551 /* Wait for the mC146818A seconds counter to change. */
554 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
555 sec = rtcin(RTC_SEC);
556 if (sec != start_sec)
563 /* Start keeping track of the i8254 counter. */
564 prev_count = sys_cputimer->count();
570 old_tsc = 0; /* shut up gcc */
573 * Wait for the mc146818A seconds counter to change. Read the i8254
574 * counter for each iteration since this is convenient and only
575 * costs a few usec of inaccuracy. The timing of the final reads
576 * of the counters almost matches the timing of the initial reads,
577 * so the main cause of inaccuracy is the varying latency from
578 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
579 * rtcin(RTC_SEC) that returns a changed seconds count. The
580 * maximum inaccuracy from this cause is < 10 usec on 486's.
584 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
585 sec = rtcin(RTC_SEC);
586 count = sys_cputimer->count();
587 tot_count += (int)(count - prev_count);
589 if (sec != start_sec)
596 * Read the cpu cycle counter. The timing considerations are
597 * similar to those for the i8254 clock.
600 tsc_frequency = rdtsc() - old_tsc;
604 kprintf("TSC clock: %llu Hz, ", (long long)tsc_frequency);
605 kprintf("i8254 clock: %u Hz\n", tot_count);
609 kprintf("failed, using default i8254 clock of %u Hz\n",
610 i8254_cputimer.freq);
611 return (i8254_cputimer.freq);
617 timer0_state = ACQUIRED;
622 * Timer0 is our fine-grained variable clock interrupt
624 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
625 outb(TIMER_CNTR0, 2); /* lsb */
626 outb(TIMER_CNTR0, 0); /* msb */
630 cputimer_intr_register(&i8254_cputimer_intr);
631 cputimer_intr_select(&i8254_cputimer_intr, 0);
635 * Timer1 or timer2 is our free-running clock, but only if another
636 * has not been selected.
638 cputimer_register(&i8254_cputimer);
639 cputimer_select(&i8254_cputimer, 0);
643 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
648 * Should we use timer 1 or timer 2 ?
651 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
652 if (which != 1 && which != 2)
657 timer->name = "i8254_timer1";
658 timer->type = CPUTIMER_8254_SEL1;
659 i8254_walltimer_sel = TIMER_SEL1;
660 i8254_walltimer_cntr = TIMER_CNTR1;
661 timer1_state = ACQUIRED;
664 timer->name = "i8254_timer2";
665 timer->type = CPUTIMER_8254_SEL2;
666 i8254_walltimer_sel = TIMER_SEL2;
667 i8254_walltimer_cntr = TIMER_CNTR2;
668 timer2_state = ACQUIRED;
672 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
675 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
676 outb(i8254_walltimer_cntr, 0); /* lsb */
677 outb(i8254_walltimer_cntr, 0); /* msb */
678 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
683 i8254_cputimer_destruct(struct cputimer *timer)
685 switch(timer->type) {
686 case CPUTIMER_8254_SEL1:
687 timer1_state = RELEASED;
689 case CPUTIMER_8254_SEL2:
690 timer2_state = RELEASED;
701 /* Restore all of the RTC's "status" (actually, control) registers. */
702 writertc(RTC_STATUSB, RTCSB_24HR);
703 writertc(RTC_STATUSA, rtc_statusa);
704 writertc(RTC_STATUSB, rtc_statusb);
708 * Restore all the timers.
710 * This function is called to resynchronize our core timekeeping after a
711 * long halt, e.g. from apm_default_resume() and friends. It is also
712 * called if after a BIOS call we have detected munging of the 8254.
713 * It is necessary because cputimer_count() counter's delta may have grown
714 * too large for nanouptime() and friends to handle, or (in the case of 8254
715 * munging) might cause the SYSTIMER code to prematurely trigger.
721 i8254_restore(); /* restore timer_freq and hz */
722 rtc_restore(); /* reenable RTC interrupts */
727 * Initialize 8254 timer 0 early so that it can be used in DELAY().
735 * Can we use the TSC?
737 if (cpu_feature & CPUID_TSC)
743 * Initial RTC state, don't do anything unexpected
745 writertc(RTC_STATUSA, rtc_statusa);
746 writertc(RTC_STATUSB, RTCSB_24HR);
749 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
750 * generate an interrupt, which we will ignore for now.
752 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
753 * (so it counts a full 2^16 and repeats). We will use this timer
757 freq = calibrate_clocks();
758 #ifdef CLK_CALIBRATION_LOOP
761 "Press a key on the console to abort clock calibration\n");
762 while (cncheckc() == -1)
768 * Use the calibrated i8254 frequency if it seems reasonable.
769 * Otherwise use the default, and don't use the calibrated i586
772 delta = freq > i8254_cputimer.freq ?
773 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
774 if (delta < i8254_cputimer.freq / 100) {
775 #ifndef CLK_USE_I8254_CALIBRATION
778 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
779 freq = i8254_cputimer.freq;
783 * Interrupt timer's freq must be adjusted
784 * before we change the cuptimer's frequency.
786 i8254_cputimer_intr.freq = freq;
787 cputimer_set_frequency(&i8254_cputimer, freq);
791 "%d Hz differs from default of %d Hz by more than 1%%\n",
792 freq, i8254_cputimer.freq);
796 #ifndef CLK_USE_TSC_CALIBRATION
797 if (tsc_frequency != 0) {
800 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
804 if (tsc_present && tsc_frequency == 0) {
806 * Calibration of the i586 clock relative to the mc146818A
807 * clock failed. Do a less accurate calibration relative
808 * to the i8254 clock.
810 u_int64_t old_tsc = rdtsc();
813 tsc_frequency = rdtsc() - old_tsc;
814 #ifdef CLK_USE_TSC_CALIBRATION
816 kprintf("TSC clock: %llu Hz (Method B)\n",
822 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
826 * Sync the time of day back to the RTC on shutdown, but only if
827 * we have already loaded it and have not crashed.
830 resettodr_on_shutdown(void *arg __unused)
832 if (rtc_loaded && panicstr == NULL) {
838 * Initialize the time of day register, based on the time base which is, e.g.
842 inittodr(time_t base)
844 unsigned long sec, days;
855 /* Look if we have a RTC present and the time is valid */
856 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
859 /* wait for time update to complete */
860 /* If RTCSA_TUP is zero, we have at least 244us before next update */
862 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
868 #ifdef USE_RTC_CENTURY
869 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
871 year = readrtc(RTC_YEAR) + 1900;
879 month = readrtc(RTC_MONTH);
880 for (m = 1; m < month; m++)
881 days += daysinmonth[m-1];
882 if ((month > 2) && LEAPYEAR(year))
884 days += readrtc(RTC_DAY) - 1;
885 for (y = 1970; y < year; y++)
886 days += DAYSPERYEAR + LEAPYEAR(y);
887 sec = ((( days * 24 +
888 readrtc(RTC_HRS)) * 60 +
889 readrtc(RTC_MIN)) * 60 +
891 /* sec now contains the number of seconds, since Jan 1 1970,
892 in the local time zone */
894 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
896 y = time_second - sec;
897 if (y <= -2 || y >= 2) {
898 /* badly off, adjust it */
908 kprintf("Invalid time in real time clock.\n");
909 kprintf("Check and reset the date immediately!\n");
913 * Write system time back to RTC
930 /* Disable RTC updates and interrupts. */
931 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
933 /* Calculate local time to put in RTC */
935 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
937 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
938 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
939 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
941 /* We have now the days since 01-01-1970 in tm */
942 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
943 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
945 y++, m = DAYSPERYEAR + LEAPYEAR(y))
948 /* Now we have the years in y and the day-of-the-year in tm */
949 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
950 #ifdef USE_RTC_CENTURY
951 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
957 if (m == 1 && LEAPYEAR(y))
964 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
965 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
967 /* Reenable RTC updates and interrupts. */
968 writertc(RTC_STATUSB, rtc_statusb);
973 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
979 * Following code assumes the 8254 is the cpu timer,
980 * so make sure it is.
982 KKASSERT(sys_cputimer == &i8254_cputimer);
983 KKASSERT(cti == &i8254_cputimer_intr);
985 lastcnt = get_interrupt_counter(irq, mycpuid);
988 * Force an 8254 Timer0 interrupt and wait 1/100s for
989 * it to happen, then see if we got it.
991 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
993 i8254_intr_reload(cti, 2);
994 base = sys_cputimer->count();
995 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
998 if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
1004 * Start both clocks running. DragonFly note: the stat clock is no longer
1005 * used. Instead, 8254 based systimers are used for all major clock
1009 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1011 void *clkdesc = NULL;
1012 int irq = 0, mixed_mode = 0, error;
1014 KKASSERT(mycpuid == 0);
1015 callout_init_mp(&sysbeepstop_ch);
1017 if (!selected && i8254_intr_disable)
1021 * The stat interrupt mask is different without the
1022 * statistics clock. Also, don't set the interrupt
1023 * flag which would normally cause the RTC to generate
1026 rtc_statusb = RTCSB_24HR;
1028 /* Finish initializing 8254 timer 0. */
1029 if (ioapic_enable) {
1030 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1031 INTR_POLARITY_HIGH);
1034 error = ioapic_conf_legacy_extint(0);
1036 irq = machintr_legacy_intr_find(0,
1037 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1044 kprintf("IOAPIC: setup mixed mode for "
1045 "irq 0 failed: %d\n", error);
1048 panic("IOAPIC: setup mixed mode for "
1049 "irq 0 failed: %d\n", error);
1054 clkdesc = register_int(irq, clkintr, NULL, "clk",
1056 INTR_EXCL | INTR_CLOCK |
1057 INTR_NOPOLL | INTR_MPSAFE |
1060 register_int(0, clkintr, NULL, "clk", NULL,
1061 INTR_EXCL | INTR_CLOCK |
1062 INTR_NOPOLL | INTR_MPSAFE |
1066 /* Initialize RTC. */
1067 writertc(RTC_STATUSA, rtc_statusa);
1068 writertc(RTC_STATUSB, RTCSB_24HR);
1070 if (ioapic_enable) {
1071 error = i8254_ioapic_trial(irq, cti);
1075 kprintf("IOAPIC: mixed mode for irq %d "
1076 "trial failed: %d\n",
1080 panic("IOAPIC: mixed mode for irq %d "
1081 "trial failed: %d\n", irq, error);
1084 kprintf("IOAPIC: warning 8254 is not connected "
1085 "to the correct pin, try mixed mode\n");
1086 unregister_int(clkdesc, 0);
1087 goto mixed_mode_setup;
1094 i8254_nointr = 1; /* don't try to register again */
1095 cputimer_intr_deregister(cti);
1099 setstatclockrate(int newhz)
1101 if (newhz == RTC_PROFRATE)
1102 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1104 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1105 writertc(RTC_STATUSA, rtc_statusa);
1110 tsc_get_timecount(struct timecounter *tc)
1116 #ifdef KERN_TIMESTAMP
1117 #define KERN_TIMESTAMP_SIZE 16384
1118 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1119 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1120 sizeof(tsc), "LU", "Kernel timestamps");
1126 tsc[i] = (u_int32_t)rdtsc();
1129 if (i >= KERN_TIMESTAMP_SIZE)
1131 tsc[i] = 0; /* mark last entry */
1133 #endif /* KERN_TIMESTAMP */
1140 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1147 if (sys_cputimer == &i8254_cputimer)
1148 count = sys_cputimer->count();
1156 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1157 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1160 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1161 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1163 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1164 0, 0, hw_i8254_timestamp, "A", "");
1166 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1167 &tsc_present, 0, "TSC Available");
1168 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1169 &tsc_frequency, 0, "TSC Frequency");