2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/ioapic_abi.h>
60 #include <machine_base/apic/lapic.h>
61 #include <machine_base/apic/ioapic.h>
62 #include <machine/psl.h>
63 #include <machine/segments.h>
64 #include <machine/tss.h>
65 #include <machine/specialreg.h>
66 #include <machine/globaldata.h>
67 #include <machine/pmap_inval.h>
69 #include <machine/md_var.h> /* setidt() */
70 #include <machine_base/icu/icu.h> /* IPIs */
71 #include <machine/intr_machdep.h> /* IPIs */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
270 u_int32_t cpu_apic_versions[MAXCPU];
272 extern int64_t tsc_offsets[];
274 extern u_long ebda_addr;
276 #ifdef SMP /* APIC-IO */
277 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
281 * APIC ID logical/physical mapping structures.
282 * We oversize these to simplify boot-time config.
284 int cpu_num_to_apic_id[NAPICID];
285 int apic_id_to_logical[NAPICID];
287 /* AP uses this during bootstrap. Do not staticize. */
291 /* Hotwire a 0->4MB V==P mapping */
292 extern pt_entry_t *KPTphys;
295 * SMP page table page. Setup by locore to point to a page table
296 * page from which we allocate per-cpu privatespace areas io_apics,
300 #define IO_MAPPING_START_INDEX \
301 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
303 extern pt_entry_t *SMPpt;
304 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
306 struct pcb stoppcbs[MAXCPU];
308 static basetable_entry basetable_entry_types[] =
310 {0, 20, "Processor"},
318 * Local data and functions.
321 static u_int boot_address;
322 static u_int base_memory;
323 static int mp_finish;
324 static int mp_finish_lapic;
326 static void mp_enable(u_int boot_addr);
328 static int mptable_iterate_entries(const mpcth_t,
329 mptable_iter_func, void *);
330 static int mptable_search(void);
331 static int mptable_search_sig(u_int32_t target, int count);
332 static int mptable_hyperthread_fixup(cpumask_t, int);
333 static int mptable_map(struct mptable_pos *);
334 static void mptable_unmap(struct mptable_pos *);
335 static void mptable_bus_info_alloc(const mpcth_t,
336 struct mptable_bus_info *);
337 static void mptable_bus_info_free(struct mptable_bus_info *);
339 static int mptable_lapic_probe(struct lapic_enumerator *);
340 static void mptable_lapic_enumerate(struct lapic_enumerator *);
341 static void mptable_lapic_default(void);
343 static int mptable_ioapic_probe(struct ioapic_enumerator *);
344 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
346 static int start_all_aps(u_int boot_addr);
347 static void install_ap_tramp(u_int boot_addr);
348 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
349 static int smitest(void);
351 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
352 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
353 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
354 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
358 static vm_paddr_t mptable_fps_phyaddr;
359 static int mptable_use_default;
360 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
361 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
362 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
363 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
366 * Calculate usable address in base memory for AP trampoline code.
369 mp_bootaddress(u_int basemem)
371 POSTCODE(MP_BOOTADDRESS_POST);
373 base_memory = basemem;
375 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
376 if ((base_memory - boot_address) < bootMP_size)
377 boot_address -= 4096; /* not enough, lower by 4k */
386 struct mptable_pos mpt;
389 KKASSERT(mptable_fps_phyaddr == 0);
391 mptable_fps_phyaddr = mptable_search();
392 if (mptable_fps_phyaddr == 0)
395 error = mptable_map(&mpt);
397 mptable_fps_phyaddr = 0;
401 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
402 kprintf("MPTABLE: use default configuration\n");
403 mptable_use_default = 1;
405 if (mpt.mp_fps->mpfb2 & 0x80)
410 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
413 * Look for an Intel MP spec table (ie, SMP capable hardware).
422 * Make sure our SMPpt[] page table is big enough to hold all the
425 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
427 POSTCODE(MP_PROBE_POST);
429 /* see if EBDA exists */
430 if (ebda_addr != 0) {
431 /* search first 1K of EBDA */
432 target = (u_int32_t)ebda_addr;
433 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
436 /* last 1K of base memory, effective 'top of base' passed in */
437 target = (u_int32_t)(base_memory - 0x400);
438 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
442 /* search the BIOS */
443 target = (u_int32_t)BIOS_BASE;
444 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
447 /* search the extended BIOS */
448 target = (u_int32_t)BIOS_BASE2;
449 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
457 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
459 int count, total_size;
460 const void *position;
462 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
463 total_size = cth->base_table_length - sizeof(struct MPCTH);
464 position = (const uint8_t *)cth + sizeof(struct MPCTH);
465 count = cth->entry_count;
470 KKASSERT(total_size >= 0);
471 if (total_size == 0) {
472 kprintf("invalid base MP table, "
473 "entry count and length mismatch\n");
477 type = *(const uint8_t *)position;
479 case 0: /* processor_entry */
480 case 1: /* bus_entry */
481 case 2: /* io_apic_entry */
482 case 3: /* int_entry */
483 case 4: /* int_entry */
486 kprintf("unknown base MP table entry type %d\n", type);
490 if (total_size < basetable_entry_types[type].length) {
491 kprintf("invalid base MP table length, "
492 "does not contain all entries\n");
495 total_size -= basetable_entry_types[type].length;
497 error = func(arg, position, type);
501 position = (const uint8_t *)position +
502 basetable_entry_types[type].length;
509 * Startup the SMP processors.
514 POSTCODE(MP_START_POST);
515 mp_enable(boot_address);
520 * Print various information about the SMP system hardware and setup.
527 POSTCODE(MP_ANNOUNCE_POST);
529 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
530 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
531 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
532 for (x = 1; x <= mp_naps; ++x) {
533 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
534 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
538 kprintf(" Warning: APIC I/O disabled\n");
542 * AP cpu's call this to sync up protected mode.
544 * WARNING! We must ensure that the cpu is sufficiently initialized to
545 * be able to use to the FP for our optimized bzero/bcopy code before
546 * we enter more mainstream C code.
548 * WARNING! %fs is not set up on entry. This routine sets up %fs.
554 int x, myid = bootAP;
556 struct mdglobaldata *md;
557 struct privatespace *ps;
559 ps = &CPU_prvspace[myid];
561 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
562 gdt_segs[GPROC0_SEL].ssd_base =
563 (int) &ps->mdglobaldata.gd_common_tss;
564 ps->mdglobaldata.mi.gd_prvspace = ps;
566 for (x = 0; x < NGDT; x++) {
567 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
570 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
571 r_gdt.rd_base = (int) &gdt[myid * NGDT];
572 lgdt(&r_gdt); /* does magic intra-segment return */
577 mdcpu->gd_currentldt = _default_ldt;
579 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
580 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
582 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
584 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
585 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
586 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
587 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
588 md->gd_common_tssd = *md->gd_tss_gdt;
592 * Set to a known state:
593 * Set by mpboot.s: CR0_PG, CR0_PE
594 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
597 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
599 pmap_set_opt(); /* PSE/4MB pages, etc */
601 /* set up CPU registers and state */
604 /* set up FPU state on the AP */
605 npxinit(__INITIAL_NPXCW__);
607 /* set up SSE registers */
611 /*******************************************************************
612 * local functions and data
616 * start the SMP system
619 mp_enable(u_int boot_addr)
621 POSTCODE(MP_ENABLE_POST);
625 /* Initialize BSP's local APIC */
628 /* start each Application Processor */
629 start_all_aps(boot_addr);
635 MachIntrABI.finalize();
640 * look for the MP spec signature
643 /* string defined by the Intel MP Spec as identifying the MP table */
644 #define MP_SIG 0x5f504d5f /* _MP_ */
645 #define NEXT(X) ((X) += 4)
647 mptable_search_sig(u_int32_t target, int count)
653 KKASSERT(target != 0);
655 map_size = count * sizeof(u_int32_t);
656 addr = pmap_mapdev((vm_paddr_t)target, map_size);
659 for (x = 0; x < count; NEXT(x)) {
660 if (addr[x] == MP_SIG) {
661 /* make array index a byte index */
662 ret = target + (x * sizeof(u_int32_t));
667 pmap_unmapdev((vm_offset_t)addr, map_size);
671 static int processor_entry (const struct PROCENTRY *entry, int cpu);
674 * Check if we should perform a hyperthreading "fix-up" to
675 * enumerate any logical CPU's that aren't already listed
678 * XXX: We assume that all of the physical CPUs in the
679 * system have the same number of logical CPUs.
681 * XXX: We assume that APIC ID's are allocated such that
682 * the APIC ID's for a physical processor are aligned
683 * with the number of logical CPU's in the processor.
686 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
688 int i, id, lcpus_max, logical_cpus;
690 if ((cpu_feature & CPUID_HTT) == 0)
693 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
697 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
699 * INSTRUCTION SET REFERENCE, A-M (#253666)
700 * Page 3-181, Table 3-20
701 * "The nearest power-of-2 integer that is not smaller
702 * than EBX[23:16] is the number of unique initial APIC
703 * IDs reserved for addressing different logical
704 * processors in a physical package."
707 if ((1 << i) >= lcpus_max) {
714 KKASSERT(cpu_count != 0);
715 if (cpu_count == lcpus_max) {
716 /* We have nothing to fix */
718 } else if (cpu_count == 1) {
719 /* XXX this may be incorrect */
720 logical_cpus = lcpus_max;
725 * Calculate the distances between two nearest
726 * APIC IDs. If all such distances are same,
727 * then it is the number of missing cpus that
728 * we are going to fill later.
730 dist = cur = prev = -1;
731 for (id = 0; id < MAXCPU; ++id) {
732 if ((id_mask & CPUMASK(id)) == 0)
737 int new_dist = cur - prev;
743 * Make sure that all distances
744 * between two nearest APIC IDs
747 if (dist != new_dist)
755 /* Must be power of 2 */
756 if (dist & (dist - 1))
759 /* Can't exceed CPU package capacity */
760 if (dist > lcpus_max)
761 logical_cpus = lcpus_max;
767 * For each APIC ID of a CPU that is set in the mask,
768 * scan the other candidate APIC ID's for this
769 * physical processor. If any of those ID's are
770 * already in the table, then kill the fixup.
772 for (id = 0; id < MAXCPU; id++) {
773 if ((id_mask & CPUMASK(id)) == 0)
775 /* First, make sure we are on a logical_cpus boundary. */
776 if (id % logical_cpus != 0)
778 for (i = id + 1; i < id + logical_cpus; i++)
779 if ((id_mask & CPUMASK(i)) != 0)
786 mptable_map(struct mptable_pos *mpt)
790 vm_size_t cth_mapsz = 0;
792 KKASSERT(mptable_fps_phyaddr != 0);
794 bzero(mpt, sizeof(*mpt));
796 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
799 * Map configuration table header to get
800 * the base table size
802 cth = pmap_mapdev(fps->pap, sizeof(*cth));
803 cth_mapsz = cth->base_table_length;
804 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
806 if (cth_mapsz < sizeof(*cth)) {
807 kprintf("invalid base MP table length %d\n",
809 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
816 cth = pmap_mapdev(fps->pap, cth_mapsz);
821 mpt->mp_cth_mapsz = cth_mapsz;
827 mptable_unmap(struct mptable_pos *mpt)
829 if (mpt->mp_cth != NULL) {
830 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
832 mpt->mp_cth_mapsz = 0;
834 if (mpt->mp_fps != NULL) {
835 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
841 mp_set_cpuids(int cpu_id, int apic_id)
843 CPU_TO_ID(cpu_id) = apic_id;
844 ID_TO_CPU(apic_id) = cpu_id;
848 processor_entry(const struct PROCENTRY *entry, int cpu)
852 /* check for usability */
853 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
856 /* check for BSP flag */
857 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
858 mp_set_cpuids(0, entry->apic_id);
859 return 0; /* its already been counted */
862 /* add another AP to list, if less than max number of CPUs */
863 else if (cpu < MAXCPU) {
864 mp_set_cpuids(cpu, entry->apic_id);
872 * Map a physical memory address representing I/O into KVA. The I/O
873 * block is assumed not to cross a page boundary.
876 ioapic_map(vm_paddr_t pa)
882 KKASSERT(pa < 0x100000000LL);
884 pgeflag = 0; /* not used for SMP yet */
887 * If the requested physical address has already been incidently
888 * mapped, just use the existing mapping. Otherwise create a new
891 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
892 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
893 ((vm_offset_t)pa & PG_FRAME)) {
897 if (i == SMPpt_alloc_index) {
898 if (i == NPTEPG - 2) {
899 panic("permanent_io_mapping: We ran out of space"
902 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
903 ((vm_offset_t)pa & PG_FRAME));
906 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
907 ((vm_offset_t)pa & PAGE_MASK);
908 return ((void *)vaddr);
912 * start each AP in our list
915 start_all_aps(u_int boot_addr)
923 u_long mpbioswarmvec;
924 struct mdglobaldata *gd;
925 struct privatespace *ps;
929 POSTCODE(START_ALL_APS_POST);
931 /* install the AP 1st level boot code */
932 install_ap_tramp(boot_addr);
935 /* save the current value of the warm-start vector */
936 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
937 outb(CMOS_REG, BIOS_RESET);
938 mpbiosreason = inb(CMOS_DATA);
940 /* setup a vector to our boot code */
941 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
942 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
943 outb(CMOS_REG, BIOS_RESET);
944 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
947 * If we have a TSC we can figure out the SMI interrupt rate.
948 * The SMI does not necessarily use a constant rate. Spend
949 * up to 250ms trying to figure it out.
952 if (cpu_feature & CPUID_TSC) {
953 set_apic_timer(275000);
954 smilast = read_apic_timer();
955 for (x = 0; x < 20 && read_apic_timer(); ++x) {
956 smicount = smitest();
957 if (smibest == 0 || smilast - smicount < smibest)
958 smibest = smilast - smicount;
961 if (smibest > 250000)
964 smibest = smibest * (int64_t)1000000 /
965 get_apic_timer_frequency();
969 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
970 1000000 / smibest, smibest);
973 /* set up temporary P==V mapping for AP boot */
974 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
975 kptbase = (uintptr_t)(void *)KPTphys;
976 for (x = 0; x < NKPT; x++) {
977 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
978 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
983 for (x = 1; x <= mp_naps; ++x) {
985 /* This is a bit verbose, it will go away soon. */
987 /* first page of AP's private space */
988 pg = x * i386_btop(sizeof(struct privatespace));
990 /* allocate new private data page(s) */
991 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
992 MDGLOBALDATA_BASEALLOC_SIZE);
993 /* wire it into the private page table page */
994 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
995 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
996 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
998 pg += MDGLOBALDATA_BASEALLOC_PAGES;
1000 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
1001 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
1002 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
1003 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
1005 /* allocate and set up an idle stack data page */
1006 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
1007 for (i = 0; i < UPAGES; i++) {
1008 SMPpt[pg + 4 + i] = (pt_entry_t)
1009 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
1012 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
1013 bzero(gd, sizeof(*gd));
1014 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
1016 /* prime data page for it to use */
1017 mi_gdinit(&gd->mi, x);
1019 gd->gd_CMAP1 = &SMPpt[pg + 0];
1020 gd->gd_CMAP2 = &SMPpt[pg + 1];
1021 gd->gd_CMAP3 = &SMPpt[pg + 2];
1022 gd->gd_PMAP1 = &SMPpt[pg + 3];
1023 gd->gd_CADDR1 = ps->CPAGE1;
1024 gd->gd_CADDR2 = ps->CPAGE2;
1025 gd->gd_CADDR3 = ps->CPAGE3;
1026 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
1029 * Per-cpu pmap for get_ptbase().
1031 gd->gd_GDADDR1= (unsigned *)
1032 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
1033 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
1035 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
1036 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
1039 * Setup the AP boot stack
1041 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
1044 /* attempt to start the Application Processor */
1045 CHECK_INIT(99); /* setup checkpoints */
1046 if (!start_ap(gd, boot_addr, smibest)) {
1047 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
1048 CHECK_PRINT("trace"); /* show checkpoints */
1049 /* better panic as the AP may be running loose */
1050 kprintf("panic y/n? [y] ");
1051 if (cngetc() != 'n')
1054 CHECK_PRINT("trace"); /* show checkpoints */
1056 /* record its version info */
1057 cpu_apic_versions[x] = cpu_apic_versions[0];
1060 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
1063 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
1064 for (shift = 0; (1 << shift) <= ncpus; ++shift)
1067 ncpus2_shift = shift;
1068 ncpus2 = 1 << shift;
1069 ncpus2_mask = ncpus2 - 1;
1071 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
1072 if ((1 << shift) < ncpus)
1074 ncpus_fit = 1 << shift;
1075 ncpus_fit_mask = ncpus_fit - 1;
1077 /* build our map of 'other' CPUs */
1078 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1079 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1080 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1082 /* fill in our (BSP) APIC version */
1083 cpu_apic_versions[0] = lapic.version;
1085 /* restore the warmstart vector */
1086 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1087 outb(CMOS_REG, BIOS_RESET);
1088 outb(CMOS_DATA, mpbiosreason);
1091 * NOTE! The idlestack for the BSP was setup by locore. Finish
1092 * up, clean out the P==V mapping we did earlier.
1094 for (x = 0; x < NKPT; x++)
1099 * Wait all APs to finish initializing LAPIC
1101 mp_finish_lapic = 1;
1103 kprintf("SMP: Waiting APs LAPIC initialization\n");
1104 if (cpu_feature & CPUID_TSC)
1105 tsc0_offset = rdtsc();
1108 while (smp_lapic_mask != smp_startup_mask) {
1110 if (cpu_feature & CPUID_TSC)
1111 tsc0_offset = rdtsc();
1113 while (try_mplock() == 0)
1116 /* number of APs actually started */
1121 * load the 1st level AP boot code into base memory.
1124 /* targets for relocation */
1125 extern void bigJump(void);
1126 extern void bootCodeSeg(void);
1127 extern void bootDataSeg(void);
1128 extern void MPentry(void);
1129 extern u_int MP_GDT;
1130 extern u_int mp_gdtbase;
1133 install_ap_tramp(u_int boot_addr)
1136 int size = *(int *) ((u_long) & bootMP_size);
1137 u_char *src = (u_char *) ((u_long) bootMP);
1138 u_char *dst = (u_char *) boot_addr + KERNBASE;
1139 u_int boot_base = (u_int) bootMP;
1144 POSTCODE(INSTALL_AP_TRAMP_POST);
1146 for (x = 0; x < size; ++x)
1150 * modify addresses in code we just moved to basemem. unfortunately we
1151 * need fairly detailed info about mpboot.s for this to work. changes
1152 * to mpboot.s might require changes here.
1155 /* boot code is located in KERNEL space */
1156 dst = (u_char *) boot_addr + KERNBASE;
1158 /* modify the lgdt arg */
1159 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1160 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1162 /* modify the ljmp target for MPentry() */
1163 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1164 *dst32 = ((u_int) MPentry - KERNBASE);
1166 /* modify the target for boot code segment */
1167 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1168 dst8 = (u_int8_t *) (dst16 + 1);
1169 *dst16 = (u_int) boot_addr & 0xffff;
1170 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1172 /* modify the target for boot data segment */
1173 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1174 dst8 = (u_int8_t *) (dst16 + 1);
1175 *dst16 = (u_int) boot_addr & 0xffff;
1176 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1181 * This function starts the AP (application processor) identified
1182 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1183 * to accomplish this. This is necessary because of the nuances
1184 * of the different hardware we might encounter. It ain't pretty,
1185 * but it seems to work.
1187 * NOTE: eventually an AP gets to ap_init(), which is called just
1188 * before the AP goes into the LWKT scheduler's idle loop.
1191 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
1195 u_long icr_lo, icr_hi;
1197 POSTCODE(START_AP_POST);
1199 /* get the PHYSICAL APIC ID# */
1200 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
1202 /* calculate the vector */
1203 vector = (boot_addr >> 12) & 0xff;
1205 /* We don't want anything interfering */
1208 /* Make sure the target cpu sees everything */
1212 * Try to detect when a SMI has occurred, wait up to 200ms.
1214 * If a SMI occurs during an AP reset but before we issue
1215 * the STARTUP command, the AP may brick. To work around
1216 * this problem we hold off doing the AP startup until
1217 * after we have detected the SMI. Hopefully another SMI
1218 * will not occur before we finish the AP startup.
1220 * Retries don't seem to help. SMIs have a window of opportunity
1221 * and if USB->legacy keyboard emulation is enabled in the BIOS
1222 * the interrupt rate can be quite high.
1224 * NOTE: Don't worry about the L1 cache load, it might bloat
1225 * ldelta a little but ndelta will be so huge when the SMI
1226 * occurs the detection logic will still work fine.
1229 set_apic_timer(200000);
1234 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1235 * and running the target CPU. OR this INIT IPI might be latched (P5
1236 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1239 * see apic/apicreg.h for icr bit definitions.
1241 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
1245 * Setup the address for the target AP. We can setup
1246 * icr_hi once and then just trigger operations with
1249 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
1250 icr_hi |= (physical_cpu << 24);
1251 icr_lo = lapic.icr_lo & 0xfff00000;
1252 lapic.icr_hi = icr_hi;
1255 * Do an INIT IPI: assert RESET
1257 * Use edge triggered mode to assert INIT
1259 lapic.icr_lo = icr_lo | 0x0000c500;
1260 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1264 * The spec calls for a 10ms delay but we may have to use a
1265 * MUCH lower delay to avoid bricking an AP due to a fast SMI
1266 * interrupt. We have other loops here too and dividing by 2
1267 * doesn't seem to be enough even after subtracting 350us,
1268 * so we divide by 4.
1270 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
1271 * interrupt was detected we use the full 10ms.
1275 else if (smibest < 150 * 4 + 350)
1277 else if ((smibest - 350) / 4 < 10000)
1278 u_sleep((smibest - 350) / 4);
1283 * Do an INIT IPI: deassert RESET
1285 * Use level triggered mode to deassert. It is unclear
1286 * why we need to do this.
1288 lapic.icr_lo = icr_lo | 0x00008500;
1289 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1291 u_sleep(150); /* wait 150us */
1294 * Next we do a STARTUP IPI: the previous INIT IPI might still be
1295 * latched, (P5 bug) this 1st STARTUP would then terminate
1296 * immediately, and the previously started INIT IPI would continue. OR
1297 * the previous INIT IPI has already run. and this STARTUP IPI will
1298 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1301 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1302 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1304 u_sleep(200); /* wait ~200uS */
1307 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1308 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1309 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1310 * recognized after hardware RESET or INIT IPI.
1312 lapic.icr_lo = icr_lo | 0x00000600 | vector;
1313 while (lapic.icr_lo & APIC_DELSTAT_MASK)
1316 /* Resume normal operation */
1319 /* wait for it to start, see ap_init() */
1320 set_apic_timer(5000000);/* == 5 seconds */
1321 while (read_apic_timer()) {
1322 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
1323 return 1; /* return SUCCESS */
1326 return 0; /* return FAILURE */
1341 while (read_apic_timer()) {
1343 for (count = 0; count < 100; ++count)
1344 ntsc = rdtsc(); /* force loop to occur */
1346 ndelta = ntsc - ltsc;
1347 if (ldelta > ndelta)
1349 if (ndelta > ldelta * 2)
1352 ldelta = ntsc - ltsc;
1355 return(read_apic_timer());
1359 * Lazy flush the TLB on all other CPU's. DEPRECATED.
1361 * If for some reason we were unable to start all cpus we cannot safely
1362 * use broadcast IPIs.
1365 static cpumask_t smp_invltlb_req;
1366 #define SMP_INVLTLB_DEBUG
1372 struct mdglobaldata *md = mdcpu;
1373 #ifdef SMP_INVLTLB_DEBUG
1378 crit_enter_gd(&md->mi);
1379 md->gd_invltlb_ret = 0;
1380 ++md->mi.gd_cnt.v_smpinvltlb;
1381 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1382 #ifdef SMP_INVLTLB_DEBUG
1385 if (smp_startup_mask == smp_active_mask) {
1386 all_but_self_ipi(XINVLTLB_OFFSET);
1388 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
1389 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1392 #ifdef SMP_INVLTLB_DEBUG
1394 kprintf("smp_invltlb: ipi sent\n");
1396 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
1397 (smp_active_mask & ~md->mi.gd_cpumask)) {
1400 #ifdef SMP_INVLTLB_DEBUG
1402 if (++count == 400000000) {
1403 print_backtrace(-1);
1404 kprintf("smp_invltlb: endless loop %08lx %08lx, "
1405 "rflags %016lx retry",
1406 (long)md->gd_invltlb_ret,
1407 (long)smp_invltlb_req,
1408 (long)read_eflags());
1409 __asm __volatile ("sti");
1412 lwkt_process_ipiq();
1414 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
1415 ~md->mi.gd_cpumask &
1418 kprintf("bcpu %d\n", bcpu);
1419 xgd = globaldata_find(bcpu);
1420 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
1429 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1430 crit_exit_gd(&md->mi);
1437 * Called from Xinvltlb assembly with interrupts disabled. We didn't
1438 * bother to bump the critical section count or nested interrupt count
1439 * so only do very low level operations here.
1442 smp_invltlb_intr(void)
1444 struct mdglobaldata *md = mdcpu;
1445 struct mdglobaldata *omd;
1449 mask = smp_invltlb_req;
1453 cpu = BSFCPUMASK(mask);
1454 mask &= ~CPUMASK(cpu);
1455 omd = (struct mdglobaldata *)globaldata_find(cpu);
1456 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
1463 * When called the executing CPU will send an IPI to all other CPUs
1464 * requesting that they halt execution.
1466 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1468 * - Signals all CPUs in map to stop.
1469 * - Waits for each to stop.
1476 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1477 * from executing at same time.
1480 stop_cpus(cpumask_t map)
1482 map &= smp_active_mask;
1484 /* send the Xcpustop IPI to all CPUs in map */
1485 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1487 while ((stopped_cpus & map) != map)
1495 * Called by a CPU to restart stopped CPUs.
1497 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1499 * - Signals all CPUs in map to restart.
1500 * - Waits for each to restart.
1508 restart_cpus(cpumask_t map)
1510 /* signal other cpus to restart */
1511 started_cpus = map & smp_active_mask;
1513 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
1520 * This is called once the mpboot code has gotten us properly relocated
1521 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1522 * and when it returns the scheduler will call the real cpu_idle() main
1523 * loop for the idlethread. Interrupts are disabled on entry and should
1524 * remain disabled at return.
1532 * Adjust smp_startup_mask to signal the BSP that we have started
1533 * up successfully. Note that we do not yet hold the BGL. The BSP
1534 * is waiting for our signal.
1536 * We can't set our bit in smp_active_mask yet because we are holding
1537 * interrupts physically disabled and remote cpus could deadlock
1538 * trying to send us an IPI.
1540 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
1544 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1545 * non-zero, then get the MP lock.
1547 * Note: We are in a critical section.
1549 * Note: we are the idle thread, we can only spin.
1551 * Note: The load fence is memory volatile and prevents the compiler
1552 * from improperly caching mp_finish_lapic, and the cpu from improperly
1555 while (mp_finish_lapic == 0)
1557 while (try_mplock() == 0)
1560 if (cpu_feature & CPUID_TSC) {
1562 * The BSP is constantly updating tsc0_offset, figure out
1563 * the relative difference to synchronize ktrdump.
1565 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1568 /* BSP may have changed PTD while we're waiting for the lock */
1571 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
1575 /* Build our map of 'other' CPUs. */
1576 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1578 /* A quick check from sanity claus */
1579 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
1580 if (mycpu->gd_cpuid != apic_id) {
1581 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1582 kprintf("SMP: apic_id = %d\n", apic_id);
1583 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1584 panic("cpuid mismatch! boom!!");
1587 /* Initialize AP's local APIC for irq's */
1590 /* LAPIC initialization is done */
1591 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1594 /* Let BSP move onto the next initialization stage */
1598 * Interlock for finalization. Wait until mp_finish is non-zero,
1599 * then get the MP lock.
1601 * Note: We are in a critical section.
1603 * Note: we are the idle thread, we can only spin.
1605 * Note: The load fence is memory volatile and prevents the compiler
1606 * from improperly caching mp_finish, and the cpu from improperly
1609 while (mp_finish == 0)
1611 while (try_mplock() == 0)
1614 /* BSP may have changed PTD while we're waiting for the lock */
1617 /* Set memory range attributes for this CPU to match the BSP */
1618 mem_range_AP_init();
1621 * Once we go active we must process any IPIQ messages that may
1622 * have been queued, because no actual IPI will occur until we
1623 * set our bit in the smp_active_mask. If we don't the IPI
1624 * message interlock could be left set which would also prevent
1627 * The idle loop doesn't expect the BGL to be held and while
1628 * lwkt_switch() normally cleans things up this is a special case
1629 * because we returning almost directly into the idle loop.
1631 * The idle thread is never placed on the runq, make sure
1632 * nothing we've done put it there.
1634 KKASSERT(get_mplock_count(curthread) == 1);
1635 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1638 * Enable interrupts here. idle_restore will also do it, but
1639 * doing it here lets us clean up any strays that got posted to
1640 * the CPU during the AP boot while we are still in a critical
1643 __asm __volatile("sti; pause; pause"::);
1644 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1646 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1647 lwkt_process_ipiq();
1650 * Releasing the mp lock lets the BSP finish up the SMP init
1653 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1657 * Get SMP fully working before we start initializing devices.
1665 kprintf("Finish MP startup\n");
1667 while (smp_active_mask != smp_startup_mask)
1669 while (try_mplock() == 0)
1672 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
1675 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1678 cpu_send_ipiq(int dcpu)
1680 if (CPUMASK(dcpu) & smp_active_mask)
1681 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1684 #if 0 /* single_apic_ipi_passive() not working yet */
1686 * Returns 0 on failure, 1 on success
1689 cpu_send_ipiq_passive(int dcpu)
1692 if (CPUMASK(dcpu) & smp_active_mask) {
1693 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1694 APIC_DELMODE_FIXED);
1701 mptable_bus_info_callback(void *xarg, const void *pos, int type)
1703 struct mptable_bus_info *bus_info = xarg;
1704 const struct BUSENTRY *ent;
1705 struct mptable_bus *bus;
1711 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
1712 if (bus->mb_id == ent->bus_id) {
1713 kprintf("mptable_bus_info_alloc: duplicated bus id "
1714 "(%d)\n", bus->mb_id);
1720 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
1721 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1722 bus->mb_type = MPTABLE_BUS_PCI;
1723 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
1724 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1725 bus->mb_type = MPTABLE_BUS_ISA;
1729 bus->mb_id = ent->bus_id;
1730 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
1736 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
1740 bzero(bus_info, sizeof(*bus_info));
1741 TAILQ_INIT(&bus_info->mbi_list);
1743 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
1745 mptable_bus_info_free(bus_info);
1749 mptable_bus_info_free(struct mptable_bus_info *bus_info)
1751 struct mptable_bus *bus;
1753 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
1754 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
1759 struct mptable_lapic_cbarg1 {
1762 u_int ht_apicid_mask;
1766 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
1768 const struct PROCENTRY *ent;
1769 struct mptable_lapic_cbarg1 *arg = xarg;
1775 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1779 if (ent->apic_id < 32) {
1780 arg->ht_apicid_mask |= 1 << ent->apic_id;
1781 } else if (arg->ht_fixup) {
1782 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
1788 struct mptable_lapic_cbarg2 {
1795 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
1797 const struct PROCENTRY *ent;
1798 struct mptable_lapic_cbarg2 *arg = xarg;
1804 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1805 KKASSERT(!arg->found_bsp);
1809 if (processor_entry(ent, arg->cpu))
1812 if (arg->logical_cpus) {
1813 struct PROCENTRY proc;
1817 * Create fake mptable processor entries
1818 * and feed them to processor_entry() to
1819 * enumerate the logical CPUs.
1821 bzero(&proc, sizeof(proc));
1823 proc.cpu_flags = PROCENTRY_FLAG_EN;
1824 proc.apic_id = ent->apic_id;
1826 for (i = 1; i < arg->logical_cpus; i++) {
1828 processor_entry(&proc, arg->cpu);
1836 mptable_lapic_default(void)
1838 int ap_apicid, bsp_apicid;
1840 mp_naps = 1; /* exclude BSP */
1842 /* Map local apic before the id field is accessed */
1843 lapic_map(DEFAULT_APIC_BASE);
1845 bsp_apicid = APIC_ID(lapic.id);
1846 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
1849 mp_set_cpuids(0, bsp_apicid);
1850 /* one and only AP */
1851 mp_set_cpuids(1, ap_apicid);
1857 * ID_TO_CPU(N), APIC ID to logical CPU table
1858 * CPU_TO_ID(N), logical CPU to APIC ID table
1861 mptable_lapic_enumerate(struct lapic_enumerator *e)
1863 struct mptable_pos mpt;
1864 struct mptable_lapic_cbarg1 arg1;
1865 struct mptable_lapic_cbarg2 arg2;
1867 int error, logical_cpus = 0;
1868 vm_offset_t lapic_addr;
1870 if (mptable_use_default) {
1871 mptable_lapic_default();
1875 error = mptable_map(&mpt);
1877 panic("mptable_lapic_enumerate mptable_map failed\n");
1878 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1882 /* Save local apic address */
1883 lapic_addr = (vm_offset_t)cth->apic_address;
1884 KKASSERT(lapic_addr != 0);
1887 * Find out how many CPUs do we have
1889 bzero(&arg1, sizeof(arg1));
1890 arg1.ht_fixup = 1; /* Apply ht fixup by default */
1892 error = mptable_iterate_entries(cth,
1893 mptable_lapic_pass1_callback, &arg1);
1895 panic("mptable_iterate_entries(lapic_pass1) failed\n");
1896 KKASSERT(arg1.cpu_count != 0);
1898 /* See if we need to fixup HT logical CPUs. */
1899 if (arg1.ht_fixup) {
1900 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
1902 if (logical_cpus != 0)
1903 arg1.cpu_count *= logical_cpus;
1905 mp_naps = arg1.cpu_count;
1907 /* Qualify the numbers again, after possible HT fixup */
1908 if (mp_naps > MAXCPU) {
1909 kprintf("Warning: only using %d of %d available CPUs!\n",
1914 --mp_naps; /* subtract the BSP */
1917 * Link logical CPU id to local apic id
1919 bzero(&arg2, sizeof(arg2));
1921 arg2.logical_cpus = logical_cpus;
1923 error = mptable_iterate_entries(cth,
1924 mptable_lapic_pass2_callback, &arg2);
1926 panic("mptable_iterate_entries(lapic_pass2) failed\n");
1927 KKASSERT(arg2.found_bsp);
1929 /* Map local apic */
1930 lapic_map(lapic_addr);
1932 mptable_unmap(&mpt);
1935 struct mptable_lapic_probe_cbarg {
1941 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
1943 const struct PROCENTRY *ent;
1944 struct mptable_lapic_probe_cbarg *arg = xarg;
1950 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1954 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1955 if (arg->found_bsp) {
1956 kprintf("more than one BSP in base MP table\n");
1965 mptable_lapic_probe(struct lapic_enumerator *e)
1967 struct mptable_pos mpt;
1968 struct mptable_lapic_probe_cbarg arg;
1972 if (mptable_fps_phyaddr == 0)
1975 if (mptable_use_default)
1978 error = mptable_map(&mpt);
1981 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1986 if (cth->apic_address == 0)
1989 bzero(&arg, sizeof(arg));
1990 error = mptable_iterate_entries(cth,
1991 mptable_lapic_probe_callback, &arg);
1993 if (arg.cpu_count == 0) {
1994 kprintf("MP table contains no processor entries\n");
1996 } else if (!arg.found_bsp) {
1997 kprintf("MP table does not contains BSP entry\n");
2002 mptable_unmap(&mpt);
2006 static struct lapic_enumerator mptable_lapic_enumerator = {
2007 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2008 .lapic_probe = mptable_lapic_probe,
2009 .lapic_enumerate = mptable_lapic_enumerate
2013 mptable_lapic_enum_register(void)
2015 lapic_enumerator_register(&mptable_lapic_enumerator);
2017 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2018 mptable_lapic_enum_register, 0);
2021 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
2023 const struct IOAPICENTRY *ent;
2024 struct mptable_ioapic *nioapic, *ioapic;
2030 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
2033 if (ent->apic_address == 0) {
2034 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
2038 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2039 if (ioapic->mio_apic_id == ent->apic_id) {
2040 kprintf("mptable_ioapic_create_list: duplicated "
2041 "apic id %d\n", ioapic->mio_apic_id);
2044 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
2045 kprintf("mptable_ioapic_create_list: overlapped "
2046 "IOAPIC addr 0x%08x", ioapic->mio_addr);
2051 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2052 nioapic->mio_apic_id = ent->apic_id;
2053 nioapic->mio_addr = (uint32_t)ent->apic_address;
2056 * Create IOAPIC list in ascending order of APIC ID
2058 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
2059 mptable_ioapic_list, mio_link) {
2060 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
2061 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
2062 ioapic, nioapic, mio_link);
2067 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
2073 mptable_ioapic_create_list(void)
2075 struct mptable_ioapic *ioapic;
2076 struct mptable_pos mpt;
2079 if (mptable_fps_phyaddr == 0)
2082 if (mptable_use_default) {
2083 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2084 ioapic->mio_idx = 0;
2085 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
2086 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
2088 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
2092 error = mptable_map(&mpt);
2094 panic("mptable_ioapic_create_list: mptable_map failed\n");
2095 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2097 error = mptable_iterate_entries(mpt.mp_cth,
2098 mptable_ioapic_list_callback, NULL);
2100 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
2101 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
2102 kfree(ioapic, M_DEVBUF);
2108 * Assign index number for each IOAPIC
2111 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2112 ioapic->mio_idx = idx;
2116 mptable_unmap(&mpt);
2118 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
2119 mptable_ioapic_create_list, 0);
2122 mptable_pci_int_callback(void *xarg, const void *pos, int type)
2124 const struct mptable_bus_info *bus_info = xarg;
2125 const struct mptable_ioapic *ioapic;
2126 const struct mptable_bus *bus;
2127 struct mptable_pci_int *pci_int;
2128 const struct INTENTRY *ent;
2129 int pci_pin, pci_dev;
2135 if (ent->int_type != 0)
2138 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2139 if (bus->mb_type == MPTABLE_BUS_PCI &&
2140 bus->mb_id == ent->src_bus_id)
2146 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2147 if (ioapic->mio_apic_id == ent->dst_apic_id)
2150 if (ioapic == NULL) {
2151 kprintf("MPTABLE: warning PCI int dst apic id %d "
2152 "does not exist\n", ent->dst_apic_id);
2156 pci_pin = ent->src_bus_irq & 0x3;
2157 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
2159 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2160 if (pci_int->mpci_bus == ent->src_bus_id &&
2161 pci_int->mpci_dev == pci_dev &&
2162 pci_int->mpci_pin == pci_pin) {
2163 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
2164 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
2165 kprintf("MPTABLE: warning duplicated "
2166 "PCI int entry for "
2167 "bus %d, dev %d, pin %d\n",
2173 kprintf("mptable_pci_int_register: "
2174 "conflict PCI int entry for "
2175 "bus %d, dev %d, pin %d, "
2176 "IOAPIC %d.%d -> %d.%d\n",
2180 pci_int->mpci_ioapic_idx,
2181 pci_int->mpci_ioapic_pin,
2189 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
2191 pci_int->mpci_bus = ent->src_bus_id;
2192 pci_int->mpci_dev = pci_dev;
2193 pci_int->mpci_pin = pci_pin;
2194 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
2195 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
2197 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
2203 mptable_pci_int_register(void)
2205 struct mptable_bus_info bus_info;
2206 const struct mptable_bus *bus;
2207 struct mptable_pci_int *pci_int;
2208 struct mptable_pos mpt;
2209 int error, force_pci0, npcibus;
2212 if (mptable_fps_phyaddr == 0)
2215 if (mptable_use_default)
2218 if (TAILQ_EMPTY(&mptable_ioapic_list))
2221 error = mptable_map(&mpt);
2223 panic("mptable_pci_int_register: mptable_map failed\n");
2224 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2228 mptable_bus_info_alloc(cth, &bus_info);
2229 if (TAILQ_EMPTY(&bus_info.mbi_list))
2234 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
2235 if (bus->mb_type == MPTABLE_BUS_PCI)
2239 mptable_bus_info_free(&bus_info);
2241 } else if (npcibus == 1) {
2245 error = mptable_iterate_entries(cth,
2246 mptable_pci_int_callback, &bus_info);
2248 mptable_bus_info_free(&bus_info);
2251 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
2252 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
2253 kfree(pci_int, M_DEVBUF);
2259 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
2260 pci_int->mpci_bus = 0;
2263 mptable_unmap(&mpt);
2265 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2266 mptable_pci_int_register, 0);
2268 struct mptable_ioapic_probe_cbarg {
2269 const struct mptable_bus_info *bus_info;
2273 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
2275 struct mptable_ioapic_probe_cbarg *arg = xarg;
2276 const struct mptable_ioapic *ioapic;
2277 const struct mptable_bus *bus;
2278 const struct INTENTRY *ent;
2284 if (ent->int_type != 0)
2287 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2288 if (bus->mb_type == MPTABLE_BUS_ISA &&
2289 bus->mb_id == ent->src_bus_id)
2295 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2296 if (ioapic->mio_apic_id == ent->dst_apic_id)
2299 if (ioapic == NULL) {
2300 kprintf("MPTABLE: warning ISA int dst apic id %d "
2301 "does not exist\n", ent->dst_apic_id);
2305 /* XXX magic number */
2306 if (ent->src_bus_irq >= 16) {
2307 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
2315 mptable_ioapic_probe(struct ioapic_enumerator *e)
2317 struct mptable_ioapic_probe_cbarg arg;
2318 struct mptable_bus_info bus_info;
2319 struct mptable_pos mpt;
2323 if (mptable_fps_phyaddr == 0)
2326 if (mptable_use_default)
2329 if (TAILQ_EMPTY(&mptable_ioapic_list))
2332 error = mptable_map(&mpt);
2334 panic("mptable_ioapic_probe: mptable_map failed\n");
2335 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2339 mptable_bus_info_alloc(cth, &bus_info);
2341 bzero(&arg, sizeof(arg));
2342 arg.bus_info = &bus_info;
2344 error = mptable_iterate_entries(cth,
2345 mptable_ioapic_probe_callback, &arg);
2347 mptable_bus_info_free(&bus_info);
2348 mptable_unmap(&mpt);
2353 struct mptable_ioapic_int_cbarg {
2354 const struct mptable_bus_info *bus_info;
2359 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
2361 struct mptable_ioapic_int_cbarg *arg = xarg;
2362 const struct mptable_ioapic *ioapic;
2363 const struct mptable_bus *bus;
2364 const struct INTENTRY *ent;
2373 if (ent->int_type != 0)
2376 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2377 if (bus->mb_type == MPTABLE_BUS_ISA &&
2378 bus->mb_id == ent->src_bus_id)
2384 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2385 if (ioapic->mio_apic_id == ent->dst_apic_id)
2388 if (ioapic == NULL) {
2389 kprintf("MPTABLE: warning ISA int dst apic id %d "
2390 "does not exist\n", ent->dst_apic_id);
2394 if (ent->dst_apic_int >= ioapic->mio_npin) {
2395 panic("mptable_ioapic_enumerate: invalid I/O APIC "
2396 "pin %d, should be < %d",
2397 ent->dst_apic_int, ioapic->mio_npin);
2399 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
2401 if (ent->src_bus_irq != gsi) {
2403 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
2404 ent->src_bus_irq, gsi);
2406 ioapic_intsrc(ent->src_bus_irq, gsi,
2407 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2413 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
2415 struct mptable_bus_info bus_info;
2416 struct mptable_ioapic *ioapic;
2417 struct mptable_pos mpt;
2421 KKASSERT(mptable_fps_phyaddr != 0);
2422 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
2424 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2425 const struct mptable_ioapic *prev_ioapic;
2429 addr = ioapic_map(ioapic->mio_addr);
2431 ver = ioapic_read(addr, IOAPIC_VER);
2432 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
2433 >> MAXREDIRSHIFT) + 1;
2435 prev_ioapic = TAILQ_PREV(ioapic,
2436 mptable_ioapic_list, mio_link);
2437 if (prev_ioapic == NULL) {
2438 ioapic->mio_gsi_base = 0;
2440 ioapic->mio_gsi_base =
2441 prev_ioapic->mio_gsi_base +
2442 prev_ioapic->mio_npin;
2444 ioapic_add(addr, ioapic->mio_gsi_base,
2448 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
2449 "apic id %d, idx %d, gsi base %d, npin %d\n",
2451 ioapic->mio_apic_id,
2453 ioapic->mio_gsi_base,
2458 if (mptable_use_default) {
2460 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
2461 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2465 error = mptable_map(&mpt);
2467 panic("mptable_ioapic_probe: mptable_map failed\n");
2468 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2472 mptable_bus_info_alloc(cth, &bus_info);
2474 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
2476 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
2477 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2479 struct mptable_ioapic_int_cbarg arg;
2481 bzero(&arg, sizeof(arg));
2482 arg.bus_info = &bus_info;
2484 error = mptable_iterate_entries(cth,
2485 mptable_ioapic_int_callback, &arg);
2487 panic("mptable_ioapic_int failed\n");
2489 if (arg.ioapic_nint == 0) {
2491 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
2494 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
2495 INTR_POLARITY_HIGH);
2499 mptable_bus_info_free(&bus_info);
2501 mptable_unmap(&mpt);
2504 static struct ioapic_enumerator mptable_ioapic_enumerator = {
2505 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
2506 .ioapic_probe = mptable_ioapic_probe,
2507 .ioapic_enumerate = mptable_ioapic_enumerate
2511 mptable_ioapic_enum_register(void)
2513 ioapic_enumerator_register(&mptable_ioapic_enumerator);
2515 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2516 mptable_ioapic_enum_register, 0);
2519 mptable_pci_int_dump(void)
2521 const struct mptable_pci_int *pci_int;
2523 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2524 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
2527 pci_int->mpci_pin + 'A',
2528 pci_int->mpci_ioapic_idx,
2529 pci_int->mpci_ioapic_pin);
2534 mptable_pci_int_route(int bus, int dev, int pin, int intline)
2536 const struct mptable_pci_int *pci_int;
2540 --pin; /* zero based */
2542 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2543 if (pci_int->mpci_bus == bus &&
2544 pci_int->mpci_dev == dev &&
2545 pci_int->mpci_pin == pin)
2548 if (pci_int != NULL) {
2551 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
2552 pci_int->mpci_ioapic_pin);
2554 irq = ioapic_abi_find_gsi(gsi,
2555 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2561 kprintf("MPTABLE: fixed interrupt routing "
2562 "for %d:%d INT%c\n", bus, dev, pin + 'A');
2565 irq = ioapic_abi_find_irq(intline,
2566 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2569 if (irq >= 0 && bootverbose) {
2570 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
2571 bus, dev, pin + 'A', irq);