1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-codes.h"
36 #include "insn-attr.h"
45 #include "basic-block.h"
48 #include "target-def.h"
49 #include "langhooks.h"
54 #include "tm-constrs.h"
58 static int x86_builtin_vectorization_cost (bool);
59 static rtx legitimize_dllimport_symbol (rtx, bool);
61 #ifndef CHECK_STACK_LIMIT
62 #define CHECK_STACK_LIMIT (-1)
65 /* Return index of given mode in mult and division cost tables. */
66 #define MODE_INDEX(mode) \
67 ((mode) == QImode ? 0 \
68 : (mode) == HImode ? 1 \
69 : (mode) == SImode ? 2 \
70 : (mode) == DImode ? 3 \
73 /* Processor costs (relative to an add) */
74 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
75 #define COSTS_N_BYTES(N) ((N) * 2)
77 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall}}}
80 struct processor_costs ix86_size_cost = {/* costs for tuning for size */
81 COSTS_N_BYTES (2), /* cost of an add instruction */
82 COSTS_N_BYTES (3), /* cost of a lea instruction */
83 COSTS_N_BYTES (2), /* variable shift costs */
84 COSTS_N_BYTES (3), /* constant shift costs */
85 {COSTS_N_BYTES (3), /* cost of starting multiply for QI */
86 COSTS_N_BYTES (3), /* HI */
87 COSTS_N_BYTES (3), /* SI */
88 COSTS_N_BYTES (3), /* DI */
89 COSTS_N_BYTES (5)}, /* other */
90 0, /* cost of multiply per each bit set */
91 {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */
92 COSTS_N_BYTES (3), /* HI */
93 COSTS_N_BYTES (3), /* SI */
94 COSTS_N_BYTES (3), /* DI */
95 COSTS_N_BYTES (5)}, /* other */
96 COSTS_N_BYTES (3), /* cost of movsx */
97 COSTS_N_BYTES (3), /* cost of movzx */
100 2, /* cost for loading QImode using movzbl */
101 {2, 2, 2}, /* cost of loading integer registers
102 in QImode, HImode and SImode.
103 Relative to reg-reg move (2). */
104 {2, 2, 2}, /* cost of storing integer registers */
105 2, /* cost of reg,reg fld/fst */
106 {2, 2, 2}, /* cost of loading fp registers
107 in SFmode, DFmode and XFmode */
108 {2, 2, 2}, /* cost of storing fp registers
109 in SFmode, DFmode and XFmode */
110 3, /* cost of moving MMX register */
111 {3, 3}, /* cost of loading MMX registers
112 in SImode and DImode */
113 {3, 3}, /* cost of storing MMX registers
114 in SImode and DImode */
115 3, /* cost of moving SSE register */
116 {3, 3, 3}, /* cost of loading SSE registers
117 in SImode, DImode and TImode */
118 {3, 3, 3}, /* cost of storing SSE registers
119 in SImode, DImode and TImode */
120 3, /* MMX or SSE register to integer */
121 0, /* size of l1 cache */
122 0, /* size of l2 cache */
123 0, /* size of prefetch block */
124 0, /* number of parallel prefetches */
126 COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */
127 COSTS_N_BYTES (2), /* cost of FMUL instruction. */
128 COSTS_N_BYTES (2), /* cost of FDIV instruction. */
129 COSTS_N_BYTES (2), /* cost of FABS instruction. */
130 COSTS_N_BYTES (2), /* cost of FCHS instruction. */
131 COSTS_N_BYTES (2), /* cost of FSQRT instruction. */
132 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
133 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
134 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
135 {rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}}},
136 1, /* scalar_stmt_cost. */
137 1, /* scalar load_cost. */
138 1, /* scalar_store_cost. */
139 1, /* vec_stmt_cost. */
140 1, /* vec_to_scalar_cost. */
141 1, /* scalar_to_vec_cost. */
142 1, /* vec_align_load_cost. */
143 1, /* vec_unalign_load_cost. */
144 1, /* vec_store_cost. */
145 1, /* cond_taken_branch_cost. */
146 1, /* cond_not_taken_branch_cost. */
149 /* Processor costs (relative to an add) */
151 struct processor_costs i386_cost = { /* 386 specific costs */
152 COSTS_N_INSNS (1), /* cost of an add instruction */
153 COSTS_N_INSNS (1), /* cost of a lea instruction */
154 COSTS_N_INSNS (3), /* variable shift costs */
155 COSTS_N_INSNS (2), /* constant shift costs */
156 {COSTS_N_INSNS (6), /* cost of starting multiply for QI */
157 COSTS_N_INSNS (6), /* HI */
158 COSTS_N_INSNS (6), /* SI */
159 COSTS_N_INSNS (6), /* DI */
160 COSTS_N_INSNS (6)}, /* other */
161 COSTS_N_INSNS (1), /* cost of multiply per each bit set */
162 {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */
163 COSTS_N_INSNS (23), /* HI */
164 COSTS_N_INSNS (23), /* SI */
165 COSTS_N_INSNS (23), /* DI */
166 COSTS_N_INSNS (23)}, /* other */
167 COSTS_N_INSNS (3), /* cost of movsx */
168 COSTS_N_INSNS (2), /* cost of movzx */
169 15, /* "large" insn */
171 4, /* cost for loading QImode using movzbl */
172 {2, 4, 2}, /* cost of loading integer registers
173 in QImode, HImode and SImode.
174 Relative to reg-reg move (2). */
175 {2, 4, 2}, /* cost of storing integer registers */
176 2, /* cost of reg,reg fld/fst */
177 {8, 8, 8}, /* cost of loading fp registers
178 in SFmode, DFmode and XFmode */
179 {8, 8, 8}, /* cost of storing fp registers
180 in SFmode, DFmode and XFmode */
181 2, /* cost of moving MMX register */
182 {4, 8}, /* cost of loading MMX registers
183 in SImode and DImode */
184 {4, 8}, /* cost of storing MMX registers
185 in SImode and DImode */
186 2, /* cost of moving SSE register */
187 {4, 8, 16}, /* cost of loading SSE registers
188 in SImode, DImode and TImode */
189 {4, 8, 16}, /* cost of storing SSE registers
190 in SImode, DImode and TImode */
191 3, /* MMX or SSE register to integer */
192 0, /* size of l1 cache */
193 0, /* size of l2 cache */
194 0, /* size of prefetch block */
195 0, /* number of parallel prefetches */
197 COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */
198 COSTS_N_INSNS (27), /* cost of FMUL instruction. */
199 COSTS_N_INSNS (88), /* cost of FDIV instruction. */
200 COSTS_N_INSNS (22), /* cost of FABS instruction. */
201 COSTS_N_INSNS (24), /* cost of FCHS instruction. */
202 COSTS_N_INSNS (122), /* cost of FSQRT instruction. */
203 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
204 DUMMY_STRINGOP_ALGS},
205 {{rep_prefix_1_byte, {{-1, rep_prefix_1_byte}}},
206 DUMMY_STRINGOP_ALGS},
207 1, /* scalar_stmt_cost. */
208 1, /* scalar load_cost. */
209 1, /* scalar_store_cost. */
210 1, /* vec_stmt_cost. */
211 1, /* vec_to_scalar_cost. */
212 1, /* scalar_to_vec_cost. */
213 1, /* vec_align_load_cost. */
214 2, /* vec_unalign_load_cost. */
215 1, /* vec_store_cost. */
216 3, /* cond_taken_branch_cost. */
217 1, /* cond_not_taken_branch_cost. */
221 struct processor_costs i486_cost = { /* 486 specific costs */
222 COSTS_N_INSNS (1), /* cost of an add instruction */
223 COSTS_N_INSNS (1), /* cost of a lea instruction */
224 COSTS_N_INSNS (3), /* variable shift costs */
225 COSTS_N_INSNS (2), /* constant shift costs */
226 {COSTS_N_INSNS (12), /* cost of starting multiply for QI */
227 COSTS_N_INSNS (12), /* HI */
228 COSTS_N_INSNS (12), /* SI */
229 COSTS_N_INSNS (12), /* DI */
230 COSTS_N_INSNS (12)}, /* other */
231 1, /* cost of multiply per each bit set */
232 {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */
233 COSTS_N_INSNS (40), /* HI */
234 COSTS_N_INSNS (40), /* SI */
235 COSTS_N_INSNS (40), /* DI */
236 COSTS_N_INSNS (40)}, /* other */
237 COSTS_N_INSNS (3), /* cost of movsx */
238 COSTS_N_INSNS (2), /* cost of movzx */
239 15, /* "large" insn */
241 4, /* cost for loading QImode using movzbl */
242 {2, 4, 2}, /* cost of loading integer registers
243 in QImode, HImode and SImode.
244 Relative to reg-reg move (2). */
245 {2, 4, 2}, /* cost of storing integer registers */
246 2, /* cost of reg,reg fld/fst */
247 {8, 8, 8}, /* cost of loading fp registers
248 in SFmode, DFmode and XFmode */
249 {8, 8, 8}, /* cost of storing fp registers
250 in SFmode, DFmode and XFmode */
251 2, /* cost of moving MMX register */
252 {4, 8}, /* cost of loading MMX registers
253 in SImode and DImode */
254 {4, 8}, /* cost of storing MMX registers
255 in SImode and DImode */
256 2, /* cost of moving SSE register */
257 {4, 8, 16}, /* cost of loading SSE registers
258 in SImode, DImode and TImode */
259 {4, 8, 16}, /* cost of storing SSE registers
260 in SImode, DImode and TImode */
261 3, /* MMX or SSE register to integer */
262 4, /* size of l1 cache. 486 has 8kB cache
263 shared for code and data, so 4kB is
264 not really precise. */
265 4, /* size of l2 cache */
266 0, /* size of prefetch block */
267 0, /* number of parallel prefetches */
269 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
270 COSTS_N_INSNS (16), /* cost of FMUL instruction. */
271 COSTS_N_INSNS (73), /* cost of FDIV instruction. */
272 COSTS_N_INSNS (3), /* cost of FABS instruction. */
273 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
274 COSTS_N_INSNS (83), /* cost of FSQRT instruction. */
275 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
276 DUMMY_STRINGOP_ALGS},
277 {{rep_prefix_4_byte, {{-1, rep_prefix_4_byte}}},
278 DUMMY_STRINGOP_ALGS},
279 1, /* scalar_stmt_cost. */
280 1, /* scalar load_cost. */
281 1, /* scalar_store_cost. */
282 1, /* vec_stmt_cost. */
283 1, /* vec_to_scalar_cost. */
284 1, /* scalar_to_vec_cost. */
285 1, /* vec_align_load_cost. */
286 2, /* vec_unalign_load_cost. */
287 1, /* vec_store_cost. */
288 3, /* cond_taken_branch_cost. */
289 1, /* cond_not_taken_branch_cost. */
293 struct processor_costs pentium_cost = {
294 COSTS_N_INSNS (1), /* cost of an add instruction */
295 COSTS_N_INSNS (1), /* cost of a lea instruction */
296 COSTS_N_INSNS (4), /* variable shift costs */
297 COSTS_N_INSNS (1), /* constant shift costs */
298 {COSTS_N_INSNS (11), /* cost of starting multiply for QI */
299 COSTS_N_INSNS (11), /* HI */
300 COSTS_N_INSNS (11), /* SI */
301 COSTS_N_INSNS (11), /* DI */
302 COSTS_N_INSNS (11)}, /* other */
303 0, /* cost of multiply per each bit set */
304 {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */
305 COSTS_N_INSNS (25), /* HI */
306 COSTS_N_INSNS (25), /* SI */
307 COSTS_N_INSNS (25), /* DI */
308 COSTS_N_INSNS (25)}, /* other */
309 COSTS_N_INSNS (3), /* cost of movsx */
310 COSTS_N_INSNS (2), /* cost of movzx */
311 8, /* "large" insn */
313 6, /* cost for loading QImode using movzbl */
314 {2, 4, 2}, /* cost of loading integer registers
315 in QImode, HImode and SImode.
316 Relative to reg-reg move (2). */
317 {2, 4, 2}, /* cost of storing integer registers */
318 2, /* cost of reg,reg fld/fst */
319 {2, 2, 6}, /* cost of loading fp registers
320 in SFmode, DFmode and XFmode */
321 {4, 4, 6}, /* cost of storing fp registers
322 in SFmode, DFmode and XFmode */
323 8, /* cost of moving MMX register */
324 {8, 8}, /* cost of loading MMX registers
325 in SImode and DImode */
326 {8, 8}, /* cost of storing MMX registers
327 in SImode and DImode */
328 2, /* cost of moving SSE register */
329 {4, 8, 16}, /* cost of loading SSE registers
330 in SImode, DImode and TImode */
331 {4, 8, 16}, /* cost of storing SSE registers
332 in SImode, DImode and TImode */
333 3, /* MMX or SSE register to integer */
334 8, /* size of l1 cache. */
335 8, /* size of l2 cache */
336 0, /* size of prefetch block */
337 0, /* number of parallel prefetches */
339 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
340 COSTS_N_INSNS (3), /* cost of FMUL instruction. */
341 COSTS_N_INSNS (39), /* cost of FDIV instruction. */
342 COSTS_N_INSNS (1), /* cost of FABS instruction. */
343 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
344 COSTS_N_INSNS (70), /* cost of FSQRT instruction. */
345 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
346 DUMMY_STRINGOP_ALGS},
347 {{libcall, {{-1, rep_prefix_4_byte}}},
348 DUMMY_STRINGOP_ALGS},
349 1, /* scalar_stmt_cost. */
350 1, /* scalar load_cost. */
351 1, /* scalar_store_cost. */
352 1, /* vec_stmt_cost. */
353 1, /* vec_to_scalar_cost. */
354 1, /* scalar_to_vec_cost. */
355 1, /* vec_align_load_cost. */
356 2, /* vec_unalign_load_cost. */
357 1, /* vec_store_cost. */
358 3, /* cond_taken_branch_cost. */
359 1, /* cond_not_taken_branch_cost. */
363 struct processor_costs pentiumpro_cost = {
364 COSTS_N_INSNS (1), /* cost of an add instruction */
365 COSTS_N_INSNS (1), /* cost of a lea instruction */
366 COSTS_N_INSNS (1), /* variable shift costs */
367 COSTS_N_INSNS (1), /* constant shift costs */
368 {COSTS_N_INSNS (4), /* cost of starting multiply for QI */
369 COSTS_N_INSNS (4), /* HI */
370 COSTS_N_INSNS (4), /* SI */
371 COSTS_N_INSNS (4), /* DI */
372 COSTS_N_INSNS (4)}, /* other */
373 0, /* cost of multiply per each bit set */
374 {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */
375 COSTS_N_INSNS (17), /* HI */
376 COSTS_N_INSNS (17), /* SI */
377 COSTS_N_INSNS (17), /* DI */
378 COSTS_N_INSNS (17)}, /* other */
379 COSTS_N_INSNS (1), /* cost of movsx */
380 COSTS_N_INSNS (1), /* cost of movzx */
381 8, /* "large" insn */
383 2, /* cost for loading QImode using movzbl */
384 {4, 4, 4}, /* cost of loading integer registers
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
387 {2, 2, 2}, /* cost of storing integer registers */
388 2, /* cost of reg,reg fld/fst */
389 {2, 2, 6}, /* cost of loading fp registers
390 in SFmode, DFmode and XFmode */
391 {4, 4, 6}, /* cost of storing fp registers
392 in SFmode, DFmode and XFmode */
393 2, /* cost of moving MMX register */
394 {2, 2}, /* cost of loading MMX registers
395 in SImode and DImode */
396 {2, 2}, /* cost of storing MMX registers
397 in SImode and DImode */
398 2, /* cost of moving SSE register */
399 {2, 2, 8}, /* cost of loading SSE registers
400 in SImode, DImode and TImode */
401 {2, 2, 8}, /* cost of storing SSE registers
402 in SImode, DImode and TImode */
403 3, /* MMX or SSE register to integer */
404 8, /* size of l1 cache. */
405 256, /* size of l2 cache */
406 32, /* size of prefetch block */
407 6, /* number of parallel prefetches */
409 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
410 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
411 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
412 COSTS_N_INSNS (2), /* cost of FABS instruction. */
413 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
414 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
415 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes (we ensure
416 the alignment). For small blocks inline loop is still a noticeable win, for bigger
417 blocks either rep movsl or rep movsb is way to go. Rep movsb has apparently
418 more expensive startup time in CPU, but after 4K the difference is down in the noise.
420 {{rep_prefix_4_byte, {{128, loop}, {1024, unrolled_loop},
421 {8192, rep_prefix_4_byte}, {-1, rep_prefix_1_byte}}},
422 DUMMY_STRINGOP_ALGS},
423 {{rep_prefix_4_byte, {{1024, unrolled_loop},
424 {8192, rep_prefix_4_byte}, {-1, libcall}}},
425 DUMMY_STRINGOP_ALGS},
426 1, /* scalar_stmt_cost. */
427 1, /* scalar load_cost. */
428 1, /* scalar_store_cost. */
429 1, /* vec_stmt_cost. */
430 1, /* vec_to_scalar_cost. */
431 1, /* scalar_to_vec_cost. */
432 1, /* vec_align_load_cost. */
433 2, /* vec_unalign_load_cost. */
434 1, /* vec_store_cost. */
435 3, /* cond_taken_branch_cost. */
436 1, /* cond_not_taken_branch_cost. */
440 struct processor_costs geode_cost = {
441 COSTS_N_INSNS (1), /* cost of an add instruction */
442 COSTS_N_INSNS (1), /* cost of a lea instruction */
443 COSTS_N_INSNS (2), /* variable shift costs */
444 COSTS_N_INSNS (1), /* constant shift costs */
445 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
446 COSTS_N_INSNS (4), /* HI */
447 COSTS_N_INSNS (7), /* SI */
448 COSTS_N_INSNS (7), /* DI */
449 COSTS_N_INSNS (7)}, /* other */
450 0, /* cost of multiply per each bit set */
451 {COSTS_N_INSNS (15), /* cost of a divide/mod for QI */
452 COSTS_N_INSNS (23), /* HI */
453 COSTS_N_INSNS (39), /* SI */
454 COSTS_N_INSNS (39), /* DI */
455 COSTS_N_INSNS (39)}, /* other */
456 COSTS_N_INSNS (1), /* cost of movsx */
457 COSTS_N_INSNS (1), /* cost of movzx */
458 8, /* "large" insn */
460 1, /* cost for loading QImode using movzbl */
461 {1, 1, 1}, /* cost of loading integer registers
462 in QImode, HImode and SImode.
463 Relative to reg-reg move (2). */
464 {1, 1, 1}, /* cost of storing integer registers */
465 1, /* cost of reg,reg fld/fst */
466 {1, 1, 1}, /* cost of loading fp registers
467 in SFmode, DFmode and XFmode */
468 {4, 6, 6}, /* cost of storing fp registers
469 in SFmode, DFmode and XFmode */
471 1, /* cost of moving MMX register */
472 {1, 1}, /* cost of loading MMX registers
473 in SImode and DImode */
474 {1, 1}, /* cost of storing MMX registers
475 in SImode and DImode */
476 1, /* cost of moving SSE register */
477 {1, 1, 1}, /* cost of loading SSE registers
478 in SImode, DImode and TImode */
479 {1, 1, 1}, /* cost of storing SSE registers
480 in SImode, DImode and TImode */
481 1, /* MMX or SSE register to integer */
482 64, /* size of l1 cache. */
483 128, /* size of l2 cache. */
484 32, /* size of prefetch block */
485 1, /* number of parallel prefetches */
487 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
488 COSTS_N_INSNS (11), /* cost of FMUL instruction. */
489 COSTS_N_INSNS (47), /* cost of FDIV instruction. */
490 COSTS_N_INSNS (1), /* cost of FABS instruction. */
491 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
492 COSTS_N_INSNS (54), /* cost of FSQRT instruction. */
493 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
494 DUMMY_STRINGOP_ALGS},
495 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
496 DUMMY_STRINGOP_ALGS},
497 1, /* scalar_stmt_cost. */
498 1, /* scalar load_cost. */
499 1, /* scalar_store_cost. */
500 1, /* vec_stmt_cost. */
501 1, /* vec_to_scalar_cost. */
502 1, /* scalar_to_vec_cost. */
503 1, /* vec_align_load_cost. */
504 2, /* vec_unalign_load_cost. */
505 1, /* vec_store_cost. */
506 3, /* cond_taken_branch_cost. */
507 1, /* cond_not_taken_branch_cost. */
511 struct processor_costs k6_cost = {
512 COSTS_N_INSNS (1), /* cost of an add instruction */
513 COSTS_N_INSNS (2), /* cost of a lea instruction */
514 COSTS_N_INSNS (1), /* variable shift costs */
515 COSTS_N_INSNS (1), /* constant shift costs */
516 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
517 COSTS_N_INSNS (3), /* HI */
518 COSTS_N_INSNS (3), /* SI */
519 COSTS_N_INSNS (3), /* DI */
520 COSTS_N_INSNS (3)}, /* other */
521 0, /* cost of multiply per each bit set */
522 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
523 COSTS_N_INSNS (18), /* HI */
524 COSTS_N_INSNS (18), /* SI */
525 COSTS_N_INSNS (18), /* DI */
526 COSTS_N_INSNS (18)}, /* other */
527 COSTS_N_INSNS (2), /* cost of movsx */
528 COSTS_N_INSNS (2), /* cost of movzx */
529 8, /* "large" insn */
531 3, /* cost for loading QImode using movzbl */
532 {4, 5, 4}, /* cost of loading integer registers
533 in QImode, HImode and SImode.
534 Relative to reg-reg move (2). */
535 {2, 3, 2}, /* cost of storing integer registers */
536 4, /* cost of reg,reg fld/fst */
537 {6, 6, 6}, /* cost of loading fp registers
538 in SFmode, DFmode and XFmode */
539 {4, 4, 4}, /* cost of storing fp registers
540 in SFmode, DFmode and XFmode */
541 2, /* cost of moving MMX register */
542 {2, 2}, /* cost of loading MMX registers
543 in SImode and DImode */
544 {2, 2}, /* cost of storing MMX registers
545 in SImode and DImode */
546 2, /* cost of moving SSE register */
547 {2, 2, 8}, /* cost of loading SSE registers
548 in SImode, DImode and TImode */
549 {2, 2, 8}, /* cost of storing SSE registers
550 in SImode, DImode and TImode */
551 6, /* MMX or SSE register to integer */
552 32, /* size of l1 cache. */
553 32, /* size of l2 cache. Some models
554 have integrated l2 cache, but
555 optimizing for k6 is not important
556 enough to worry about that. */
557 32, /* size of prefetch block */
558 1, /* number of parallel prefetches */
560 COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */
561 COSTS_N_INSNS (2), /* cost of FMUL instruction. */
562 COSTS_N_INSNS (56), /* cost of FDIV instruction. */
563 COSTS_N_INSNS (2), /* cost of FABS instruction. */
564 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
565 COSTS_N_INSNS (56), /* cost of FSQRT instruction. */
566 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
567 DUMMY_STRINGOP_ALGS},
568 {{libcall, {{256, rep_prefix_4_byte}, {-1, libcall}}},
569 DUMMY_STRINGOP_ALGS},
570 1, /* scalar_stmt_cost. */
571 1, /* scalar load_cost. */
572 1, /* scalar_store_cost. */
573 1, /* vec_stmt_cost. */
574 1, /* vec_to_scalar_cost. */
575 1, /* scalar_to_vec_cost. */
576 1, /* vec_align_load_cost. */
577 2, /* vec_unalign_load_cost. */
578 1, /* vec_store_cost. */
579 3, /* cond_taken_branch_cost. */
580 1, /* cond_not_taken_branch_cost. */
584 struct processor_costs athlon_cost = {
585 COSTS_N_INSNS (1), /* cost of an add instruction */
586 COSTS_N_INSNS (2), /* cost of a lea instruction */
587 COSTS_N_INSNS (1), /* variable shift costs */
588 COSTS_N_INSNS (1), /* constant shift costs */
589 {COSTS_N_INSNS (5), /* cost of starting multiply for QI */
590 COSTS_N_INSNS (5), /* HI */
591 COSTS_N_INSNS (5), /* SI */
592 COSTS_N_INSNS (5), /* DI */
593 COSTS_N_INSNS (5)}, /* other */
594 0, /* cost of multiply per each bit set */
595 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
596 COSTS_N_INSNS (26), /* HI */
597 COSTS_N_INSNS (42), /* SI */
598 COSTS_N_INSNS (74), /* DI */
599 COSTS_N_INSNS (74)}, /* other */
600 COSTS_N_INSNS (1), /* cost of movsx */
601 COSTS_N_INSNS (1), /* cost of movzx */
602 8, /* "large" insn */
604 4, /* cost for loading QImode using movzbl */
605 {3, 4, 3}, /* cost of loading integer registers
606 in QImode, HImode and SImode.
607 Relative to reg-reg move (2). */
608 {3, 4, 3}, /* cost of storing integer registers */
609 4, /* cost of reg,reg fld/fst */
610 {4, 4, 12}, /* cost of loading fp registers
611 in SFmode, DFmode and XFmode */
612 {6, 6, 8}, /* cost of storing fp registers
613 in SFmode, DFmode and XFmode */
614 2, /* cost of moving MMX register */
615 {4, 4}, /* cost of loading MMX registers
616 in SImode and DImode */
617 {4, 4}, /* cost of storing MMX registers
618 in SImode and DImode */
619 2, /* cost of moving SSE register */
620 {4, 4, 6}, /* cost of loading SSE registers
621 in SImode, DImode and TImode */
622 {4, 4, 5}, /* cost of storing SSE registers
623 in SImode, DImode and TImode */
624 5, /* MMX or SSE register to integer */
625 64, /* size of l1 cache. */
626 256, /* size of l2 cache. */
627 64, /* size of prefetch block */
628 6, /* number of parallel prefetches */
630 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
631 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
632 COSTS_N_INSNS (24), /* cost of FDIV instruction. */
633 COSTS_N_INSNS (2), /* cost of FABS instruction. */
634 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
635 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
636 /* For some reason, Athlon deals better with REP prefix (relative to loops)
637 compared to K8. Alignment becomes important after 8 bytes for memcpy and
638 128 bytes for memset. */
639 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
640 DUMMY_STRINGOP_ALGS},
641 {{libcall, {{2048, rep_prefix_4_byte}, {-1, libcall}}},
642 DUMMY_STRINGOP_ALGS},
643 1, /* scalar_stmt_cost. */
644 1, /* scalar load_cost. */
645 1, /* scalar_store_cost. */
646 1, /* vec_stmt_cost. */
647 1, /* vec_to_scalar_cost. */
648 1, /* scalar_to_vec_cost. */
649 1, /* vec_align_load_cost. */
650 2, /* vec_unalign_load_cost. */
651 1, /* vec_store_cost. */
652 3, /* cond_taken_branch_cost. */
653 1, /* cond_not_taken_branch_cost. */
657 struct processor_costs k8_cost = {
658 COSTS_N_INSNS (1), /* cost of an add instruction */
659 COSTS_N_INSNS (2), /* cost of a lea instruction */
660 COSTS_N_INSNS (1), /* variable shift costs */
661 COSTS_N_INSNS (1), /* constant shift costs */
662 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
663 COSTS_N_INSNS (4), /* HI */
664 COSTS_N_INSNS (3), /* SI */
665 COSTS_N_INSNS (4), /* DI */
666 COSTS_N_INSNS (5)}, /* other */
667 0, /* cost of multiply per each bit set */
668 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
669 COSTS_N_INSNS (26), /* HI */
670 COSTS_N_INSNS (42), /* SI */
671 COSTS_N_INSNS (74), /* DI */
672 COSTS_N_INSNS (74)}, /* other */
673 COSTS_N_INSNS (1), /* cost of movsx */
674 COSTS_N_INSNS (1), /* cost of movzx */
675 8, /* "large" insn */
677 4, /* cost for loading QImode using movzbl */
678 {3, 4, 3}, /* cost of loading integer registers
679 in QImode, HImode and SImode.
680 Relative to reg-reg move (2). */
681 {3, 4, 3}, /* cost of storing integer registers */
682 4, /* cost of reg,reg fld/fst */
683 {4, 4, 12}, /* cost of loading fp registers
684 in SFmode, DFmode and XFmode */
685 {6, 6, 8}, /* cost of storing fp registers
686 in SFmode, DFmode and XFmode */
687 2, /* cost of moving MMX register */
688 {3, 3}, /* cost of loading MMX registers
689 in SImode and DImode */
690 {4, 4}, /* cost of storing MMX registers
691 in SImode and DImode */
692 2, /* cost of moving SSE register */
693 {4, 3, 6}, /* cost of loading SSE registers
694 in SImode, DImode and TImode */
695 {4, 4, 5}, /* cost of storing SSE registers
696 in SImode, DImode and TImode */
697 5, /* MMX or SSE register to integer */
698 64, /* size of l1 cache. */
699 512, /* size of l2 cache. */
700 64, /* size of prefetch block */
701 /* New AMD processors never drop prefetches; if they cannot be performed
702 immediately, they are queued. We set number of simultaneous prefetches
703 to a large constant to reflect this (it probably is not a good idea not
704 to limit number of prefetches at all, as their execution also takes some
706 100, /* number of parallel prefetches */
708 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
709 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
710 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
711 COSTS_N_INSNS (2), /* cost of FABS instruction. */
712 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
713 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
714 /* K8 has optimized REP instruction for medium sized blocks, but for very small
715 blocks it is better to use loop. For large blocks, libcall can do
716 nontemporary accesses and beat inline considerably. */
717 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
718 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
719 {{libcall, {{8, loop}, {24, unrolled_loop},
720 {2048, rep_prefix_4_byte}, {-1, libcall}}},
721 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
722 4, /* scalar_stmt_cost. */
723 2, /* scalar load_cost. */
724 2, /* scalar_store_cost. */
725 5, /* vec_stmt_cost. */
726 0, /* vec_to_scalar_cost. */
727 2, /* scalar_to_vec_cost. */
728 2, /* vec_align_load_cost. */
729 3, /* vec_unalign_load_cost. */
730 3, /* vec_store_cost. */
731 3, /* cond_taken_branch_cost. */
732 2, /* cond_not_taken_branch_cost. */
735 struct processor_costs amdfam10_cost = {
736 COSTS_N_INSNS (1), /* cost of an add instruction */
737 COSTS_N_INSNS (2), /* cost of a lea instruction */
738 COSTS_N_INSNS (1), /* variable shift costs */
739 COSTS_N_INSNS (1), /* constant shift costs */
740 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
741 COSTS_N_INSNS (4), /* HI */
742 COSTS_N_INSNS (3), /* SI */
743 COSTS_N_INSNS (4), /* DI */
744 COSTS_N_INSNS (5)}, /* other */
745 0, /* cost of multiply per each bit set */
746 {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
747 COSTS_N_INSNS (35), /* HI */
748 COSTS_N_INSNS (51), /* SI */
749 COSTS_N_INSNS (83), /* DI */
750 COSTS_N_INSNS (83)}, /* other */
751 COSTS_N_INSNS (1), /* cost of movsx */
752 COSTS_N_INSNS (1), /* cost of movzx */
753 8, /* "large" insn */
755 4, /* cost for loading QImode using movzbl */
756 {3, 4, 3}, /* cost of loading integer registers
757 in QImode, HImode and SImode.
758 Relative to reg-reg move (2). */
759 {3, 4, 3}, /* cost of storing integer registers */
760 4, /* cost of reg,reg fld/fst */
761 {4, 4, 12}, /* cost of loading fp registers
762 in SFmode, DFmode and XFmode */
763 {6, 6, 8}, /* cost of storing fp registers
764 in SFmode, DFmode and XFmode */
765 2, /* cost of moving MMX register */
766 {3, 3}, /* cost of loading MMX registers
767 in SImode and DImode */
768 {4, 4}, /* cost of storing MMX registers
769 in SImode and DImode */
770 2, /* cost of moving SSE register */
771 {4, 4, 3}, /* cost of loading SSE registers
772 in SImode, DImode and TImode */
773 {4, 4, 5}, /* cost of storing SSE registers
774 in SImode, DImode and TImode */
775 3, /* MMX or SSE register to integer */
777 MOVD reg64, xmmreg Double FSTORE 4
778 MOVD reg32, xmmreg Double FSTORE 4
780 MOVD reg64, xmmreg Double FADD 3
782 MOVD reg32, xmmreg Double FADD 3
784 64, /* size of l1 cache. */
785 512, /* size of l2 cache. */
786 64, /* size of prefetch block */
787 /* New AMD processors never drop prefetches; if they cannot be performed
788 immediately, they are queued. We set number of simultaneous prefetches
789 to a large constant to reflect this (it probably is not a good idea not
790 to limit number of prefetches at all, as their execution also takes some
792 100, /* number of parallel prefetches */
794 COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */
795 COSTS_N_INSNS (4), /* cost of FMUL instruction. */
796 COSTS_N_INSNS (19), /* cost of FDIV instruction. */
797 COSTS_N_INSNS (2), /* cost of FABS instruction. */
798 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
799 COSTS_N_INSNS (35), /* cost of FSQRT instruction. */
801 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
802 very small blocks it is better to use loop. For large blocks, libcall can
803 do nontemporary accesses and beat inline considerably. */
804 {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
805 {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
806 {{libcall, {{8, loop}, {24, unrolled_loop},
807 {2048, rep_prefix_4_byte}, {-1, libcall}}},
808 {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
809 4, /* scalar_stmt_cost. */
810 2, /* scalar load_cost. */
811 2, /* scalar_store_cost. */
812 6, /* vec_stmt_cost. */
813 0, /* vec_to_scalar_cost. */
814 2, /* scalar_to_vec_cost. */
815 2, /* vec_align_load_cost. */
816 2, /* vec_unalign_load_cost. */
817 2, /* vec_store_cost. */
818 2, /* cond_taken_branch_cost. */
819 1, /* cond_not_taken_branch_cost. */
823 struct processor_costs pentium4_cost = {
824 COSTS_N_INSNS (1), /* cost of an add instruction */
825 COSTS_N_INSNS (3), /* cost of a lea instruction */
826 COSTS_N_INSNS (4), /* variable shift costs */
827 COSTS_N_INSNS (4), /* constant shift costs */
828 {COSTS_N_INSNS (15), /* cost of starting multiply for QI */
829 COSTS_N_INSNS (15), /* HI */
830 COSTS_N_INSNS (15), /* SI */
831 COSTS_N_INSNS (15), /* DI */
832 COSTS_N_INSNS (15)}, /* other */
833 0, /* cost of multiply per each bit set */
834 {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */
835 COSTS_N_INSNS (56), /* HI */
836 COSTS_N_INSNS (56), /* SI */
837 COSTS_N_INSNS (56), /* DI */
838 COSTS_N_INSNS (56)}, /* other */
839 COSTS_N_INSNS (1), /* cost of movsx */
840 COSTS_N_INSNS (1), /* cost of movzx */
841 16, /* "large" insn */
843 2, /* cost for loading QImode using movzbl */
844 {4, 5, 4}, /* cost of loading integer registers
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
847 {2, 3, 2}, /* cost of storing integer registers */
848 2, /* cost of reg,reg fld/fst */
849 {2, 2, 6}, /* cost of loading fp registers
850 in SFmode, DFmode and XFmode */
851 {4, 4, 6}, /* cost of storing fp registers
852 in SFmode, DFmode and XFmode */
853 2, /* cost of moving MMX register */
854 {2, 2}, /* cost of loading MMX registers
855 in SImode and DImode */
856 {2, 2}, /* cost of storing MMX registers
857 in SImode and DImode */
858 12, /* cost of moving SSE register */
859 {12, 12, 12}, /* cost of loading SSE registers
860 in SImode, DImode and TImode */
861 {2, 2, 8}, /* cost of storing SSE registers
862 in SImode, DImode and TImode */
863 10, /* MMX or SSE register to integer */
864 8, /* size of l1 cache. */
865 256, /* size of l2 cache. */
866 64, /* size of prefetch block */
867 6, /* number of parallel prefetches */
869 COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */
870 COSTS_N_INSNS (7), /* cost of FMUL instruction. */
871 COSTS_N_INSNS (43), /* cost of FDIV instruction. */
872 COSTS_N_INSNS (2), /* cost of FABS instruction. */
873 COSTS_N_INSNS (2), /* cost of FCHS instruction. */
874 COSTS_N_INSNS (43), /* cost of FSQRT instruction. */
875 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
876 DUMMY_STRINGOP_ALGS},
877 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
879 DUMMY_STRINGOP_ALGS},
880 1, /* scalar_stmt_cost. */
881 1, /* scalar load_cost. */
882 1, /* scalar_store_cost. */
883 1, /* vec_stmt_cost. */
884 1, /* vec_to_scalar_cost. */
885 1, /* scalar_to_vec_cost. */
886 1, /* vec_align_load_cost. */
887 2, /* vec_unalign_load_cost. */
888 1, /* vec_store_cost. */
889 3, /* cond_taken_branch_cost. */
890 1, /* cond_not_taken_branch_cost. */
894 struct processor_costs nocona_cost = {
895 COSTS_N_INSNS (1), /* cost of an add instruction */
896 COSTS_N_INSNS (1), /* cost of a lea instruction */
897 COSTS_N_INSNS (1), /* variable shift costs */
898 COSTS_N_INSNS (1), /* constant shift costs */
899 {COSTS_N_INSNS (10), /* cost of starting multiply for QI */
900 COSTS_N_INSNS (10), /* HI */
901 COSTS_N_INSNS (10), /* SI */
902 COSTS_N_INSNS (10), /* DI */
903 COSTS_N_INSNS (10)}, /* other */
904 0, /* cost of multiply per each bit set */
905 {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */
906 COSTS_N_INSNS (66), /* HI */
907 COSTS_N_INSNS (66), /* SI */
908 COSTS_N_INSNS (66), /* DI */
909 COSTS_N_INSNS (66)}, /* other */
910 COSTS_N_INSNS (1), /* cost of movsx */
911 COSTS_N_INSNS (1), /* cost of movzx */
912 16, /* "large" insn */
914 4, /* cost for loading QImode using movzbl */
915 {4, 4, 4}, /* cost of loading integer registers
916 in QImode, HImode and SImode.
917 Relative to reg-reg move (2). */
918 {4, 4, 4}, /* cost of storing integer registers */
919 3, /* cost of reg,reg fld/fst */
920 {12, 12, 12}, /* cost of loading fp registers
921 in SFmode, DFmode and XFmode */
922 {4, 4, 4}, /* cost of storing fp registers
923 in SFmode, DFmode and XFmode */
924 6, /* cost of moving MMX register */
925 {12, 12}, /* cost of loading MMX registers
926 in SImode and DImode */
927 {12, 12}, /* cost of storing MMX registers
928 in SImode and DImode */
929 6, /* cost of moving SSE register */
930 {12, 12, 12}, /* cost of loading SSE registers
931 in SImode, DImode and TImode */
932 {12, 12, 12}, /* cost of storing SSE registers
933 in SImode, DImode and TImode */
934 8, /* MMX or SSE register to integer */
935 8, /* size of l1 cache. */
936 1024, /* size of l2 cache. */
937 128, /* size of prefetch block */
938 8, /* number of parallel prefetches */
940 COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
941 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
942 COSTS_N_INSNS (40), /* cost of FDIV instruction. */
943 COSTS_N_INSNS (3), /* cost of FABS instruction. */
944 COSTS_N_INSNS (3), /* cost of FCHS instruction. */
945 COSTS_N_INSNS (44), /* cost of FSQRT instruction. */
946 {{libcall, {{12, loop_1_byte}, {-1, rep_prefix_4_byte}}},
947 {libcall, {{32, loop}, {20000, rep_prefix_8_byte},
948 {100000, unrolled_loop}, {-1, libcall}}}},
949 {{libcall, {{6, loop_1_byte}, {48, loop}, {20480, rep_prefix_4_byte},
951 {libcall, {{24, loop}, {64, unrolled_loop},
952 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
953 1, /* scalar_stmt_cost. */
954 1, /* scalar load_cost. */
955 1, /* scalar_store_cost. */
956 1, /* vec_stmt_cost. */
957 1, /* vec_to_scalar_cost. */
958 1, /* scalar_to_vec_cost. */
959 1, /* vec_align_load_cost. */
960 2, /* vec_unalign_load_cost. */
961 1, /* vec_store_cost. */
962 3, /* cond_taken_branch_cost. */
963 1, /* cond_not_taken_branch_cost. */
967 struct processor_costs core2_cost = {
968 COSTS_N_INSNS (1), /* cost of an add instruction */
969 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
970 COSTS_N_INSNS (1), /* variable shift costs */
971 COSTS_N_INSNS (1), /* constant shift costs */
972 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
973 COSTS_N_INSNS (3), /* HI */
974 COSTS_N_INSNS (3), /* SI */
975 COSTS_N_INSNS (3), /* DI */
976 COSTS_N_INSNS (3)}, /* other */
977 0, /* cost of multiply per each bit set */
978 {COSTS_N_INSNS (22), /* cost of a divide/mod for QI */
979 COSTS_N_INSNS (22), /* HI */
980 COSTS_N_INSNS (22), /* SI */
981 COSTS_N_INSNS (22), /* DI */
982 COSTS_N_INSNS (22)}, /* other */
983 COSTS_N_INSNS (1), /* cost of movsx */
984 COSTS_N_INSNS (1), /* cost of movzx */
985 8, /* "large" insn */
987 2, /* cost for loading QImode using movzbl */
988 {6, 6, 6}, /* cost of loading integer registers
989 in QImode, HImode and SImode.
990 Relative to reg-reg move (2). */
991 {4, 4, 4}, /* cost of storing integer registers */
992 2, /* cost of reg,reg fld/fst */
993 {6, 6, 6}, /* cost of loading fp registers
994 in SFmode, DFmode and XFmode */
995 {4, 4, 4}, /* cost of storing fp registers
996 in SFmode, DFmode and XFmode */
997 2, /* cost of moving MMX register */
998 {6, 6}, /* cost of loading MMX registers
999 in SImode and DImode */
1000 {4, 4}, /* cost of storing MMX registers
1001 in SImode and DImode */
1002 2, /* cost of moving SSE register */
1003 {6, 6, 6}, /* cost of loading SSE registers
1004 in SImode, DImode and TImode */
1005 {4, 4, 4}, /* cost of storing SSE registers
1006 in SImode, DImode and TImode */
1007 2, /* MMX or SSE register to integer */
1008 32, /* size of l1 cache. */
1009 2048, /* size of l2 cache. */
1010 128, /* size of prefetch block */
1011 8, /* number of parallel prefetches */
1012 3, /* Branch cost */
1013 COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */
1014 COSTS_N_INSNS (5), /* cost of FMUL instruction. */
1015 COSTS_N_INSNS (32), /* cost of FDIV instruction. */
1016 COSTS_N_INSNS (1), /* cost of FABS instruction. */
1017 COSTS_N_INSNS (1), /* cost of FCHS instruction. */
1018 COSTS_N_INSNS (58), /* cost of FSQRT instruction. */
1019 {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
1020 {libcall, {{32, loop}, {64, rep_prefix_4_byte},
1021 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1022 {{libcall, {{8, loop}, {15, unrolled_loop},
1023 {2048, rep_prefix_4_byte}, {-1, libcall}}},
1024 {libcall, {{24, loop}, {32, unrolled_loop},
1025 {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1026 1, /* scalar_stmt_cost. */
1027 1, /* scalar load_cost. */
1028 1, /* scalar_store_cost. */
1029 1, /* vec_stmt_cost. */
1030 1, /* vec_to_scalar_cost. */
1031 1, /* scalar_to_vec_cost. */
1032 1, /* vec_align_load_cost. */
1033 2, /* vec_unalign_load_cost. */
1034 1, /* vec_store_cost. */
1035 3, /* cond_taken_branch_cost. */
1036 1, /* cond_not_taken_branch_cost. */
1039 /* Generic64 should produce code tuned for Nocona and K8. */
1041 struct processor_costs generic64_cost = {
1042 COSTS_N_INSNS (1), /* cost of an add instruction */
1043 /* On all chips taken into consideration lea is 2 cycles and more. With
1044 this cost however our current implementation of synth_mult results in
1045 use of unnecessary temporary registers causing regression on several
1046 SPECfp benchmarks. */
1047 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1048 COSTS_N_INSNS (1), /* variable shift costs */
1049 COSTS_N_INSNS (1), /* constant shift costs */
1050 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1051 COSTS_N_INSNS (4), /* HI */
1052 COSTS_N_INSNS (3), /* SI */
1053 COSTS_N_INSNS (4), /* DI */
1054 COSTS_N_INSNS (2)}, /* other */
1055 0, /* cost of multiply per each bit set */
1056 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1057 COSTS_N_INSNS (26), /* HI */
1058 COSTS_N_INSNS (42), /* SI */
1059 COSTS_N_INSNS (74), /* DI */
1060 COSTS_N_INSNS (74)}, /* other */
1061 COSTS_N_INSNS (1), /* cost of movsx */
1062 COSTS_N_INSNS (1), /* cost of movzx */
1063 8, /* "large" insn */
1064 17, /* MOVE_RATIO */
1065 4, /* cost for loading QImode using movzbl */
1066 {4, 4, 4}, /* cost of loading integer registers
1067 in QImode, HImode and SImode.
1068 Relative to reg-reg move (2). */
1069 {4, 4, 4}, /* cost of storing integer registers */
1070 4, /* cost of reg,reg fld/fst */
1071 {12, 12, 12}, /* cost of loading fp registers
1072 in SFmode, DFmode and XFmode */
1073 {6, 6, 8}, /* cost of storing fp registers
1074 in SFmode, DFmode and XFmode */
1075 2, /* cost of moving MMX register */
1076 {8, 8}, /* cost of loading MMX registers
1077 in SImode and DImode */
1078 {8, 8}, /* cost of storing MMX registers
1079 in SImode and DImode */
1080 2, /* cost of moving SSE register */
1081 {8, 8, 8}, /* cost of loading SSE registers
1082 in SImode, DImode and TImode */
1083 {8, 8, 8}, /* cost of storing SSE registers
1084 in SImode, DImode and TImode */
1085 5, /* MMX or SSE register to integer */
1086 32, /* size of l1 cache. */
1087 512, /* size of l2 cache. */
1088 64, /* size of prefetch block */
1089 6, /* number of parallel prefetches */
1090 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value
1091 is increased to perhaps more appropriate value of 5. */
1092 3, /* Branch cost */
1093 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1094 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1095 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1096 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1097 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1098 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1099 {DUMMY_STRINGOP_ALGS,
1100 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1101 {DUMMY_STRINGOP_ALGS,
1102 {libcall, {{32, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
1103 1, /* scalar_stmt_cost. */
1104 1, /* scalar load_cost. */
1105 1, /* scalar_store_cost. */
1106 1, /* vec_stmt_cost. */
1107 1, /* vec_to_scalar_cost. */
1108 1, /* scalar_to_vec_cost. */
1109 1, /* vec_align_load_cost. */
1110 2, /* vec_unalign_load_cost. */
1111 1, /* vec_store_cost. */
1112 3, /* cond_taken_branch_cost. */
1113 1, /* cond_not_taken_branch_cost. */
1116 /* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */
1118 struct processor_costs generic32_cost = {
1119 COSTS_N_INSNS (1), /* cost of an add instruction */
1120 COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
1121 COSTS_N_INSNS (1), /* variable shift costs */
1122 COSTS_N_INSNS (1), /* constant shift costs */
1123 {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
1124 COSTS_N_INSNS (4), /* HI */
1125 COSTS_N_INSNS (3), /* SI */
1126 COSTS_N_INSNS (4), /* DI */
1127 COSTS_N_INSNS (2)}, /* other */
1128 0, /* cost of multiply per each bit set */
1129 {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
1130 COSTS_N_INSNS (26), /* HI */
1131 COSTS_N_INSNS (42), /* SI */
1132 COSTS_N_INSNS (74), /* DI */
1133 COSTS_N_INSNS (74)}, /* other */
1134 COSTS_N_INSNS (1), /* cost of movsx */
1135 COSTS_N_INSNS (1), /* cost of movzx */
1136 8, /* "large" insn */
1137 17, /* MOVE_RATIO */
1138 4, /* cost for loading QImode using movzbl */
1139 {4, 4, 4}, /* cost of loading integer registers
1140 in QImode, HImode and SImode.
1141 Relative to reg-reg move (2). */
1142 {4, 4, 4}, /* cost of storing integer registers */
1143 4, /* cost of reg,reg fld/fst */
1144 {12, 12, 12}, /* cost of loading fp registers
1145 in SFmode, DFmode and XFmode */
1146 {6, 6, 8}, /* cost of storing fp registers
1147 in SFmode, DFmode and XFmode */
1148 2, /* cost of moving MMX register */
1149 {8, 8}, /* cost of loading MMX registers
1150 in SImode and DImode */
1151 {8, 8}, /* cost of storing MMX registers
1152 in SImode and DImode */
1153 2, /* cost of moving SSE register */
1154 {8, 8, 8}, /* cost of loading SSE registers
1155 in SImode, DImode and TImode */
1156 {8, 8, 8}, /* cost of storing SSE registers
1157 in SImode, DImode and TImode */
1158 5, /* MMX or SSE register to integer */
1159 32, /* size of l1 cache. */
1160 256, /* size of l2 cache. */
1161 64, /* size of prefetch block */
1162 6, /* number of parallel prefetches */
1163 3, /* Branch cost */
1164 COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
1165 COSTS_N_INSNS (8), /* cost of FMUL instruction. */
1166 COSTS_N_INSNS (20), /* cost of FDIV instruction. */
1167 COSTS_N_INSNS (8), /* cost of FABS instruction. */
1168 COSTS_N_INSNS (8), /* cost of FCHS instruction. */
1169 COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
1170 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1171 DUMMY_STRINGOP_ALGS},
1172 {{libcall, {{32, loop}, {8192, rep_prefix_4_byte}, {-1, libcall}}},
1173 DUMMY_STRINGOP_ALGS},
1174 1, /* scalar_stmt_cost. */
1175 1, /* scalar load_cost. */
1176 1, /* scalar_store_cost. */
1177 1, /* vec_stmt_cost. */
1178 1, /* vec_to_scalar_cost. */
1179 1, /* scalar_to_vec_cost. */
1180 1, /* vec_align_load_cost. */
1181 2, /* vec_unalign_load_cost. */
1182 1, /* vec_store_cost. */
1183 3, /* cond_taken_branch_cost. */
1184 1, /* cond_not_taken_branch_cost. */
1187 const struct processor_costs *ix86_cost = &pentium_cost;
1189 /* Processor feature/optimization bitmasks. */
1190 #define m_386 (1<<PROCESSOR_I386)
1191 #define m_486 (1<<PROCESSOR_I486)
1192 #define m_PENT (1<<PROCESSOR_PENTIUM)
1193 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1194 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1195 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1196 #define m_CORE2 (1<<PROCESSOR_CORE2)
1198 #define m_GEODE (1<<PROCESSOR_GEODE)
1199 #define m_K6 (1<<PROCESSOR_K6)
1200 #define m_K6_GEODE (m_K6 | m_GEODE)
1201 #define m_K8 (1<<PROCESSOR_K8)
1202 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1203 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1204 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1205 #define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10)
1207 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1208 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1210 /* Generic instruction choice should be common subset of supported CPUs
1211 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1212 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1214 /* Feature tests against the various tunings. */
1215 unsigned char ix86_tune_features[X86_TUNE_LAST];
1217 /* Feature tests against the various tunings used to create ix86_tune_features
1218 based on the processor mask. */
1219 static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
1220 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1221 negatively, so enabling for Generic64 seems like good code size
1222 tradeoff. We can't enable it for 32bit generic because it does not
1223 work well with PPro base chips. */
1224 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC64,
1226 /* X86_TUNE_PUSH_MEMORY */
1227 m_386 | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4
1228 | m_NOCONA | m_CORE2 | m_GENERIC,
1230 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1233 /* X86_TUNE_UNROLL_STRLEN */
1234 m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
1236 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
1237 m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
1239 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1240 on simulation result. But after P4 was made, no performance benefit
1241 was observed with branch hints. It also increases the code size.
1242 As a result, icc never generates branch hints. */
1245 /* X86_TUNE_DOUBLE_WITH_ADD */
1248 /* X86_TUNE_USE_SAHF */
1249 m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
1250 | m_NOCONA | m_CORE2 | m_GENERIC,
1252 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1253 partial dependencies. */
1254 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
1255 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
1257 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1258 register stalls on Generic32 compilation setting as well. However
1259 in current implementation the partial register stalls are not eliminated
1260 very well - they can be introduced via subregs synthesized by combine
1261 and can happen in caller/callee saving sequences. Because this option
1262 pays back little on PPro based chips and is in conflict with partial reg
1263 dependencies used by Athlon/P4 based chips, it is better to leave it off
1264 for generic32 for now. */
1267 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1268 m_CORE2 | m_GENERIC,
1270 /* X86_TUNE_USE_HIMODE_FIOP */
1271 m_386 | m_486 | m_K6_GEODE,
1273 /* X86_TUNE_USE_SIMODE_FIOP */
1274 ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
1276 /* X86_TUNE_USE_MOV0 */
1279 /* X86_TUNE_USE_CLTD */
1280 ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
1282 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1285 /* X86_TUNE_SPLIT_LONG_MOVES */
1288 /* X86_TUNE_READ_MODIFY_WRITE */
1291 /* X86_TUNE_READ_MODIFY */
1294 /* X86_TUNE_PROMOTE_QIMODE */
1295 m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
1296 | m_GENERIC /* | m_PENT4 ? */,
1298 /* X86_TUNE_FAST_PREFIX */
1299 ~(m_PENT | m_486 | m_386),
1301 /* X86_TUNE_SINGLE_STRINGOP */
1302 m_386 | m_PENT4 | m_NOCONA,
1304 /* X86_TUNE_QIMODE_MATH */
1307 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1308 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1309 might be considered for Generic32 if our scheme for avoiding partial
1310 stalls was more effective. */
1313 /* X86_TUNE_PROMOTE_QI_REGS */
1316 /* X86_TUNE_PROMOTE_HI_REGS */
1319 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
1320 m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1322 /* X86_TUNE_ADD_ESP_8 */
1323 m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
1324 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1326 /* X86_TUNE_SUB_ESP_4 */
1327 m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1329 /* X86_TUNE_SUB_ESP_8 */
1330 m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
1331 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1333 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1334 for DFmode copies */
1335 ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
1336 | m_GENERIC | m_GEODE),
1338 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1339 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1341 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1342 conflict here in between PPro/Pentium4 based chips that thread 128bit
1343 SSE registers as single units versus K8 based chips that divide SSE
1344 registers to two 64bit halves. This knob promotes all store destinations
1345 to be 128bit to allow register renaming on 128bit SSE units, but usually
1346 results in one extra microop on 64bit SSE units. Experimental results
1347 shows that disabling this option on P4 brings over 20% SPECfp regression,
1348 while enabling it on K8 brings roughly 2.4% regression that can be partly
1349 masked by careful scheduling of moves. */
1350 m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
1352 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
1355 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1356 are resolved on SSE register parts instead of whole registers, so we may
1357 maintain just lower part of scalar values in proper format leaving the
1358 upper part undefined. */
1361 /* X86_TUNE_SSE_TYPELESS_STORES */
1364 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1365 m_PPRO | m_PENT4 | m_NOCONA,
1367 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1368 m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1370 /* X86_TUNE_PROLOGUE_USING_MOVE */
1371 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1373 /* X86_TUNE_EPILOGUE_USING_MOVE */
1374 m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
1376 /* X86_TUNE_SHIFT1 */
1379 /* X86_TUNE_USE_FFREEP */
1382 /* X86_TUNE_INTER_UNIT_MOVES */
1383 ~(m_AMD_MULTIPLE | m_GENERIC),
1385 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1388 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1389 than 4 branch instructions in the 16 byte window. */
1390 m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
1392 /* X86_TUNE_SCHEDULE */
1393 m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
1395 /* X86_TUNE_USE_BT */
1396 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1398 /* X86_TUNE_USE_INCDEC */
1399 ~(m_PENT4 | m_NOCONA | m_GENERIC),
1401 /* X86_TUNE_PAD_RETURNS */
1402 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
1404 /* X86_TUNE_EXT_80387_CONSTANTS */
1405 m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
1407 /* X86_TUNE_SHORTEN_X87_SSE */
1410 /* X86_TUNE_AVOID_VECTOR_DECODE */
1413 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1414 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1417 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1418 vector path on AMD machines. */
1419 m_K8 | m_GENERIC64 | m_AMDFAM10,
1421 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1423 m_K8 | m_GENERIC64 | m_AMDFAM10,
1425 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1429 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1430 but one byte longer. */
1433 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1434 operand that cannot be represented using a modRM byte. The XOR
1435 replacement is long decoded, so this split helps here as well. */
1438 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1440 m_AMDFAM10 | m_GENERIC,
1442 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1443 from integer to FP. */
1446 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
1447 with a subsequent conditional jump instruction into a single
1448 compare-and-branch uop. */
1452 /* Feature tests against the various architecture variations. */
1453 unsigned char ix86_arch_features[X86_ARCH_LAST];
1455 /* Feature tests against the various architecture variations, used to create
1456 ix86_arch_features based on the processor mask. */
1457 static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = {
1458 /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */
1459 ~(m_386 | m_486 | m_PENT | m_K6),
1461 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
1464 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
1467 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
1470 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
1474 static const unsigned int x86_accumulate_outgoing_args
1475 = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
1477 static const unsigned int x86_arch_always_fancy_math_387
1478 = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
1479 | m_NOCONA | m_CORE2 | m_GENERIC;
1481 static enum stringop_alg stringop_alg = no_stringop;
1483 /* In case the average insn count for single function invocation is
1484 lower than this constant, emit fast (but longer) prologue and
1486 #define FAST_PROLOGUE_INSN_COUNT 20
1488 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
1489 static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
1490 static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
1491 static const char *const hi_reg_name[] = HI_REGISTER_NAMES;
1493 /* Array of the smallest class containing reg number REGNO, indexed by
1494 REGNO. Used by REGNO_REG_CLASS in i386.h. */
1496 enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
1498 /* ax, dx, cx, bx */
1499 AREG, DREG, CREG, BREG,
1500 /* si, di, bp, sp */
1501 SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
1503 FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
1504 FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
1507 /* flags, fpsr, fpcr, frame */
1508 NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
1510 SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1513 MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
1516 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1517 NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
1518 /* SSE REX registers */
1519 SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
1523 /* The "default" register map used in 32bit mode. */
1525 int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
1527 0, 2, 1, 3, 6, 7, 4, 5, /* general regs */
1528 12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
1529 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1530 21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
1531 29, 30, 31, 32, 33, 34, 35, 36, /* MMX */
1532 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1533 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1536 /* The "default" register map used in 64bit mode. */
1538 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
1540 0, 1, 2, 3, 4, 5, 6, 7, /* general regs */
1541 33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
1542 -1, -1, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1543 17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
1544 41, 42, 43, 44, 45, 46, 47, 48, /* MMX */
1545 8,9,10,11,12,13,14,15, /* extended integer registers */
1546 25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
1549 /* Define the register numbers to be used in Dwarf debugging information.
1550 The SVR4 reference port C compiler uses the following register numbers
1551 in its Dwarf output code:
1552 0 for %eax (gcc regno = 0)
1553 1 for %ecx (gcc regno = 2)
1554 2 for %edx (gcc regno = 1)
1555 3 for %ebx (gcc regno = 3)
1556 4 for %esp (gcc regno = 7)
1557 5 for %ebp (gcc regno = 6)
1558 6 for %esi (gcc regno = 4)
1559 7 for %edi (gcc regno = 5)
1560 The following three DWARF register numbers are never generated by
1561 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
1562 believes these numbers have these meanings.
1563 8 for %eip (no gcc equivalent)
1564 9 for %eflags (gcc regno = 17)
1565 10 for %trapno (no gcc equivalent)
1566 It is not at all clear how we should number the FP stack registers
1567 for the x86 architecture. If the version of SDB on x86/svr4 were
1568 a bit less brain dead with respect to floating-point then we would
1569 have a precedent to follow with respect to DWARF register numbers
1570 for x86 FP registers, but the SDB on x86/svr4 is so completely
1571 broken with respect to FP registers that it is hardly worth thinking
1572 of it as something to strive for compatibility with.
1573 The version of x86/svr4 SDB I have at the moment does (partially)
1574 seem to believe that DWARF register number 11 is associated with
1575 the x86 register %st(0), but that's about all. Higher DWARF
1576 register numbers don't seem to be associated with anything in
1577 particular, and even for DWARF regno 11, SDB only seems to under-
1578 stand that it should say that a variable lives in %st(0) (when
1579 asked via an `=' command) if we said it was in DWARF regno 11,
1580 but SDB still prints garbage when asked for the value of the
1581 variable in question (via a `/' command).
1582 (Also note that the labels SDB prints for various FP stack regs
1583 when doing an `x' command are all wrong.)
1584 Note that these problems generally don't affect the native SVR4
1585 C compiler because it doesn't allow the use of -O with -g and
1586 because when it is *not* optimizing, it allocates a memory
1587 location for each floating-point variable, and the memory
1588 location is what gets described in the DWARF AT_location
1589 attribute for the variable in question.
1590 Regardless of the severe mental illness of the x86/svr4 SDB, we
1591 do something sensible here and we use the following DWARF
1592 register numbers. Note that these are all stack-top-relative
1594 11 for %st(0) (gcc regno = 8)
1595 12 for %st(1) (gcc regno = 9)
1596 13 for %st(2) (gcc regno = 10)
1597 14 for %st(3) (gcc regno = 11)
1598 15 for %st(4) (gcc regno = 12)
1599 16 for %st(5) (gcc regno = 13)
1600 17 for %st(6) (gcc regno = 14)
1601 18 for %st(7) (gcc regno = 15)
1603 int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
1605 0, 2, 1, 3, 6, 7, 5, 4, /* general regs */
1606 11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
1607 -1, 9, -1, -1, -1, /* arg, flags, fpsr, fpcr, frame */
1608 21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
1609 29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
1610 -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
1611 -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
1614 /* Test and compare insns in i386.md store the information needed to
1615 generate branch and scc insns here. */
1617 rtx ix86_compare_op0 = NULL_RTX;
1618 rtx ix86_compare_op1 = NULL_RTX;
1619 rtx ix86_compare_emitted = NULL_RTX;
1621 /* Define parameter passing and return registers. */
1623 static int const x86_64_int_parameter_registers[6] =
1625 DI_REG, SI_REG, DX_REG, CX_REG, R8_REG, R9_REG
1628 static int const x86_64_ms_abi_int_parameter_registers[4] =
1630 CX_REG, DX_REG, R8_REG, R9_REG
1633 static int const x86_64_int_return_registers[4] =
1635 AX_REG, DX_REG, DI_REG, SI_REG
1638 /* Define the structure for the machine field in struct function. */
1640 struct stack_local_entry GTY(())
1642 unsigned short mode;
1645 struct stack_local_entry *next;
1648 /* Structure describing stack frame layout.
1649 Stack grows downward:
1655 saved frame pointer if frame_pointer_needed
1656 <- HARD_FRAME_POINTER
1665 [va_arg registers] (
1666 > to_allocate <- FRAME_POINTER
1678 HOST_WIDE_INT frame;
1680 int outgoing_arguments_size;
1683 HOST_WIDE_INT to_allocate;
1684 /* The offsets relative to ARG_POINTER. */
1685 HOST_WIDE_INT frame_pointer_offset;
1686 HOST_WIDE_INT hard_frame_pointer_offset;
1687 HOST_WIDE_INT stack_pointer_offset;
1689 /* When save_regs_using_mov is set, emit prologue using
1690 move instead of push instructions. */
1691 bool save_regs_using_mov;
1694 /* Code model option. */
1695 enum cmodel ix86_cmodel;
1697 enum asm_dialect ix86_asm_dialect = ASM_ATT;
1699 enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;
1701 /* Which unit we are generating floating point math for. */
1702 enum fpmath_unit ix86_fpmath;
1704 /* Which cpu are we scheduling for. */
1705 enum attr_cpu ix86_schedule;
1707 /* Which cpu are we optimizing for. */
1708 enum processor_type ix86_tune;
1710 /* Which instruction set architecture to use. */
1711 enum processor_type ix86_arch;
1713 /* true if sse prefetch instruction is not NOOP. */
1714 int x86_prefetch_sse;
1716 /* ix86_regparm_string as a number */
1717 static int ix86_regparm;
1719 /* -mstackrealign option */
1720 extern int ix86_force_align_arg_pointer;
1721 static const char ix86_force_align_arg_pointer_string[]
1722 = "force_align_arg_pointer";
1724 static rtx (*ix86_gen_leave) (void);
1725 static rtx (*ix86_gen_pop1) (rtx);
1726 static rtx (*ix86_gen_add3) (rtx, rtx, rtx);
1727 static rtx (*ix86_gen_sub3) (rtx, rtx, rtx);
1728 static rtx (*ix86_gen_sub3_carry) (rtx, rtx, rtx, rtx);
1729 static rtx (*ix86_gen_one_cmpl2) (rtx, rtx);
1730 static rtx (*ix86_gen_monitor) (rtx, rtx, rtx);
1731 static rtx (*ix86_gen_andsp) (rtx, rtx, rtx);
1733 /* Preferred alignment for stack boundary in bits. */
1734 unsigned int ix86_preferred_stack_boundary;
1736 /* Alignment for incoming stack boundary in bits specified at
1738 static unsigned int ix86_user_incoming_stack_boundary;
1740 /* Default alignment for incoming stack boundary in bits. */
1741 static unsigned int ix86_default_incoming_stack_boundary;
1743 /* Alignment for incoming stack boundary in bits. */
1744 unsigned int ix86_incoming_stack_boundary;
1746 /* Values 1-5: see jump.c */
1747 int ix86_branch_cost;
1749 /* Calling abi specific va_list type nodes. */
1750 static GTY(()) tree sysv_va_list_type_node;
1751 static GTY(()) tree ms_va_list_type_node;
1753 /* Variables which are this size or smaller are put in the data/bss
1754 or ldata/lbss sections. */
1756 int ix86_section_threshold = 65536;
1758 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
1759 char internal_label_prefix[16];
1760 int internal_label_prefix_len;
1762 /* Fence to use after loop using movnt. */
1765 /* Register class used for passing given 64bit part of the argument.
1766 These represent classes as documented by the PS ABI, with the exception
1767 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
1768 use SF or DFmode move instead of DImode to avoid reformatting penalties.
1770 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
1771 whenever possible (upper half does contain padding). */
1772 enum x86_64_reg_class
1775 X86_64_INTEGER_CLASS,
1776 X86_64_INTEGERSI_CLASS,
1783 X86_64_COMPLEX_X87_CLASS,
1787 #define MAX_CLASSES 4
1789 /* Table of constants used by fldpi, fldln2, etc.... */
1790 static REAL_VALUE_TYPE ext_80387_constants_table [5];
1791 static bool ext_80387_constants_init = 0;
1794 static struct machine_function * ix86_init_machine_status (void);
1795 static rtx ix86_function_value (const_tree, const_tree, bool);
1796 static int ix86_function_regparm (const_tree, const_tree);
1797 static void ix86_compute_frame_layout (struct ix86_frame *);
1798 static bool ix86_expand_vector_init_one_nonzero (bool, enum machine_mode,
1800 static void ix86_add_new_builtins (int);
1802 enum ix86_function_specific_strings
1804 IX86_FUNCTION_SPECIFIC_ARCH,
1805 IX86_FUNCTION_SPECIFIC_TUNE,
1806 IX86_FUNCTION_SPECIFIC_FPMATH,
1807 IX86_FUNCTION_SPECIFIC_MAX
1810 static char *ix86_target_string (int, int, const char *, const char *,
1811 const char *, bool);
1812 static void ix86_debug_options (void) ATTRIBUTE_UNUSED;
1813 static void ix86_function_specific_save (struct cl_target_option *);
1814 static void ix86_function_specific_restore (struct cl_target_option *);
1815 static void ix86_function_specific_print (FILE *, int,
1816 struct cl_target_option *);
1817 static bool ix86_valid_target_attribute_p (tree, tree, tree, int);
1818 static bool ix86_valid_target_attribute_inner_p (tree, char *[]);
1819 static bool ix86_can_inline_p (tree, tree);
1820 static void ix86_set_current_function (tree);
1823 /* The svr4 ABI for the i386 says that records and unions are returned
1825 #ifndef DEFAULT_PCC_STRUCT_RETURN
1826 #define DEFAULT_PCC_STRUCT_RETURN 1
1829 /* Whether -mtune= or -march= were specified */
1830 static int ix86_tune_defaulted;
1831 static int ix86_arch_specified;
1833 /* Bit flags that specify the ISA we are compiling for. */
1834 int ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT;
1836 /* A mask of ix86_isa_flags that includes bit X if X
1837 was set or cleared on the command line. */
1838 static int ix86_isa_flags_explicit;
1840 /* Define a set of ISAs which are available when a given ISA is
1841 enabled. MMX and SSE ISAs are handled separately. */
1843 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
1844 #define OPTION_MASK_ISA_3DNOW_SET \
1845 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
1847 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
1848 #define OPTION_MASK_ISA_SSE2_SET \
1849 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
1850 #define OPTION_MASK_ISA_SSE3_SET \
1851 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
1852 #define OPTION_MASK_ISA_SSSE3_SET \
1853 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
1854 #define OPTION_MASK_ISA_SSE4_1_SET \
1855 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
1856 #define OPTION_MASK_ISA_SSE4_2_SET \
1857 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
1858 #define OPTION_MASK_ISA_AVX_SET \
1859 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET)
1860 #define OPTION_MASK_ISA_FMA_SET \
1861 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
1863 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
1865 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
1867 #define OPTION_MASK_ISA_SSE4A_SET \
1868 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
1869 #define OPTION_MASK_ISA_SSE5_SET \
1870 (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
1872 /* AES and PCLMUL need SSE2 because they use xmm registers */
1873 #define OPTION_MASK_ISA_AES_SET \
1874 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
1875 #define OPTION_MASK_ISA_PCLMUL_SET \
1876 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
1878 #define OPTION_MASK_ISA_ABM_SET \
1879 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
1880 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
1881 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
1882 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
1884 /* Define a set of ISAs which aren't available when a given ISA is
1885 disabled. MMX and SSE ISAs are handled separately. */
1887 #define OPTION_MASK_ISA_MMX_UNSET \
1888 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
1889 #define OPTION_MASK_ISA_3DNOW_UNSET \
1890 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
1891 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
1893 #define OPTION_MASK_ISA_SSE_UNSET \
1894 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
1895 #define OPTION_MASK_ISA_SSE2_UNSET \
1896 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
1897 #define OPTION_MASK_ISA_SSE3_UNSET \
1898 (OPTION_MASK_ISA_SSE3 \
1899 | OPTION_MASK_ISA_SSSE3_UNSET \
1900 | OPTION_MASK_ISA_SSE4A_UNSET )
1901 #define OPTION_MASK_ISA_SSSE3_UNSET \
1902 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
1903 #define OPTION_MASK_ISA_SSE4_1_UNSET \
1904 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
1905 #define OPTION_MASK_ISA_SSE4_2_UNSET \
1906 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
1907 #define OPTION_MASK_ISA_AVX_UNSET \
1908 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET)
1909 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
1911 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
1913 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
1915 #define OPTION_MASK_ISA_SSE4A_UNSET \
1916 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
1917 #define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
1918 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
1919 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
1920 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
1921 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
1922 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
1923 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
1925 /* Vectorization library interface and handlers. */
1926 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
1927 static tree ix86_veclibabi_svml (enum built_in_function, tree, tree);
1928 static tree ix86_veclibabi_acml (enum built_in_function, tree, tree);
1930 /* Processor target table, indexed by processor number */
1933 const struct processor_costs *cost; /* Processor costs */
1934 const int align_loop; /* Default alignments. */
1935 const int align_loop_max_skip;
1936 const int align_jump;
1937 const int align_jump_max_skip;
1938 const int align_func;
1941 static const struct ptt processor_target_table[PROCESSOR_max] =
1943 {&i386_cost, 4, 3, 4, 3, 4},
1944 {&i486_cost, 16, 15, 16, 15, 16},
1945 {&pentium_cost, 16, 7, 16, 7, 16},
1946 {&pentiumpro_cost, 16, 15, 16, 10, 16},
1947 {&geode_cost, 0, 0, 0, 0, 0},
1948 {&k6_cost, 32, 7, 32, 7, 32},
1949 {&athlon_cost, 16, 7, 16, 7, 16},
1950 {&pentium4_cost, 0, 0, 0, 0, 0},
1951 {&k8_cost, 16, 7, 16, 7, 16},
1952 {&nocona_cost, 0, 0, 0, 0, 0},
1953 {&core2_cost, 16, 10, 16, 10, 16},
1954 {&generic32_cost, 16, 7, 16, 7, 16},
1955 {&generic64_cost, 16, 10, 16, 10, 16},
1956 {&amdfam10_cost, 32, 24, 32, 7, 32}
1959 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
1984 /* Implement TARGET_HANDLE_OPTION. */
1987 ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value)
1994 ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
1995 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
1999 ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
2000 ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
2007 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
2008 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
2012 ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
2013 ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
2023 ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
2024 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
2028 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
2029 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
2036 ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
2037 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
2041 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
2042 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
2049 ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
2050 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
2054 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
2055 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
2062 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
2063 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
2067 ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
2068 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
2075 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
2076 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
2080 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
2081 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
2088 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
2089 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
2093 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
2094 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
2101 ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
2102 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
2106 ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
2107 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
2114 ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
2115 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
2119 ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
2120 ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
2125 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
2126 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
2130 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
2131 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
2137 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
2138 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
2142 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
2143 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
2150 ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
2151 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
2155 ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
2156 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
2163 ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
2164 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
2168 ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
2169 ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
2176 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
2177 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
2181 ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
2182 ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
2189 ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
2190 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
2194 ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
2195 ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
2202 ix86_isa_flags |= OPTION_MASK_ISA_CX16_SET;
2203 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_SET;
2207 ix86_isa_flags &= ~OPTION_MASK_ISA_CX16_UNSET;
2208 ix86_isa_flags_explicit |= OPTION_MASK_ISA_CX16_UNSET;
2215 ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
2216 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
2220 ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
2221 ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
2228 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
2229 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
2233 ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
2234 ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
2243 /* Return a string the documents the current -m options. The caller is
2244 responsible for freeing the string. */
2247 ix86_target_string (int isa, int flags, const char *arch, const char *tune,
2248 const char *fpmath, bool add_nl_p)
2250 struct ix86_target_opts
2252 const char *option; /* option string */
2253 int mask; /* isa mask options */
2256 /* This table is ordered so that options like -msse5 or -msse4.2 that imply
2257 preceding options while match those first. */
2258 static struct ix86_target_opts isa_opts[] =
2260 { "-m64", OPTION_MASK_ISA_64BIT },
2261 { "-msse5", OPTION_MASK_ISA_SSE5 },
2262 { "-msse4a", OPTION_MASK_ISA_SSE4A },
2263 { "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
2264 { "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
2265 { "-mssse3", OPTION_MASK_ISA_SSSE3 },
2266 { "-msse3", OPTION_MASK_ISA_SSE3 },
2267 { "-msse2", OPTION_MASK_ISA_SSE2 },
2268 { "-msse", OPTION_MASK_ISA_SSE },
2269 { "-m3dnow", OPTION_MASK_ISA_3DNOW },
2270 { "-m3dnowa", OPTION_MASK_ISA_3DNOW_A },
2271 { "-mmmx", OPTION_MASK_ISA_MMX },
2272 { "-mabm", OPTION_MASK_ISA_ABM },
2273 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
2274 { "-maes", OPTION_MASK_ISA_AES },
2275 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
2279 static struct ix86_target_opts flag_opts[] =
2281 { "-m128bit-long-double", MASK_128BIT_LONG_DOUBLE },
2282 { "-m80387", MASK_80387 },
2283 { "-maccumulate-outgoing-args", MASK_ACCUMULATE_OUTGOING_ARGS },
2284 { "-malign-double", MASK_ALIGN_DOUBLE },
2285 { "-mcld", MASK_CLD },
2286 { "-mfp-ret-in-387", MASK_FLOAT_RETURNS },
2287 { "-mieee-fp", MASK_IEEE_FP },
2288 { "-minline-all-stringops", MASK_INLINE_ALL_STRINGOPS },
2289 { "-minline-stringops-dynamically", MASK_INLINE_STRINGOPS_DYNAMICALLY },
2290 { "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
2291 { "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
2292 { "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
2293 { "-mno-fused-madd", MASK_NO_FUSED_MADD },
2294 { "-mno-push-args", MASK_NO_PUSH_ARGS },
2295 { "-mno-red-zone", MASK_NO_RED_ZONE },
2296 { "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
2297 { "-mrecip", MASK_RECIP },
2298 { "-mrtd", MASK_RTD },
2299 { "-msseregparm", MASK_SSEREGPARM },
2300 { "-mstack-arg-probe", MASK_STACK_PROBE },
2301 { "-mtls-direct-seg-refs", MASK_TLS_DIRECT_SEG_REFS },
2304 const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
2307 char target_other[40];
2316 memset (opts, '\0', sizeof (opts));
2318 /* Add -march= option. */
2321 opts[num][0] = "-march=";
2322 opts[num++][1] = arch;
2325 /* Add -mtune= option. */
2328 opts[num][0] = "-mtune=";
2329 opts[num++][1] = tune;
2332 /* Pick out the options in isa options. */
2333 for (i = 0; i < ARRAY_SIZE (isa_opts); i++)
2335 if ((isa & isa_opts[i].mask) != 0)
2337 opts[num++][0] = isa_opts[i].option;
2338 isa &= ~ isa_opts[i].mask;
2342 if (isa && add_nl_p)
2344 opts[num++][0] = isa_other;
2345 sprintf (isa_other, "(other isa: 0x%x)", isa);
2348 /* Add flag options. */
2349 for (i = 0; i < ARRAY_SIZE (flag_opts); i++)
2351 if ((flags & flag_opts[i].mask) != 0)
2353 opts[num++][0] = flag_opts[i].option;
2354 flags &= ~ flag_opts[i].mask;
2358 if (flags && add_nl_p)
2360 opts[num++][0] = target_other;
2361 sprintf (target_other, "(other flags: 0x%x)", flags);
2364 /* Add -fpmath= option. */
2367 opts[num][0] = "-mfpmath=";
2368 opts[num++][1] = fpmath;
2375 gcc_assert (num < ARRAY_SIZE (opts));
2377 /* Size the string. */
2379 sep_len = (add_nl_p) ? 3 : 1;
2380 for (i = 0; i < num; i++)
2383 for (j = 0; j < 2; j++)
2385 len += strlen (opts[i][j]);
2388 /* Build the string. */
2389 ret = ptr = (char *) xmalloc (len);
2392 for (i = 0; i < num; i++)
2396 for (j = 0; j < 2; j++)
2397 len2[j] = (opts[i][j]) ? strlen (opts[i][j]) : 0;
2404 if (add_nl_p && line_len + len2[0] + len2[1] > 70)
2412 for (j = 0; j < 2; j++)
2415 memcpy (ptr, opts[i][j], len2[j]);
2417 line_len += len2[j];
2422 gcc_assert (ret + len >= ptr);
2427 /* Function that is callable from the debugger to print the current
2430 ix86_debug_options (void)
2432 char *opts = ix86_target_string (ix86_isa_flags, target_flags,
2433 ix86_arch_string, ix86_tune_string,
2434 ix86_fpmath_string, true);
2438 fprintf (stderr, "%s\n\n", opts);
2442 fprintf (stderr, "<no options>\n\n");
2447 /* Sometimes certain combinations of command options do not make
2448 sense on a particular target machine. You can define a macro
2449 `OVERRIDE_OPTIONS' to take account of this. This macro, if
2450 defined, is executed once just after all the command options have
2453 Don't use this macro to turn on various extra optimizations for
2454 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
2457 override_options (bool main_args_p)
2460 unsigned int ix86_arch_mask, ix86_tune_mask;
2465 /* Comes from final.c -- no real reason to change it. */
2466 #define MAX_CODE_ALIGN 16
2474 PTA_PREFETCH_SSE = 1 << 4,
2476 PTA_3DNOW_A = 1 << 6,
2480 PTA_POPCNT = 1 << 10,
2482 PTA_SSE4A = 1 << 12,
2483 PTA_NO_SAHF = 1 << 13,
2484 PTA_SSE4_1 = 1 << 14,
2485 PTA_SSE4_2 = 1 << 15,
2488 PTA_PCLMUL = 1 << 18,
2495 const char *const name; /* processor name or nickname. */
2496 const enum processor_type processor;
2497 const enum attr_cpu schedule;
2498 const unsigned /*enum pta_flags*/ flags;
2500 const processor_alias_table[] =
2502 {"i386", PROCESSOR_I386, CPU_NONE, 0},
2503 {"i486", PROCESSOR_I486, CPU_NONE, 0},
2504 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2505 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
2506 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
2507 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
2508 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2509 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
2510 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_SSE},
2511 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2512 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
2513 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX},
2514 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2516 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2518 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
2519 PTA_MMX | PTA_SSE | PTA_SSE2},
2520 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
2521 PTA_MMX |PTA_SSE | PTA_SSE2},
2522 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
2523 PTA_MMX | PTA_SSE | PTA_SSE2},
2524 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
2525 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
2526 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
2527 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2528 | PTA_CX16 | PTA_NO_SAHF},
2529 {"core2", PROCESSOR_CORE2, CPU_CORE2,
2530 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
2531 | PTA_SSSE3 | PTA_CX16},
2532 {"geode", PROCESSOR_GEODE, CPU_GEODE,
2533 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
2534 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
2535 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2536 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
2537 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
2538 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2539 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
2540 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
2541 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
2542 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2543 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
2544 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2545 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
2546 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE},
2547 {"x86-64", PROCESSOR_K8, CPU_K8,
2548 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF},
2549 {"k8", PROCESSOR_K8, CPU_K8,
2550 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2551 | PTA_SSE2 | PTA_NO_SAHF},
2552 {"k8-sse3", PROCESSOR_K8, CPU_K8,
2553 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2554 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2555 {"opteron", PROCESSOR_K8, CPU_K8,
2556 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2557 | PTA_SSE2 | PTA_NO_SAHF},
2558 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
2559 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2560 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2561 {"athlon64", PROCESSOR_K8, CPU_K8,
2562 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2563 | PTA_SSE2 | PTA_NO_SAHF},
2564 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
2565 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2566 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF},
2567 {"athlon-fx", PROCESSOR_K8, CPU_K8,
2568 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2569 | PTA_SSE2 | PTA_NO_SAHF},
2570 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2571 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2572 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2573 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
2574 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
2575 | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM},
2576 {"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
2577 0 /* flags are only used for -march switch. */ },
2578 {"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
2579 PTA_64BIT /* flags are only used for -march switch. */ },
2582 int const pta_size = ARRAY_SIZE (processor_alias_table);
2584 /* Set up prefix/suffix so the error messages refer to either the command
2585 line argument, or the attribute(target). */
2594 prefix = "option(\"";
2599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2600 SUBTARGET_OVERRIDE_OPTIONS;
2603 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2604 SUBSUBTARGET_OVERRIDE_OPTIONS;
2607 /* -fPIC is the default for x86_64. */
2608 if (TARGET_MACHO && TARGET_64BIT)
2611 /* Set the default values for switches whose default depends on TARGET_64BIT
2612 in case they weren't overwritten by command line options. */
2615 /* Mach-O doesn't support omitting the frame pointer for now. */
2616 if (flag_omit_frame_pointer == 2)
2617 flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1);
2618 if (flag_asynchronous_unwind_tables == 2)
2619 flag_asynchronous_unwind_tables = 1;
2620 if (flag_pcc_struct_return == 2)
2621 flag_pcc_struct_return = 0;
2625 if (flag_omit_frame_pointer == 2)
2626 flag_omit_frame_pointer = 0;
2627 if (flag_asynchronous_unwind_tables == 2)
2628 flag_asynchronous_unwind_tables = 0;
2629 if (flag_pcc_struct_return == 2)
2630 flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
2633 /* Need to check -mtune=generic first. */
2634 if (ix86_tune_string)
2636 if (!strcmp (ix86_tune_string, "generic")
2637 || !strcmp (ix86_tune_string, "i686")
2638 /* As special support for cross compilers we read -mtune=native
2639 as -mtune=generic. With native compilers we won't see the
2640 -mtune=native, as it was changed by the driver. */
2641 || !strcmp (ix86_tune_string, "native"))
2644 ix86_tune_string = "generic64";
2646 ix86_tune_string = "generic32";
2648 /* If this call is for setting the option attribute, allow the
2649 generic32/generic64 that was previously set. */
2650 else if (!main_args_p
2651 && (!strcmp (ix86_tune_string, "generic32")
2652 || !strcmp (ix86_tune_string, "generic64")))
2654 else if (!strncmp (ix86_tune_string, "generic", 7))
2655 error ("bad value (%s) for %stune=%s %s",
2656 ix86_tune_string, prefix, suffix, sw);
2660 if (ix86_arch_string)
2661 ix86_tune_string = ix86_arch_string;
2662 if (!ix86_tune_string)
2664 ix86_tune_string = cpu_names[TARGET_CPU_DEFAULT];
2665 ix86_tune_defaulted = 1;
2668 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
2669 need to use a sensible tune option. */
2670 if (!strcmp (ix86_tune_string, "generic")
2671 || !strcmp (ix86_tune_string, "x86-64")
2672 || !strcmp (ix86_tune_string, "i686"))
2675 ix86_tune_string = "generic64";
2677 ix86_tune_string = "generic32";
2680 if (ix86_stringop_string)
2682 if (!strcmp (ix86_stringop_string, "rep_byte"))
2683 stringop_alg = rep_prefix_1_byte;
2684 else if (!strcmp (ix86_stringop_string, "libcall"))
2685 stringop_alg = libcall;
2686 else if (!strcmp (ix86_stringop_string, "rep_4byte"))
2687 stringop_alg = rep_prefix_4_byte;
2688 else if (!strcmp (ix86_stringop_string, "rep_8byte")
2690 /* rep; movq isn't available in 32-bit code. */
2691 stringop_alg = rep_prefix_8_byte;
2692 else if (!strcmp (ix86_stringop_string, "byte_loop"))
2693 stringop_alg = loop_1_byte;
2694 else if (!strcmp (ix86_stringop_string, "loop"))
2695 stringop_alg = loop;
2696 else if (!strcmp (ix86_stringop_string, "unrolled_loop"))
2697 stringop_alg = unrolled_loop;
2699 error ("bad value (%s) for %sstringop-strategy=%s %s",
2700 ix86_stringop_string, prefix, suffix, sw);
2702 if (!strcmp (ix86_tune_string, "x86-64"))
2703 warning (OPT_Wdeprecated, "%stune=x86-64%s is deprecated. Use "
2704 "%stune=k8%s or %stune=generic%s instead as appropriate.",
2705 prefix, suffix, prefix, suffix, prefix, suffix);
2707 if (!ix86_arch_string)
2708 ix86_arch_string = TARGET_64BIT ? "x86-64" : "i486";
2710 ix86_arch_specified = 1;
2712 if (!strcmp (ix86_arch_string, "generic"))
2713 error ("generic CPU can be used only for %stune=%s %s",
2714 prefix, suffix, sw);
2715 if (!strncmp (ix86_arch_string, "generic", 7))
2716 error ("bad value (%s) for %sarch=%s %s",
2717 ix86_arch_string, prefix, suffix, sw);
2719 if (ix86_cmodel_string != 0)
2721 if (!strcmp (ix86_cmodel_string, "small"))
2722 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2723 else if (!strcmp (ix86_cmodel_string, "medium"))
2724 ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM;
2725 else if (!strcmp (ix86_cmodel_string, "large"))
2726 ix86_cmodel = flag_pic ? CM_LARGE_PIC : CM_LARGE;
2728 error ("code model %s does not support PIC mode", ix86_cmodel_string);
2729 else if (!strcmp (ix86_cmodel_string, "32"))
2730 ix86_cmodel = CM_32;
2731 else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
2732 ix86_cmodel = CM_KERNEL;
2734 error ("bad value (%s) for %scmodel=%s %s",
2735 ix86_cmodel_string, prefix, suffix, sw);
2739 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
2740 use of rip-relative addressing. This eliminates fixups that
2741 would otherwise be needed if this object is to be placed in a
2742 DLL, and is essentially just as efficient as direct addressing. */
2743 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
2744 ix86_cmodel = CM_SMALL_PIC, flag_pic = 1;
2745 else if (TARGET_64BIT)
2746 ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
2748 ix86_cmodel = CM_32;
2750 if (ix86_asm_string != 0)
2753 && !strcmp (ix86_asm_string, "intel"))
2754 ix86_asm_dialect = ASM_INTEL;
2755 else if (!strcmp (ix86_asm_string, "att"))
2756 ix86_asm_dialect = ASM_ATT;
2758 error ("bad value (%s) for %sasm=%s %s",
2759 ix86_asm_string, prefix, suffix, sw);
2761 if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
2762 error ("code model %qs not supported in the %s bit mode",
2763 ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
2764 if ((TARGET_64BIT != 0) != ((ix86_isa_flags & OPTION_MASK_ISA_64BIT) != 0))
2765 sorry ("%i-bit mode not compiled in",
2766 (ix86_isa_flags & OPTION_MASK_ISA_64BIT) ? 64 : 32);
2768 for (i = 0; i < pta_size; i++)
2769 if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
2771 ix86_schedule = processor_alias_table[i].schedule;
2772 ix86_arch = processor_alias_table[i].processor;
2773 /* Default cpu tuning to the architecture. */
2774 ix86_tune = ix86_arch;
2776 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2777 error ("CPU you selected does not support x86-64 "
2780 if (processor_alias_table[i].flags & PTA_MMX
2781 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
2782 ix86_isa_flags |= OPTION_MASK_ISA_MMX;
2783 if (processor_alias_table[i].flags & PTA_3DNOW
2784 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
2785 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
2786 if (processor_alias_table[i].flags & PTA_3DNOW_A
2787 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
2788 ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
2789 if (processor_alias_table[i].flags & PTA_SSE
2790 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
2791 ix86_isa_flags |= OPTION_MASK_ISA_SSE;
2792 if (processor_alias_table[i].flags & PTA_SSE2
2793 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
2794 ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
2795 if (processor_alias_table[i].flags & PTA_SSE3
2796 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
2797 ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
2798 if (processor_alias_table[i].flags & PTA_SSSE3
2799 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
2800 ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
2801 if (processor_alias_table[i].flags & PTA_SSE4_1
2802 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
2803 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
2804 if (processor_alias_table[i].flags & PTA_SSE4_2
2805 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
2806 ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
2807 if (processor_alias_table[i].flags & PTA_AVX
2808 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
2809 ix86_isa_flags |= OPTION_MASK_ISA_AVX;
2810 if (processor_alias_table[i].flags & PTA_FMA
2811 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
2812 ix86_isa_flags |= OPTION_MASK_ISA_FMA;
2813 if (processor_alias_table[i].flags & PTA_SSE4A
2814 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
2815 ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
2816 if (processor_alias_table[i].flags & PTA_SSE5
2817 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
2818 ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
2819 if (processor_alias_table[i].flags & PTA_ABM
2820 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
2821 ix86_isa_flags |= OPTION_MASK_ISA_ABM;
2822 if (processor_alias_table[i].flags & PTA_CX16
2823 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
2824 ix86_isa_flags |= OPTION_MASK_ISA_CX16;
2825 if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
2826 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
2827 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
2828 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
2829 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
2830 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
2831 if (processor_alias_table[i].flags & PTA_AES
2832 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
2833 ix86_isa_flags |= OPTION_MASK_ISA_AES;
2834 if (processor_alias_table[i].flags & PTA_PCLMUL
2835 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
2836 ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
2837 if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
2838 x86_prefetch_sse = true;
2844 error ("bad value (%s) for %sarch=%s %s",
2845 ix86_arch_string, prefix, suffix, sw);
2847 ix86_arch_mask = 1u << ix86_arch;
2848 for (i = 0; i < X86_ARCH_LAST; ++i)
2849 ix86_arch_features[i] = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
2851 for (i = 0; i < pta_size; i++)
2852 if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
2854 ix86_schedule = processor_alias_table[i].schedule;
2855 ix86_tune = processor_alias_table[i].processor;
2856 if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
2858 if (ix86_tune_defaulted)
2860 ix86_tune_string = "x86-64";
2861 for (i = 0; i < pta_size; i++)
2862 if (! strcmp (ix86_tune_string,
2863 processor_alias_table[i].name))
2865 ix86_schedule = processor_alias_table[i].schedule;
2866 ix86_tune = processor_alias_table[i].processor;
2869 error ("CPU you selected does not support x86-64 "
2872 /* Intel CPUs have always interpreted SSE prefetch instructions as
2873 NOPs; so, we can enable SSE prefetch instructions even when
2874 -mtune (rather than -march) points us to a processor that has them.
2875 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
2876 higher processors. */
2878 && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
2879 x86_prefetch_sse = true;
2883 error ("bad value (%s) for %stune=%s %s",
2884 ix86_tune_string, prefix, suffix, sw);
2886 ix86_tune_mask = 1u << ix86_tune;
2887 for (i = 0; i < X86_TUNE_LAST; ++i)
2888 ix86_tune_features[i] = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
2891 ix86_cost = &ix86_size_cost;
2893 ix86_cost = processor_target_table[ix86_tune].cost;
2895 /* Arrange to set up i386_stack_locals for all functions. */
2896 init_machine_status = ix86_init_machine_status;
2898 /* Validate -mregparm= value. */
2899 if (ix86_regparm_string)
2902 warning (0, "%sregparm%s is ignored in 64-bit mode", prefix, suffix);
2903 i = atoi (ix86_regparm_string);
2904 if (i < 0 || i > REGPARM_MAX)
2905 error ("%sregparm=%d%s is not between 0 and %d",
2906 prefix, i, suffix, REGPARM_MAX);
2911 ix86_regparm = REGPARM_MAX;
2913 /* If the user has provided any of the -malign-* options,
2914 warn and use that value only if -falign-* is not set.
2915 Remove this code in GCC 3.2 or later. */
2916 if (ix86_align_loops_string)
2918 warning (0, "%salign-loops%s is obsolete, use -falign-loops%s",
2919 prefix, suffix, suffix);
2920 if (align_loops == 0)
2922 i = atoi (ix86_align_loops_string);
2923 if (i < 0 || i > MAX_CODE_ALIGN)
2924 error ("%salign-loops=%d%s is not between 0 and %d",
2925 prefix, i, suffix, MAX_CODE_ALIGN);
2927 align_loops = 1 << i;
2931 if (ix86_align_jumps_string)
2933 warning (0, "%salign-jumps%s is obsolete, use -falign-jumps%s",
2934 prefix, suffix, suffix);
2935 if (align_jumps == 0)
2937 i = atoi (ix86_align_jumps_string);
2938 if (i < 0 || i > MAX_CODE_ALIGN)
2939 error ("%salign-loops=%d%s is not between 0 and %d",
2940 prefix, i, suffix, MAX_CODE_ALIGN);
2942 align_jumps = 1 << i;
2946 if (ix86_align_funcs_string)
2948 warning (0, "%salign-functions%s is obsolete, use -falign-functions%s",
2949 prefix, suffix, suffix);
2950 if (align_functions == 0)
2952 i = atoi (ix86_align_funcs_string);
2953 if (i < 0 || i > MAX_CODE_ALIGN)
2954 error ("%salign-loops=%d%s is not between 0 and %d",
2955 prefix, i, suffix, MAX_CODE_ALIGN);
2957 align_functions = 1 << i;
2961 /* Default align_* from the processor table. */
2962 if (align_loops == 0)
2964 align_loops = processor_target_table[ix86_tune].align_loop;
2965 align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
2967 if (align_jumps == 0)
2969 align_jumps = processor_target_table[ix86_tune].align_jump;
2970 align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
2972 if (align_functions == 0)
2974 align_functions = processor_target_table[ix86_tune].align_func;
2977 /* Validate -mbranch-cost= value, or provide default. */
2978 ix86_branch_cost = ix86_cost->branch_cost;
2979 if (ix86_branch_cost_string)
2981 i = atoi (ix86_branch_cost_string);
2983 error ("%sbranch-cost=%d%s is not between 0 and 5", prefix, i, suffix);
2985 ix86_branch_cost = i;
2987 if (ix86_section_threshold_string)
2989 i = atoi (ix86_section_threshold_string);
2991 error ("%slarge-data-threshold=%d%s is negative", prefix, i, suffix);
2993 ix86_section_threshold = i;
2996 if (ix86_tls_dialect_string)
2998 if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
2999 ix86_tls_dialect = TLS_DIALECT_GNU;
3000 else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0)
3001 ix86_tls_dialect = TLS_DIALECT_GNU2;
3002 else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
3003 ix86_tls_dialect = TLS_DIALECT_SUN;
3005 error ("bad value (%s) for %stls-dialect=%s %s",
3006 ix86_tls_dialect_string, prefix, suffix, sw);
3009 if (ix87_precision_string)
3011 i = atoi (ix87_precision_string);
3012 if (i != 32 && i != 64 && i != 80)
3013 error ("pc%d is not valid precision setting (32, 64 or 80)", i);
3018 target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
3020 /* Enable by default the SSE and MMX builtins. Do allow the user to
3021 explicitly disable any of these. In particular, disabling SSE and
3022 MMX for kernel code is extremely useful. */
3023 if (!ix86_arch_specified)
3025 |= ((OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_MMX
3026 | TARGET_SUBTARGET64_ISA_DEFAULT) & ~ix86_isa_flags_explicit);
3029 warning (0, "%srtd%s is ignored in 64bit mode", prefix, suffix);
3033 target_flags |= TARGET_SUBTARGET32_DEFAULT & ~target_flags_explicit;
3035 if (!ix86_arch_specified)
3037 |= TARGET_SUBTARGET32_ISA_DEFAULT & ~ix86_isa_flags_explicit;
3039 /* i386 ABI does not specify red zone. It still makes sense to use it
3040 when programmer takes care to stack from being destroyed. */
3041 if (!(target_flags_explicit & MASK_NO_RED_ZONE))
3042 target_flags |= MASK_NO_RED_ZONE;
3045 /* Keep nonleaf frame pointers. */
3046 if (flag_omit_frame_pointer)
3047 target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
3048 else if (TARGET_OMIT_LEAF_FRAME_POINTER)
3049 flag_omit_frame_pointer = 1;
3051 /* If we're doing fast math, we don't care about comparison order
3052 wrt NaNs. This lets us use a shorter comparison sequence. */
3053 if (flag_finite_math_only)
3054 target_flags &= ~MASK_IEEE_FP;
3056 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3057 since the insns won't need emulation. */
3058 if (x86_arch_always_fancy_math_387 & ix86_arch_mask)
3059 target_flags &= ~MASK_NO_FANCY_MATH_387;
3061 /* Likewise, if the target doesn't have a 387, or we've specified
3062 software floating point, don't use 387 inline intrinsics. */
3064 target_flags |= MASK_NO_FANCY_MATH_387;
3066 /* Turn on MMX builtins for -msse. */
3069 ix86_isa_flags |= OPTION_MASK_ISA_MMX & ~ix86_isa_flags_explicit;
3070 x86_prefetch_sse = true;
3073 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3074 if (TARGET_SSE4_2 || TARGET_ABM)
3075 ix86_isa_flags |= OPTION_MASK_ISA_POPCNT & ~ix86_isa_flags_explicit;
3077 /* Validate -mpreferred-stack-boundary= value or default it to
3078 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3079 ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
3080 if (ix86_preferred_stack_boundary_string)
3082 i = atoi (ix86_preferred_stack_boundary_string);
3083 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3084 error ("%spreferred-stack-boundary=%d%s is not between %d and 12",
3085 prefix, i, suffix, TARGET_64BIT ? 4 : 2);
3087 ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
3090 /* Set the default value for -mstackrealign. */
3091 if (ix86_force_align_arg_pointer == -1)
3092 ix86_force_align_arg_pointer = STACK_REALIGN_DEFAULT;
3094 /* Validate -mincoming-stack-boundary= value or default it to
3095 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3096 if (ix86_force_align_arg_pointer)
3097 ix86_default_incoming_stack_boundary = MIN_STACK_BOUNDARY;
3099 ix86_default_incoming_stack_boundary = PREFERRED_STACK_BOUNDARY;
3100 ix86_incoming_stack_boundary = ix86_default_incoming_stack_boundary;
3101 if (ix86_incoming_stack_boundary_string)
3103 i = atoi (ix86_incoming_stack_boundary_string);
3104 if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
3105 error ("-mincoming-stack-boundary=%d is not between %d and 12",
3106 i, TARGET_64BIT ? 4 : 2);
3109 ix86_user_incoming_stack_boundary = (1 << i) * BITS_PER_UNIT;
3110 ix86_incoming_stack_boundary
3111 = ix86_user_incoming_stack_boundary;
3115 /* Accept -msseregparm only if at least SSE support is enabled. */
3116 if (TARGET_SSEREGPARM
3118 error ("%ssseregparm%s used without SSE enabled", prefix, suffix);
3120 ix86_fpmath = TARGET_FPMATH_DEFAULT;
3121 if (ix86_fpmath_string != 0)
3123 if (! strcmp (ix86_fpmath_string, "387"))
3124 ix86_fpmath = FPMATH_387;
3125 else if (! strcmp (ix86_fpmath_string, "sse"))
3129 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3130 ix86_fpmath = FPMATH_387;
3133 ix86_fpmath = FPMATH_SSE;
3135 else if (! strcmp (ix86_fpmath_string, "387,sse")
3136 || ! strcmp (ix86_fpmath_string, "387+sse")
3137 || ! strcmp (ix86_fpmath_string, "sse,387")
3138 || ! strcmp (ix86_fpmath_string, "sse+387")
3139 || ! strcmp (ix86_fpmath_string, "both"))
3143 warning (0, "SSE instruction set disabled, using 387 arithmetics");
3144 ix86_fpmath = FPMATH_387;
3146 else if (!TARGET_80387)
3148 warning (0, "387 instruction set disabled, using SSE arithmetics");
3149 ix86_fpmath = FPMATH_SSE;
3152 ix86_fpmath = (enum fpmath_unit) (FPMATH_SSE | FPMATH_387);
3155 error ("bad value (%s) for %sfpmath=%s %s",
3156 ix86_fpmath_string, prefix, suffix, sw);
3159 /* If the i387 is disabled, then do not return values in it. */
3161 target_flags &= ~MASK_FLOAT_RETURNS;
3163 /* Use external vectorized library in vectorizing intrinsics. */
3164 if (ix86_veclibabi_string)
3166 if (strcmp (ix86_veclibabi_string, "svml") == 0)
3167 ix86_veclib_handler = ix86_veclibabi_svml;
3168 else if (strcmp (ix86_veclibabi_string, "acml") == 0)
3169 ix86_veclib_handler = ix86_veclibabi_acml;
3171 error ("unknown vectorization library ABI type (%s) for "
3172 "%sveclibabi=%s %s", ix86_veclibabi_string,
3173 prefix, suffix, sw);
3176 if ((x86_accumulate_outgoing_args & ix86_tune_mask)
3177 && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3179 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3181 /* ??? Unwind info is not correct around the CFG unless either a frame
3182 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3183 unwind info generation to be aware of the CFG and propagating states
3185 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
3186 || flag_exceptions || flag_non_call_exceptions)
3187 && flag_omit_frame_pointer
3188 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3190 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3191 warning (0, "unwind tables currently require either a frame pointer "
3192 "or %saccumulate-outgoing-args%s for correctness",
3194 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3197 /* If stack probes are required, the space used for large function
3198 arguments on the stack must also be probed, so enable
3199 -maccumulate-outgoing-args so this happens in the prologue. */
3200 if (TARGET_STACK_PROBE
3201 && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS))
3203 if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
3204 warning (0, "stack probing requires %saccumulate-outgoing-args%s "
3205 "for correctness", prefix, suffix);
3206 target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;
3209 /* For sane SSE instruction set generation we need fcomi instruction.
3210 It is safe to enable all CMOVE instructions. */
3214 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3217 ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
3218 p = strchr (internal_label_prefix, 'X');
3219 internal_label_prefix_len = p - internal_label_prefix;
3223 /* When scheduling description is not available, disable scheduler pass
3224 so it won't slow down the compilation and make x87 code slower. */
3225 if (!TARGET_SCHEDULE)
3226 flag_schedule_insns_after_reload = flag_schedule_insns = 0;
3228 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
3229 set_param_value ("simultaneous-prefetches",
3230 ix86_cost->simultaneous_prefetches);
3231 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
3232 set_param_value ("l1-cache-line-size", ix86_cost->prefetch_block);
3233 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
3234 set_param_value ("l1-cache-size", ix86_cost->l1_cache_size);
3235 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
3236 set_param_value ("l2-cache-size", ix86_cost->l2_cache_size);
3238 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3239 can be optimized to ap = __builtin_next_arg (0). */
3241 targetm.expand_builtin_va_start = NULL;
3245 ix86_gen_leave = gen_leave_rex64;
3246 ix86_gen_pop1 = gen_popdi1;
3247 ix86_gen_add3 = gen_adddi3;
3248 ix86_gen_sub3 = gen_subdi3;
3249 ix86_gen_sub3_carry = gen_subdi3_carry_rex64;
3250 ix86_gen_one_cmpl2 = gen_one_cmpldi2;
3251 ix86_gen_monitor = gen_sse3_monitor64;
3252 ix86_gen_andsp = gen_anddi3;
3256 ix86_gen_leave = gen_leave;
3257 ix86_gen_pop1 = gen_popsi1;
3258 ix86_gen_add3 = gen_addsi3;
3259 ix86_gen_sub3 = gen_subsi3;
3260 ix86_gen_sub3_carry = gen_subsi3_carry;
3261 ix86_gen_one_cmpl2 = gen_one_cmplsi2;
3262 ix86_gen_monitor = gen_sse3_monitor;
3263 ix86_gen_andsp = gen_andsi3;
3267 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3269 target_flags |= MASK_CLD & ~target_flags_explicit;
3272 /* Save the initial options in case the user does function specific options */
3274 target_option_default_node = target_option_current_node
3275 = build_target_option_node ();
3278 /* Update register usage after having seen the compiler flags. */
3281 ix86_conditional_register_usage (void)
3286 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3288 if (fixed_regs[i] > 1)
3289 fixed_regs[i] = (fixed_regs[i] == (TARGET_64BIT ? 3 : 2));
3290 if (call_used_regs[i] > 1)
3291 call_used_regs[i] = (call_used_regs[i] == (TARGET_64BIT ? 3 : 2));
3294 /* The PIC register, if it exists, is fixed. */
3295 j = PIC_OFFSET_TABLE_REGNUM;
3296 if (j != INVALID_REGNUM)
3297 fixed_regs[j] = call_used_regs[j] = 1;
3299 /* The MS_ABI changes the set of call-used registers. */
3300 if (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)
3302 call_used_regs[SI_REG] = 0;
3303 call_used_regs[DI_REG] = 0;
3304 call_used_regs[XMM6_REG] = 0;
3305 call_used_regs[XMM7_REG] = 0;
3306 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3307 call_used_regs[i] = 0;
3310 /* The default setting of CLOBBERED_REGS is for 32-bit; add in the
3311 other call-clobbered regs for 64-bit. */
3314 CLEAR_HARD_REG_SET (reg_class_contents[(int)CLOBBERED_REGS]);
3316 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3317 if (TEST_HARD_REG_BIT (reg_class_contents[(int)GENERAL_REGS], i)
3318 && call_used_regs[i])
3319 SET_HARD_REG_BIT (reg_class_contents[(int)CLOBBERED_REGS], i);
3322 /* If MMX is disabled, squash the registers. */
3324 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3325 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i))
3326 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3328 /* If SSE is disabled, squash the registers. */
3330 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3331 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i))
3332 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3334 /* If the FPU is disabled, squash the registers. */
3335 if (! (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387))
3336 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3337 if (TEST_HARD_REG_BIT (reg_class_contents[(int)FLOAT_REGS], i))
3338 fixed_regs[i] = call_used_regs[i] = 1, reg_names[i] = "";
3340 /* If 32-bit, squash the 64-bit registers. */
3343 for (i = FIRST_REX_INT_REG; i <= LAST_REX_INT_REG; i++)
3345 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
3351 /* Save the current options */
3354 ix86_function_specific_save (struct cl_target_option *ptr)
3356 gcc_assert (IN_RANGE (ix86_arch, 0, 255));
3357 gcc_assert (IN_RANGE (ix86_schedule, 0, 255));
3358 gcc_assert (IN_RANGE (ix86_tune, 0, 255));
3359 gcc_assert (IN_RANGE (ix86_fpmath, 0, 255));
3360 gcc_assert (IN_RANGE (ix86_branch_cost, 0, 255));
3362 ptr->arch = ix86_arch;
3363 ptr->schedule = ix86_schedule;
3364 ptr->tune = ix86_tune;
3365 ptr->fpmath = ix86_fpmath;
3366 ptr->branch_cost = ix86_branch_cost;
3367 ptr->tune_defaulted = ix86_tune_defaulted;
3368 ptr->arch_specified = ix86_arch_specified;
3369 ptr->ix86_isa_flags_explicit = ix86_isa_flags_explicit;
3370 ptr->target_flags_explicit = target_flags_explicit;
3373 /* Restore the current options */
3376 ix86_function_specific_restore (struct cl_target_option *ptr)
3378 enum processor_type old_tune = ix86_tune;
3379 enum processor_type old_arch = ix86_arch;
3380 unsigned int ix86_arch_mask, ix86_tune_mask;
3383 ix86_arch = ptr->arch;
3384 ix86_schedule = ptr->schedule;
3385 ix86_tune = ptr->tune;
3386 ix86_fpmath = ptr->fpmath;
3387 ix86_branch_cost = ptr->branch_cost;
3388 ix86_tune_defaulted = ptr->tune_defaulted;
3389 ix86_arch_specified = ptr->arch_specified;
3390 ix86_isa_flags_explicit = ptr->ix86_isa_flags_explicit;
3391 target_flags_explicit = ptr->target_flags_explicit;
3393 /* Recreate the arch feature tests if the arch changed */
3394 if (old_arch != ix86_arch)
3396 ix86_arch_mask = 1u << ix86_arch;
3397 for (i = 0; i < X86_ARCH_LAST; ++i)
3398 ix86_arch_features[i]
3399 = !!(initial_ix86_arch_features[i] & ix86_arch_mask);
3402 /* Recreate the tune optimization tests */
3403 if (old_tune != ix86_tune)
3405 ix86_tune_mask = 1u << ix86_tune;
3406 for (i = 0; i < X86_TUNE_LAST; ++i)
3407 ix86_tune_features[i]
3408 = !!(initial_ix86_tune_features[i] & ix86_tune_mask);
3412 /* Print the current options */
3415 ix86_function_specific_print (FILE *file, int indent,
3416 struct cl_target_option *ptr)
3419 = ix86_target_string (ptr->ix86_isa_flags, ptr->target_flags,
3420 NULL, NULL, NULL, false);
3422 fprintf (file, "%*sarch = %d (%s)\n",
3425 ((ptr->arch < TARGET_CPU_DEFAULT_max)
3426 ? cpu_names[ptr->arch]
3429 fprintf (file, "%*stune = %d (%s)\n",
3432 ((ptr->tune < TARGET_CPU_DEFAULT_max)
3433 ? cpu_names[ptr->tune]
3436 fprintf (file, "%*sfpmath = %d%s%s\n", indent, "", ptr->fpmath,
3437 (ptr->fpmath & FPMATH_387) ? ", 387" : "",
3438 (ptr->fpmath & FPMATH_SSE) ? ", sse" : "");
3439 fprintf (file, "%*sbranch_cost = %d\n", indent, "", ptr->branch_cost);
3443 fprintf (file, "%*s%s\n", indent, "", target_string);
3444 free (target_string);
3449 /* Inner function to process the attribute((target(...))), take an argument and
3450 set the current options from the argument. If we have a list, recursively go
3454 ix86_valid_target_attribute_inner_p (tree args, char *p_strings[])
3459 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
3460 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
3461 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
3462 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
3477 enum ix86_opt_type type;
3482 IX86_ATTR_ISA ("3dnow", OPT_m3dnow),
3483 IX86_ATTR_ISA ("abm", OPT_mabm),
3484 IX86_ATTR_ISA ("aes", OPT_maes),
3485 IX86_ATTR_ISA ("avx", OPT_mavx),
3486 IX86_ATTR_ISA ("mmx", OPT_mmmx),
3487 IX86_ATTR_ISA ("pclmul", OPT_mpclmul),
3488 IX86_ATTR_ISA ("popcnt", OPT_mpopcnt),
3489 IX86_ATTR_ISA ("sse", OPT_msse),
3490 IX86_ATTR_ISA ("sse2", OPT_msse2),
3491 IX86_ATTR_ISA ("sse3", OPT_msse3),
3492 IX86_ATTR_ISA ("sse4", OPT_msse4),
3493 IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
3494 IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
3495 IX86_ATTR_ISA ("sse4a", OPT_msse4a),
3496 IX86_ATTR_ISA ("sse5", OPT_msse5),
3497 IX86_ATTR_ISA ("ssse3", OPT_mssse3),
3499 /* string options */
3500 IX86_ATTR_STR ("arch=", IX86_FUNCTION_SPECIFIC_ARCH),
3501 IX86_ATTR_STR ("fpmath=", IX86_FUNCTION_SPECIFIC_FPMATH),
3502 IX86_ATTR_STR ("tune=", IX86_FUNCTION_SPECIFIC_TUNE),
3505 IX86_ATTR_YES ("cld",
3509 IX86_ATTR_NO ("fancy-math-387",
3510 OPT_mfancy_math_387,
3511 MASK_NO_FANCY_MATH_387),
3513 IX86_ATTR_NO ("fused-madd",
3515 MASK_NO_FUSED_MADD),
3517 IX86_ATTR_YES ("ieee-fp",
3521 IX86_ATTR_YES ("inline-all-stringops",
3522 OPT_minline_all_stringops,
3523 MASK_INLINE_ALL_STRINGOPS),
3525 IX86_ATTR_YES ("inline-stringops-dynamically",
3526 OPT_minline_stringops_dynamically,
3527 MASK_INLINE_STRINGOPS_DYNAMICALLY),
3529 IX86_ATTR_NO ("align-stringops",
3530 OPT_mno_align_stringops,
3531 MASK_NO_ALIGN_STRINGOPS),
3533 IX86_ATTR_YES ("recip",
3539 /* If this is a list, recurse to get the options. */
3540 if (TREE_CODE (args) == TREE_LIST)
3544 for (; args; args = TREE_CHAIN (args))
3545 if (TREE_VALUE (args)
3546 && !ix86_valid_target_attribute_inner_p (TREE_VALUE (args), p_strings))
3552 else if (TREE_CODE (args) != STRING_CST)
3555 /* Handle multiple arguments separated by commas. */
3556 next_optstr = ASTRDUP (TREE_STRING_POINTER (args));
3558 while (next_optstr && *next_optstr != '\0')
3560 char *p = next_optstr;
3562 char *comma = strchr (next_optstr, ',');
3563 const char *opt_string;
3564 size_t len, opt_len;
3569 enum ix86_opt_type type = ix86_opt_unknown;
3575 len = comma - next_optstr;
3576 next_optstr = comma + 1;
3584 /* Recognize no-xxx. */
3585 if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-')
3594 /* Find the option. */
3597 for (i = 0; i < ARRAY_SIZE (attrs); i++)
3599 type = attrs[i].type;
3600 opt_len = attrs[i].len;
3601 if (ch == attrs[i].string[0]
3602 && ((type != ix86_opt_str) ? len == opt_len : len > opt_len)
3603 && memcmp (p, attrs[i].string, opt_len) == 0)
3606 mask = attrs[i].mask;
3607 opt_string = attrs[i].string;
3612 /* Process the option. */
3615 error ("attribute(target(\"%s\")) is unknown", orig_p);
3619 else if (type == ix86_opt_isa)
3620 ix86_handle_option (opt, p, opt_set_p);
3622 else if (type == ix86_opt_yes || type == ix86_opt_no)
3624 if (type == ix86_opt_no)
3625 opt_set_p = !opt_set_p;
3628 target_flags |= mask;
3630 target_flags &= ~mask;
3633 else if (type == ix86_opt_str)
3637 error ("option(\"%s\") was already specified", opt_string);
3641 p_strings[opt] = xstrdup (p + opt_len);
3651 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
3654 ix86_valid_target_attribute_tree (tree args)
3656 const char *orig_arch_string = ix86_arch_string;
3657 const char *orig_tune_string = ix86_tune_string;
3658 const char *orig_fpmath_string = ix86_fpmath_string;
3659 int orig_tune_defaulted = ix86_tune_defaulted;
3660 int orig_arch_specified = ix86_arch_specified;
3661 char *option_strings[IX86_FUNCTION_SPECIFIC_MAX] = { NULL, NULL, NULL };
3664 struct cl_target_option *def
3665 = TREE_TARGET_OPTION (target_option_default_node);
3667 /* Process each of the options on the chain. */
3668 if (! ix86_valid_target_attribute_inner_p (args, option_strings))
3671 /* If the changed options are different from the default, rerun override_options,
3672 and then save the options away. The string options are are attribute options,
3673 and will be undone when we copy the save structure. */
3674 if (ix86_isa_flags != def->ix86_isa_flags
3675 || target_flags != def->target_flags
3676 || option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
3677 || option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
3678 || option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3680 /* If we are using the default tune= or arch=, undo the string assigned,
3681 and use the default. */
3682 if (option_strings[IX86_FUNCTION_SPECIFIC_ARCH])
3683 ix86_arch_string = option_strings[IX86_FUNCTION_SPECIFIC_ARCH];
3684 else if (!orig_arch_specified)
3685 ix86_arch_string = NULL;
3687 if (option_strings[IX86_FUNCTION_SPECIFIC_TUNE])
3688 ix86_tune_string = option_strings[IX86_FUNCTION_SPECIFIC_TUNE];
3689 else if (orig_tune_defaulted)
3690 ix86_tune_string = NULL;
3692 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
3693 if (option_strings[IX86_FUNCTION_SPECIFIC_FPMATH])
3694 ix86_fpmath_string = option_strings[IX86_FUNCTION_SPECIFIC_FPMATH];
3695 else if (!TARGET_64BIT && TARGET_SSE)
3696 ix86_fpmath_string = "sse,387";
3698 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
3699 override_options (false);
3701 /* Add any builtin functions with the new isa if any. */
3702 ix86_add_new_builtins (ix86_isa_flags);
3704 /* Save the current options unless we are validating options for
3706 t = build_target_option_node ();
3708 ix86_arch_string = orig_arch_string;
3709 ix86_tune_string = orig_tune_string;
3710 ix86_fpmath_string = orig_fpmath_string;
3712 /* Free up memory allocated to hold the strings */
3713 for (i = 0; i < IX86_FUNCTION_SPECIFIC_MAX; i++)
3714 if (option_strings[i])
3715 free (option_strings[i]);
3721 /* Hook to validate attribute((target("string"))). */
3724 ix86_valid_target_attribute_p (tree fndecl,
3725 tree ARG_UNUSED (name),
3727 int ARG_UNUSED (flags))
3729 struct cl_target_option cur_target;
3731 tree old_optimize = build_optimization_node ();
3732 tree new_target, new_optimize;
3733 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
3735 /* If the function changed the optimization levels as well as setting target
3736 options, start with the optimizations specified. */
3737 if (func_optimize && func_optimize != old_optimize)
3738 cl_optimization_restore (TREE_OPTIMIZATION (func_optimize));
3740 /* The target attributes may also change some optimization flags, so update
3741 the optimization options if necessary. */
3742 cl_target_option_save (&cur_target);
3743 new_target = ix86_valid_target_attribute_tree (args);
3744 new_optimize = build_optimization_node ();
3751 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
3753 if (old_optimize != new_optimize)
3754 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
3757 cl_target_option_restore (&cur_target);
3759 if (old_optimize != new_optimize)
3760 cl_optimization_restore (TREE_OPTIMIZATION (old_optimize));
3766 /* Hook to determine if one function can safely inline another. */
3769 ix86_can_inline_p (tree caller, tree callee)
3772 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
3773 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
3775 /* If callee has no option attributes, then it is ok to inline. */
3779 /* If caller has no option attributes, but callee does then it is not ok to
3781 else if (!caller_tree)
3786 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
3787 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
3789 /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
3790 can inline a SSE2 function but a SSE2 function can't inline a SSE5
3792 if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
3793 != callee_opts->ix86_isa_flags)
3796 /* See if we have the same non-isa options. */
3797 else if (caller_opts->target_flags != callee_opts->target_flags)
3800 /* See if arch, tune, etc. are the same. */
3801 else if (caller_opts->arch != callee_opts->arch)
3804 else if (caller_opts->tune != callee_opts->tune)
3807 else if (caller_opts->fpmath != callee_opts->fpmath)
3810 else if (caller_opts->branch_cost != callee_opts->branch_cost)
3821 /* Remember the last target of ix86_set_current_function. */
3822 static GTY(()) tree ix86_previous_fndecl;
3824 /* Establish appropriate back-end context for processing the function
3825 FNDECL. The argument might be NULL to indicate processing at top
3826 level, outside of any function scope. */
3828 ix86_set_current_function (tree fndecl)
3830 /* Only change the context if the function changes. This hook is called
3831 several times in the course of compiling a function, and we don't want to
3832 slow things down too much or call target_reinit when it isn't safe. */
3833 if (fndecl && fndecl != ix86_previous_fndecl)
3835 tree old_tree = (ix86_previous_fndecl
3836 ? DECL_FUNCTION_SPECIFIC_TARGET (ix86_previous_fndecl)
3839 tree new_tree = (fndecl
3840 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
3843 ix86_previous_fndecl = fndecl;
3844 if (old_tree == new_tree)
3849 cl_target_option_restore (TREE_TARGET_OPTION (new_tree));
3855 struct cl_target_option *def
3856 = TREE_TARGET_OPTION (target_option_current_node);
3858 cl_target_option_restore (def);
3865 /* Return true if this goes in large data/bss. */
3868 ix86_in_large_data_p (tree exp)
3870 if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC)
3873 /* Functions are never large data. */
3874 if (TREE_CODE (exp) == FUNCTION_DECL)
3877 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
3879 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
3880 if (strcmp (section, ".ldata") == 0
3881 || strcmp (section, ".lbss") == 0)
3887 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
3889 /* If this is an incomplete type with size 0, then we can't put it
3890 in data because it might be too big when completed. */
3891 if (!size || size > ix86_section_threshold)
3898 /* Switch to the appropriate section for output of DECL.
3899 DECL is either a `VAR_DECL' node or a constant of some sort.
3900 RELOC indicates whether forming the initial value of DECL requires
3901 link-time relocations. */
3903 static section * x86_64_elf_select_section (tree, int, unsigned HOST_WIDE_INT)
3907 x86_64_elf_select_section (tree decl, int reloc,
3908 unsigned HOST_WIDE_INT align)
3910 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3911 && ix86_in_large_data_p (decl))
3913 const char *sname = NULL;
3914 unsigned int flags = SECTION_WRITE;
3915 switch (categorize_decl_for_section (decl, reloc))
3920 case SECCAT_DATA_REL:
3921 sname = ".ldata.rel";
3923 case SECCAT_DATA_REL_LOCAL:
3924 sname = ".ldata.rel.local";
3926 case SECCAT_DATA_REL_RO:
3927 sname = ".ldata.rel.ro";
3929 case SECCAT_DATA_REL_RO_LOCAL:
3930 sname = ".ldata.rel.ro.local";
3934 flags |= SECTION_BSS;
3937 case SECCAT_RODATA_MERGE_STR:
3938 case SECCAT_RODATA_MERGE_STR_INIT:
3939 case SECCAT_RODATA_MERGE_CONST:
3943 case SECCAT_SRODATA:
3950 /* We don't split these for medium model. Place them into
3951 default sections and hope for best. */
3953 case SECCAT_EMUTLS_VAR:
3954 case SECCAT_EMUTLS_TMPL:
3959 /* We might get called with string constants, but get_named_section
3960 doesn't like them as they are not DECLs. Also, we need to set
3961 flags in that case. */
3963 return get_section (sname, flags, NULL);
3964 return get_named_section (decl, sname, reloc);
3967 return default_elf_select_section (decl, reloc, align);
3970 /* Build up a unique section name, expressed as a
3971 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
3972 RELOC indicates whether the initial value of EXP requires
3973 link-time relocations. */
3975 static void ATTRIBUTE_UNUSED
3976 x86_64_elf_unique_section (tree decl, int reloc)
3978 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
3979 && ix86_in_large_data_p (decl))
3981 const char *prefix = NULL;
3982 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
3983 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP;
3985 switch (categorize_decl_for_section (decl, reloc))
3988 case SECCAT_DATA_REL:
3989 case SECCAT_DATA_REL_LOCAL:
3990 case SECCAT_DATA_REL_RO:
3991 case SECCAT_DATA_REL_RO_LOCAL:
3992 prefix = one_only ? ".ld" : ".ldata";
3995 prefix = one_only ? ".lb" : ".lbss";
3998 case SECCAT_RODATA_MERGE_STR:
3999 case SECCAT_RODATA_MERGE_STR_INIT:
4000 case SECCAT_RODATA_MERGE_CONST:
4001 prefix = one_only ? ".lr" : ".lrodata";
4003 case SECCAT_SRODATA:
4010 /* We don't split these for medium model. Place them into
4011 default sections and hope for best. */
4013 case SECCAT_EMUTLS_VAR:
4014 prefix = targetm.emutls.var_section;
4016 case SECCAT_EMUTLS_TMPL:
4017 prefix = targetm.emutls.tmpl_section;
4022 const char *name, *linkonce;
4025 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
4026 name = targetm.strip_name_encoding (name);
4028 /* If we're using one_only, then there needs to be a .gnu.linkonce
4029 prefix to the section name. */
4030 linkonce = one_only ? ".gnu.linkonce" : "";
4032 string = ACONCAT ((linkonce, prefix, ".", name, NULL));
4034 DECL_SECTION_NAME (decl) = build_string (strlen (string), string);
4038 default_unique_section (decl, reloc);
4041 #ifdef COMMON_ASM_OP
4042 /* This says how to output assembler code to declare an
4043 uninitialized external linkage data object.
4045 For medium model x86-64 we need to use .largecomm opcode for
4048 x86_elf_aligned_common (FILE *file,
4049 const char *name, unsigned HOST_WIDE_INT size,
4052 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4053 && size > (unsigned int)ix86_section_threshold)
4054 fprintf (file, ".largecomm\t");
4056 fprintf (file, "%s", COMMON_ASM_OP);
4057 assemble_name (file, name);
4058 fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n",
4059 size, align / BITS_PER_UNIT);
4063 /* Utility function for targets to use in implementing
4064 ASM_OUTPUT_ALIGNED_BSS. */
4067 x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED,
4068 const char *name, unsigned HOST_WIDE_INT size,
4071 if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC)
4072 && size > (unsigned int)ix86_section_threshold)
4073 switch_to_section (get_named_section (decl, ".lbss", 0));
4075 switch_to_section (bss_section);
4076 ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT));
4077 #ifdef ASM_DECLARE_OBJECT_NAME
4078 last_assemble_variable_decl = decl;
4079 ASM_DECLARE_OBJECT_NAME (file, name, decl);
4081 /* Standard thing is just output label for the object. */
4082 ASM_OUTPUT_LABEL (file, name);
4083 #endif /* ASM_DECLARE_OBJECT_NAME */
4084 ASM_OUTPUT_SKIP (file, size ? size : 1);
4088 optimization_options (int level, int size ATTRIBUTE_UNUSED)
4090 /* For -O2 and beyond, turn off -fschedule-insns by default. It tends to
4091 make the problem with not enough registers even worse. */
4092 #ifdef INSN_SCHEDULING
4094 flag_schedule_insns = 0;
4098 /* The Darwin libraries never set errno, so we might as well
4099 avoid calling them when that's the only reason we would. */
4100 flag_errno_math = 0;
4102 /* The default values of these switches depend on the TARGET_64BIT
4103 that is not known at this moment. Mark these values with 2 and
4104 let user the to override these. In case there is no command line option
4105 specifying them, we will set the defaults in override_options. */
4107 flag_omit_frame_pointer = 2;
4108 flag_pcc_struct_return = 2;
4109 flag_asynchronous_unwind_tables = 2;
4110 flag_vect_cost_model = 1;
4111 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
4112 SUBTARGET_OPTIMIZATION_OPTIONS;
4116 /* Decide whether we can make a sibling call to a function. DECL is the
4117 declaration of the function being targeted by the call and EXP is the
4118 CALL_EXPR representing the call. */
4121 ix86_function_ok_for_sibcall (tree decl, tree exp)
4123 tree type, decl_or_type;
4126 /* If we are generating position-independent code, we cannot sibcall
4127 optimize any indirect call, or a direct call to a global function,
4128 as the PLT requires %ebx be live. */
4129 if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl)))
4132 /* If we need to align the outgoing stack, then sibcalling would
4133 unalign the stack, which may break the called function. */
4134 if (ix86_incoming_stack_boundary < PREFERRED_STACK_BOUNDARY)
4139 decl_or_type = decl;
4140 type = TREE_TYPE (decl);
4144 /* We're looking at the CALL_EXPR, we need the type of the function. */
4145 type = CALL_EXPR_FN (exp); /* pointer expression */
4146 type = TREE_TYPE (type); /* pointer type */
4147 type = TREE_TYPE (type); /* function type */
4148 decl_or_type = type;
4151 /* Check that the return value locations are the same. Like
4152 if we are returning floats on the 80387 register stack, we cannot
4153 make a sibcall from a function that doesn't return a float to a
4154 function that does or, conversely, from a function that does return
4155 a float to a function that doesn't; the necessary stack adjustment
4156 would not be executed. This is also the place we notice
4157 differences in the return value ABI. Note that it is ok for one
4158 of the functions to have void return type as long as the return
4159 value of the other is passed in a register. */
4160 a = ix86_function_value (TREE_TYPE (exp), decl_or_type, false);
4161 b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
4163 if (STACK_REG_P (a) || STACK_REG_P (b))
4165 if (!rtx_equal_p (a, b))
4168 else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
4170 else if (!rtx_equal_p (a, b))
4175 /* The SYSV ABI has more call-clobbered registers;
4176 disallow sibcalls from MS to SYSV. */
4177 if (cfun->machine->call_abi == MS_ABI
4178 && ix86_function_type_abi (type) == SYSV_ABI)
4183 /* If this call is indirect, we'll need to be able to use a
4184 call-clobbered register for the address of the target function.
4185 Make sure that all such registers are not used for passing
4186 parameters. Note that DLLIMPORT functions are indirect. */
4188 || (TARGET_DLLIMPORT_DECL_ATTRIBUTES && DECL_DLLIMPORT_P (decl)))
4190 if (ix86_function_regparm (type, NULL) >= 3)
4192 /* ??? Need to count the actual number of registers to be used,
4193 not the possible number of registers. Fix later. */
4199 /* Otherwise okay. That also includes certain types of indirect calls. */
4203 /* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm"
4204 calling convention attributes;
4205 arguments as in struct attribute_spec.handler. */
4208 ix86_handle_cconv_attribute (tree *node, tree name,
4210 int flags ATTRIBUTE_UNUSED,
4213 if (TREE_CODE (*node) != FUNCTION_TYPE
4214 && TREE_CODE (*node) != METHOD_TYPE
4215 && TREE_CODE (*node) != FIELD_DECL
4216 && TREE_CODE (*node) != TYPE_DECL)
4218 warning (OPT_Wattributes, "%qs attribute only applies to functions",
4219 IDENTIFIER_POINTER (name));
4220 *no_add_attrs = true;
4224 /* Can combine regparm with all attributes but fastcall. */
4225 if (is_attribute_p ("regparm", name))
4229 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4231 error ("fastcall and regparm attributes are not compatible");
4234 cst = TREE_VALUE (args);
4235 if (TREE_CODE (cst) != INTEGER_CST)
4237 warning (OPT_Wattributes,
4238 "%qs attribute requires an integer constant argument",
4239 IDENTIFIER_POINTER (name));
4240 *no_add_attrs = true;
4242 else if (compare_tree_int (cst, REGPARM_MAX) > 0)
4244 warning (OPT_Wattributes, "argument to %qs attribute larger than %d",
4245 IDENTIFIER_POINTER (name), REGPARM_MAX);
4246 *no_add_attrs = true;
4254 /* Do not warn when emulating the MS ABI. */
4255 if (TREE_CODE (*node) != FUNCTION_TYPE || ix86_function_type_abi (*node)!=MS_ABI)
4256 warning (OPT_Wattributes, "%qs attribute ignored",
4257 IDENTIFIER_POINTER (name));
4258 *no_add_attrs = true;
4262 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4263 if (is_attribute_p ("fastcall", name))
4265 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4267 error ("fastcall and cdecl attributes are not compatible");
4269 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4271 error ("fastcall and stdcall attributes are not compatible");
4273 if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
4275 error ("fastcall and regparm attributes are not compatible");
4279 /* Can combine stdcall with fastcall (redundant), regparm and
4281 else if (is_attribute_p ("stdcall", name))
4283 if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node)))
4285 error ("stdcall and cdecl attributes are not compatible");
4287 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4289 error ("stdcall and fastcall attributes are not compatible");
4293 /* Can combine cdecl with regparm and sseregparm. */
4294 else if (is_attribute_p ("cdecl", name))
4296 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
4298 error ("stdcall and cdecl attributes are not compatible");
4300 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
4302 error ("fastcall and cdecl attributes are not compatible");
4306 /* Can combine sseregparm with all attributes. */
4311 /* Return 0 if the attributes for two types are incompatible, 1 if they
4312 are compatible, and 2 if they are nearly compatible (which causes a
4313 warning to be generated). */
4316 ix86_comp_type_attributes (const_tree type1, const_tree type2)
4318 /* Check for mismatch of non-default calling convention. */
4319 const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";
4321 if (TREE_CODE (type1) != FUNCTION_TYPE
4322 && TREE_CODE (type1) != METHOD_TYPE)
4325 /* Check for mismatched fastcall/regparm types. */
4326 if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
4327 != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
4328 || (ix86_function_regparm (type1, NULL)
4329 != ix86_function_regparm (type2, NULL)))
4332 /* Check for mismatched sseregparm types. */
4333 if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1))
4334 != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2)))
4337 /* Check for mismatched return types (cdecl vs stdcall). */
4338 if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
4339 != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
4345 /* Return the regparm value for a function with the indicated TYPE and DECL.
4346 DECL may be NULL when calling function indirectly
4347 or considering a libcall. */
4350 ix86_function_regparm (const_tree type, const_tree decl)
4355 static bool error_issued;
4358 return (ix86_function_type_abi (type) == SYSV_ABI
4359 ? X86_64_REGPARM_MAX : X64_REGPARM_MAX);
4361 regparm = ix86_regparm;
4362 attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
4366 = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
4368 if (decl && TREE_CODE (decl) == FUNCTION_DECL)
4370 /* We can't use regparm(3) for nested functions because
4371 these pass static chain pointer in %ecx register. */
4372 if (!error_issued && regparm == 3
4373 && decl_function_context (decl)
4374 && !DECL_NO_STATIC_CHAIN (decl))
4376 error ("nested functions are limited to 2 register parameters");
4377 error_issued = true;
4385 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
4388 /* Use register calling convention for local functions when possible. */
4390 && TREE_CODE (decl) == FUNCTION_DECL
4394 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4395 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4398 int local_regparm, globals = 0, regno;
4401 /* Make sure no regparm register is taken by a
4402 fixed register variable. */
4403 for (local_regparm = 0; local_regparm < REGPARM_MAX; local_regparm++)
4404 if (fixed_regs[local_regparm])
4407 /* We can't use regparm(3) for nested functions as these use
4408 static chain pointer in third argument. */
4409 if (local_regparm == 3
4410 && decl_function_context (decl)
4411 && !DECL_NO_STATIC_CHAIN (decl))
4414 /* If the function realigns its stackpointer, the prologue will
4415 clobber %ecx. If we've already generated code for the callee,
4416 the callee DECL_STRUCT_FUNCTION is gone, so we fall back to
4417 scanning the attributes for the self-realigning property. */
4418 f = DECL_STRUCT_FUNCTION (decl);
4419 /* Since current internal arg pointer won't conflict with
4420 parameter passing regs, so no need to change stack
4421 realignment and adjust regparm number.
4423 Each fixed register usage increases register pressure,
4424 so less registers should be used for argument passing.
4425 This functionality can be overriden by an explicit
4427 for (regno = 0; regno <= DI_REG; regno++)
4428 if (fixed_regs[regno])
4432 = globals < local_regparm ? local_regparm - globals : 0;
4434 if (local_regparm > regparm)
4435 regparm = local_regparm;
4442 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
4443 DFmode (2) arguments in SSE registers for a function with the
4444 indicated TYPE and DECL. DECL may be NULL when calling function
4445 indirectly or considering a libcall. Otherwise return 0. */
4448 ix86_function_sseregparm (const_tree type, const_tree decl, bool warn)
4450 gcc_assert (!TARGET_64BIT);
4452 /* Use SSE registers to pass SFmode and DFmode arguments if requested
4453 by the sseregparm attribute. */
4454 if (TARGET_SSEREGPARM
4455 || (type && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type))))
4462 error ("Calling %qD with attribute sseregparm without "
4463 "SSE/SSE2 enabled", decl);
4465 error ("Calling %qT with attribute sseregparm without "
4466 "SSE/SSE2 enabled", type);
4474 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
4475 (and DFmode for SSE2) arguments in SSE registers. */
4476 if (decl && TARGET_SSE_MATH && optimize && !profile_flag)
4478 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
4479 struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
4481 return TARGET_SSE2 ? 2 : 1;
4487 /* Return true if EAX is live at the start of the function. Used by
4488 ix86_expand_prologue to determine if we need special help before
4489 calling allocate_stack_worker. */
4492 ix86_eax_live_at_start_p (void)
4494 /* Cheat. Don't bother working forward from ix86_function_regparm
4495 to the function type to whether an actual argument is located in
4496 eax. Instead just look at cfg info, which is still close enough
4497 to correct at this point. This gives false positives for broken
4498 functions that might use uninitialized data that happens to be
4499 allocated in eax, but who cares? */
4500 return REGNO_REG_SET_P (df_get_live_out (ENTRY_BLOCK_PTR), 0);
4503 /* Value is the number of bytes of arguments automatically
4504 popped when returning from a subroutine call.
4505 FUNDECL is the declaration node of the function (as a tree),
4506 FUNTYPE is the data type of the function (as a tree),
4507 or for a library call it is an identifier node for the subroutine name.
4508 SIZE is the number of bytes of arguments passed on the stack.
4510 On the 80386, the RTD insn may be used to pop them if the number
4511 of args is fixed, but if the number is variable then the caller
4512 must pop them all. RTD can't be used for library calls now
4513 because the library is compiled with the Unix compiler.
4514 Use of RTD is a selectable option, since it is incompatible with
4515 standard Unix calling sequences. If the option is not selected,
4516 the caller must always pop the args.
4518 The attribute stdcall is equivalent to RTD on a per module basis. */
4521 ix86_return_pops_args (tree fundecl, tree funtype, int size)
4525 /* None of the 64-bit ABIs pop arguments. */
4529 rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);
4531 /* Cdecl functions override -mrtd, and never pop the stack. */
4532 if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype)))
4534 /* Stdcall and fastcall functions will pop the stack if not
4536 if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
4537 || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
4540 if (rtd && ! stdarg_p (funtype))
4544 /* Lose any fake structure return argument if it is passed on the stack. */
4545 if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
4546 && !KEEP_AGGREGATE_RETURN_POINTER)
4548 int nregs = ix86_function_regparm (funtype, fundecl);
4550 return GET_MODE_SIZE (Pmode);
4556 /* Argument support functions. */
4558 /* Return true when register may be used to pass function parameters. */
4560 ix86_function_arg_regno_p (int regno)
4563 const int *parm_regs;
4568 return (regno < REGPARM_MAX
4569 || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
4571 return (regno < REGPARM_MAX
4572 || (TARGET_MMX && MMX_REGNO_P (regno)
4573 && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX))
4574 || (TARGET_SSE && SSE_REGNO_P (regno)
4575 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)));
4580 if (SSE_REGNO_P (regno) && TARGET_SSE)
4585 if (TARGET_SSE && SSE_REGNO_P (regno)
4586 && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))
4590 /* TODO: The function should depend on current function ABI but
4591 builtins.c would need updating then. Therefore we use the
4594 /* RAX is used as hidden argument to va_arg functions. */
4595 if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
4598 if (DEFAULT_ABI == MS_ABI)
4599 parm_regs = x86_64_ms_abi_int_parameter_registers;
4601 parm_regs = x86_64_int_parameter_registers;
4602 for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
4603 : X86_64_REGPARM_MAX); i++)
4604 if (regno == parm_regs[i])
4609 /* Return if we do not know how to pass TYPE solely in registers. */
4612 ix86_must_pass_in_stack (enum machine_mode mode, const_tree type)
4614 if (must_pass_in_stack_var_size_or_pad (mode, type))
4617 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
4618 The layout_type routine is crafty and tries to trick us into passing
4619 currently unsupported vector types on the stack by using TImode. */
4620 return (!TARGET_64BIT && mode == TImode
4621 && type && TREE_CODE (type) != VECTOR_TYPE);
4624 /* It returns the size, in bytes, of the area reserved for arguments passed
4625 in registers for the function represented by fndecl dependent to the used
4628 ix86_reg_parm_stack_space (const_tree fndecl)
4630 int call_abi = SYSV_ABI;
4631 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
4632 call_abi = ix86_function_abi (fndecl);
4634 call_abi = ix86_function_type_abi (fndecl);
4635 if (call_abi == MS_ABI)
4640 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
4643 ix86_function_type_abi (const_tree fntype)
4645 if (TARGET_64BIT && fntype != NULL)
4648 if (DEFAULT_ABI == SYSV_ABI)
4649 abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
4651 abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
4659 ix86_function_abi (const_tree fndecl)
4663 return ix86_function_type_abi (TREE_TYPE (fndecl));
4666 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
4669 ix86_cfun_abi (void)
4671 if (! cfun || ! TARGET_64BIT)
4673 return cfun->machine->call_abi;
4677 extern void init_regs (void);
4679 /* Implementation of call abi switching target hook. Specific to FNDECL
4680 the specific call register sets are set. See also CONDITIONAL_REGISTER_USAGE
4681 for more details. */
4683 ix86_call_abi_override (const_tree fndecl)
4685 if (fndecl == NULL_TREE)
4686 cfun->machine->call_abi = DEFAULT_ABI;
4688 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
4691 /* MS and SYSV ABI have different set of call used registers. Avoid expensive
4692 re-initialization of init_regs each time we switch function context since
4693 this is needed only during RTL expansion. */
4695 ix86_maybe_switch_abi (void)
4698 call_used_regs[SI_REG] == (cfun->machine->call_abi == MS_ABI))
4702 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4703 for a call to a function whose data type is FNTYPE.
4704 For a library call, FNTYPE is 0. */
4707 init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */
4708 tree fntype, /* tree ptr for function decl */
4709 rtx libname, /* SYMBOL_REF of library name or 0 */
4712 struct cgraph_local_info *i = fndecl ? cgraph_local_info (fndecl) : NULL;
4713 memset (cum, 0, sizeof (*cum));
4716 cum->call_abi = ix86_function_abi (fndecl);
4718 cum->call_abi = ix86_function_type_abi (fntype);
4719 /* Set up the number of registers to use for passing arguments. */
4721 if (cum->call_abi == MS_ABI && !ACCUMULATE_OUTGOING_ARGS)
4722 sorry ("ms_abi attribute requires -maccumulate-outgoing-args "
4723 "or subtarget optimization implying it");
4724 cum->nregs = ix86_regparm;
4727 if (cum->call_abi != DEFAULT_ABI)
4728 cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
4733 cum->sse_nregs = SSE_REGPARM_MAX;
4736 if (cum->call_abi != DEFAULT_ABI)
4737 cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
4738 : X64_SSE_REGPARM_MAX;
4742 cum->mmx_nregs = MMX_REGPARM_MAX;
4743 cum->warn_avx = true;
4744 cum->warn_sse = true;
4745 cum->warn_mmx = true;
4747 /* Because type might mismatch in between caller and callee, we need to
4748 use actual type of function for local calls.
4749 FIXME: cgraph_analyze can be told to actually record if function uses
4750 va_start so for local functions maybe_vaarg can be made aggressive
4752 FIXME: once typesytem is fixed, we won't need this code anymore. */
4754 fntype = TREE_TYPE (fndecl);
4755 cum->maybe_vaarg = (fntype
4756 ? (!prototype_p (fntype) || stdarg_p (fntype))
4761 /* If there are variable arguments, then we won't pass anything
4762 in registers in 32-bit mode. */
4763 if (stdarg_p (fntype))
4774 /* Use ecx and edx registers if function has fastcall attribute,
4775 else look for regparm information. */
4778 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
4784 cum->nregs = ix86_function_regparm (fntype, fndecl);
4787 /* Set up the number of SSE registers used for passing SFmode
4788 and DFmode arguments. Warn for mismatching ABI. */
4789 cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl, true);
4793 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
4794 But in the case of vector types, it is some vector mode.
4796 When we have only some of our vector isa extensions enabled, then there
4797 are some modes for which vector_mode_supported_p is false. For these
4798 modes, the generic vector support in gcc will choose some non-vector mode
4799 in order to implement the type. By computing the natural mode, we'll
4800 select the proper ABI location for the operand and not depend on whatever
4801 the middle-end decides to do with these vector types.
4803 The midde-end can't deal with the vector types > 16 bytes. In this
4804 case, we return the original mode and warn ABI change if CUM isn't
4807 static enum machine_mode
4808 type_natural_mode (const_tree type, CUMULATIVE_ARGS *cum)
4810 enum machine_mode mode = TYPE_MODE (type);
4812 if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
4814 HOST_WIDE_INT size = int_size_in_bytes (type);
4815 if ((size == 8 || size == 16 || size == 32)
4816 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
4817 && TYPE_VECTOR_SUBPARTS (type) > 1)
4819 enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));
4821 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
4822 mode = MIN_MODE_VECTOR_FLOAT;
4824 mode = MIN_MODE_VECTOR_INT;
4826 /* Get the mode which has this inner mode and number of units. */
4827 for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
4828 if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
4829 && GET_MODE_INNER (mode) == innermode)
4831 if (size == 32 && !TARGET_AVX)
4833 static bool warnedavx;
4840 warning (0, "AVX vector argument without AVX "
4841 "enabled changes the ABI");
4843 return TYPE_MODE (type);
4856 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
4857 this may not agree with the mode that the type system has chosen for the
4858 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
4859 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
4862 gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
4867 if (orig_mode != BLKmode)
4868 tmp = gen_rtx_REG (orig_mode, regno);
4871 tmp = gen_rtx_REG (mode, regno);
4872 tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
4873 tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
4879 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
4880 of this code is to classify each 8bytes of incoming argument by the register
4881 class and assign registers accordingly. */
4883 /* Return the union class of CLASS1 and CLASS2.
4884 See the x86-64 PS ABI for details. */
4886 static enum x86_64_reg_class
4887 merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
4889 /* Rule #1: If both classes are equal, this is the resulting class. */
4890 if (class1 == class2)
4893 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
4895 if (class1 == X86_64_NO_CLASS)
4897 if (class2 == X86_64_NO_CLASS)
4900 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
4901 if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
4902 return X86_64_MEMORY_CLASS;
4904 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
4905 if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
4906 || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
4907 return X86_64_INTEGERSI_CLASS;
4908 if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
4909 || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
4910 return X86_64_INTEGER_CLASS;
4912 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
4914 if (class1 == X86_64_X87_CLASS
4915 || class1 == X86_64_X87UP_CLASS
4916 || class1 == X86_64_COMPLEX_X87_CLASS
4917 || class2 == X86_64_X87_CLASS
4918 || class2 == X86_64_X87UP_CLASS
4919 || class2 == X86_64_COMPLEX_X87_CLASS)
4920 return X86_64_MEMORY_CLASS;
4922 /* Rule #6: Otherwise class SSE is used. */
4923 return X86_64_SSE_CLASS;
4926 /* Classify the argument of type TYPE and mode MODE.
4927 CLASSES will be filled by the register class used to pass each word
4928 of the operand. The number of words is returned. In case the parameter
4929 should be passed in memory, 0 is returned. As a special case for zero
4930 sized containers, classes[0] will be NO_CLASS and 1 is returned.
4932 BIT_OFFSET is used internally for handling records and specifies offset
4933 of the offset in bits modulo 256 to avoid overflow cases.
4935 See the x86-64 PS ABI for details.
4939 classify_argument (enum machine_mode mode, const_tree type,
4940 enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
4942 HOST_WIDE_INT bytes =
4943 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
4944 int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4946 /* Variable sized entities are always passed/returned in memory. */
4950 if (mode != VOIDmode
4951 && targetm.calls.must_pass_in_stack (mode, type))
4954 if (type && AGGREGATE_TYPE_P (type))
4958 enum x86_64_reg_class subclasses[MAX_CLASSES];
4960 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
4964 for (i = 0; i < words; i++)
4965 classes[i] = X86_64_NO_CLASS;
4967 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
4968 signalize memory class, so handle it as special case. */
4971 classes[0] = X86_64_NO_CLASS;
4975 /* Classify each field of record and merge classes. */
4976 switch (TREE_CODE (type))
4979 /* And now merge the fields of structure. */
4980 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4982 if (TREE_CODE (field) == FIELD_DECL)
4986 if (TREE_TYPE (field) == error_mark_node)
4989 /* Bitfields are always classified as integer. Handle them
4990 early, since later code would consider them to be
4991 misaligned integers. */
4992 if (DECL_BIT_FIELD (field))
4994 for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
4995 i < ((int_bit_position (field) + (bit_offset % 64))
4996 + tree_low_cst (DECL_SIZE (field), 0)
4999 merge_classes (X86_64_INTEGER_CLASS,
5004 type = TREE_TYPE (field);
5006 /* Flexible array member is ignored. */
5007 if (TYPE_MODE (type) == BLKmode
5008 && TREE_CODE (type) == ARRAY_TYPE
5009 && TYPE_SIZE (type) == NULL_TREE
5010 && TYPE_DOMAIN (type) != NULL_TREE
5011 && (TYPE_MAX_VALUE (TYPE_DOMAIN (type))
5016 if (!warned && warn_psabi)
5019 inform (input_location,
5020 "The ABI of passing struct with"
5021 " a flexible array member has"
5022 " changed in GCC 4.4");
5026 num = classify_argument (TYPE_MODE (type), type,
5028 (int_bit_position (field)
5029 + bit_offset) % 256);
5032 for (i = 0; i < num; i++)
5035 (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
5037 merge_classes (subclasses[i], classes[i + pos]);
5045 /* Arrays are handled as small records. */
5048 num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
5049 TREE_TYPE (type), subclasses, bit_offset);
5053 /* The partial classes are now full classes. */
5054 if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
5055 subclasses[0] = X86_64_SSE_CLASS;
5056 if (subclasses[0] == X86_64_INTEGERSI_CLASS
5057 && !((bit_offset % 64) == 0 && bytes == 4))
5058 subclasses[0] = X86_64_INTEGER_CLASS;
5060 for (i = 0; i < words; i++)
5061 classes[i] = subclasses[i % num];
5066 case QUAL_UNION_TYPE:
5067 /* Unions are similar to RECORD_TYPE but offset is always 0.
5069 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5071 if (TREE_CODE (field) == FIELD_DECL)
5075 if (TREE_TYPE (field) == error_mark_node)
5078 num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
5079 TREE_TYPE (field), subclasses,
5083 for (i = 0; i < num; i++)
5084 classes[i] = merge_classes (subclasses[i], classes[i]);
5095 /* When size > 16 bytes, if the first one isn't
5096 X86_64_SSE_CLASS or any other ones aren't
5097 X86_64_SSEUP_CLASS, everything should be passed in
5099 if (classes[0] != X86_64_SSE_CLASS)
5102 for (i = 1; i < words; i++)
5103 if (classes[i] != X86_64_SSEUP_CLASS)
5107 /* Final merger cleanup. */
5108 for (i = 0; i < words; i++)
5110 /* If one class is MEMORY, everything should be passed in
5112 if (classes[i] == X86_64_MEMORY_CLASS)
5115 /* The X86_64_SSEUP_CLASS should be always preceded by
5116 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
5117 if (classes[i] == X86_64_SSEUP_CLASS
5118 && classes[i - 1] != X86_64_SSE_CLASS
5119 && classes[i - 1] != X86_64_SSEUP_CLASS)
5121 /* The first one should never be X86_64_SSEUP_CLASS. */
5122 gcc_assert (i != 0);
5123 classes[i] = X86_64_SSE_CLASS;
5126 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
5127 everything should be passed in memory. */
5128 if (classes[i] == X86_64_X87UP_CLASS
5129 && (classes[i - 1] != X86_64_X87_CLASS))
5133 /* The first one should never be X86_64_X87UP_CLASS. */
5134 gcc_assert (i != 0);
5135 if (!warned && warn_psabi)
5138 inform (input_location,
5139 "The ABI of passing union with long double"
5140 " has changed in GCC 4.4");
5148 /* Compute alignment needed. We align all types to natural boundaries with
5149 exception of XFmode that is aligned to 64bits. */
5150 if (mode != VOIDmode && mode != BLKmode)
5152 int mode_alignment = GET_MODE_BITSIZE (mode);
5155 mode_alignment = 128;
5156 else if (mode == XCmode)
5157 mode_alignment = 256;
5158 if (COMPLEX_MODE_P (mode))
5159 mode_alignment /= 2;
5160 /* Misaligned fields are always returned in memory. */
5161 if (bit_offset % mode_alignment)
5165 /* for V1xx modes, just use the base mode */
5166 if (VECTOR_MODE_P (mode) && mode != V1DImode
5167 && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
5168 mode = GET_MODE_INNER (mode);
5170 /* Classification of atomic types. */
5175 classes[0] = X86_64_SSE_CLASS;
5178 classes[0] = X86_64_SSE_CLASS;
5179 classes[1] = X86_64_SSEUP_CLASS;
5189 int size = (bit_offset % 64)+ (int) GET_MODE_BITSIZE (mode);
5193 classes[0] = X86_64_INTEGERSI_CLASS;
5196 else if (size <= 64)
5198 classes[0] = X86_64_INTEGER_CLASS;
5201 else if (size <= 64+32)
5203 classes[0] = X86_64_INTEGER_CLASS;
5204 classes[1] = X86_64_INTEGERSI_CLASS;
5207 else if (size <= 64+64)
5209 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5217 classes[0] = classes[1] = X86_64_INTEGER_CLASS;
5221 /* OImode shouldn't be used directly. */
5226 if (!(bit_offset % 64))
5227 classes[0] = X86_64_SSESF_CLASS;
5229 classes[0] = X86_64_SSE_CLASS;
5232 classes[0] = X86_64_SSEDF_CLASS;
5235 classes[0] = X86_64_X87_CLASS;
5236 classes[1] = X86_64_X87UP_CLASS;
5239 classes[0] = X86_64_SSE_CLASS;
5240 classes[1] = X86_64_SSEUP_CLASS;
5243 classes[0] = X86_64_SSE_CLASS;
5244 if (!(bit_offset % 64))
5250 if (!warned && warn_psabi)
5253 inform (input_location,
5254 "The ABI of passing structure with complex float"
5255 " member has changed in GCC 4.4");
5257 classes[1] = X86_64_SSESF_CLASS;
5261 classes[0] = X86_64_SSEDF_CLASS;
5262 classes[1] = X86_64_SSEDF_CLASS;
5265 classes[0] = X86_64_COMPLEX_X87_CLASS;
5268 /* This modes is larger than 16 bytes. */
5276 classes[0] = X86_64_SSE_CLASS;
5277 classes[1] = X86_64_SSEUP_CLASS;
5278 classes[2] = X86_64_SSEUP_CLASS;
5279 classes[3] = X86_64_SSEUP_CLASS;
5287 classes[0] = X86_64_SSE_CLASS;
5288 classes[1] = X86_64_SSEUP_CLASS;
5295 classes[0] = X86_64_SSE_CLASS;
5301 gcc_assert (VECTOR_MODE_P (mode));
5306 gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT);
5308 if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
5309 classes[0] = X86_64_INTEGERSI_CLASS;
5311 classes[0] = X86_64_INTEGER_CLASS;
5312 classes[1] = X86_64_INTEGER_CLASS;
5313 return 1 + (bytes > 8);
5317 /* Examine the argument and return set number of register required in each
5318 class. Return 0 iff parameter should be passed in memory. */
5320 examine_argument (enum machine_mode mode, const_tree type, int in_return,
5321 int *int_nregs, int *sse_nregs)
5323 enum x86_64_reg_class regclass[MAX_CLASSES];
5324 int n = classify_argument (mode, type, regclass, 0);
5330 for (n--; n >= 0; n--)
5331 switch (regclass[n])
5333 case X86_64_INTEGER_CLASS:
5334 case X86_64_INTEGERSI_CLASS:
5337 case X86_64_SSE_CLASS:
5338 case X86_64_SSESF_CLASS:
5339 case X86_64_SSEDF_CLASS:
5342 case X86_64_NO_CLASS:
5343 case X86_64_SSEUP_CLASS:
5345 case X86_64_X87_CLASS:
5346 case X86_64_X87UP_CLASS:
5350 case X86_64_COMPLEX_X87_CLASS:
5351 return in_return ? 2 : 0;
5352 case X86_64_MEMORY_CLASS:
5358 /* Construct container for the argument used by GCC interface. See
5359 FUNCTION_ARG for the detailed description. */
5362 construct_container (enum machine_mode mode, enum machine_mode orig_mode,
5363 const_tree type, int in_return, int nintregs, int nsseregs,
5364 const int *intreg, int sse_regno)
5366 /* The following variables hold the static issued_error state. */
5367 static bool issued_sse_arg_error;
5368 static bool issued_sse_ret_error;
5369 static bool issued_x87_ret_error;
5371 enum machine_mode tmpmode;
5373 (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
5374 enum x86_64_reg_class regclass[MAX_CLASSES];
5378 int needed_sseregs, needed_intregs;
5379 rtx exp[MAX_CLASSES];
5382 n = classify_argument (mode, type, regclass, 0);
5385 if (!examine_argument (mode, type, in_return, &needed_intregs,
5388 if (needed_intregs > nintregs || needed_sseregs > nsseregs)
5391 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
5392 some less clueful developer tries to use floating-point anyway. */
5393 if (needed_sseregs && !TARGET_SSE)
5397 if (!issued_sse_ret_error)
5399 error ("SSE register return with SSE disabled");
5400 issued_sse_ret_error = true;
5403 else if (!issued_sse_arg_error)
5405 error ("SSE register argument with SSE disabled");
5406 issued_sse_arg_error = true;
5411 /* Likewise, error if the ABI requires us to return values in the
5412 x87 registers and the user specified -mno-80387. */
5413 if (!TARGET_80387 && in_return)
5414 for (i = 0; i < n; i++)
5415 if (regclass[i] == X86_64_X87_CLASS
5416 || regclass[i] == X86_64_X87UP_CLASS
5417 || regclass[i] == X86_64_COMPLEX_X87_CLASS)
5419 if (!issued_x87_ret_error)
5421 error ("x87 register return with x87 disabled");
5422 issued_x87_ret_error = true;
5427 /* First construct simple cases. Avoid SCmode, since we want to use
5428 single register to pass this type. */
5429 if (n == 1 && mode != SCmode)
5430 switch (regclass[0])
5432 case X86_64_INTEGER_CLASS:
5433 case X86_64_INTEGERSI_CLASS:
5434 return gen_rtx_REG (mode, intreg[0]);
5435 case X86_64_SSE_CLASS:
5436 case X86_64_SSESF_CLASS:
5437 case X86_64_SSEDF_CLASS:
5438 if (mode != BLKmode)
5439 return gen_reg_or_parallel (mode, orig_mode,
5440 SSE_REGNO (sse_regno));
5442 case X86_64_X87_CLASS:
5443 case X86_64_COMPLEX_X87_CLASS:
5444 return gen_rtx_REG (mode, FIRST_STACK_REG);
5445 case X86_64_NO_CLASS:
5446 /* Zero sized array, struct or class. */
5451 if (n == 2 && regclass[0] == X86_64_SSE_CLASS
5452 && regclass[1] == X86_64_SSEUP_CLASS && mode != BLKmode)
5453 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5455 && regclass[0] == X86_64_SSE_CLASS
5456 && regclass[1] == X86_64_SSEUP_CLASS
5457 && regclass[2] == X86_64_SSEUP_CLASS
5458 && regclass[3] == X86_64_SSEUP_CLASS
5460 return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
5463 && regclass[0] == X86_64_X87_CLASS && regclass[1] == X86_64_X87UP_CLASS)
5464 return gen_rtx_REG (XFmode, FIRST_STACK_REG);
5465 if (n == 2 && regclass[0] == X86_64_INTEGER_CLASS
5466 && regclass[1] == X86_64_INTEGER_CLASS
5467 && (mode == CDImode || mode == TImode || mode == TFmode)
5468 && intreg[0] + 1 == intreg[1])
5469 return gen_rtx_REG (mode, intreg[0]);
5471 /* Otherwise figure out the entries of the PARALLEL. */
5472 for (i = 0; i < n; i++)
5476 switch (regclass[i])
5478 case X86_64_NO_CLASS:
5480 case X86_64_INTEGER_CLASS:
5481 case X86_64_INTEGERSI_CLASS:
5482 /* Merge TImodes on aligned occasions here too. */
5483 if (i * 8 + 8 > bytes)
5484 tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
5485 else if (regclass[i] == X86_64_INTEGERSI_CLASS)
5489 /* We've requested 24 bytes we don't have mode for. Use DImode. */
5490 if (tmpmode == BLKmode)
5492 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5493 gen_rtx_REG (tmpmode, *intreg),
5497 case X86_64_SSESF_CLASS:
5498 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5499 gen_rtx_REG (SFmode,
5500 SSE_REGNO (sse_regno)),
5504 case X86_64_SSEDF_CLASS:
5505 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5506 gen_rtx_REG (DFmode,
5507 SSE_REGNO (sse_regno)),
5511 case X86_64_SSE_CLASS:
5519 if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
5529 && regclass[1] == X86_64_SSEUP_CLASS
5530 && regclass[2] == X86_64_SSEUP_CLASS
5531 && regclass[3] == X86_64_SSEUP_CLASS);
5538 exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
5539 gen_rtx_REG (tmpmode,
5540 SSE_REGNO (sse_regno)),
5549 /* Empty aligned struct, union or class. */
5553 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
5554 for (i = 0; i < nexps; i++)
5555 XVECEXP (ret, 0, i) = exp [i];
5559 /* Update the data in CUM to advance over an argument of mode MODE
5560 and data type TYPE. (TYPE is null for libcalls where that information
5561 may not be available.) */
5564 function_arg_advance_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5565 tree type, HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5581 cum->words += words;
5582 cum->nregs -= words;
5583 cum->regno += words;
5585 if (cum->nregs <= 0)
5593 /* OImode shouldn't be used directly. */
5597 if (cum->float_in_sse < 2)
5600 if (cum->float_in_sse < 1)
5617 if (!type || !AGGREGATE_TYPE_P (type))
5619 cum->sse_words += words;
5620 cum->sse_nregs -= 1;
5621 cum->sse_regno += 1;
5622 if (cum->sse_nregs <= 0)
5635 if (!type || !AGGREGATE_TYPE_P (type))
5637 cum->mmx_words += words;
5638 cum->mmx_nregs -= 1;
5639 cum->mmx_regno += 1;
5640 if (cum->mmx_nregs <= 0)
5651 function_arg_advance_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5652 tree type, HOST_WIDE_INT words, int named)
5654 int int_nregs, sse_nregs;
5656 /* Unnamed 256bit vector mode parameters are passed on stack. */
5657 if (!named && VALID_AVX256_REG_MODE (mode))
5660 if (examine_argument (mode, type, 0, &int_nregs, &sse_nregs)
5661 && sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
5663 cum->nregs -= int_nregs;
5664 cum->sse_nregs -= sse_nregs;
5665 cum->regno += int_nregs;
5666 cum->sse_regno += sse_nregs;
5670 int align = ix86_function_arg_boundary (mode, type) / BITS_PER_WORD;
5671 cum->words = (cum->words + align - 1) & ~(align - 1);
5672 cum->words += words;
5677 function_arg_advance_ms_64 (CUMULATIVE_ARGS *cum, HOST_WIDE_INT bytes,
5678 HOST_WIDE_INT words)
5680 /* Otherwise, this should be passed indirect. */
5681 gcc_assert (bytes == 1 || bytes == 2 || bytes == 4 || bytes == 8);
5683 cum->words += words;
5692 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5693 tree type, int named)
5695 HOST_WIDE_INT bytes, words;
5697 if (mode == BLKmode)
5698 bytes = int_size_in_bytes (type);
5700 bytes = GET_MODE_SIZE (mode);
5701 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5704 mode = type_natural_mode (type, NULL);
5706 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5707 function_arg_advance_ms_64 (cum, bytes, words);
5708 else if (TARGET_64BIT)
5709 function_arg_advance_64 (cum, mode, type, words, named);
5711 function_arg_advance_32 (cum, mode, type, bytes, words);
5714 /* Define where to put the arguments to a function.
5715 Value is zero to push the argument on the stack,
5716 or a hard register in which to store the argument.
5718 MODE is the argument's machine mode.
5719 TYPE is the data type of the argument (as a tree).
5720 This is null for libcalls where that information may
5722 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5723 the preceding args and about the function being called.
5724 NAMED is nonzero if this argument is a named parameter
5725 (otherwise it is an extra parameter matching an ellipsis). */
5728 function_arg_32 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5729 enum machine_mode orig_mode, tree type,
5730 HOST_WIDE_INT bytes, HOST_WIDE_INT words)
5732 static bool warnedsse, warnedmmx;
5734 /* Avoid the AL settings for the Unix64 ABI. */
5735 if (mode == VOIDmode)
5751 if (words <= cum->nregs)
5753 int regno = cum->regno;
5755 /* Fastcall allocates the first two DWORD (SImode) or
5756 smaller arguments to ECX and EDX if it isn't an
5762 || (type && AGGREGATE_TYPE_P (type)))
5765 /* ECX not EAX is the first allocated register. */
5766 if (regno == AX_REG)
5769 return gen_rtx_REG (mode, regno);
5774 if (cum->float_in_sse < 2)
5777 if (cum->float_in_sse < 1)
5781 /* In 32bit, we pass TImode in xmm registers. */
5788 if (!type || !AGGREGATE_TYPE_P (type))
5790 if (!TARGET_SSE && !warnedsse && cum->warn_sse)
5793 warning (0, "SSE vector argument without SSE enabled "
5797 return gen_reg_or_parallel (mode, orig_mode,
5798 cum->sse_regno + FIRST_SSE_REG);
5803 /* OImode shouldn't be used directly. */
5812 if (!type || !AGGREGATE_TYPE_P (type))
5815 return gen_reg_or_parallel (mode, orig_mode,
5816 cum->sse_regno + FIRST_SSE_REG);
5825 if (!type || !AGGREGATE_TYPE_P (type))
5827 if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
5830 warning (0, "MMX vector argument without MMX enabled "
5834 return gen_reg_or_parallel (mode, orig_mode,
5835 cum->mmx_regno + FIRST_MMX_REG);
5844 function_arg_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5845 enum machine_mode orig_mode, tree type, int named)
5847 /* Handle a hidden AL argument containing number of registers
5848 for varargs x86-64 functions. */
5849 if (mode == VOIDmode)
5850 return GEN_INT (cum->maybe_vaarg
5851 ? (cum->sse_nregs < 0
5852 ? (cum->call_abi == DEFAULT_ABI
5854 : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
5855 : X64_SSE_REGPARM_MAX))
5870 /* Unnamed 256bit vector mode parameters are passed on stack. */
5876 return construct_container (mode, orig_mode, type, 0, cum->nregs,
5878 &x86_64_int_parameter_registers [cum->regno],
5883 function_arg_ms_64 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5884 enum machine_mode orig_mode, int named,
5885 HOST_WIDE_INT bytes)
5889 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
5890 We use value of -2 to specify that current function call is MSABI. */
5891 if (mode == VOIDmode)
5892 return GEN_INT (-2);
5894 /* If we've run out of registers, it goes on the stack. */
5895 if (cum->nregs == 0)
5898 regno = x86_64_ms_abi_int_parameter_registers[cum->regno];
5900 /* Only floating point modes are passed in anything but integer regs. */
5901 if (TARGET_SSE && (mode == SFmode || mode == DFmode))
5904 regno = cum->regno + FIRST_SSE_REG;
5909 /* Unnamed floating parameters are passed in both the
5910 SSE and integer registers. */
5911 t1 = gen_rtx_REG (mode, cum->regno + FIRST_SSE_REG);
5912 t2 = gen_rtx_REG (mode, regno);
5913 t1 = gen_rtx_EXPR_LIST (VOIDmode, t1, const0_rtx);
5914 t2 = gen_rtx_EXPR_LIST (VOIDmode, t2, const0_rtx);
5915 return gen_rtx_PARALLEL (mode, gen_rtvec (2, t1, t2));
5918 /* Handle aggregated types passed in register. */
5919 if (orig_mode == BLKmode)
5921 if (bytes > 0 && bytes <= 8)
5922 mode = (bytes > 4 ? DImode : SImode);
5923 if (mode == BLKmode)
5927 return gen_reg_or_parallel (mode, orig_mode, regno);
5931 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode omode,
5932 tree type, int named)
5934 enum machine_mode mode = omode;
5935 HOST_WIDE_INT bytes, words;
5937 if (mode == BLKmode)
5938 bytes = int_size_in_bytes (type);
5940 bytes = GET_MODE_SIZE (mode);
5941 words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5943 /* To simplify the code below, represent vector types with a vector mode
5944 even if MMX/SSE are not active. */
5945 if (type && TREE_CODE (type) == VECTOR_TYPE)
5946 mode = type_natural_mode (type, cum);
5948 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5949 return function_arg_ms_64 (cum, mode, omode, named, bytes);
5950 else if (TARGET_64BIT)
5951 return function_arg_64 (cum, mode, omode, type, named);
5953 return function_arg_32 (cum, mode, omode, type, bytes, words);
5956 /* A C expression that indicates when an argument must be passed by
5957 reference. If nonzero for an argument, a copy of that argument is
5958 made in memory and a pointer to the argument is passed instead of
5959 the argument itself. The pointer is passed in whatever way is
5960 appropriate for passing a pointer to that type. */
5963 ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5964 enum machine_mode mode ATTRIBUTE_UNUSED,
5965 const_tree type, bool named ATTRIBUTE_UNUSED)
5967 /* See Windows x64 Software Convention. */
5968 if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
5970 int msize = (int) GET_MODE_SIZE (mode);
5973 /* Arrays are passed by reference. */
5974 if (TREE_CODE (type) == ARRAY_TYPE)
5977 if (AGGREGATE_TYPE_P (type))
5979 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
5980 are passed by reference. */
5981 msize = int_size_in_bytes (type);
5985 /* __m128 is passed by reference. */
5987 case 1: case 2: case 4: case 8:
5993 else if (TARGET_64BIT && type && int_size_in_bytes (type) == -1)
5999 /* Return true when TYPE should be 128bit aligned for 32bit argument passing
6002 contains_aligned_value_p (const_tree type)
6004 enum machine_mode mode = TYPE_MODE (type);
6005 if (((TARGET_SSE && SSE_REG_MODE_P (mode))
6009 && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
6011 if (TYPE_ALIGN (type) < 128)
6014 if (AGGREGATE_TYPE_P (type))
6016 /* Walk the aggregates recursively. */
6017 switch (TREE_CODE (type))
6021 case QUAL_UNION_TYPE:
6025 /* Walk all the structure fields. */
6026 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
6028 if (TREE_CODE (field) == FIELD_DECL
6029 && contains_aligned_value_p (TREE_TYPE (field)))
6036 /* Just for use if some languages passes arrays by value. */
6037 if (contains_aligned_value_p (TREE_TYPE (type)))
6048 /* Gives the alignment boundary, in bits, of an argument with the
6049 specified mode and type. */
6052 ix86_function_arg_boundary (enum machine_mode mode, const_tree type)
6057 /* Since canonical type is used for call, we convert it to
6058 canonical type if needed. */
6059 if (!TYPE_STRUCTURAL_EQUALITY_P (type))
6060 type = TYPE_CANONICAL (type);
6061 align = TYPE_ALIGN (type);
6064 align = GET_MODE_ALIGNMENT (mode);
6065 if (align < PARM_BOUNDARY)
6066 align = PARM_BOUNDARY;
6067 /* In 32bit, only _Decimal128 and __float128 are aligned to their
6068 natural boundaries. */
6069 if (!TARGET_64BIT && mode != TDmode && mode != TFmode)
6071 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
6072 make an exception for SSE modes since these require 128bit
6075 The handling here differs from field_alignment. ICC aligns MMX
6076 arguments to 4 byte boundaries, while structure fields are aligned
6077 to 8 byte boundaries. */
6080 if (!(TARGET_SSE && SSE_REG_MODE_P (mode)))
6081 align = PARM_BOUNDARY;
6085 if (!contains_aligned_value_p (type))
6086 align = PARM_BOUNDARY;
6089 if (align > BIGGEST_ALIGNMENT)
6090 align = BIGGEST_ALIGNMENT;
6094 /* Return true if N is a possible register number of function value. */
6097 ix86_function_value_regno_p (int regno)
6104 case FIRST_FLOAT_REG:
6105 /* TODO: The function should depend on current function ABI but
6106 builtins.c would need updating then. Therefore we use the
6108 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
6110 return TARGET_FLOAT_RETURNS_IN_80387;
6116 if (TARGET_MACHO || TARGET_64BIT)
6124 /* Define how to find the value returned by a function.
6125 VALTYPE is the data type of the value (as a tree).
6126 If the precise function being called is known, FUNC is its FUNCTION_DECL;
6127 otherwise, FUNC is 0. */
6130 function_value_32 (enum machine_mode orig_mode, enum machine_mode mode,
6131 const_tree fntype, const_tree fn)
6135 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
6136 we normally prevent this case when mmx is not available. However
6137 some ABIs may require the result to be returned like DImode. */
6138 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6139 regno = TARGET_MMX ? FIRST_MMX_REG : 0;
6141 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
6142 we prevent this case when sse is not available. However some ABIs
6143 may require the result to be returned like integer TImode. */
6144 else if (mode == TImode
6145 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6146 regno = TARGET_SSE ? FIRST_SSE_REG : 0;
6148 /* 32-byte vector modes in %ymm0. */
6149 else if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 32)
6150 regno = TARGET_AVX ? FIRST_SSE_REG : 0;
6152 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
6153 else if (X87_FLOAT_MODE_P (mode) && TARGET_FLOAT_RETURNS_IN_80387)
6154 regno = FIRST_FLOAT_REG;
6156 /* Most things go in %eax. */
6159 /* Override FP return register with %xmm0 for local functions when
6160 SSE math is enabled or for functions with sseregparm attribute. */
6161 if ((fn || fntype) && (mode == SFmode || mode == DFmode))
6163 int sse_level = ix86_function_sseregparm (fntype, fn, false);
6164 if ((sse_level >= 1 && mode == SFmode)
6165 || (sse_level == 2 && mode == DFmode))
6166 regno = FIRST_SSE_REG;
6169 /* OImode shouldn't be used directly. */
6170 gcc_assert (mode != OImode);
6172 return gen_rtx_REG (orig_mode, regno);
6176 function_value_64 (enum machine_mode orig_mode, enum machine_mode mode,
6181 /* Handle libcalls, which don't provide a type node. */
6182 if (valtype == NULL)
6194 return gen_rtx_REG (mode, FIRST_SSE_REG);
6197 return gen_rtx_REG (mode, FIRST_FLOAT_REG);
6201 return gen_rtx_REG (mode, AX_REG);
6205 ret = construct_container (mode, orig_mode, valtype, 1,
6206 X86_64_REGPARM_MAX, X86_64_SSE_REGPARM_MAX,
6207 x86_64_int_return_registers, 0);
6209 /* For zero sized structures, construct_container returns NULL, but we
6210 need to keep rest of compiler happy by returning meaningful value. */
6212 ret = gen_rtx_REG (orig_mode, AX_REG);
6218 function_value_ms_64 (enum machine_mode orig_mode, enum machine_mode mode)
6220 unsigned int regno = AX_REG;
6224 switch (GET_MODE_SIZE (mode))
6227 if((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6228 && !COMPLEX_MODE_P (mode))
6229 regno = FIRST_SSE_REG;
6233 if (mode == SFmode || mode == DFmode)
6234 regno = FIRST_SSE_REG;
6240 return gen_rtx_REG (orig_mode, regno);
6244 ix86_function_value_1 (const_tree valtype, const_tree fntype_or_decl,
6245 enum machine_mode orig_mode, enum machine_mode mode)
6247 const_tree fn, fntype;
6250 if (fntype_or_decl && DECL_P (fntype_or_decl))
6251 fn = fntype_or_decl;
6252 fntype = fn ? TREE_TYPE (fn) : fntype_or_decl;
6254 if (TARGET_64BIT && ix86_function_type_abi (fntype) == MS_ABI)
6255 return function_value_ms_64 (orig_mode, mode);
6256 else if (TARGET_64BIT)
6257 return function_value_64 (orig_mode, mode, valtype);
6259 return function_value_32 (orig_mode, mode, fntype, fn);
6263 ix86_function_value (const_tree valtype, const_tree fntype_or_decl,
6264 bool outgoing ATTRIBUTE_UNUSED)
6266 enum machine_mode mode, orig_mode;
6268 orig_mode = TYPE_MODE (valtype);
6269 mode = type_natural_mode (valtype, NULL);
6270 return ix86_function_value_1 (valtype, fntype_or_decl, orig_mode, mode);
6274 ix86_libcall_value (enum machine_mode mode)
6276 return ix86_function_value_1 (NULL, NULL, mode, mode);
6279 /* Return true iff type is returned in memory. */
6281 static int ATTRIBUTE_UNUSED
6282 return_in_memory_32 (const_tree type, enum machine_mode mode)
6286 if (mode == BLKmode)
6289 size = int_size_in_bytes (type);
6291 if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
6294 if (VECTOR_MODE_P (mode) || mode == TImode)
6296 /* User-created vectors small enough to fit in EAX. */
6300 /* MMX/3dNow values are returned in MM0,
6301 except when it doesn't exits. */
6303 return (TARGET_MMX ? 0 : 1);
6305 /* SSE values are returned in XMM0, except when it doesn't exist. */
6307 return (TARGET_SSE ? 0 : 1);
6309 /* AVX values are returned in YMM0, except when it doesn't exist. */
6311 return TARGET_AVX ? 0 : 1;
6320 /* OImode shouldn't be used directly. */
6321 gcc_assert (mode != OImode);
6326 static int ATTRIBUTE_UNUSED
6327 return_in_memory_64 (const_tree type, enum machine_mode mode)
6329 int needed_intregs, needed_sseregs;
6330 return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
6333 static int ATTRIBUTE_UNUSED
6334 return_in_memory_ms_64 (const_tree type, enum machine_mode mode)
6336 HOST_WIDE_INT size = int_size_in_bytes (type);
6338 /* __m128 is returned in xmm0. */
6339 if ((SCALAR_INT_MODE_P (mode) || VECTOR_MODE_P (mode))
6340 && !COMPLEX_MODE_P (mode) && (GET_MODE_SIZE (mode) == 16 || size == 16))
6343 /* Otherwise, the size must be exactly in [1248]. */
6344 return (size != 1 && size != 2 && size != 4 && size != 8);
6348 ix86_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6350 #ifdef SUBTARGET_RETURN_IN_MEMORY
6351 return SUBTARGET_RETURN_IN_MEMORY (type, fntype);
6353 const enum machine_mode mode = type_natural_mode (type, NULL);
6357 if (ix86_function_type_abi (fntype) == MS_ABI)
6358 return return_in_memory_ms_64 (type, mode);
6360 return return_in_memory_64 (type, mode);
6363 return return_in_memory_32 (type, mode);
6367 /* Return false iff TYPE is returned in memory. This version is used
6368 on Solaris 2. It is similar to the generic ix86_return_in_memory,
6369 but differs notably in that when MMX is available, 8-byte vectors
6370 are returned in memory, rather than in MMX registers. */
6373 ix86_solaris_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
6376 enum machine_mode mode = type_natural_mode (type, NULL);
6379 return return_in_memory_64 (type, mode);
6381 if (mode == BLKmode)
6384 size = int_size_in_bytes (type);
6386 if (VECTOR_MODE_P (mode))
6388 /* Return in memory only if MMX registers *are* available. This
6389 seems backwards, but it is consistent with the existing
6396 else if (mode == TImode)
6398 else if (mode == XFmode)
6404 /* When returning SSE vector types, we have a choice of either
6405 (1) being abi incompatible with a -march switch, or
6406 (2) generating an error.
6407 Given no good solution, I think the safest thing is one warning.
6408 The user won't be able to use -Werror, but....
6410 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
6411 called in response to actually generating a caller or callee that
6412 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
6413 via aggregate_value_p for general type probing from tree-ssa. */
6416 ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
6418 static bool warnedsse, warnedmmx;
6420 if (!TARGET_64BIT && type)
6422 /* Look at the return type of the function, not the function type. */
6423 enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));
6425 if (!TARGET_SSE && !warnedsse)
6428 || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
6431 warning (0, "SSE vector return without SSE enabled "
6436 if (!TARGET_MMX && !warnedmmx)
6438 if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8)
6441 warning (0, "MMX vector return without MMX enabled "
6451 /* Create the va_list data type. */
6453 /* Returns the calling convention specific va_list date type.
6454 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
6457 ix86_build_builtin_va_list_abi (enum calling_abi abi)
6459 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
6461 /* For i386 we use plain pointer to argument area. */
6462 if (!TARGET_64BIT || abi == MS_ABI)
6463 return build_pointer_type (char_type_node);
6465 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6466 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6468 f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
6469 unsigned_type_node);
6470 f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
6471 unsigned_type_node);
6472 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6474 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6477 va_list_gpr_counter_field = f_gpr;
6478 va_list_fpr_counter_field = f_fpr;
6480 DECL_FIELD_CONTEXT (f_gpr) = record;
6481 DECL_FIELD_CONTEXT (f_fpr) = record;
6482 DECL_FIELD_CONTEXT (f_ovf) = record;
6483 DECL_FIELD_CONTEXT (f_sav) = record;
6485 TREE_CHAIN (record) = type_decl;
6486 TYPE_NAME (record) = type_decl;
6487 TYPE_FIELDS (record) = f_gpr;
6488 TREE_CHAIN (f_gpr) = f_fpr;
6489 TREE_CHAIN (f_fpr) = f_ovf;
6490 TREE_CHAIN (f_ovf) = f_sav;
6492 layout_type (record);
6494 /* The correct type is an array type of one element. */
6495 return build_array_type (record, build_index_type (size_zero_node));
6498 /* Setup the builtin va_list data type and for 64-bit the additional
6499 calling convention specific va_list data types. */
6502 ix86_build_builtin_va_list (void)
6504 tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
6506 /* Initialize abi specific va_list builtin types. */
6510 if (DEFAULT_ABI == MS_ABI)
6512 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
6513 if (TREE_CODE (t) != RECORD_TYPE)
6514 t = build_variant_type_copy (t);
6515 sysv_va_list_type_node = t;
6520 if (TREE_CODE (t) != RECORD_TYPE)
6521 t = build_variant_type_copy (t);
6522 sysv_va_list_type_node = t;
6524 if (DEFAULT_ABI != MS_ABI)
6526 t = ix86_build_builtin_va_list_abi (MS_ABI);
6527 if (TREE_CODE (t) != RECORD_TYPE)
6528 t = build_variant_type_copy (t);
6529 ms_va_list_type_node = t;
6534 if (TREE_CODE (t) != RECORD_TYPE)
6535 t = build_variant_type_copy (t);
6536 ms_va_list_type_node = t;
6543 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
6546 setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
6555 int regparm = ix86_regparm;
6557 if (cum->call_abi != DEFAULT_ABI)
6558 regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
6560 /* GPR size of varargs save area. */
6561 if (cfun->va_list_gpr_size)
6562 ix86_varargs_gpr_size = X86_64_REGPARM_MAX * UNITS_PER_WORD;
6564 ix86_varargs_gpr_size = 0;
6566 /* FPR size of varargs save area. We don't need it if we don't pass
6567 anything in SSE registers. */
6568 if (cum->sse_nregs && cfun->va_list_fpr_size)
6569 ix86_varargs_fpr_size = X86_64_SSE_REGPARM_MAX * 16;
6571 ix86_varargs_fpr_size = 0;
6573 if (! ix86_varargs_gpr_size && ! ix86_varargs_fpr_size)
6576 save_area = frame_pointer_rtx;
6577 set = get_varargs_alias_set ();
6579 for (i = cum->regno;
6581 && i < cum->regno + cfun->va_list_gpr_size / UNITS_PER_WORD;
6584 mem = gen_rtx_MEM (Pmode,
6585 plus_constant (save_area, i * UNITS_PER_WORD));
6586 MEM_NOTRAP_P (mem) = 1;
6587 set_mem_alias_set (mem, set);
6588 emit_move_insn (mem, gen_rtx_REG (Pmode,
6589 x86_64_int_parameter_registers[i]));
6592 if (ix86_varargs_fpr_size)
6594 /* Stack must be aligned to 16byte for FP register save area. */
6595 if (crtl->stack_alignment_needed < 128)
6596 crtl->stack_alignment_needed = 128;
6598 /* Now emit code to save SSE registers. The AX parameter contains number
6599 of SSE parameter registers used to call this function. We use
6600 sse_prologue_save insn template that produces computed jump across
6601 SSE saves. We need some preparation work to get this working. */
6603 label = gen_label_rtx ();
6604 label_ref = gen_rtx_LABEL_REF (Pmode, label);
6606 /* Compute address to jump to :
6607 label - eax*4 + nnamed_sse_arguments*4 Or
6608 label - eax*5 + nnamed_sse_arguments*5 for AVX. */
6609 tmp_reg = gen_reg_rtx (Pmode);
6610 nsse_reg = gen_reg_rtx (Pmode);
6611 emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
6612 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6613 gen_rtx_MULT (Pmode, nsse_reg,
6616 /* vmovaps is one byte longer than movaps. */
6618 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6619 gen_rtx_PLUS (Pmode, tmp_reg,
6625 gen_rtx_CONST (DImode,
6626 gen_rtx_PLUS (DImode,
6628 GEN_INT (cum->sse_regno
6629 * (TARGET_AVX ? 5 : 4)))));
6631 emit_move_insn (nsse_reg, label_ref);
6632 emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
6634 /* Compute address of memory block we save into. We always use pointer
6635 pointing 127 bytes after first byte to store - this is needed to keep
6636 instruction size limited by 4 bytes (5 bytes for AVX) with one
6637 byte displacement. */
6638 tmp_reg = gen_reg_rtx (Pmode);
6639 emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
6640 plus_constant (save_area,
6641 ix86_varargs_gpr_size + 127)));
6642 mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
6643 MEM_NOTRAP_P (mem) = 1;
6644 set_mem_alias_set (mem, set);
6645 set_mem_align (mem, BITS_PER_WORD);
6647 /* And finally do the dirty job! */
6648 emit_insn (gen_sse_prologue_save (mem, nsse_reg,
6649 GEN_INT (cum->sse_regno), label));
6654 setup_incoming_varargs_ms_64 (CUMULATIVE_ARGS *cum)
6656 alias_set_type set = get_varargs_alias_set ();
6659 for (i = cum->regno; i < X64_REGPARM_MAX; i++)
6663 mem = gen_rtx_MEM (Pmode,
6664 plus_constant (virtual_incoming_args_rtx,
6665 i * UNITS_PER_WORD));
6666 MEM_NOTRAP_P (mem) = 1;
6667 set_mem_alias_set (mem, set);
6669 reg = gen_rtx_REG (Pmode, x86_64_ms_abi_int_parameter_registers[i]);
6670 emit_move_insn (mem, reg);
6675 ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6676 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6679 CUMULATIVE_ARGS next_cum;
6682 /* This argument doesn't appear to be used anymore. Which is good,
6683 because the old code here didn't suppress rtl generation. */
6684 gcc_assert (!no_rtl);
6689 fntype = TREE_TYPE (current_function_decl);
6691 /* For varargs, we do not want to skip the dummy va_dcl argument.
6692 For stdargs, we do want to skip the last named argument. */
6694 if (stdarg_p (fntype))
6695 function_arg_advance (&next_cum, mode, type, 1);
6697 if (cum->call_abi == MS_ABI)
6698 setup_incoming_varargs_ms_64 (&next_cum);
6700 setup_incoming_varargs_64 (&next_cum);
6703 /* Checks if TYPE is of kind va_list char *. */
6706 is_va_list_char_pointer (tree type)
6710 /* For 32-bit it is always true. */
6713 canonic = ix86_canonical_va_list_type (type);
6714 return (canonic == ms_va_list_type_node
6715 || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
6718 /* Implement va_start. */
6721 ix86_va_start (tree valist, rtx nextarg)
6723 HOST_WIDE_INT words, n_gpr, n_fpr;
6724 tree f_gpr, f_fpr, f_ovf, f_sav;
6725 tree gpr, fpr, ovf, sav, t;
6728 /* Only 64bit target needs something special. */
6729 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6731 std_expand_builtin_va_start (valist, nextarg);
6735 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6736 f_fpr = TREE_CHAIN (f_gpr);
6737 f_ovf = TREE_CHAIN (f_fpr);
6738 f_sav = TREE_CHAIN (f_ovf);
6740 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
6741 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6742 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6743 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6744 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6746 /* Count number of gp and fp argument registers used. */
6747 words = crtl->args.info.words;
6748 n_gpr = crtl->args.info.regno;
6749 n_fpr = crtl->args.info.sse_regno;
6751 if (cfun->va_list_gpr_size)
6753 type = TREE_TYPE (gpr);
6754 t = build2 (MODIFY_EXPR, type,
6755 gpr, build_int_cst (type, n_gpr * 8));
6756 TREE_SIDE_EFFECTS (t) = 1;
6757 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6760 if (TARGET_SSE && cfun->va_list_fpr_size)
6762 type = TREE_TYPE (fpr);
6763 t = build2 (MODIFY_EXPR, type, fpr,
6764 build_int_cst (type, n_fpr * 16 + 8*X86_64_REGPARM_MAX));
6765 TREE_SIDE_EFFECTS (t) = 1;
6766 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6769 /* Find the overflow area. */
6770 type = TREE_TYPE (ovf);
6771 t = make_tree (type, crtl->args.internal_arg_pointer);
6773 t = build2 (POINTER_PLUS_EXPR, type, t,
6774 size_int (words * UNITS_PER_WORD));
6775 t = build2 (MODIFY_EXPR, type, ovf, t);
6776 TREE_SIDE_EFFECTS (t) = 1;
6777 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6779 if (ix86_varargs_gpr_size || ix86_varargs_fpr_size)
6781 /* Find the register save area.
6782 Prologue of the function save it right above stack frame. */
6783 type = TREE_TYPE (sav);
6784 t = make_tree (type, frame_pointer_rtx);
6785 if (!ix86_varargs_gpr_size)
6786 t = build2 (POINTER_PLUS_EXPR, type, t,
6787 size_int (-8 * X86_64_REGPARM_MAX));
6788 t = build2 (MODIFY_EXPR, type, sav, t);
6789 TREE_SIDE_EFFECTS (t) = 1;
6790 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6794 /* Implement va_arg. */
6797 ix86_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6800 static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
6801 tree f_gpr, f_fpr, f_ovf, f_sav;
6802 tree gpr, fpr, ovf, sav, t;
6804 tree lab_false, lab_over = NULL_TREE;
6809 enum machine_mode nat_mode;
6812 /* Only 64bit target needs something special. */
6813 if (!TARGET_64BIT || is_va_list_char_pointer (TREE_TYPE (valist)))
6814 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6816 f_gpr = TYPE_FIELDS (TREE_TYPE (sysv_va_list_type_node));
6817 f_fpr = TREE_CHAIN (f_gpr);
6818 f_ovf = TREE_CHAIN (f_fpr);
6819 f_sav = TREE_CHAIN (f_ovf);
6821 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr),
6822 build_va_arg_indirect_ref (valist), f_gpr, NULL_TREE);
6823 valist = build_va_arg_indirect_ref (valist);
6824 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6825 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6826 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6828 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6830 type = build_pointer_type (type);
6831 size = int_size_in_bytes (type);
6832 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
6834 nat_mode = type_natural_mode (type, NULL);
6843 /* Unnamed 256bit vector mode parameters are passed on stack. */
6844 if (ix86_cfun_abi () == SYSV_ABI)
6851 container = construct_container (nat_mode, TYPE_MODE (type),
6852 type, 0, X86_64_REGPARM_MAX,
6853 X86_64_SSE_REGPARM_MAX, intreg,
6858 /* Pull the value out of the saved registers. */
6860 addr = create_tmp_var (ptr_type_node, "addr");
6861 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6865 int needed_intregs, needed_sseregs;
6867 tree int_addr, sse_addr;
6869 lab_false = create_artificial_label ();
6870 lab_over = create_artificial_label ();
6872 examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);
6874 need_temp = (!REG_P (container)
6875 && ((needed_intregs && TYPE_ALIGN (type) > 64)
6876 || TYPE_ALIGN (type) > 128));
6878 /* In case we are passing structure, verify that it is consecutive block
6879 on the register save area. If not we need to do moves. */
6880 if (!need_temp && !REG_P (container))
6882 /* Verify that all registers are strictly consecutive */
6883 if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
6887 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6889 rtx slot = XVECEXP (container, 0, i);
6890 if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
6891 || INTVAL (XEXP (slot, 1)) != i * 16)
6899 for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
6901 rtx slot = XVECEXP (container, 0, i);
6902 if (REGNO (XEXP (slot, 0)) != (unsigned int) i
6903 || INTVAL (XEXP (slot, 1)) != i * 8)
6915 int_addr = create_tmp_var (ptr_type_node, "int_addr");
6916 DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
6917 sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
6918 DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
6921 /* First ensure that we fit completely in registers. */
6924 t = build_int_cst (TREE_TYPE (gpr),
6925 (X86_64_REGPARM_MAX - needed_intregs + 1) * 8);
6926 t = build2 (GE_EXPR, boolean_type_node, gpr, t);
6927 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6928 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6929 gimplify_and_add (t, pre_p);
6933 t = build_int_cst (TREE_TYPE (fpr),
6934 (X86_64_SSE_REGPARM_MAX - needed_sseregs + 1) * 16
6935 + X86_64_REGPARM_MAX * 8);
6936 t = build2 (GE_EXPR, boolean_type_node, fpr, t);
6937 t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
6938 t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE);
6939 gimplify_and_add (t, pre_p);
6942 /* Compute index to start of area used for integer regs. */
6945 /* int_addr = gpr + sav; */
6946 t = fold_convert (sizetype, gpr);
6947 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6948 gimplify_assign (int_addr, t, pre_p);
6952 /* sse_addr = fpr + sav; */
6953 t = fold_convert (sizetype, fpr);
6954 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, t);
6955 gimplify_assign (sse_addr, t, pre_p);
6960 tree temp = create_tmp_var (type, "va_arg_tmp");
6963 t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
6964 gimplify_assign (addr, t, pre_p);
6966 for (i = 0; i < XVECLEN (container, 0); i++)
6968 rtx slot = XVECEXP (container, 0, i);
6969 rtx reg = XEXP (slot, 0);
6970 enum machine_mode mode = GET_MODE (reg);
6971 tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
6972 tree addr_type = build_pointer_type (piece_type);
6973 tree daddr_type = build_pointer_type_for_mode (piece_type,
6977 tree dest_addr, dest;
6979 if (SSE_REGNO_P (REGNO (reg)))
6981 src_addr = sse_addr;
6982 src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
6986 src_addr = int_addr;
6987 src_offset = REGNO (reg) * 8;
6989 src_addr = fold_convert (addr_type, src_addr);
6990 src_addr = fold_build2 (POINTER_PLUS_EXPR, addr_type, src_addr,
6991 size_int (src_offset));
6992 src = build_va_arg_indirect_ref (src_addr);
6994 dest_addr = fold_convert (daddr_type, addr);
6995 dest_addr = fold_build2 (POINTER_PLUS_EXPR, daddr_type, dest_addr,
6996 size_int (INTVAL (XEXP (slot, 1))));
6997 dest = build_va_arg_indirect_ref (dest_addr);
6999 gimplify_assign (dest, src, pre_p);
7005 t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
7006 build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
7007 gimplify_assign (gpr, t, pre_p);
7012 t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
7013 build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
7014 gimplify_assign (fpr, t, pre_p);
7017 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
7019 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
7022 /* ... otherwise out of the overflow area. */
7024 /* When we align parameter on stack for caller, if the parameter
7025 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
7026 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
7027 here with caller. */
7028 arg_boundary = FUNCTION_ARG_BOUNDARY (VOIDmode, type);
7029 if ((unsigned int) arg_boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
7030 arg_boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
7032 /* Care for on-stack alignment if needed. */
7033 if (arg_boundary <= 64
7034 || integer_zerop (TYPE_SIZE (type)))
7038 HOST_WIDE_INT align = arg_boundary / 8;
7039 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), ovf,
7040 size_int (align - 1));
7041 t = fold_convert (sizetype, t);
7042 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
7044 t = fold_convert (TREE_TYPE (ovf), t);
7046 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
7047 gimplify_assign (addr, t, pre_p);
7049 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t,
7050 size_int (rsize * UNITS_PER_WORD));
7051 gimplify_assign (unshare_expr (ovf), t, pre_p);
7054 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
7056 ptrtype = build_pointer_type (type);
7057 addr = fold_convert (ptrtype, addr);
7060 addr = build_va_arg_indirect_ref (addr);
7061 return build_va_arg_indirect_ref (addr);
7064 /* Return nonzero if OPNUM's MEM should be matched
7065 in movabs* patterns. */
7068 ix86_check_movabs (rtx insn, int opnum)
7072 set = PATTERN (insn);
7073 if (GET_CODE (set) == PARALLEL)
7074 set = XVECEXP (set, 0, 0);
7075 gcc_assert (GET_CODE (set) == SET);
7076 mem = XEXP (set, opnum);
7077 while (GET_CODE (mem) == SUBREG)
7078 mem = SUBREG_REG (mem);
7079 gcc_assert (MEM_P (mem));
7080 return (volatile_ok || !MEM_VOLATILE_P (mem));
7083 /* Initialize the table of extra 80387 mathematical constants. */
7086 init_ext_80387_constants (void)
7088 static const char * cst[5] =
7090 "0.3010299956639811952256464283594894482", /* 0: fldlg2 */
7091 "0.6931471805599453094286904741849753009", /* 1: fldln2 */
7092 "1.4426950408889634073876517827983434472", /* 2: fldl2e */
7093 "3.3219280948873623478083405569094566090", /* 3: fldl2t */
7094 "3.1415926535897932385128089594061862044", /* 4: fldpi */
7098 for (i = 0; i < 5; i++)
7100 real_from_string (&ext_80387_constants_table[i], cst[i]);
7101 /* Ensure each constant is rounded to XFmode precision. */
7102 real_convert (&ext_80387_constants_table[i],
7103 XFmode, &ext_80387_constants_table[i]);
7106 ext_80387_constants_init = 1;
7109 /* Return true if the constant is something that can be loaded with
7110 a special instruction. */
7113 standard_80387_constant_p (rtx x)
7115 enum machine_mode mode = GET_MODE (x);
7119 if (!(X87_FLOAT_MODE_P (mode) && (GET_CODE (x) == CONST_DOUBLE)))
7122 if (x == CONST0_RTX (mode))
7124 if (x == CONST1_RTX (mode))
7127 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7129 /* For XFmode constants, try to find a special 80387 instruction when
7130 optimizing for size or on those CPUs that benefit from them. */
7132 && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
7136 if (! ext_80387_constants_init)
7137 init_ext_80387_constants ();
7139 for (i = 0; i < 5; i++)
7140 if (real_identical (&r, &ext_80387_constants_table[i]))
7144 /* Load of the constant -0.0 or -1.0 will be split as
7145 fldz;fchs or fld1;fchs sequence. */
7146 if (real_isnegzero (&r))
7148 if (real_identical (&r, &dconstm1))
7154 /* Return the opcode of the special instruction to be used to load
7158 standard_80387_constant_opcode (rtx x)
7160 switch (standard_80387_constant_p (x))
7184 /* Return the CONST_DOUBLE representing the 80387 constant that is
7185 loaded by the specified special instruction. The argument IDX
7186 matches the return value from standard_80387_constant_p. */
7189 standard_80387_constant_rtx (int idx)
7193 if (! ext_80387_constants_init)
7194 init_ext_80387_constants ();
7210 return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
7214 /* Return 1 if mode is a valid mode for sse. */
7216 standard_sse_mode_p (enum machine_mode mode)
7233 /* Return 1 if X is all 0s. For all 1s, return 2 if X is in 128bit
7234 SSE modes and SSE2 is enabled, return 3 if X is in 256bit AVX
7235 modes and AVX is enabled. */
7238 standard_sse_constant_p (rtx x)
7240 enum machine_mode mode = GET_MODE (x);
7242 if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
7244 if (vector_all_ones_operand (x, mode))
7246 if (standard_sse_mode_p (mode))
7247 return TARGET_SSE2 ? 2 : -2;
7248 else if (VALID_AVX256_REG_MODE (mode))
7249 return TARGET_AVX ? 3 : -3;
7255 /* Return the opcode of the special instruction to be used to load
7259 standard_sse_constant_opcode (rtx insn, rtx x)
7261 switch (standard_sse_constant_p (x))
7264 switch (get_attr_mode (insn))
7267 return TARGET_AVX ? "vxorps\t%0, %0, %0" : "xorps\t%0, %0";
7269 return TARGET_AVX ? "vxorpd\t%0, %0, %0" : "xorpd\t%0, %0";
7271 return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
7273 return "vxorps\t%x0, %x0, %x0";
7275 return "vxorpd\t%x0, %x0, %x0";
7277 return "vpxor\t%x0, %x0, %x0";
7283 switch (get_attr_mode (insn))
7288 return "vpcmpeqd\t%0, %0, %0";
7294 return "pcmpeqd\t%0, %0";
7299 /* Returns 1 if OP contains a symbol reference */
7302 symbolic_reference_mentioned_p (rtx op)
7307 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
7310 fmt = GET_RTX_FORMAT (GET_CODE (op));
7311 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
7317 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
7318 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
7322 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
7329 /* Return 1 if it is appropriate to emit `ret' instructions in the
7330 body of a function. Do this only if the epilogue is simple, needing a
7331 couple of insns. Prior to reloading, we can't tell how many registers
7332 must be saved, so return 0 then. Return 0 if there is no frame
7333 marker to de-allocate. */
7336 ix86_can_use_return_insn_p (void)
7338 struct ix86_frame frame;
7340 if (! reload_completed || frame_pointer_needed)
7343 /* Don't allow more than 32 pop, since that's all we can do
7344 with one instruction. */
7345 if (crtl->args.pops_args
7346 && crtl->args.size >= 32768)
7349 ix86_compute_frame_layout (&frame);
7350 return frame.to_allocate == 0 && frame.padding0 == 0
7351 && (frame.nregs + frame.nsseregs) == 0;
7354 /* Value should be nonzero if functions must have frame pointers.
7355 Zero means the frame pointer need not be set up (and parms may
7356 be accessed via the stack pointer) in functions that seem suitable. */
7359 ix86_frame_pointer_required (void)
7361 /* If we accessed previous frames, then the generated code expects
7362 to be able to access the saved ebp value in our frame. */
7363 if (cfun->machine->accesses_prev_frame)
7366 /* Several x86 os'es need a frame pointer for other reasons,
7367 usually pertaining to setjmp. */
7368 if (SUBTARGET_FRAME_POINTER_REQUIRED)
7371 /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
7372 the frame pointer by default. Turn it back on now if we've not
7373 got a leaf function. */
7374 if (TARGET_OMIT_LEAF_FRAME_POINTER
7375 && (!current_function_is_leaf
7376 || ix86_current_function_calls_tls_descriptor))
7385 /* Record that the current function accesses previous call frames. */
7388 ix86_setup_frame_addresses (void)
7390 cfun->machine->accesses_prev_frame = 1;
7393 #ifndef USE_HIDDEN_LINKONCE
7394 # if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO
7395 # define USE_HIDDEN_LINKONCE 1
7397 # define USE_HIDDEN_LINKONCE 0
7401 static int pic_labels_used;
7403 /* Fills in the label name that should be used for a pc thunk for
7404 the given register. */
7407 get_pc_thunk_name (char name[32], unsigned int regno)
7409 gcc_assert (!TARGET_64BIT);
7411 if (USE_HIDDEN_LINKONCE)
7412 sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
7414 ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
7418 /* This function generates code for -fpic that loads %ebx with
7419 the return address of the caller and then returns. */
7422 ix86_file_end (void)
7427 for (regno = 0; regno < 8; ++regno)
7431 if (! ((pic_labels_used >> regno) & 1))
7434 get_pc_thunk_name (name, regno);
7439 switch_to_section (darwin_sections[text_coal_section]);
7440 fputs ("\t.weak_definition\t", asm_out_file);
7441 assemble_name (asm_out_file, name);
7442 fputs ("\n\t.private_extern\t", asm_out_file);
7443 assemble_name (asm_out_file, name);
7444 fputs ("\n", asm_out_file);
7445 ASM_OUTPUT_LABEL (asm_out_file, name);
7449 if (USE_HIDDEN_LINKONCE)
7453 decl = build_decl (FUNCTION_DECL, get_identifier (name),
7455 TREE_PUBLIC (decl) = 1;
7456 TREE_STATIC (decl) = 1;
7457 DECL_ONE_ONLY (decl) = 1;
7459 (*targetm.asm_out.unique_section) (decl, 0);
7460 switch_to_section (get_named_section (decl, NULL, 0));
7462 (*targetm.asm_out.globalize_label) (asm_out_file, name);
7463 fputs ("\t.hidden\t", asm_out_file);
7464 assemble_name (asm_out_file, name);
7465 fputc ('\n', asm_out_file);
7466 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
7470 switch_to_section (text_section);
7471 ASM_OUTPUT_LABEL (asm_out_file, name);
7474 xops[0] = gen_rtx_REG (Pmode, regno);
7475 xops[1] = gen_rtx_MEM (Pmode, stack_pointer_rtx);
7476 output_asm_insn ("mov%z0\t{%1, %0|%0, %1}", xops);
7477 output_asm_insn ("ret", xops);
7480 if (NEED_INDICATE_EXEC_STACK)
7481 file_end_indicate_exec_stack ();
7484 /* Emit code for the SET_GOT patterns. */
7487 output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED)
7493 if (TARGET_VXWORKS_RTP && flag_pic)
7495 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
7496 xops[2] = gen_rtx_MEM (Pmode,
7497 gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE));
7498 output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
7500 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
7501 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
7502 an unadorned address. */
7503 xops[2] = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7504 SYMBOL_REF_FLAGS (xops[2]) |= SYMBOL_FLAG_LOCAL;
7505 output_asm_insn ("mov{l}\t{%P2(%0), %0|%0, DWORD PTR %P2[%0]}", xops);
7509 xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);
7511 if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
7513 xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ());
7516 output_asm_insn ("mov%z0\t{%2, %0|%0, %2}", xops);
7518 output_asm_insn ("call\t%a2", xops);
7521 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7522 is what will be referenced by the Mach-O PIC subsystem. */
7524 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7527 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7528 CODE_LABEL_NUMBER (XEXP (xops[2], 0)));
7531 output_asm_insn ("pop%z0\t%0", xops);
7536 get_pc_thunk_name (name, REGNO (dest));
7537 pic_labels_used |= 1 << REGNO (dest);
7539 xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
7540 xops[2] = gen_rtx_MEM (QImode, xops[2]);
7541 output_asm_insn ("call\t%X2", xops);
7542 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
7543 is what will be referenced by the Mach-O PIC subsystem. */
7546 ASM_OUTPUT_LABEL (asm_out_file, MACHOPIC_FUNCTION_BASE_NAME);
7548 targetm.asm_out.internal_label (asm_out_file, "L",
7549 CODE_LABEL_NUMBER (label));
7556 if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
7557 output_asm_insn ("add%z0\t{%1, %0|%0, %1}", xops);
7559 output_asm_insn ("add%z0\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);
7564 /* Generate an "push" pattern for input ARG. */
7569 return gen_rtx_SET (VOIDmode,
7571 gen_rtx_PRE_DEC (Pmode,
7572 stack_pointer_rtx)),
7576 /* Return >= 0 if there is an unused call-clobbered register available
7577 for the entire function. */
7580 ix86_select_alt_pic_regnum (void)
7582 if (current_function_is_leaf && !crtl->profile
7583 && !ix86_current_function_calls_tls_descriptor)
7586 /* Can't use the same register for both PIC and DRAP. */
7588 drap = REGNO (crtl->drap_reg);
7591 for (i = 2; i >= 0; --i)
7592 if (i != drap && !df_regs_ever_live_p (i))
7596 return INVALID_REGNUM;
7599 /* Return 1 if we need to save REGNO. */
7601 ix86_save_reg (unsigned int regno, int maybe_eh_return)
7603 if (pic_offset_table_rtx
7604 && regno == REAL_PIC_OFFSET_TABLE_REGNUM
7605 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
7607 || crtl->calls_eh_return
7608 || crtl->uses_const_pool))
7610 if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
7615 if (crtl->calls_eh_return && maybe_eh_return)
7620 unsigned test = EH_RETURN_DATA_REGNO (i);
7621 if (test == INVALID_REGNUM)
7629 && regno == REGNO (crtl->drap_reg))
7632 return (df_regs_ever_live_p (regno)
7633 && !call_used_regs[regno]
7634 && !fixed_regs[regno]
7635 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
7638 /* Return number of saved general prupose registers. */
7641 ix86_nsaved_regs (void)
7646 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7647 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7652 /* Return number of saved SSE registrers. */
7655 ix86_nsaved_sseregs (void)
7660 if (ix86_cfun_abi () != MS_ABI)
7662 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7663 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7668 /* Given FROM and TO register numbers, say whether this elimination is
7669 allowed. If stack alignment is needed, we can only replace argument
7670 pointer with hard frame pointer, or replace frame pointer with stack
7671 pointer. Otherwise, frame pointer elimination is automatically
7672 handled and all other eliminations are valid. */
7675 ix86_can_eliminate (int from, int to)
7677 if (stack_realign_fp)
7678 return ((from == ARG_POINTER_REGNUM
7679 && to == HARD_FRAME_POINTER_REGNUM)
7680 || (from == FRAME_POINTER_REGNUM
7681 && to == STACK_POINTER_REGNUM));
7683 return to == STACK_POINTER_REGNUM ? !frame_pointer_needed : 1;
7686 /* Return the offset between two registers, one to be eliminated, and the other
7687 its replacement, at the start of a routine. */
7690 ix86_initial_elimination_offset (int from, int to)
7692 struct ix86_frame frame;
7693 ix86_compute_frame_layout (&frame);
7695 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
7696 return frame.hard_frame_pointer_offset;
7697 else if (from == FRAME_POINTER_REGNUM
7698 && to == HARD_FRAME_POINTER_REGNUM)
7699 return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
7702 gcc_assert (to == STACK_POINTER_REGNUM);
7704 if (from == ARG_POINTER_REGNUM)
7705 return frame.stack_pointer_offset;
7707 gcc_assert (from == FRAME_POINTER_REGNUM);
7708 return frame.stack_pointer_offset - frame.frame_pointer_offset;
7712 /* In a dynamically-aligned function, we can't know the offset from
7713 stack pointer to frame pointer, so we must ensure that setjmp
7714 eliminates fp against the hard fp (%ebp) rather than trying to
7715 index from %esp up to the top of the frame across a gap that is
7716 of unknown (at compile-time) size. */
7718 ix86_builtin_setjmp_frame_value (void)
7720 return stack_realign_fp ? hard_frame_pointer_rtx : virtual_stack_vars_rtx;
7723 /* Fill structure ix86_frame about frame of currently computed function. */
7726 ix86_compute_frame_layout (struct ix86_frame *frame)
7728 HOST_WIDE_INT total_size;
7729 unsigned int stack_alignment_needed;
7730 HOST_WIDE_INT offset;
7731 unsigned int preferred_alignment;
7732 HOST_WIDE_INT size = get_frame_size ();
7734 frame->nregs = ix86_nsaved_regs ();
7735 frame->nsseregs = ix86_nsaved_sseregs ();
7738 stack_alignment_needed = crtl->stack_alignment_needed / BITS_PER_UNIT;
7739 preferred_alignment = crtl->preferred_stack_boundary / BITS_PER_UNIT;
7741 /* MS ABI seem to require stack alignment to be always 16 except for function
7743 if (ix86_cfun_abi () == MS_ABI && preferred_alignment < 16)
7745 preferred_alignment = 16;
7746 stack_alignment_needed = 16;
7747 crtl->preferred_stack_boundary = 128;
7748 crtl->stack_alignment_needed = 128;
7751 gcc_assert (!size || stack_alignment_needed);
7752 gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT);
7753 gcc_assert (preferred_alignment <= stack_alignment_needed);
7755 /* During reload iteration the amount of registers saved can change.
7756 Recompute the value as needed. Do not recompute when amount of registers
7757 didn't change as reload does multiple calls to the function and does not
7758 expect the decision to change within single iteration. */
7759 if (!optimize_function_for_size_p (cfun)
7760 && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
7762 int count = frame->nregs;
7764 cfun->machine->use_fast_prologue_epilogue_nregs = count;
7765 /* The fast prologue uses move instead of push to save registers. This
7766 is significantly longer, but also executes faster as modern hardware
7767 can execute the moves in parallel, but can't do that for push/pop.
7769 Be careful about choosing what prologue to emit: When function takes
7770 many instructions to execute we may use slow version as well as in
7771 case function is known to be outside hot spot (this is known with
7772 feedback only). Weight the size of function by number of registers
7773 to save as it is cheap to use one or two push instructions but very
7774 slow to use many of them. */
7776 count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
7777 if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
7778 || (flag_branch_probabilities
7779 && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
7780 cfun->machine->use_fast_prologue_epilogue = false;
7782 cfun->machine->use_fast_prologue_epilogue
7783 = !expensive_function_p (count);
7785 if (TARGET_PROLOGUE_USING_MOVE
7786 && cfun->machine->use_fast_prologue_epilogue)
7787 frame->save_regs_using_mov = true;
7789 frame->save_regs_using_mov = false;
7792 /* Skip return address and saved base pointer. */
7793 offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;
7795 frame->hard_frame_pointer_offset = offset;
7797 /* Set offset to aligned because the realigned frame starts from
7799 if (stack_realign_fp)
7800 offset = (offset + stack_alignment_needed -1) & -stack_alignment_needed;
7802 /* Register save area */
7803 offset += frame->nregs * UNITS_PER_WORD;
7805 /* Align SSE reg save area. */
7806 if (frame->nsseregs)
7807 frame->padding0 = ((offset + 16 - 1) & -16) - offset;
7809 frame->padding0 = 0;
7811 /* SSE register save area. */
7812 offset += frame->padding0 + frame->nsseregs * 16;
7815 frame->va_arg_size = ix86_varargs_gpr_size + ix86_varargs_fpr_size;
7816 offset += frame->va_arg_size;
7818 /* Align start of frame for local function. */
7819 frame->padding1 = ((offset + stack_alignment_needed - 1)
7820 & -stack_alignment_needed) - offset;
7822 offset += frame->padding1;
7824 /* Frame pointer points here. */
7825 frame->frame_pointer_offset = offset;
7829 /* Add outgoing arguments area. Can be skipped if we eliminated
7830 all the function calls as dead code.
7831 Skipping is however impossible when function calls alloca. Alloca
7832 expander assumes that last crtl->outgoing_args_size
7833 of stack frame are unused. */
7834 if (ACCUMULATE_OUTGOING_ARGS
7835 && (!current_function_is_leaf || cfun->calls_alloca
7836 || ix86_current_function_calls_tls_descriptor))
7838 offset += crtl->outgoing_args_size;
7839 frame->outgoing_arguments_size = crtl->outgoing_args_size;
7842 frame->outgoing_arguments_size = 0;
7844 /* Align stack boundary. Only needed if we're calling another function
7846 if (!current_function_is_leaf || cfun->calls_alloca
7847 || ix86_current_function_calls_tls_descriptor)
7848 frame->padding2 = ((offset + preferred_alignment - 1)
7849 & -preferred_alignment) - offset;
7851 frame->padding2 = 0;
7853 offset += frame->padding2;
7855 /* We've reached end of stack frame. */
7856 frame->stack_pointer_offset = offset;
7858 /* Size prologue needs to allocate. */
7859 frame->to_allocate =
7860 (size + frame->padding1 + frame->padding2
7861 + frame->outgoing_arguments_size + frame->va_arg_size);
7863 if ((!frame->to_allocate && frame->nregs <= 1)
7864 || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
7865 frame->save_regs_using_mov = false;
7867 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
7868 && current_function_sp_is_unchanging
7869 && current_function_is_leaf
7870 && !ix86_current_function_calls_tls_descriptor)
7872 frame->red_zone_size = frame->to_allocate;
7873 if (frame->save_regs_using_mov)
7874 frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
7875 if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
7876 frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
7879 frame->red_zone_size = 0;
7880 frame->to_allocate -= frame->red_zone_size;
7881 frame->stack_pointer_offset -= frame->red_zone_size;
7883 fprintf (stderr, "\n");
7884 fprintf (stderr, "size: %ld\n", (long)size);
7885 fprintf (stderr, "nregs: %ld\n", (long)frame->nregs);
7886 fprintf (stderr, "nsseregs: %ld\n", (long)frame->nsseregs);
7887 fprintf (stderr, "padding0: %ld\n", (long)frame->padding0);
7888 fprintf (stderr, "alignment1: %ld\n", (long)stack_alignment_needed);
7889 fprintf (stderr, "padding1: %ld\n", (long)frame->padding1);
7890 fprintf (stderr, "va_arg: %ld\n", (long)frame->va_arg_size);
7891 fprintf (stderr, "padding2: %ld\n", (long)frame->padding2);
7892 fprintf (stderr, "to_allocate: %ld\n", (long)frame->to_allocate);
7893 fprintf (stderr, "red_zone_size: %ld\n", (long)frame->red_zone_size);
7894 fprintf (stderr, "frame_pointer_offset: %ld\n", (long)frame->frame_pointer_offset);
7895 fprintf (stderr, "hard_frame_pointer_offset: %ld\n",
7896 (long)frame->hard_frame_pointer_offset);
7897 fprintf (stderr, "stack_pointer_offset: %ld\n", (long)frame->stack_pointer_offset);
7898 fprintf (stderr, "current_function_is_leaf: %ld\n", (long)current_function_is_leaf);
7899 fprintf (stderr, "cfun->calls_alloca: %ld\n", (long)cfun->calls_alloca);
7900 fprintf (stderr, "x86_current_function_calls_tls_descriptor: %ld\n", (long)ix86_current_function_calls_tls_descriptor);
7904 /* Emit code to save registers in the prologue. */
7907 ix86_emit_save_regs (void)
7912 for (regno = FIRST_PSEUDO_REGISTER - 1; regno-- > 0; )
7913 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7915 insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
7916 RTX_FRAME_RELATED_P (insn) = 1;
7920 /* Emit code to save registers using MOV insns. First register
7921 is restored from POINTER + OFFSET. */
7923 ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7928 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7929 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7931 insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
7933 gen_rtx_REG (Pmode, regno));
7934 RTX_FRAME_RELATED_P (insn) = 1;
7935 offset += UNITS_PER_WORD;
7939 /* Emit code to save registers using MOV insns. First register
7940 is restored from POINTER + OFFSET. */
7942 ix86_emit_save_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
7948 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
7949 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, true))
7951 mem = adjust_address (gen_rtx_MEM (TImode, pointer), TImode, offset);
7952 set_mem_align (mem, 128);
7953 insn = emit_move_insn (mem, gen_rtx_REG (TImode, regno));
7954 RTX_FRAME_RELATED_P (insn) = 1;
7959 /* Expand prologue or epilogue stack adjustment.
7960 The pattern exist to put a dependency on all ebp-based memory accesses.
7961 STYLE should be negative if instructions should be marked as frame related,
7962 zero if %r11 register is live and cannot be freely used and positive
7966 pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
7971 insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
7972 else if (x86_64_immediate_operand (offset, DImode))
7973 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
7977 /* r11 is used by indirect sibcall return as well, set before the
7978 epilogue and used after the epilogue. ATM indirect sibcall
7979 shouldn't be used together with huge frame sizes in one
7980 function because of the frame_size check in sibcall.c. */
7982 r11 = gen_rtx_REG (DImode, R11_REG);
7983 insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
7985 RTX_FRAME_RELATED_P (insn) = 1;
7986 insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
7990 RTX_FRAME_RELATED_P (insn) = 1;
7993 /* Find an available register to be used as dynamic realign argument
7994 pointer regsiter. Such a register will be written in prologue and
7995 used in begin of body, so it must not be
7996 1. parameter passing register.
7998 We reuse static-chain register if it is available. Otherwise, we
7999 use DI for i386 and R13 for x86-64. We chose R13 since it has
8002 Return: the regno of chosen register. */
8005 find_drap_reg (void)
8007 tree decl = cfun->decl;
8011 /* Use R13 for nested function or function need static chain.
8012 Since function with tail call may use any caller-saved
8013 registers in epilogue, DRAP must not use caller-saved
8014 register in such case. */
8015 if ((decl_function_context (decl)
8016 && !DECL_NO_STATIC_CHAIN (decl))
8017 || crtl->tail_call_emit)
8024 /* Use DI for nested function or function need static chain.
8025 Since function with tail call may use any caller-saved
8026 registers in epilogue, DRAP must not use caller-saved
8027 register in such case. */
8028 if ((decl_function_context (decl)
8029 && !DECL_NO_STATIC_CHAIN (decl))
8030 || crtl->tail_call_emit)
8033 /* Reuse static chain register if it isn't used for parameter
8035 if (ix86_function_regparm (TREE_TYPE (decl), decl) <= 2
8036 && !lookup_attribute ("fastcall",
8037 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
8044 /* Update incoming stack boundary and estimated stack alignment. */
8047 ix86_update_stack_boundary (void)
8049 /* Prefer the one specified at command line. */
8050 ix86_incoming_stack_boundary
8051 = (ix86_user_incoming_stack_boundary
8052 ? ix86_user_incoming_stack_boundary
8053 : ix86_default_incoming_stack_boundary);
8055 /* Incoming stack alignment can be changed on individual functions
8056 via force_align_arg_pointer attribute. We use the smallest
8057 incoming stack boundary. */
8058 if (ix86_incoming_stack_boundary > MIN_STACK_BOUNDARY
8059 && lookup_attribute (ix86_force_align_arg_pointer_string,
8060 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl))))
8061 ix86_incoming_stack_boundary = MIN_STACK_BOUNDARY;
8063 /* The incoming stack frame has to be aligned at least at
8064 parm_stack_boundary. */
8065 if (ix86_incoming_stack_boundary < crtl->parm_stack_boundary)
8066 ix86_incoming_stack_boundary = crtl->parm_stack_boundary;
8068 /* Stack at entrance of main is aligned by runtime. We use the
8069 smallest incoming stack boundary. */
8070 if (ix86_incoming_stack_boundary > MAIN_STACK_BOUNDARY
8071 && DECL_NAME (current_function_decl)
8072 && MAIN_NAME_P (DECL_NAME (current_function_decl))
8073 && DECL_FILE_SCOPE_P (current_function_decl))
8074 ix86_incoming_stack_boundary = MAIN_STACK_BOUNDARY;
8076 /* x86_64 vararg needs 16byte stack alignment for register save
8080 && crtl->stack_alignment_estimated < 128)
8081 crtl->stack_alignment_estimated = 128;
8084 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
8085 needed or an rtx for DRAP otherwise. */
8088 ix86_get_drap_rtx (void)
8090 if (ix86_force_drap || !ACCUMULATE_OUTGOING_ARGS)
8091 crtl->need_drap = true;
8093 if (stack_realign_drap)
8095 /* Assign DRAP to vDRAP and returns vDRAP */
8096 unsigned int regno = find_drap_reg ();
8101 arg_ptr = gen_rtx_REG (Pmode, regno);
8102 crtl->drap_reg = arg_ptr;
8105 drap_vreg = copy_to_reg (arg_ptr);
8109 insn = emit_insn_before (seq, NEXT_INSN (entry_of_function ()));
8110 RTX_FRAME_RELATED_P (insn) = 1;
8117 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
8120 ix86_internal_arg_pointer (void)
8122 return virtual_incoming_args_rtx;
8125 /* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook.
8126 This is called from dwarf2out.c to emit call frame instructions
8127 for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */
8129 ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
8131 rtx unspec = SET_SRC (pattern);
8132 gcc_assert (GET_CODE (unspec) == UNSPEC);
8136 case UNSPEC_REG_SAVE:
8137 dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0),
8138 SET_DEST (pattern));
8140 case UNSPEC_DEF_CFA:
8141 dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)),
8142 INTVAL (XVECEXP (unspec, 0, 0)));
8149 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
8150 to be generated in correct form. */
8152 ix86_finalize_stack_realign_flags (void)
8154 /* Check if stack realign is really needed after reload, and
8155 stores result in cfun */
8156 unsigned int incoming_stack_boundary
8157 = (crtl->parm_stack_boundary > ix86_incoming_stack_boundary
8158 ? crtl->parm_stack_boundary : ix86_incoming_stack_boundary);
8159 unsigned int stack_realign = (incoming_stack_boundary
8160 < (current_function_is_leaf
8161 ? crtl->max_used_stack_slot_alignment
8162 : crtl->stack_alignment_needed));
8164 if (crtl->stack_realign_finalized)
8166 /* After stack_realign_needed is finalized, we can't no longer
8168 gcc_assert (crtl->stack_realign_needed == stack_realign);
8172 crtl->stack_realign_needed = stack_realign;
8173 crtl->stack_realign_finalized = true;
8177 /* Expand the prologue into a bunch of separate insns. */
8180 ix86_expand_prologue (void)
8184 struct ix86_frame frame;
8185 HOST_WIDE_INT allocate;
8187 ix86_finalize_stack_realign_flags ();
8189 /* DRAP should not coexist with stack_realign_fp */
8190 gcc_assert (!(crtl->drap_reg && stack_realign_fp));
8192 ix86_compute_frame_layout (&frame);
8194 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
8195 of DRAP is needed and stack realignment is really needed after reload */
8196 if (crtl->drap_reg && crtl->stack_realign_needed)
8199 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8200 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8201 ? 0 : UNITS_PER_WORD);
8203 gcc_assert (stack_realign_drap);
8205 /* Grab the argument pointer. */
8206 x = plus_constant (stack_pointer_rtx,
8207 (UNITS_PER_WORD + param_ptr_offset));
8210 /* Only need to push parameter pointer reg if it is caller
8212 if (!call_used_regs[REGNO (crtl->drap_reg)])
8214 /* Push arg pointer reg */
8215 insn = emit_insn (gen_push (y));
8216 RTX_FRAME_RELATED_P (insn) = 1;
8219 insn = emit_insn (gen_rtx_SET (VOIDmode, y, x));
8220 RTX_FRAME_RELATED_P (insn) = 1;
8222 /* Align the stack. */
8223 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8225 GEN_INT (-align_bytes)));
8226 RTX_FRAME_RELATED_P (insn) = 1;
8228 /* Replicate the return address on the stack so that return
8229 address can be reached via (argp - 1) slot. This is needed
8230 to implement macro RETURN_ADDR_RTX and intrinsic function
8231 expand_builtin_return_addr etc. */
8233 x = gen_frame_mem (Pmode,
8234 plus_constant (x, -UNITS_PER_WORD));
8235 insn = emit_insn (gen_push (x));
8236 RTX_FRAME_RELATED_P (insn) = 1;
8239 /* Note: AT&T enter does NOT have reversed args. Enter is probably
8240 slower on all targets. Also sdb doesn't like it. */
8242 if (frame_pointer_needed)
8244 insn = emit_insn (gen_push (hard_frame_pointer_rtx));
8245 RTX_FRAME_RELATED_P (insn) = 1;
8247 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8248 RTX_FRAME_RELATED_P (insn) = 1;
8251 if (stack_realign_fp)
8253 int align_bytes = crtl->stack_alignment_needed / BITS_PER_UNIT;
8254 gcc_assert (align_bytes > MIN_STACK_BOUNDARY / BITS_PER_UNIT);
8256 /* Align the stack. */
8257 insn = emit_insn ((*ix86_gen_andsp) (stack_pointer_rtx,
8259 GEN_INT (-align_bytes)));
8260 RTX_FRAME_RELATED_P (insn) = 1;
8263 allocate = frame.to_allocate + frame.nsseregs * 16 + frame.padding0;
8265 if (!frame.save_regs_using_mov)
8266 ix86_emit_save_regs ();
8268 allocate += frame.nregs * UNITS_PER_WORD;
8270 /* When using red zone we may start register saving before allocating
8271 the stack frame saving one cycle of the prologue. However I will
8272 avoid doing this if I am going to have to probe the stack since
8273 at least on x86_64 the stack probe can turn into a call that clobbers
8274 a red zone location */
8275 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE && frame.save_regs_using_mov
8276 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT))
8277 ix86_emit_save_regs_using_mov ((frame_pointer_needed
8278 && !crtl->stack_realign_needed)
8279 ? hard_frame_pointer_rtx
8280 : stack_pointer_rtx,
8281 -frame.nregs * UNITS_PER_WORD);
8285 else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
8286 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8287 GEN_INT (-allocate), -1);
8290 rtx eax = gen_rtx_REG (Pmode, AX_REG);
8294 if (cfun->machine->call_abi == MS_ABI)
8297 eax_live = ix86_eax_live_at_start_p ();
8301 emit_insn (gen_push (eax));
8302 allocate -= UNITS_PER_WORD;
8305 emit_move_insn (eax, GEN_INT (allocate));
8308 insn = gen_allocate_stack_worker_64 (eax, eax);
8310 insn = gen_allocate_stack_worker_32 (eax, eax);
8311 insn = emit_insn (insn);
8312 RTX_FRAME_RELATED_P (insn) = 1;
8313 t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
8314 t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
8315 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8316 t, REG_NOTES (insn));
8320 if (frame_pointer_needed)
8321 t = plus_constant (hard_frame_pointer_rtx,
8324 - frame.nregs * UNITS_PER_WORD);
8326 t = plus_constant (stack_pointer_rtx, allocate);
8327 emit_move_insn (eax, gen_rtx_MEM (Pmode, t));
8331 if (frame.save_regs_using_mov
8332 && !(!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE
8333 && (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)))
8335 if (!frame_pointer_needed
8336 || !(frame.to_allocate + frame.padding0)
8337 || crtl->stack_realign_needed)
8338 ix86_emit_save_regs_using_mov (stack_pointer_rtx,
8340 + frame.nsseregs * 16 + frame.padding0);
8342 ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
8343 -frame.nregs * UNITS_PER_WORD);
8345 if (!frame_pointer_needed
8346 || !(frame.to_allocate + frame.padding0)
8347 || crtl->stack_realign_needed)
8348 ix86_emit_save_sse_regs_using_mov (stack_pointer_rtx,
8351 ix86_emit_save_sse_regs_using_mov (hard_frame_pointer_rtx,
8352 - frame.nregs * UNITS_PER_WORD
8353 - frame.nsseregs * 16
8356 pic_reg_used = false;
8357 if (pic_offset_table_rtx
8358 && (df_regs_ever_live_p (REAL_PIC_OFFSET_TABLE_REGNUM)
8361 unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();
8363 if (alt_pic_reg_used != INVALID_REGNUM)
8364 SET_REGNO (pic_offset_table_rtx, alt_pic_reg_used);
8366 pic_reg_used = true;
8373 if (ix86_cmodel == CM_LARGE_PIC)
8375 rtx tmp_reg = gen_rtx_REG (DImode, R11_REG);
8376 rtx label = gen_label_rtx ();
8378 LABEL_PRESERVE_P (label) = 1;
8379 gcc_assert (REGNO (pic_offset_table_rtx) != REGNO (tmp_reg));
8380 insn = emit_insn (gen_set_rip_rex64 (pic_offset_table_rtx, label));
8381 insn = emit_insn (gen_set_got_offset_rex64 (tmp_reg, label));
8382 insn = emit_insn (gen_adddi3 (pic_offset_table_rtx,
8383 pic_offset_table_rtx, tmp_reg));
8386 insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx));
8389 insn = emit_insn (gen_set_got (pic_offset_table_rtx));
8392 /* In the pic_reg_used case, make sure that the got load isn't deleted
8393 when mcount needs it. Blockage to avoid call movement across mcount
8394 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
8396 if (crtl->profile && pic_reg_used)
8397 emit_insn (gen_prologue_use (pic_offset_table_rtx));
8399 if (crtl->drap_reg && !crtl->stack_realign_needed)
8401 /* vDRAP is setup but after reload it turns out stack realign
8402 isn't necessary, here we will emit prologue to setup DRAP
8403 without stack realign adjustment */
8404 int drap_bp_offset = UNITS_PER_WORD * 2;
8405 rtx x = plus_constant (hard_frame_pointer_rtx, drap_bp_offset);
8406 insn = emit_insn (gen_rtx_SET (VOIDmode, crtl->drap_reg, x));
8409 /* Prevent instructions from being scheduled into register save push
8410 sequence when access to the redzone area is done through frame pointer.
8411 The offset betweeh the frame pointer and the stack pointer is calculated
8412 relative to the value of the stack pointer at the end of the function
8413 prologue, and moving instructions that access redzone area via frame
8414 pointer inside push sequence violates this assumption. */
8415 if (frame_pointer_needed && frame.red_zone_size)
8416 emit_insn (gen_memory_blockage ());
8418 /* Emit cld instruction if stringops are used in the function. */
8419 if (TARGET_CLD && ix86_current_function_needs_cld)
8420 emit_insn (gen_cld ());
8423 /* Emit code to restore saved registers using MOV insns. First register
8424 is restored from POINTER + OFFSET. */
8426 ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8427 int maybe_eh_return)
8430 rtx base_address = gen_rtx_MEM (Pmode, pointer);
8432 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8433 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8435 /* Ensure that adjust_address won't be forced to produce pointer
8436 out of range allowed by x86-64 instruction set. */
8437 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8441 r11 = gen_rtx_REG (DImode, R11_REG);
8442 emit_move_insn (r11, GEN_INT (offset));
8443 emit_insn (gen_adddi3 (r11, r11, pointer));
8444 base_address = gen_rtx_MEM (Pmode, r11);
8447 emit_move_insn (gen_rtx_REG (Pmode, regno),
8448 adjust_address (base_address, Pmode, offset));
8449 offset += UNITS_PER_WORD;
8453 /* Emit code to restore saved registers using MOV insns. First register
8454 is restored from POINTER + OFFSET. */
8456 ix86_emit_restore_sse_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
8457 int maybe_eh_return)
8460 rtx base_address = gen_rtx_MEM (TImode, pointer);
8463 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8464 if (SSE_REGNO_P (regno) && ix86_save_reg (regno, maybe_eh_return))
8466 /* Ensure that adjust_address won't be forced to produce pointer
8467 out of range allowed by x86-64 instruction set. */
8468 if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
8472 r11 = gen_rtx_REG (DImode, R11_REG);
8473 emit_move_insn (r11, GEN_INT (offset));
8474 emit_insn (gen_adddi3 (r11, r11, pointer));
8475 base_address = gen_rtx_MEM (TImode, r11);
8478 mem = adjust_address (base_address, TImode, offset);
8479 set_mem_align (mem, 128);
8480 emit_move_insn (gen_rtx_REG (TImode, regno), mem);
8485 /* Restore function stack, frame, and registers. */
8488 ix86_expand_epilogue (int style)
8492 struct ix86_frame frame;
8493 HOST_WIDE_INT offset;
8495 ix86_finalize_stack_realign_flags ();
8497 /* When stack is realigned, SP must be valid. */
8498 sp_valid = (!frame_pointer_needed
8499 || current_function_sp_is_unchanging
8500 || stack_realign_fp);
8502 ix86_compute_frame_layout (&frame);
8504 /* See the comment about red zone and frame
8505 pointer usage in ix86_expand_prologue. */
8506 if (frame_pointer_needed && frame.red_zone_size)
8507 emit_insn (gen_memory_blockage ());
8509 /* Calculate start of saved registers relative to ebp. Special care
8510 must be taken for the normal return case of a function using
8511 eh_return: the eax and edx registers are marked as saved, but not
8512 restored along this path. */
8513 offset = frame.nregs;
8514 if (crtl->calls_eh_return && style != 2)
8516 offset *= -UNITS_PER_WORD;
8517 offset -= frame.nsseregs * 16 + frame.padding0;
8519 /* If we're only restoring one register and sp is not valid then
8520 using a move instruction to restore the register since it's
8521 less work than reloading sp and popping the register.
8523 The default code result in stack adjustment using add/lea instruction,
8524 while this code results in LEAVE instruction (or discrete equivalent),
8525 so it is profitable in some other cases as well. Especially when there
8526 are no registers to restore. We also use this code when TARGET_USE_LEAVE
8527 and there is exactly one register to pop. This heuristic may need some
8528 tuning in future. */
8529 if ((!sp_valid && (frame.nregs + frame.nsseregs) <= 1)
8530 || (TARGET_EPILOGUE_USING_MOVE
8531 && cfun->machine->use_fast_prologue_epilogue
8532 && ((frame.nregs + frame.nsseregs) > 1
8533 || (frame.to_allocate + frame.padding0) != 0))
8534 || (frame_pointer_needed && !(frame.nregs + frame.nsseregs)
8535 && (frame.to_allocate + frame.padding0) != 0)
8536 || (frame_pointer_needed && TARGET_USE_LEAVE
8537 && cfun->machine->use_fast_prologue_epilogue
8538 && (frame.nregs + frame.nsseregs) == 1)
8539 || crtl->calls_eh_return)
8541 /* Restore registers. We can use ebp or esp to address the memory
8542 locations. If both are available, default to ebp, since offsets
8543 are known to be small. Only exception is esp pointing directly
8544 to the end of block of saved registers, where we may simplify
8547 If we are realigning stack with bp and sp, regs restore can't
8548 be addressed by bp. sp must be used instead. */
8550 if (!frame_pointer_needed
8551 || (sp_valid && !(frame.to_allocate + frame.padding0))
8552 || stack_realign_fp)
8554 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8555 frame.to_allocate, style == 2);
8556 ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
8558 + frame.nsseregs * 16
8559 + frame.padding0, style == 2);
8563 ix86_emit_restore_sse_regs_using_mov (hard_frame_pointer_rtx,
8564 offset, style == 2);
8565 ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
8567 + frame.nsseregs * 16
8568 + frame.padding0, style == 2);
8571 /* eh_return epilogues need %ecx added to the stack pointer. */
8574 rtx tmp, sa = EH_RETURN_STACKADJ_RTX;
8576 /* Stack align doesn't work with eh_return. */
8577 gcc_assert (!crtl->stack_realign_needed);
8579 if (frame_pointer_needed)
8581 tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
8582 tmp = plus_constant (tmp, UNITS_PER_WORD);
8583 emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));
8585 tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
8586 emit_move_insn (hard_frame_pointer_rtx, tmp);
8588 pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
8593 tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
8594 tmp = plus_constant (tmp, (frame.to_allocate
8595 + frame.nregs * UNITS_PER_WORD
8596 + frame.nsseregs * 16
8598 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
8601 else if (!frame_pointer_needed)
8602 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8603 GEN_INT (frame.to_allocate
8604 + frame.nregs * UNITS_PER_WORD
8605 + frame.nsseregs * 16
8608 /* If not an i386, mov & pop is faster than "leave". */
8609 else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
8610 || !cfun->machine->use_fast_prologue_epilogue)
8611 emit_insn ((*ix86_gen_leave) ());
8614 pro_epilogue_adjust_stack (stack_pointer_rtx,
8615 hard_frame_pointer_rtx,
8618 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8623 /* First step is to deallocate the stack frame so that we can
8626 If we realign stack with frame pointer, then stack pointer
8627 won't be able to recover via lea $offset(%bp), %sp, because
8628 there is a padding area between bp and sp for realign.
8629 "add $to_allocate, %sp" must be used instead. */
8632 gcc_assert (frame_pointer_needed);
8633 gcc_assert (!stack_realign_fp);
8634 pro_epilogue_adjust_stack (stack_pointer_rtx,
8635 hard_frame_pointer_rtx,
8636 GEN_INT (offset), style);
8637 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8639 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8640 GEN_INT (frame.nsseregs * 16 +
8641 frame.padding0), style);
8643 else if (frame.to_allocate || frame.padding0 || frame.nsseregs)
8645 ix86_emit_restore_sse_regs_using_mov (stack_pointer_rtx,
8648 pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
8649 GEN_INT (frame.to_allocate
8650 + frame.nsseregs * 16
8651 + frame.padding0), style);
8654 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8655 if (!SSE_REGNO_P (regno) && ix86_save_reg (regno, false))
8656 emit_insn ((*ix86_gen_pop1) (gen_rtx_REG (Pmode, regno)));
8657 if (frame_pointer_needed)
8659 /* Leave results in shorter dependency chains on CPUs that are
8660 able to grok it fast. */
8661 if (TARGET_USE_LEAVE)
8662 emit_insn ((*ix86_gen_leave) ());
8665 /* For stack realigned really happens, recover stack
8666 pointer to hard frame pointer is a must, if not using
8668 if (stack_realign_fp)
8669 pro_epilogue_adjust_stack (stack_pointer_rtx,
8670 hard_frame_pointer_rtx,
8672 emit_insn ((*ix86_gen_pop1) (hard_frame_pointer_rtx));
8677 if (crtl->drap_reg && crtl->stack_realign_needed)
8679 int param_ptr_offset = (call_used_regs[REGNO (crtl->drap_reg)]
8680 ? 0 : UNITS_PER_WORD);
8681 gcc_assert (stack_realign_drap);
8682 emit_insn (gen_rtx_SET
8683 (VOIDmode, stack_pointer_rtx,
8684 gen_rtx_PLUS (Pmode,
8686 GEN_INT (-(UNITS_PER_WORD
8687 + param_ptr_offset)))));
8688 if (!call_used_regs[REGNO (crtl->drap_reg)])
8689 emit_insn ((*ix86_gen_pop1) (crtl->drap_reg));
8693 /* Sibcall epilogues don't want a return instruction. */
8697 if (crtl->args.pops_args && crtl->args.size)
8699 rtx popc = GEN_INT (crtl->args.pops_args);
8701 /* i386 can only pop 64K bytes. If asked to pop more, pop
8702 return address, do explicit add, and jump indirectly to the
8705 if (crtl->args.pops_args >= 65536)
8707 rtx ecx = gen_rtx_REG (SImode, CX_REG);
8709 /* There is no "pascal" calling convention in any 64bit ABI. */
8710 gcc_assert (!TARGET_64BIT);
8712 emit_insn (gen_popsi1 (ecx));
8713 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
8714 emit_jump_insn (gen_return_indirect_internal (ecx));
8717 emit_jump_insn (gen_return_pop_internal (popc));
8720 emit_jump_insn (gen_return_internal ());
8723 /* Reset from the function's potential modifications. */
8726 ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8727 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8729 if (pic_offset_table_rtx)
8730 SET_REGNO (pic_offset_table_rtx, REAL_PIC_OFFSET_TABLE_REGNUM);
8732 /* Mach-O doesn't support labels at the end of objects, so if
8733 it looks like we might want one, insert a NOP. */
8735 rtx insn = get_last_insn ();
8738 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
8739 insn = PREV_INSN (insn);
8743 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
8744 fputs ("\tnop\n", file);
8750 /* Extract the parts of an RTL expression that is a valid memory address
8751 for an instruction. Return 0 if the structure of the address is
8752 grossly off. Return -1 if the address contains ASHIFT, so it is not
8753 strictly valid, but still used for computing length of lea instruction. */
8756 ix86_decompose_address (rtx addr, struct ix86_address *out)
8758 rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
8759 rtx base_reg, index_reg;
8760 HOST_WIDE_INT scale = 1;
8761 rtx scale_rtx = NULL_RTX;
8763 enum ix86_address_seg seg = SEG_DEFAULT;
8765 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
8767 else if (GET_CODE (addr) == PLUS)
8777 addends[n++] = XEXP (op, 1);
8780 while (GET_CODE (op) == PLUS);
8785 for (i = n; i >= 0; --i)
8788 switch (GET_CODE (op))
8793 index = XEXP (op, 0);
8794 scale_rtx = XEXP (op, 1);
8798 if (XINT (op, 1) == UNSPEC_TP
8799 && TARGET_TLS_DIRECT_SEG_REFS
8800 && seg == SEG_DEFAULT)
8801 seg = TARGET_64BIT ? SEG_FS : SEG_GS;
8830 else if (GET_CODE (addr) == MULT)
8832 index = XEXP (addr, 0); /* index*scale */
8833 scale_rtx = XEXP (addr, 1);
8835 else if (GET_CODE (addr) == ASHIFT)
8839 /* We're called for lea too, which implements ashift on occasion. */
8840 index = XEXP (addr, 0);
8841 tmp = XEXP (addr, 1);
8842 if (!CONST_INT_P (tmp))
8844 scale = INTVAL (tmp);
8845 if ((unsigned HOST_WIDE_INT) scale > 3)
8851 disp = addr; /* displacement */
8853 /* Extract the integral value of scale. */
8856 if (!CONST_INT_P (scale_rtx))
8858 scale = INTVAL (scale_rtx);
8861 base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
8862 index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;
8864 /* Allow arg pointer and stack pointer as index if there is not scaling. */
8865 if (base_reg && index_reg && scale == 1
8866 && (index_reg == arg_pointer_rtx
8867 || index_reg == frame_pointer_rtx
8868 || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
8871 tmp = base, base = index, index = tmp;
8872 tmp = base_reg, base_reg = index_reg, index_reg = tmp;
8875 /* Special case: %ebp cannot be encoded as a base without a displacement. */
8876 if ((base_reg == hard_frame_pointer_rtx
8877 || base_reg == frame_pointer_rtx
8878 || base_reg == arg_pointer_rtx) && !disp)
8881 /* Special case: on K6, [%esi] makes the instruction vector decoded.
8882 Avoid this by transforming to [%esi+0].
8883 Reload calls address legitimization without cfun defined, so we need
8884 to test cfun for being non-NULL. */
8885 if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
8886 && base_reg && !index_reg && !disp
8887 && REG_P (base_reg) && REGNO (base_reg) == SI_REG)
8890 /* Special case: encode reg+reg instead of reg*2. */
8891 if (!base && index && scale && scale == 2)
8892 base = index, base_reg = index_reg, scale = 1;
8894 /* Special case: scaling cannot be encoded without base or displacement. */
8895 if (!base && !disp && index && scale != 1)
8907 /* Return cost of the memory address x.
8908 For i386, it is better to use a complex address than let gcc copy
8909 the address into a reg and make a new pseudo. But not if the address
8910 requires to two regs - that would mean more pseudos with longer
8913 ix86_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
8915 struct ix86_address parts;
8917 int ok = ix86_decompose_address (x, &parts);
8921 if (parts.base && GET_CODE (parts.base) == SUBREG)
8922 parts.base = SUBREG_REG (parts.base);
8923 if (parts.index && GET_CODE (parts.index) == SUBREG)
8924 parts.index = SUBREG_REG (parts.index);
8926 /* Attempt to minimize number of registers in the address. */
8928 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
8930 && (!REG_P (parts.index)
8931 || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
8935 && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
8937 && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
8938 && parts.base != parts.index)
8941 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
8942 since it's predecode logic can't detect the length of instructions
8943 and it degenerates to vector decoded. Increase cost of such
8944 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
8945 to split such addresses or even refuse such addresses at all.
8947 Following addressing modes are affected:
8952 The first and last case may be avoidable by explicitly coding the zero in
8953 memory address, but I don't have AMD-K6 machine handy to check this
8957 && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
8958 || (parts.disp && !parts.base && parts.index && parts.scale != 1)
8959 || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
8965 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
8966 this is used for to form addresses to local data when -fPIC is in
8970 darwin_local_data_pic (rtx disp)
8972 return (GET_CODE (disp) == UNSPEC
8973 && XINT (disp, 1) == UNSPEC_MACHOPIC_OFFSET);
8976 /* Determine if a given RTX is a valid constant. We already know this
8977 satisfies CONSTANT_P. */
8980 legitimate_constant_p (rtx x)
8982 switch (GET_CODE (x))
8987 if (GET_CODE (x) == PLUS)
8989 if (!CONST_INT_P (XEXP (x, 1)))
8994 if (TARGET_MACHO && darwin_local_data_pic (x))
8997 /* Only some unspecs are valid as "constants". */
8998 if (GET_CODE (x) == UNSPEC)
8999 switch (XINT (x, 1))
9004 return TARGET_64BIT;
9007 x = XVECEXP (x, 0, 0);
9008 return (GET_CODE (x) == SYMBOL_REF
9009 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9011 x = XVECEXP (x, 0, 0);
9012 return (GET_CODE (x) == SYMBOL_REF
9013 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
9018 /* We must have drilled down to a symbol. */
9019 if (GET_CODE (x) == LABEL_REF)
9021 if (GET_CODE (x) != SYMBOL_REF)
9026 /* TLS symbols are never valid. */
9027 if (SYMBOL_REF_TLS_MODEL (x))
9030 /* DLLIMPORT symbols are never valid. */
9031 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
9032 && SYMBOL_REF_DLLIMPORT_P (x))
9037 if (GET_MODE (x) == TImode
9038 && x != CONST0_RTX (TImode)
9044 if (x == CONST0_RTX (GET_MODE (x)))
9052 /* Otherwise we handle everything else in the move patterns. */
9056 /* Determine if it's legal to put X into the constant pool. This
9057 is not possible for the address of thread-local symbols, which
9058 is checked above. */
9061 ix86_cannot_force_const_mem (rtx x)
9063 /* We can always put integral constants and vectors in memory. */
9064 switch (GET_CODE (x))
9074 return !legitimate_constant_p (x);
9077 /* Determine if a given RTX is a valid constant address. */
9080 constant_address_p (rtx x)
9082 return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
9085 /* Nonzero if the constant value X is a legitimate general operand
9086 when generating PIC code. It is given that flag_pic is on and
9087 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
9090 legitimate_pic_operand_p (rtx x)
9094 switch (GET_CODE (x))
9097 inner = XEXP (x, 0);
9098 if (GET_CODE (inner) == PLUS
9099 && CONST_INT_P (XEXP (inner, 1)))
9100 inner = XEXP (inner, 0);
9102 /* Only some unspecs are valid as "constants". */
9103 if (GET_CODE (inner) == UNSPEC)
9104 switch (XINT (inner, 1))
9109 return TARGET_64BIT;
9111 x = XVECEXP (inner, 0, 0);
9112 return (GET_CODE (x) == SYMBOL_REF
9113 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
9114 case UNSPEC_MACHOPIC_OFFSET:
9115 return legitimate_pic_address_disp_p (x);
9123 return legitimate_pic_address_disp_p (x);
9130 /* Determine if a given CONST RTX is a valid memory displacement
9134 legitimate_pic_address_disp_p (rtx disp)
9138 /* In 64bit mode we can allow direct addresses of symbols and labels
9139 when they are not dynamic symbols. */
9142 rtx op0 = disp, op1;
9144 switch (GET_CODE (disp))
9150 if (GET_CODE (XEXP (disp, 0)) != PLUS)
9152 op0 = XEXP (XEXP (disp, 0), 0);
9153 op1 = XEXP (XEXP (disp, 0), 1);
9154 if (!CONST_INT_P (op1)
9155 || INTVAL (op1) >= 16*1024*1024
9156 || INTVAL (op1) < -16*1024*1024)
9158 if (GET_CODE (op0) == LABEL_REF)
9160 if (GET_CODE (op0) != SYMBOL_REF)
9165 /* TLS references should always be enclosed in UNSPEC. */
9166 if (SYMBOL_REF_TLS_MODEL (op0))
9168 if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)
9169 && ix86_cmodel != CM_LARGE_PIC)
9177 if (GET_CODE (disp) != CONST)
9179 disp = XEXP (disp, 0);
9183 /* We are unsafe to allow PLUS expressions. This limit allowed distance
9184 of GOT tables. We should not need these anyway. */
9185 if (GET_CODE (disp) != UNSPEC
9186 || (XINT (disp, 1) != UNSPEC_GOTPCREL
9187 && XINT (disp, 1) != UNSPEC_GOTOFF
9188 && XINT (disp, 1) != UNSPEC_PLTOFF))
9191 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
9192 && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
9198 if (GET_CODE (disp) == PLUS)
9200 if (!CONST_INT_P (XEXP (disp, 1)))
9202 disp = XEXP (disp, 0);
9206 if (TARGET_MACHO && darwin_local_data_pic (disp))
9209 if (GET_CODE (disp) != UNSPEC)
9212 switch (XINT (disp, 1))
9217 /* We need to check for both symbols and labels because VxWorks loads
9218 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
9220 return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9221 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
9223 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
9224 While ABI specify also 32bit relocation but we don't produce it in
9225 small PIC model at all. */
9226 if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
9227 || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
9229 return gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
9231 case UNSPEC_GOTTPOFF:
9232 case UNSPEC_GOTNTPOFF:
9233 case UNSPEC_INDNTPOFF:
9236 disp = XVECEXP (disp, 0, 0);
9237 return (GET_CODE (disp) == SYMBOL_REF
9238 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
9240 disp = XVECEXP (disp, 0, 0);
9241 return (GET_CODE (disp) == SYMBOL_REF
9242 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
9244 disp = XVECEXP (disp, 0, 0);
9245 return (GET_CODE (disp) == SYMBOL_REF
9246 && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
9252 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
9253 memory address for an instruction. The MODE argument is the machine mode
9254 for the MEM expression that wants to use this address.
9256 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
9257 convert common non-canonical forms to canonical form so that they will
9261 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
9262 rtx addr, int strict)
9264 struct ix86_address parts;
9265 rtx base, index, disp;
9266 HOST_WIDE_INT scale;
9267 const char *reason = NULL;
9268 rtx reason_rtx = NULL_RTX;
9270 if (ix86_decompose_address (addr, &parts) <= 0)
9272 reason = "decomposition failed";
9277 index = parts.index;
9279 scale = parts.scale;
9281 /* Validate base register.
9283 Don't allow SUBREG's that span more than a word here. It can lead to spill
9284 failures when the base is one word out of a two word structure, which is
9285 represented internally as a DImode int. */
9294 else if (GET_CODE (base) == SUBREG
9295 && REG_P (SUBREG_REG (base))
9296 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
9298 reg = SUBREG_REG (base);
9301 reason = "base is not a register";
9305 if (GET_MODE (base) != Pmode)
9307 reason = "base is not in Pmode";
9311 if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
9312 || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
9314 reason = "base is not valid";
9319 /* Validate index register.
9321 Don't allow SUBREG's that span more than a word here -- same as above. */
9330 else if (GET_CODE (index) == SUBREG
9331 && REG_P (SUBREG_REG (index))
9332 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
9334 reg = SUBREG_REG (index);
9337 reason = "index is not a register";
9341 if (GET_MODE (index) != Pmode)
9343 reason = "index is not in Pmode";
9347 if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
9348 || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
9350 reason = "index is not valid";
9355 /* Validate scale factor. */
9358 reason_rtx = GEN_INT (scale);
9361 reason = "scale without index";
9365 if (scale != 2 && scale != 4 && scale != 8)
9367 reason = "scale is not a valid multiplier";
9372 /* Validate displacement. */
9377 if (GET_CODE (disp) == CONST
9378 && GET_CODE (XEXP (disp, 0)) == UNSPEC
9379 && XINT (XEXP (disp, 0), 1) != UNSPEC_MACHOPIC_OFFSET)
9380 switch (XINT (XEXP (disp, 0), 1))
9382 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
9383 used. While ABI specify also 32bit relocations, we don't produce
9384 them at all and use IP relative instead. */
9387 gcc_assert (flag_pic);
9389 goto is_legitimate_pic;
9390 reason = "64bit address unspec";
9393 case UNSPEC_GOTPCREL:
9394 gcc_assert (flag_pic);
9395 goto is_legitimate_pic;
9397 case UNSPEC_GOTTPOFF:
9398 case UNSPEC_GOTNTPOFF:
9399 case UNSPEC_INDNTPOFF:
9405 reason = "invalid address unspec";
9409 else if (SYMBOLIC_CONST (disp)
9413 && MACHOPIC_INDIRECT
9414 && !machopic_operand_p (disp)
9420 if (TARGET_64BIT && (index || base))
9422 /* foo@dtpoff(%rX) is ok. */
9423 if (GET_CODE (disp) != CONST
9424 || GET_CODE (XEXP (disp, 0)) != PLUS
9425 || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
9426 || !CONST_INT_P (XEXP (XEXP (disp, 0), 1))
9427 || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
9428 && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
9430 reason = "non-constant pic memory reference";
9434 else if (! legitimate_pic_address_disp_p (disp))
9436 reason = "displacement is an invalid pic construct";
9440 /* This code used to verify that a symbolic pic displacement
9441 includes the pic_offset_table_rtx register.
9443 While this is good idea, unfortunately these constructs may
9444 be created by "adds using lea" optimization for incorrect
9453 This code is nonsensical, but results in addressing
9454 GOT table with pic_offset_table_rtx base. We can't
9455 just refuse it easily, since it gets matched by
9456 "addsi3" pattern, that later gets split to lea in the
9457 case output register differs from input. While this
9458 can be handled by separate addsi pattern for this case
9459 that never results in lea, this seems to be easier and
9460 correct fix for crash to disable this test. */
9462 else if (GET_CODE (disp) != LABEL_REF
9463 && !CONST_INT_P (disp)
9464 && (GET_CODE (disp) != CONST
9465 || !legitimate_constant_p (disp))
9466 && (GET_CODE (disp) != SYMBOL_REF
9467 || !legitimate_constant_p (disp)))
9469 reason = "displacement is not constant";
9472 else if (TARGET_64BIT
9473 && !x86_64_immediate_operand (disp, VOIDmode))
9475 reason = "displacement is out of range";
9480 /* Everything looks valid. */
9487 /* Return a unique alias set for the GOT. */
9489 static alias_set_type
9490 ix86_GOT_alias_set (void)
9492 static alias_set_type set = -1;
9494 set = new_alias_set ();
9498 /* Return a legitimate reference for ORIG (an address) using the
9499 register REG. If REG is 0, a new pseudo is generated.
9501 There are two types of references that must be handled:
9503 1. Global data references must load the address from the GOT, via
9504 the PIC reg. An insn is emitted to do this load, and the reg is
9507 2. Static data references, constant pool addresses, and code labels
9508 compute the address as an offset from the GOT, whose base is in
9509 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9510 differentiate them from global data objects. The returned
9511 address is the PIC reg + an unspec constant.
9513 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
9514 reg also appears in the address. */
9517 legitimize_pic_address (rtx orig, rtx reg)
9524 if (TARGET_MACHO && !TARGET_64BIT)
9527 reg = gen_reg_rtx (Pmode);
9528 /* Use the generic Mach-O PIC machinery. */
9529 return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
9533 if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
9535 else if (TARGET_64BIT
9536 && ix86_cmodel != CM_SMALL_PIC
9537 && gotoff_operand (addr, Pmode))
9540 /* This symbol may be referenced via a displacement from the PIC
9541 base address (@GOTOFF). */
9543 if (reload_in_progress)
9544 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9545 if (GET_CODE (addr) == CONST)
9546 addr = XEXP (addr, 0);
9547 if (GET_CODE (addr) == PLUS)
9549 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9551 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9554 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9555 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9557 tmpreg = gen_reg_rtx (Pmode);
9560 emit_move_insn (tmpreg, new_rtx);
9564 new_rtx = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx,
9565 tmpreg, 1, OPTAB_DIRECT);
9568 else new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg);
9570 else if (!TARGET_64BIT && gotoff_operand (addr, Pmode))
9572 /* This symbol may be referenced via a displacement from the PIC
9573 base address (@GOTOFF). */
9575 if (reload_in_progress)
9576 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9577 if (GET_CODE (addr) == CONST)
9578 addr = XEXP (addr, 0);
9579 if (GET_CODE (addr) == PLUS)
9581 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)),
9583 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, XEXP (addr, 1));
9586 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
9587 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9588 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9592 emit_move_insn (reg, new_rtx);
9596 else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
9597 /* We can't use @GOTOFF for text labels on VxWorks;
9598 see gotoff_operand. */
9599 || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
9601 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
9603 if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
9604 return legitimize_dllimport_symbol (addr, true);
9605 if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
9606 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
9607 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
9609 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), true);
9610 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (addr, 0), 1));
9614 if (TARGET_64BIT && ix86_cmodel != CM_LARGE_PIC)
9616 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
9617 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9618 new_rtx = gen_const_mem (Pmode, new_rtx);
9619 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9622 reg = gen_reg_rtx (Pmode);
9623 /* Use directly gen_movsi, otherwise the address is loaded
9624 into register for CSE. We don't want to CSE this addresses,
9625 instead we CSE addresses from the GOT table, so skip this. */
9626 emit_insn (gen_movsi (reg, new_rtx));
9631 /* This symbol must be referenced via a load from the
9632 Global Offset Table (@GOT). */
9634 if (reload_in_progress)
9635 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9636 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
9637 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9639 new_rtx = force_reg (Pmode, new_rtx);
9640 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9641 new_rtx = gen_const_mem (Pmode, new_rtx);
9642 set_mem_alias_set (new_rtx, ix86_GOT_alias_set ());
9645 reg = gen_reg_rtx (Pmode);
9646 emit_move_insn (reg, new_rtx);
9652 if (CONST_INT_P (addr)
9653 && !x86_64_immediate_operand (addr, VOIDmode))
9657 emit_move_insn (reg, addr);
9661 new_rtx = force_reg (Pmode, addr);
9663 else if (GET_CODE (addr) == CONST)
9665 addr = XEXP (addr, 0);
9667 /* We must match stuff we generate before. Assume the only
9668 unspecs that can get here are ours. Not that we could do
9669 anything with them anyway.... */
9670 if (GET_CODE (addr) == UNSPEC
9671 || (GET_CODE (addr) == PLUS
9672 && GET_CODE (XEXP (addr, 0)) == UNSPEC))
9674 gcc_assert (GET_CODE (addr) == PLUS);
9676 if (GET_CODE (addr) == PLUS)
9678 rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
9680 /* Check first to see if this is a constant offset from a @GOTOFF
9681 symbol reference. */
9682 if (gotoff_operand (op0, Pmode)
9683 && CONST_INT_P (op1))
9687 if (reload_in_progress)
9688 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9689 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
9691 new_rtx = gen_rtx_PLUS (Pmode, new_rtx, op1);
9692 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
9693 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
9697 emit_move_insn (reg, new_rtx);
9703 if (INTVAL (op1) < -16*1024*1024
9704 || INTVAL (op1) >= 16*1024*1024)
9706 if (!x86_64_immediate_operand (op1, Pmode))
9707 op1 = force_reg (Pmode, op1);
9708 new_rtx = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
9714 base = legitimize_pic_address (XEXP (addr, 0), reg);
9715 new_rtx = legitimize_pic_address (XEXP (addr, 1),
9716 base == reg ? NULL_RTX : reg);
9718 if (CONST_INT_P (new_rtx))
9719 new_rtx = plus_constant (base, INTVAL (new_rtx));
9722 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
9724 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
9725 new_rtx = XEXP (new_rtx, 1);
9727 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9735 /* Load the thread pointer. If TO_REG is true, force it into a register. */
9738 get_thread_pointer (int to_reg)
9742 tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
9746 reg = gen_reg_rtx (Pmode);
9747 insn = gen_rtx_SET (VOIDmode, reg, tp);
9748 insn = emit_insn (insn);
9753 /* A subroutine of legitimize_address and ix86_expand_move. FOR_MOV is
9754 false if we expect this to be used for a memory address and true if
9755 we expect to load the address into a register. */
9758 legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
9760 rtx dest, base, off, pic, tp;
9765 case TLS_MODEL_GLOBAL_DYNAMIC:
9766 dest = gen_reg_rtx (Pmode);
9767 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9769 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9771 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns;
9774 emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
9775 insns = get_insns ();
9778 RTL_CONST_CALL_P (insns) = 1;
9779 emit_libcall_block (insns, dest, rax, x);
9781 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9782 emit_insn (gen_tls_global_dynamic_64 (dest, x));
9784 emit_insn (gen_tls_global_dynamic_32 (dest, x));
9786 if (TARGET_GNU2_TLS)
9788 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest));
9790 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9794 case TLS_MODEL_LOCAL_DYNAMIC:
9795 base = gen_reg_rtx (Pmode);
9796 tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0;
9798 if (TARGET_64BIT && ! TARGET_GNU2_TLS)
9800 rtx rax = gen_rtx_REG (Pmode, AX_REG), insns, note;
9803 emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
9804 insns = get_insns ();
9807 note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
9808 note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
9809 RTL_CONST_CALL_P (insns) = 1;
9810 emit_libcall_block (insns, base, rax, note);
9812 else if (TARGET_64BIT && TARGET_GNU2_TLS)
9813 emit_insn (gen_tls_local_dynamic_base_64 (base));
9815 emit_insn (gen_tls_local_dynamic_base_32 (base));
9817 if (TARGET_GNU2_TLS)
9819 rtx x = ix86_tls_module_base ();
9821 set_unique_reg_note (get_last_insn (), REG_EQUIV,
9822 gen_rtx_MINUS (Pmode, x, tp));
9825 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
9826 off = gen_rtx_CONST (Pmode, off);
9828 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off));
9830 if (TARGET_GNU2_TLS)
9832 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp));
9834 set_unique_reg_note (get_last_insn (), REG_EQUIV, x);
9839 case TLS_MODEL_INITIAL_EXEC:
9843 type = UNSPEC_GOTNTPOFF;
9847 if (reload_in_progress)
9848 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9849 pic = pic_offset_table_rtx;
9850 type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
9852 else if (!TARGET_ANY_GNU_TLS)
9854 pic = gen_reg_rtx (Pmode);
9855 emit_insn (gen_set_got (pic));
9856 type = UNSPEC_GOTTPOFF;
9861 type = UNSPEC_INDNTPOFF;
9864 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
9865 off = gen_rtx_CONST (Pmode, off);
9867 off = gen_rtx_PLUS (Pmode, pic, off);
9868 off = gen_const_mem (Pmode, off);
9869 set_mem_alias_set (off, ix86_GOT_alias_set ());
9871 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9873 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9874 off = force_reg (Pmode, off);
9875 return gen_rtx_PLUS (Pmode, base, off);
9879 base = get_thread_pointer (true);
9880 dest = gen_reg_rtx (Pmode);
9881 emit_insn (gen_subsi3 (dest, base, off));
9885 case TLS_MODEL_LOCAL_EXEC:
9886 off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
9887 (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9888 ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
9889 off = gen_rtx_CONST (Pmode, off);
9891 if (TARGET_64BIT || TARGET_ANY_GNU_TLS)
9893 base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
9894 return gen_rtx_PLUS (Pmode, base, off);
9898 base = get_thread_pointer (true);
9899 dest = gen_reg_rtx (Pmode);
9900 emit_insn (gen_subsi3 (dest, base, off));
9911 /* Create or return the unique __imp_DECL dllimport symbol corresponding
9914 static GTY((if_marked ("tree_map_marked_p"), param_is (struct tree_map)))
9915 htab_t dllimport_map;
9918 get_dllimport_decl (tree decl)
9920 struct tree_map *h, in;
9924 size_t namelen, prefixlen;
9930 dllimport_map = htab_create_ggc (512, tree_map_hash, tree_map_eq, 0);
9932 in.hash = htab_hash_pointer (decl);
9933 in.base.from = decl;
9934 loc = htab_find_slot_with_hash (dllimport_map, &in, in.hash, INSERT);
9935 h = (struct tree_map *) *loc;
9939 *loc = h = GGC_NEW (struct tree_map);
9941 h->base.from = decl;
9942 h->to = to = build_decl (VAR_DECL, NULL, ptr_type_node);
9943 DECL_ARTIFICIAL (to) = 1;
9944 DECL_IGNORED_P (to) = 1;
9945 DECL_EXTERNAL (to) = 1;
9946 TREE_READONLY (to) = 1;
9948 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9949 name = targetm.strip_name_encoding (name);
9950 prefix = name[0] == FASTCALL_PREFIX || user_label_prefix[0] == 0
9951 ? "*__imp_" : "*__imp__";
9952 namelen = strlen (name);
9953 prefixlen = strlen (prefix);
9954 imp_name = (char *) alloca (namelen + prefixlen + 1);
9955 memcpy (imp_name, prefix, prefixlen);
9956 memcpy (imp_name + prefixlen, name, namelen + 1);
9958 name = ggc_alloc_string (imp_name, namelen + prefixlen);
9959 rtl = gen_rtx_SYMBOL_REF (Pmode, name);
9960 SET_SYMBOL_REF_DECL (rtl, to);
9961 SYMBOL_REF_FLAGS (rtl) = SYMBOL_FLAG_LOCAL;
9963 rtl = gen_const_mem (Pmode, rtl);
9964 set_mem_alias_set (rtl, ix86_GOT_alias_set ());
9966 SET_DECL_RTL (to, rtl);
9967 SET_DECL_ASSEMBLER_NAME (to, get_identifier (name));
9972 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
9973 true if we require the result be a register. */
9976 legitimize_dllimport_symbol (rtx symbol, bool want_reg)
9981 gcc_assert (SYMBOL_REF_DECL (symbol));
9982 imp_decl = get_dllimport_decl (SYMBOL_REF_DECL (symbol));
9984 x = DECL_RTL (imp_decl);
9986 x = force_reg (Pmode, x);
9990 /* Try machine-dependent ways of modifying an illegitimate address
9991 to be legitimate. If we find one, return the new, valid address.
9992 This macro is used in only one place: `memory_address' in explow.c.
9994 OLDX is the address as it was before break_out_memory_refs was called.
9995 In some cases it is useful to look at this to decide what needs to be done.
9997 MODE and WIN are passed so that this macro can use
9998 GO_IF_LEGITIMATE_ADDRESS.
10000 It is always safe for this macro to do nothing. It exists to recognize
10001 opportunities to optimize the output.
10003 For the 80386, we handle X+REG by loading X into a register R and
10004 using R+REG. R will go in a general reg and indexing will be used.
10005 However, if REG is a broken-out memory address or multiplication,
10006 nothing needs to be done because REG can certainly go in a general reg.
10008 When -fpic is used, special handling is needed for symbolic references.
10009 See comments by legitimize_pic_address in i386.c for details. */
10012 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
10017 log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
10019 return legitimize_tls_address (x, (enum tls_model) log, false);
10020 if (GET_CODE (x) == CONST
10021 && GET_CODE (XEXP (x, 0)) == PLUS
10022 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10023 && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
10025 rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
10026 (enum tls_model) log, false);
10027 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10030 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
10032 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (x))
10033 return legitimize_dllimport_symbol (x, true);
10034 if (GET_CODE (x) == CONST
10035 && GET_CODE (XEXP (x, 0)) == PLUS
10036 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
10037 && SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (x, 0), 0)))
10039 rtx t = legitimize_dllimport_symbol (XEXP (XEXP (x, 0), 0), true);
10040 return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
10044 if (flag_pic && SYMBOLIC_CONST (x))
10045 return legitimize_pic_address (x, 0);
10047 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
10048 if (GET_CODE (x) == ASHIFT
10049 && CONST_INT_P (XEXP (x, 1))
10050 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
10053 log = INTVAL (XEXP (x, 1));
10054 x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
10055 GEN_INT (1 << log));
10058 if (GET_CODE (x) == PLUS)
10060 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
10062 if (GET_CODE (XEXP (x, 0)) == ASHIFT
10063 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
10064 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
10067 log = INTVAL (XEXP (XEXP (x, 0), 1));
10068 XEXP (x, 0) = gen_rtx_MULT (Pmode,
10069 force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
10070 GEN_INT (1 << log));
10073 if (GET_CODE (XEXP (x, 1)) == ASHIFT
10074 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
10075 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
10078 log = INTVAL (XEXP (XEXP (x, 1), 1));
10079 XEXP (x, 1) = gen_rtx_MULT (Pmode,
10080 force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
10081 GEN_INT (1 << log));
10084 /* Put multiply first if it isn't already. */
10085 if (GET_CODE (XEXP (x, 1)) == MULT)
10087 rtx tmp = XEXP (x, 0);
10088 XEXP (x, 0) = XEXP (x, 1);
10093 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
10094 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
10095 created by virtual register instantiation, register elimination, and
10096 similar optimizations. */
10097 if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
10100 x = gen_rtx_PLUS (Pmode,
10101 gen_rtx_PLUS (Pmode, XEXP (x, 0),
10102 XEXP (XEXP (x, 1), 0)),
10103 XEXP (XEXP (x, 1), 1));
10107 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
10108 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
10109 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
10110 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
10111 && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
10112 && CONSTANT_P (XEXP (x, 1)))
10115 rtx other = NULL_RTX;
10117 if (CONST_INT_P (XEXP (x, 1)))
10119 constant = XEXP (x, 1);
10120 other = XEXP (XEXP (XEXP (x, 0), 1), 1);
10122 else if (CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 1), 1)))
10124 constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
10125 other = XEXP (x, 1);
10133 x = gen_rtx_PLUS (Pmode,
10134 gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
10135 XEXP (XEXP (XEXP (x, 0), 1), 0)),
10136 plus_constant (other, INTVAL (constant)));
10140 if (changed && legitimate_address_p (mode, x, FALSE))
10143 if (GET_CODE (XEXP (x, 0)) == MULT)
10146 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
10149 if (GET_CODE (XEXP (x, 1)) == MULT)
10152 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
10156 && REG_P (XEXP (x, 1))
10157 && REG_P (XEXP (x, 0)))
10160 if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
10163 x = legitimize_pic_address (x, 0);
10166 if (changed && legitimate_address_p (mode, x, FALSE))
10169 if (REG_P (XEXP (x, 0)))
10171 rtx temp = gen_reg_rtx (Pmode);
10172 rtx val = force_operand (XEXP (x, 1), temp);
10174 emit_move_insn (temp, val);
10176 XEXP (x, 1) = temp;
10180 else if (REG_P (XEXP (x, 1)))
10182 rtx temp = gen_reg_rtx (Pmode);
10183 rtx val = force_operand (XEXP (x, 0), temp);
10185 emit_move_insn (temp, val);
10187 XEXP (x, 0) = temp;
10195 /* Print an integer constant expression in assembler syntax. Addition
10196 and subtraction are the only arithmetic that may appear in these
10197 expressions. FILE is the stdio stream to write to, X is the rtx, and
10198 CODE is the operand print code from the output string. */
10201 output_pic_addr_const (FILE *file, rtx x, int code)
10205 switch (GET_CODE (x))
10208 gcc_assert (flag_pic);
10213 if (! TARGET_MACHO || TARGET_64BIT)
10214 output_addr_const (file, x);
10217 const char *name = XSTR (x, 0);
10219 /* Mark the decl as referenced so that cgraph will
10220 output the function. */
10221 if (SYMBOL_REF_DECL (x))
10222 mark_decl_referenced (SYMBOL_REF_DECL (x));
10225 if (MACHOPIC_INDIRECT
10226 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10227 name = machopic_indirection_name (x, /*stub_p=*/true);
10229 assemble_name (file, name);
10231 if (!TARGET_MACHO && !(TARGET_64BIT && DEFAULT_ABI == MS_ABI)
10232 && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
10233 fputs ("@PLT", file);
10240 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
10241 assemble_name (asm_out_file, buf);
10245 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
10249 /* This used to output parentheses around the expression,
10250 but that does not work on the 386 (either ATT or BSD assembler). */
10251 output_pic_addr_const (file, XEXP (x, 0), code);
10255 if (GET_MODE (x) == VOIDmode)
10257 /* We can use %d if the number is <32 bits and positive. */
10258 if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
10259 fprintf (file, "0x%lx%08lx",
10260 (unsigned long) CONST_DOUBLE_HIGH (x),
10261 (unsigned long) CONST_DOUBLE_LOW (x));
10263 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
10266 /* We can't handle floating point constants;
10267 PRINT_OPERAND must handle them. */
10268 output_operand_lossage ("floating constant misused");
10272 /* Some assemblers need integer constants to appear first. */
10273 if (CONST_INT_P (XEXP (x, 0)))
10275 output_pic_addr_const (file, XEXP (x, 0), code);
10277 output_pic_addr_const (file, XEXP (x, 1), code);
10281 gcc_assert (CONST_INT_P (XEXP (x, 1)));
10282 output_pic_addr_const (file, XEXP (x, 1), code);
10284 output_pic_addr_const (file, XEXP (x, 0), code);
10290 putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
10291 output_pic_addr_const (file, XEXP (x, 0), code);
10293 output_pic_addr_const (file, XEXP (x, 1), code);
10295 putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
10299 gcc_assert (XVECLEN (x, 0) == 1);
10300 output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
10301 switch (XINT (x, 1))
10304 fputs ("@GOT", file);
10306 case UNSPEC_GOTOFF:
10307 fputs ("@GOTOFF", file);
10309 case UNSPEC_PLTOFF:
10310 fputs ("@PLTOFF", file);
10312 case UNSPEC_GOTPCREL:
10313 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10314 "@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
10316 case UNSPEC_GOTTPOFF:
10317 /* FIXME: This might be @TPOFF in Sun ld too. */
10318 fputs ("@GOTTPOFF", file);
10321 fputs ("@TPOFF", file);
10323 case UNSPEC_NTPOFF:
10325 fputs ("@TPOFF", file);
10327 fputs ("@NTPOFF", file);
10329 case UNSPEC_DTPOFF:
10330 fputs ("@DTPOFF", file);
10332 case UNSPEC_GOTNTPOFF:
10334 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
10335 "@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
10337 fputs ("@GOTNTPOFF", file);
10339 case UNSPEC_INDNTPOFF:
10340 fputs ("@INDNTPOFF", file);
10343 case UNSPEC_MACHOPIC_OFFSET:
10345 machopic_output_function_base_name (file);
10349 output_operand_lossage ("invalid UNSPEC as operand");
10355 output_operand_lossage ("invalid expression as operand");
10359 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
10360 We need to emit DTP-relative relocations. */
10362 static void ATTRIBUTE_UNUSED
10363 i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
10365 fputs (ASM_LONG, file);
10366 output_addr_const (file, x);
10367 fputs ("@DTPOFF", file);
10373 fputs (", 0", file);
10376 gcc_unreachable ();
10380 /* Return true if X is a representation of the PIC register. This copes
10381 with calls from ix86_find_base_term, where the register might have
10382 been replaced by a cselib value. */
10385 ix86_pic_register_p (rtx x)
10387 if (GET_CODE (x) == VALUE && CSELIB_VAL_PTR (x))
10388 return (pic_offset_table_rtx
10389 && rtx_equal_for_cselib_p (x, pic_offset_table_rtx));
10391 return REG_P (x) && REGNO (x) == PIC_OFFSET_TABLE_REGNUM;
10394 /* In the name of slightly smaller debug output, and to cater to
10395 general assembler lossage, recognize PIC+GOTOFF and turn it back
10396 into a direct symbol reference.
10398 On Darwin, this is necessary to avoid a crash, because Darwin
10399 has a different PIC label for each routine but the DWARF debugging
10400 information is not associated with any particular routine, so it's
10401 necessary to remove references to the PIC label from RTL stored by
10402 the DWARF output code. */
10405 ix86_delegitimize_address (rtx orig_x)
10408 /* reg_addend is NULL or a multiple of some register. */
10409 rtx reg_addend = NULL_RTX;
10410 /* const_addend is NULL or a const_int. */
10411 rtx const_addend = NULL_RTX;
10412 /* This is the result, or NULL. */
10413 rtx result = NULL_RTX;
10420 if (GET_CODE (x) != CONST
10421 || GET_CODE (XEXP (x, 0)) != UNSPEC
10422 || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
10423 || !MEM_P (orig_x))
10425 return XVECEXP (XEXP (x, 0), 0, 0);
10428 if (GET_CODE (x) != PLUS
10429 || GET_CODE (XEXP (x, 1)) != CONST)
10432 if (ix86_pic_register_p (XEXP (x, 0)))
10433 /* %ebx + GOT/GOTOFF */
10435 else if (GET_CODE (XEXP (x, 0)) == PLUS)
10437 /* %ebx + %reg * scale + GOT/GOTOFF */
10438 reg_addend = XEXP (x, 0);
10439 if (ix86_pic_register_p (XEXP (reg_addend, 0)))
10440 reg_addend = XEXP (reg_addend, 1);
10441 else if (ix86_pic_register_p (XEXP (reg_addend, 1)))
10442 reg_addend = XEXP (reg_addend, 0);
10445 if (!REG_P (reg_addend)
10446 && GET_CODE (reg_addend) != MULT
10447 && GET_CODE (reg_addend) != ASHIFT)
10453 x = XEXP (XEXP (x, 1), 0);
10454 if (GET_CODE (x) == PLUS
10455 && CONST_INT_P (XEXP (x, 1)))
10457 const_addend = XEXP (x, 1);
10461 if (GET_CODE (x) == UNSPEC
10462 && ((XINT (x, 1) == UNSPEC_GOT && MEM_P (orig_x))
10463 || (XINT (x, 1) == UNSPEC_GOTOFF && !MEM_P (orig_x))))
10464 result = XVECEXP (x, 0, 0);
10466 if (TARGET_MACHO && darwin_local_data_pic (x)
10467 && !MEM_P (orig_x))
10468 result = XVECEXP (x, 0, 0);
10474 result = gen_rtx_CONST (Pmode, gen_rtx_PLUS (Pmode, result, const_addend));
10476 result = gen_rtx_PLUS (Pmode, reg_addend, result);
10480 /* If X is a machine specific address (i.e. a symbol or label being
10481 referenced as a displacement from the GOT implemented using an
10482 UNSPEC), then return the base term. Otherwise return X. */
10485 ix86_find_base_term (rtx x)
10491 if (GET_CODE (x) != CONST)
10493 term = XEXP (x, 0);
10494 if (GET_CODE (term) == PLUS
10495 && (CONST_INT_P (XEXP (term, 1))
10496 || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
10497 term = XEXP (term, 0);
10498 if (GET_CODE (term) != UNSPEC
10499 || XINT (term, 1) != UNSPEC_GOTPCREL)
10502 return XVECEXP (term, 0, 0);
10505 return ix86_delegitimize_address (x);
10509 put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
10510 int fp, FILE *file)
10512 const char *suffix;
10514 if (mode == CCFPmode || mode == CCFPUmode)
10516 enum rtx_code second_code, bypass_code;
10517 ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
10518 gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN);
10519 code = ix86_fp_compare_code_to_integer (code);
10523 code = reverse_condition (code);
10574 gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode);
10578 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
10579 Those same assemblers have the same but opposite lossage on cmov. */
10580 if (mode == CCmode)
10581 suffix = fp ? "nbe" : "a";
10582 else if (mode == CCCmode)
10585 gcc_unreachable ();
10601 gcc_unreachable ();
10605 gcc_assert (mode == CCmode || mode == CCCmode);
10622 gcc_unreachable ();
10626 /* ??? As above. */
10627 gcc_assert (mode == CCmode || mode == CCCmode);
10628 suffix = fp ? "nb" : "ae";
10631 gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode);
10635 /* ??? As above. */
10636 if (mode == CCmode)
10638 else if (mode == CCCmode)
10639 suffix = fp ? "nb" : "ae";
10641 gcc_unreachable ();
10644 suffix = fp ? "u" : "p";
10647 suffix = fp ? "nu" : "np";
10650 gcc_unreachable ();
10652 fputs (suffix, file);
10655 /* Print the name of register X to FILE based on its machine mode and number.
10656 If CODE is 'w', pretend the mode is HImode.
10657 If CODE is 'b', pretend the mode is QImode.
10658 If CODE is 'k', pretend the mode is SImode.
10659 If CODE is 'q', pretend the mode is DImode.
10660 If CODE is 'x', pretend the mode is V4SFmode.
10661 If CODE is 't', pretend the mode is V8SFmode.
10662 If CODE is 'h', pretend the reg is the 'high' byte register.
10663 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
10664 If CODE is 'd', duplicate the operand for AVX instruction.
10668 print_reg (rtx x, int code, FILE *file)
10671 bool duplicated = code == 'd' && TARGET_AVX;
10673 gcc_assert (x == pc_rtx
10674 || (REGNO (x) != ARG_POINTER_REGNUM
10675 && REGNO (x) != FRAME_POINTER_REGNUM
10676 && REGNO (x) != FLAGS_REG
10677 && REGNO (x) != FPSR_REG
10678 && REGNO (x) != FPCR_REG));
10680 if (ASSEMBLER_DIALECT == ASM_ATT)
10685 gcc_assert (TARGET_64BIT);
10686 fputs ("rip", file);
10690 if (code == 'w' || MMX_REG_P (x))
10692 else if (code == 'b')
10694 else if (code == 'k')
10696 else if (code == 'q')
10698 else if (code == 'y')
10700 else if (code == 'h')
10702 else if (code == 'x')
10704 else if (code == 't')
10707 code = GET_MODE_SIZE (GET_MODE (x));
10709 /* Irritatingly, AMD extended registers use different naming convention
10710 from the normal registers. */
10711 if (REX_INT_REG_P (x))
10713 gcc_assert (TARGET_64BIT);
10717 error ("extended registers have no high halves");
10720 fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
10723 fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
10726 fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
10729 fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
10732 error ("unsupported operand size for extended register");
10742 if (STACK_TOP_P (x))
10751 if (! ANY_FP_REG_P (x))
10752 putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
10757 reg = hi_reg_name[REGNO (x)];
10760 if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
10762 reg = qi_reg_name[REGNO (x)];
10765 if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
10767 reg = qi_high_reg_name[REGNO (x)];
10772 gcc_assert (!duplicated);
10774 fputs (hi_reg_name[REGNO (x)] + 1, file);
10779 gcc_unreachable ();
10785 if (ASSEMBLER_DIALECT == ASM_ATT)
10786 fprintf (file, ", %%%s", reg);
10788 fprintf (file, ", %s", reg);
10792 /* Locate some local-dynamic symbol still in use by this function
10793 so that we can print its name in some tls_local_dynamic_base
10797 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10801 if (GET_CODE (x) == SYMBOL_REF
10802 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10804 cfun->machine->some_ld_name = XSTR (x, 0);
10811 static const char *
10812 get_some_local_dynamic_name (void)
10816 if (cfun->machine->some_ld_name)
10817 return cfun->machine->some_ld_name;
10819 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10821 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
10822 return cfun->machine->some_ld_name;
10824 gcc_unreachable ();
10827 /* Meaning of CODE:
10828 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
10829 C -- print opcode suffix for set/cmov insn.
10830 c -- like C, but print reversed condition
10831 F,f -- likewise, but for floating-point.
10832 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
10834 R -- print the prefix for register names.
10835 z -- print the opcode suffix for the size of the current operand.
10836 * -- print a star (in certain assembler syntax)
10837 A -- print an absolute memory reference.
10838 w -- print the operand as if it's a "word" (HImode) even if it isn't.
10839 s -- print a shift double count, followed by the assemblers argument
10841 b -- print the QImode name of the register for the indicated operand.
10842 %b0 would print %al if operands[0] is reg 0.
10843 w -- likewise, print the HImode name of the register.
10844 k -- likewise, print the SImode name of the register.
10845 q -- likewise, print the DImode name of the register.
10846 x -- likewise, print the V4SFmode name of the register.
10847 t -- likewise, print the V8SFmode name of the register.
10848 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
10849 y -- print "st(0)" instead of "st" as a register.
10850 d -- print duplicated register operand for AVX instruction.
10851 D -- print condition for SSE cmp instruction.
10852 P -- if PIC, print an @PLT suffix.
10853 X -- don't print any sort of PIC '@' suffix for a symbol.
10854 & -- print some in-use local-dynamic symbol name.
10855 H -- print a memory address offset by 8; used for sse high-parts
10856 Y -- print condition for SSE5 com* instruction.
10857 + -- print a branch hint as 'cs' or 'ds' prefix
10858 ; -- print a semicolon (after prefixes due to bug in older gas).
10862 print_operand (FILE *file, rtx x, int code)
10869 if (ASSEMBLER_DIALECT == ASM_ATT)
10874 assemble_name (file, get_some_local_dynamic_name ());
10878 switch (ASSEMBLER_DIALECT)
10885 /* Intel syntax. For absolute addresses, registers should not
10886 be surrounded by braces. */
10890 PRINT_OPERAND (file, x, 0);
10897 gcc_unreachable ();
10900 PRINT_OPERAND (file, x, 0);
10905 if (ASSEMBLER_DIALECT == ASM_ATT)
10910 if (ASSEMBLER_DIALECT == ASM_ATT)
10915 if (ASSEMBLER_DIALECT == ASM_ATT)
10920 if (ASSEMBLER_DIALECT == ASM_ATT)
10925 if (ASSEMBLER_DIALECT == ASM_ATT)
10930 if (ASSEMBLER_DIALECT == ASM_ATT)
10935 /* 387 opcodes don't get size suffixes if the operands are
10937 if (STACK_REG_P (x))
10940 /* Likewise if using Intel opcodes. */
10941 if (ASSEMBLER_DIALECT == ASM_INTEL)
10944 /* This is the size of op from size of operand. */
10945 switch (GET_MODE_SIZE (GET_MODE (x)))
10954 #ifdef HAVE_GAS_FILDS_FISTS
10964 if (GET_MODE (x) == SFmode)
10979 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
10983 #ifdef GAS_MNEMONICS
10998 gcc_unreachable ();
11015 if (CONST_INT_P (x) || ! SHIFT_DOUBLE_OMITS_COUNT)
11017 PRINT_OPERAND (file, x, 0);
11018 fputs (", ", file);
11023 /* Little bit of braindamage here. The SSE compare instructions
11024 does use completely different names for the comparisons that the
11025 fp conditional moves. */
11028 switch (GET_CODE (x))
11031 fputs ("eq", file);
11034 fputs ("eq_us", file);
11037 fputs ("lt", file);
11040 fputs ("nge", file);
11043 fputs ("le", file);
11046 fputs ("ngt", file);
11049 fputs ("unord", file);
11052 fputs ("neq", file);
11055 fputs ("neq_oq", file);
11058 fputs ("ge", file);
11061 fputs ("nlt", file);
11064 fputs ("gt", file);
11067 fputs ("nle", file);
11070 fputs ("ord", file);
11073 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11079 switch (GET_CODE (x))
11083 fputs ("eq", file);
11087 fputs ("lt", file);
11091 fputs ("le", file);
11094 fputs ("unord", file);
11098 fputs ("neq", file);
11102 fputs ("nlt", file);
11106 fputs ("nle", file);
11109 fputs ("ord", file);
11112 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11118 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11119 if (ASSEMBLER_DIALECT == ASM_ATT)
11121 switch (GET_MODE (x))
11123 case HImode: putc ('w', file); break;
11125 case SFmode: putc ('l', file); break;
11127 case DFmode: putc ('q', file); break;
11128 default: gcc_unreachable ();
11135 if (!COMPARISON_P (x))
11137 output_operand_lossage ("operand is neither a constant nor a "
11138 "condition code, invalid operand code "
11142 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
11145 if (!COMPARISON_P (x))
11147 output_operand_lossage ("operand is neither a constant nor a "
11148 "condition code, invalid operand code "
11152 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11153 if (ASSEMBLER_DIALECT == ASM_ATT)
11156 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
11159 /* Like above, but reverse condition */
11161 /* Check to see if argument to %c is really a constant
11162 and not a condition code which needs to be reversed. */
11163 if (!COMPARISON_P (x))
11165 output_operand_lossage ("operand is neither a constant nor a "
11166 "condition code, invalid operand "
11170 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
11173 if (!COMPARISON_P (x))
11175 output_operand_lossage ("operand is neither a constant nor a "
11176 "condition code, invalid operand "
11180 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
11181 if (ASSEMBLER_DIALECT == ASM_ATT)
11184 put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
11188 /* It doesn't actually matter what mode we use here, as we're
11189 only going to use this for printing. */
11190 x = adjust_address_nv (x, DImode, 8);
11198 || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
11201 x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
11204 int pred_val = INTVAL (XEXP (x, 0));
11206 if (pred_val < REG_BR_PROB_BASE * 45 / 100
11207 || pred_val > REG_BR_PROB_BASE * 55 / 100)
11209 int taken = pred_val > REG_BR_PROB_BASE / 2;
11210 int cputaken = final_forward_branch_p (current_output_insn) == 0;
11212 /* Emit hints only in the case default branch prediction
11213 heuristics would fail. */
11214 if (taken != cputaken)
11216 /* We use 3e (DS) prefix for taken branches and
11217 2e (CS) prefix for not taken branches. */
11219 fputs ("ds ; ", file);
11221 fputs ("cs ; ", file);
11229 switch (GET_CODE (x))
11232 fputs ("neq", file);
11235 fputs ("eq", file);
11239 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
11243 fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
11247 fputs ("le", file);
11251 fputs ("lt", file);
11254 fputs ("unord", file);
11257 fputs ("ord", file);
11260 fputs ("ueq", file);
11263 fputs ("nlt", file);
11266 fputs ("nle", file);
11269 fputs ("ule", file);
11272 fputs ("ult", file);
11275 fputs ("une", file);
11278 output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
11284 #if TARGET_MACHO || !HAVE_AS_IX86_REP_LOCK_PREFIX
11290 output_operand_lossage ("invalid operand code '%c'", code);
11295 print_reg (x, code, file);
11297 else if (MEM_P (x))
11299 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
11300 if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
11301 && GET_MODE (x) != BLKmode)
11304 switch (GET_MODE_SIZE (GET_MODE (x)))
11306 case 1: size = "BYTE"; break;
11307 case 2: size = "WORD"; break;
11308 case 4: size = "DWORD"; break;
11309 case 8: size = "QWORD"; break;
11310 case 12: size = "TBYTE"; break;
11312 if (GET_MODE (x) == XFmode)
11317 case 32: size = "YMMWORD"; break;
11319 gcc_unreachable ();
11322 /* Check for explicit size override (codes 'b', 'w' and 'k') */
11325 else if (code == 'w')
11327 else if (code == 'k')
11330 fputs (size, file);
11331 fputs (" PTR ", file);
11335 /* Avoid (%rip) for call operands. */
11336 if (CONSTANT_ADDRESS_P (x) && code == 'P'
11337 && !CONST_INT_P (x))
11338 output_addr_const (file, x);
11339 else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
11340 output_operand_lossage ("invalid constraints for operand");
11342 output_address (x);
11345 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
11350 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11351 REAL_VALUE_TO_TARGET_SINGLE (r, l);
11353 if (ASSEMBLER_DIALECT == ASM_ATT)
11355 fprintf (file, "0x%08lx", (long unsigned int) l);
11358 /* These float cases don't actually occur as immediate operands. */
11359 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
11363 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11364 fprintf (file, "%s", dstr);
11367 else if (GET_CODE (x) == CONST_DOUBLE
11368 && GET_MODE (x) == XFmode)
11372 real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
11373 fprintf (file, "%s", dstr);
11378 /* We have patterns that allow zero sets of memory, for instance.
11379 In 64-bit mode, we should probably support all 8-byte vectors,
11380 since we can in fact encode that into an immediate. */
11381 if (GET_CODE (x) == CONST_VECTOR)
11383 gcc_assert (x == CONST0_RTX (GET_MODE (x)));
11389 if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
11391 if (ASSEMBLER_DIALECT == ASM_ATT)
11394 else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
11395 || GET_CODE (x) == LABEL_REF)
11397 if (ASSEMBLER_DIALECT == ASM_ATT)
11400 fputs ("OFFSET FLAT:", file);
11403 if (CONST_INT_P (x))
11404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
11406 output_pic_addr_const (file, x, code);
11408 output_addr_const (file, x);
11412 /* Print a memory operand whose address is ADDR. */
11415 print_operand_address (FILE *file, rtx addr)
11417 struct ix86_address parts;
11418 rtx base, index, disp;
11420 int ok = ix86_decompose_address (addr, &parts);
11425 index = parts.index;
11427 scale = parts.scale;
11435 if (ASSEMBLER_DIALECT == ASM_ATT)
11437 fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
11440 gcc_unreachable ();
11443 /* Use one byte shorter RIP relative addressing for 64bit mode. */
11444 if (TARGET_64BIT && !base && !index)
11448 if (GET_CODE (disp) == CONST
11449 && GET_CODE (XEXP (disp, 0)) == PLUS
11450 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11451 symbol = XEXP (XEXP (disp, 0), 0);
11453 if (GET_CODE (symbol) == LABEL_REF
11454 || (GET_CODE (symbol) == SYMBOL_REF
11455 && SYMBOL_REF_TLS_MODEL (symbol) == 0))
11458 if (!base && !index)
11460 /* Displacement only requires special attention. */
11462 if (CONST_INT_P (disp))
11464 if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
11465 fputs ("ds:", file);
11466 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
11469 output_pic_addr_const (file, disp, 0);
11471 output_addr_const (file, disp);
11475 if (ASSEMBLER_DIALECT == ASM_ATT)
11480 output_pic_addr_const (file, disp, 0);
11481 else if (GET_CODE (disp) == LABEL_REF)
11482 output_asm_label (disp);
11484 output_addr_const (file, disp);
11489 print_reg (base, 0, file);
11493 print_reg (index, 0, file);
11495 fprintf (file, ",%d", scale);
11501 rtx offset = NULL_RTX;
11505 /* Pull out the offset of a symbol; print any symbol itself. */
11506 if (GET_CODE (disp) == CONST
11507 && GET_CODE (XEXP (disp, 0)) == PLUS
11508 && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
11510 offset = XEXP (XEXP (disp, 0), 1);
11511 disp = gen_rtx_CONST (VOIDmode,
11512 XEXP (XEXP (disp, 0), 0));
11516 output_pic_addr_const (file, disp, 0);
11517 else if (GET_CODE (disp) == LABEL_REF)
11518 output_asm_label (disp);
11519 else if (CONST_INT_P (disp))
11522 output_addr_const (file, disp);
11528 print_reg (base, 0, file);
11531 if (INTVAL (offset) >= 0)
11533 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11537 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
11544 print_reg (index, 0, file);
11546 fprintf (file, "*%d", scale);
11554 output_addr_const_extra (FILE *file, rtx x)
11558 if (GET_CODE (x) != UNSPEC)
11561 op = XVECEXP (x, 0, 0);
11562 switch (XINT (x, 1))
11564 case UNSPEC_GOTTPOFF:
11565 output_addr_const (file, op);
11566 /* FIXME: This might be @TPOFF in Sun ld. */
11567 fputs ("@GOTTPOFF", file);
11570 output_addr_const (file, op);
11571 fputs ("@TPOFF", file);
11573 case UNSPEC_NTPOFF:
11574 output_addr_const (file, op);
11576 fputs ("@TPOFF", file);
11578 fputs ("@NTPOFF", file);
11580 case UNSPEC_DTPOFF:
11581 output_addr_const (file, op);
11582 fputs ("@DTPOFF", file);
11584 case UNSPEC_GOTNTPOFF:
11585 output_addr_const (file, op);
11587 fputs (ASSEMBLER_DIALECT == ASM_ATT ?
11588 "@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
11590 fputs ("@GOTNTPOFF", file);
11592 case UNSPEC_INDNTPOFF:
11593 output_addr_const (file, op);
11594 fputs ("@INDNTPOFF", file);
11597 case UNSPEC_MACHOPIC_OFFSET:
11598 output_addr_const (file, op);
11600 machopic_output_function_base_name (file);
11611 /* Split one or more DImode RTL references into pairs of SImode
11612 references. The RTL can be REG, offsettable MEM, integer constant, or
11613 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11614 split and "num" is its length. lo_half and hi_half are output arrays
11615 that parallel "operands". */
11618 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11622 rtx op = operands[num];
11624 /* simplify_subreg refuse to split volatile memory addresses,
11625 but we still have to handle it. */
11628 lo_half[num] = adjust_address (op, SImode, 0);
11629 hi_half[num] = adjust_address (op, SImode, 4);
11633 lo_half[num] = simplify_gen_subreg (SImode, op,
11634 GET_MODE (op) == VOIDmode
11635 ? DImode : GET_MODE (op), 0);
11636 hi_half[num] = simplify_gen_subreg (SImode, op,
11637 GET_MODE (op) == VOIDmode
11638 ? DImode : GET_MODE (op), 4);
11642 /* Split one or more TImode RTL references into pairs of DImode
11643 references. The RTL can be REG, offsettable MEM, integer constant, or
11644 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
11645 split and "num" is its length. lo_half and hi_half are output arrays
11646 that parallel "operands". */
11649 split_ti (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
11653 rtx op = operands[num];
11655 /* simplify_subreg refuse to split volatile memory addresses, but we
11656 still have to handle it. */
11659 lo_half[num] = adjust_address (op, DImode, 0);
11660 hi_half[num] = adjust_address (op, DImode, 8);
11664 lo_half[num] = simplify_gen_subreg (DImode, op, TImode, 0);
11665 hi_half[num] = simplify_gen_subreg (DImode, op, TImode, 8);
11670 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
11671 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
11672 is the expression of the binary operation. The output may either be
11673 emitted here, or returned to the caller, like all output_* functions.
11675 There is no guarantee that the operands are the same mode, as they
11676 might be within FLOAT or FLOAT_EXTEND expressions. */
11678 #ifndef SYSV386_COMPAT
11679 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
11680 wants to fix the assemblers because that causes incompatibility
11681 with gcc. No-one wants to fix gcc because that causes
11682 incompatibility with assemblers... You can use the option of
11683 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
11684 #define SYSV386_COMPAT 1
11688 output_387_binary_op (rtx insn, rtx *operands)
11690 static char buf[40];
11693 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]);
11695 #ifdef ENABLE_CHECKING
11696 /* Even if we do not want to check the inputs, this documents input
11697 constraints. Which helps in understanding the following code. */
11698 if (STACK_REG_P (operands[0])
11699 && ((REG_P (operands[1])
11700 && REGNO (operands[0]) == REGNO (operands[1])
11701 && (STACK_REG_P (operands[2]) || MEM_P (operands[2])))
11702 || (REG_P (operands[2])
11703 && REGNO (operands[0]) == REGNO (operands[2])
11704 && (STACK_REG_P (operands[1]) || MEM_P (operands[1]))))
11705 && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2])))
11708 gcc_assert (is_sse);
11711 switch (GET_CODE (operands[3]))
11714 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11715 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11723 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11724 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11732 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11733 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11741 if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
11742 || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT)
11750 gcc_unreachable ();
11757 strcpy (buf, ssep);
11758 if (GET_MODE (operands[0]) == SFmode)
11759 strcat (buf, "ss\t{%2, %1, %0|%0, %1, %2}");
11761 strcat (buf, "sd\t{%2, %1, %0|%0, %1, %2}");
11765 strcpy (buf, ssep + 1);
11766 if (GET_MODE (operands[0]) == SFmode)
11767 strcat (buf, "ss\t{%2, %0|%0, %2}");
11769 strcat (buf, "sd\t{%2, %0|%0, %2}");
11775 switch (GET_CODE (operands[3]))
11779 if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2]))
11781 rtx temp = operands[2];
11782 operands[2] = operands[1];
11783 operands[1] = temp;
11786 /* know operands[0] == operands[1]. */
11788 if (MEM_P (operands[2]))
11794 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11796 if (STACK_TOP_P (operands[0]))
11797 /* How is it that we are storing to a dead operand[2]?
11798 Well, presumably operands[1] is dead too. We can't
11799 store the result to st(0) as st(0) gets popped on this
11800 instruction. Instead store to operands[2] (which I
11801 think has to be st(1)). st(1) will be popped later.
11802 gcc <= 2.8.1 didn't have this check and generated
11803 assembly code that the Unixware assembler rejected. */
11804 p = "p\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11806 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11810 if (STACK_TOP_P (operands[0]))
11811 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11813 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11818 if (MEM_P (operands[1]))
11824 if (MEM_P (operands[2]))
11830 if (find_regno_note (insn, REG_DEAD, REGNO (operands[2])))
11833 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
11834 derived assemblers, confusingly reverse the direction of
11835 the operation for fsub{r} and fdiv{r} when the
11836 destination register is not st(0). The Intel assembler
11837 doesn't have this brain damage. Read !SYSV386_COMPAT to
11838 figure out what the hardware really does. */
11839 if (STACK_TOP_P (operands[0]))
11840 p = "{p\t%0, %2|rp\t%2, %0}";
11842 p = "{rp\t%2, %0|p\t%0, %2}";
11844 if (STACK_TOP_P (operands[0]))
11845 /* As above for fmul/fadd, we can't store to st(0). */
11846 p = "rp\t{%0, %2|%2, %0}"; /* st(1) = st(0) op st(1); pop */
11848 p = "p\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0); pop */
11853 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
11856 if (STACK_TOP_P (operands[0]))
11857 p = "{rp\t%0, %1|p\t%1, %0}";
11859 p = "{p\t%1, %0|rp\t%0, %1}";
11861 if (STACK_TOP_P (operands[0]))
11862 p = "p\t{%0, %1|%1, %0}"; /* st(1) = st(1) op st(0); pop */
11864 p = "rp\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2); pop */
11869 if (STACK_TOP_P (operands[0]))
11871 if (STACK_TOP_P (operands[1]))
11872 p = "\t{%y2, %0|%0, %y2}"; /* st(0) = st(0) op st(r2) */
11874 p = "r\t{%y1, %0|%0, %y1}"; /* st(0) = st(r1) op st(0) */
11877 else if (STACK_TOP_P (operands[1]))
11880 p = "{\t%1, %0|r\t%0, %1}";
11882 p = "r\t{%1, %0|%0, %1}"; /* st(r2) = st(0) op st(r2) */
11888 p = "{r\t%2, %0|\t%0, %2}";
11890 p = "\t{%2, %0|%0, %2}"; /* st(r1) = st(r1) op st(0) */
11896 gcc_unreachable ();
11903 /* Return needed mode for entity in optimize_mode_switching pass. */
11906 ix86_mode_needed (int entity, rtx insn)
11908 enum attr_i387_cw mode;
11910 /* The mode UNINITIALIZED is used to store control word after a
11911 function call or ASM pattern. The mode ANY specify that function
11912 has no requirements on the control word and make no changes in the
11913 bits we are interested in. */
11916 || (NONJUMP_INSN_P (insn)
11917 && (asm_noperands (PATTERN (insn)) >= 0
11918 || GET_CODE (PATTERN (insn)) == ASM_INPUT)))
11919 return I387_CW_UNINITIALIZED;
11921 if (recog_memoized (insn) < 0)
11922 return I387_CW_ANY;
11924 mode = get_attr_i387_cw (insn);
11929 if (mode == I387_CW_TRUNC)
11934 if (mode == I387_CW_FLOOR)
11939 if (mode == I387_CW_CEIL)
11944 if (mode == I387_CW_MASK_PM)
11949 gcc_unreachable ();
11952 return I387_CW_ANY;
11955 /* Output code to initialize control word copies used by trunc?f?i and
11956 rounding patterns. CURRENT_MODE is set to current control word,
11957 while NEW_MODE is set to new control word. */
11960 emit_i387_cw_initialization (int mode)
11962 rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED);
11965 enum ix86_stack_slot slot;
11967 rtx reg = gen_reg_rtx (HImode);
11969 emit_insn (gen_x86_fnstcw_1 (stored_mode));
11970 emit_move_insn (reg, copy_rtx (stored_mode));
11972 if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
11973 || optimize_function_for_size_p (cfun))
11977 case I387_CW_TRUNC:
11978 /* round toward zero (truncate) */
11979 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00)));
11980 slot = SLOT_CW_TRUNC;
11983 case I387_CW_FLOOR:
11984 /* round down toward -oo */
11985 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11986 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400)));
11987 slot = SLOT_CW_FLOOR;
11991 /* round up toward +oo */
11992 emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00)));
11993 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800)));
11994 slot = SLOT_CW_CEIL;
11997 case I387_CW_MASK_PM:
11998 /* mask precision exception for nearbyint() */
11999 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12000 slot = SLOT_CW_MASK_PM;
12004 gcc_unreachable ();
12011 case I387_CW_TRUNC:
12012 /* round toward zero (truncate) */
12013 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
12014 slot = SLOT_CW_TRUNC;
12017 case I387_CW_FLOOR:
12018 /* round down toward -oo */
12019 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
12020 slot = SLOT_CW_FLOOR;
12024 /* round up toward +oo */
12025 emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
12026 slot = SLOT_CW_CEIL;
12029 case I387_CW_MASK_PM:
12030 /* mask precision exception for nearbyint() */
12031 emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020)));
12032 slot = SLOT_CW_MASK_PM;
12036 gcc_unreachable ();
12040 gcc_assert (slot < MAX_386_STACK_LOCALS);
12042 new_mode = assign_386_stack_local (HImode, slot);
12043 emit_move_insn (new_mode, reg);
12046 /* Output code for INSN to convert a float to a signed int. OPERANDS
12047 are the insn operands. The output may be [HSD]Imode and the input
12048 operand may be [SDX]Fmode. */
12051 output_fix_trunc (rtx insn, rtx *operands, int fisttp)
12053 int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12054 int dimode_p = GET_MODE (operands[0]) == DImode;
12055 int round_mode = get_attr_i387_cw (insn);
12057 /* Jump through a hoop or two for DImode, since the hardware has no
12058 non-popping instruction. We used to do this a different way, but
12059 that was somewhat fragile and broke with post-reload splitters. */
12060 if ((dimode_p || fisttp) && !stack_top_dies)
12061 output_asm_insn ("fld\t%y1", operands);
12063 gcc_assert (STACK_TOP_P (operands[1]));
12064 gcc_assert (MEM_P (operands[0]));
12065 gcc_assert (GET_MODE (operands[1]) != TFmode);
12068 output_asm_insn ("fisttp%z0\t%0", operands);
12071 if (round_mode != I387_CW_ANY)
12072 output_asm_insn ("fldcw\t%3", operands);
12073 if (stack_top_dies || dimode_p)
12074 output_asm_insn ("fistp%z0\t%0", operands);
12076 output_asm_insn ("fist%z0\t%0", operands);
12077 if (round_mode != I387_CW_ANY)
12078 output_asm_insn ("fldcw\t%2", operands);
12084 /* Output code for x87 ffreep insn. The OPNO argument, which may only
12085 have the values zero or one, indicates the ffreep insn's operand
12086 from the OPERANDS array. */
12088 static const char *
12089 output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno)
12091 if (TARGET_USE_FFREEP)
12092 #ifdef HAVE_AS_IX86_FFREEP
12093 return opno ? "ffreep\t%y1" : "ffreep\t%y0";
12096 static char retval[32];
12097 int regno = REGNO (operands[opno]);
12099 gcc_assert (FP_REGNO_P (regno));
12101 regno -= FIRST_STACK_REG;
12103 snprintf (retval, sizeof (retval), ASM_SHORT "0xc%ddf", regno);
12108 return opno ? "fstp\t%y1" : "fstp\t%y0";
12112 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
12113 should be used. UNORDERED_P is true when fucom should be used. */
12116 output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p)
12118 int stack_top_dies;
12119 rtx cmp_op0, cmp_op1;
12120 int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]);
12124 cmp_op0 = operands[0];
12125 cmp_op1 = operands[1];
12129 cmp_op0 = operands[1];
12130 cmp_op1 = operands[2];
12135 static const char ucomiss[] = "vucomiss\t{%1, %0|%0, %1}";
12136 static const char ucomisd[] = "vucomisd\t{%1, %0|%0, %1}";
12137 static const char comiss[] = "vcomiss\t{%1, %0|%0, %1}";
12138 static const char comisd[] = "vcomisd\t{%1, %0|%0, %1}";
12140 if (GET_MODE (operands[0]) == SFmode)
12142 return &ucomiss[TARGET_AVX ? 0 : 1];
12144 return &comiss[TARGET_AVX ? 0 : 1];
12147 return &ucomisd[TARGET_AVX ? 0 : 1];
12149 return &comisd[TARGET_AVX ? 0 : 1];
12152 gcc_assert (STACK_TOP_P (cmp_op0));
12154 stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0;
12156 if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1)))
12158 if (stack_top_dies)
12160 output_asm_insn ("ftst\n\tfnstsw\t%0", operands);
12161 return output_387_ffreep (operands, 1);
12164 return "ftst\n\tfnstsw\t%0";
12167 if (STACK_REG_P (cmp_op1)
12169 && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1))
12170 && REGNO (cmp_op1) != FIRST_STACK_REG)
12172 /* If both the top of the 387 stack dies, and the other operand
12173 is also a stack register that dies, then this must be a
12174 `fcompp' float compare */
12178 /* There is no double popping fcomi variant. Fortunately,
12179 eflags is immune from the fstp's cc clobbering. */
12181 output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands);
12183 output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands);
12184 return output_387_ffreep (operands, 0);
12189 return "fucompp\n\tfnstsw\t%0";
12191 return "fcompp\n\tfnstsw\t%0";
12196 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
12198 static const char * const alt[16] =
12200 "fcom%z2\t%y2\n\tfnstsw\t%0",
12201 "fcomp%z2\t%y2\n\tfnstsw\t%0",
12202 "fucom%z2\t%y2\n\tfnstsw\t%0",
12203 "fucomp%z2\t%y2\n\tfnstsw\t%0",
12205 "ficom%z2\t%y2\n\tfnstsw\t%0",
12206 "ficomp%z2\t%y2\n\tfnstsw\t%0",
12210 "fcomi\t{%y1, %0|%0, %y1}",
12211 "fcomip\t{%y1, %0|%0, %y1}",
12212 "fucomi\t{%y1, %0|%0, %y1}",
12213 "fucomip\t{%y1, %0|%0, %y1}",
12224 mask = eflags_p << 3;
12225 mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2;
12226 mask |= unordered_p << 1;
12227 mask |= stack_top_dies;
12229 gcc_assert (mask < 16);
12238 ix86_output_addr_vec_elt (FILE *file, int value)
12240 const char *directive = ASM_LONG;
12244 directive = ASM_QUAD;
12246 gcc_assert (!TARGET_64BIT);
12249 fprintf (file, "%s%s%d\n", directive, LPREFIX, value);
12253 ix86_output_addr_diff_elt (FILE *file, int value, int rel)
12255 const char *directive = ASM_LONG;
12258 if (TARGET_64BIT && CASE_VECTOR_MODE == DImode)
12259 directive = ASM_QUAD;
12261 gcc_assert (!TARGET_64BIT);
12263 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
12264 if (TARGET_64BIT || TARGET_VXWORKS_RTP)
12265 fprintf (file, "%s%s%d-%s%d\n",
12266 directive, LPREFIX, value, LPREFIX, rel);
12267 else if (HAVE_AS_GOTOFF_IN_DATA)
12268 fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
12270 else if (TARGET_MACHO)
12272 fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
12273 machopic_output_function_base_name (file);
12274 fprintf(file, "\n");
12278 asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
12279 ASM_LONG, GOT_SYMBOL_NAME, LPREFIX, value);
12282 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
12286 ix86_expand_clear (rtx dest)
12290 /* We play register width games, which are only valid after reload. */
12291 gcc_assert (reload_completed);
12293 /* Avoid HImode and its attendant prefix byte. */
12294 if (GET_MODE_SIZE (GET_MODE (dest)) < 4)
12295 dest = gen_rtx_REG (SImode, REGNO (dest));
12296 tmp = gen_rtx_SET (VOIDmode, dest, const0_rtx);
12298 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
12299 if (reload_completed && (!TARGET_USE_MOV0 || optimize_insn_for_speed_p ()))
12301 rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12302 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob));
12308 /* X is an unchanging MEM. If it is a constant pool reference, return
12309 the constant pool rtx, else NULL. */
12312 maybe_get_pool_constant (rtx x)
12314 x = ix86_delegitimize_address (XEXP (x, 0));
12316 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
12317 return get_pool_constant (x);
12323 ix86_expand_move (enum machine_mode mode, rtx operands[])
12326 enum tls_model model;
12331 if (GET_CODE (op1) == SYMBOL_REF)
12333 model = SYMBOL_REF_TLS_MODEL (op1);
12336 op1 = legitimize_tls_address (op1, model, true);
12337 op1 = force_operand (op1, op0);
12341 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12342 && SYMBOL_REF_DLLIMPORT_P (op1))
12343 op1 = legitimize_dllimport_symbol (op1, false);
12345 else if (GET_CODE (op1) == CONST
12346 && GET_CODE (XEXP (op1, 0)) == PLUS
12347 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF)
12349 rtx addend = XEXP (XEXP (op1, 0), 1);
12350 rtx symbol = XEXP (XEXP (op1, 0), 0);
12353 model = SYMBOL_REF_TLS_MODEL (symbol);
12355 tmp = legitimize_tls_address (symbol, model, true);
12356 else if (TARGET_DLLIMPORT_DECL_ATTRIBUTES
12357 && SYMBOL_REF_DLLIMPORT_P (symbol))
12358 tmp = legitimize_dllimport_symbol (symbol, true);
12362 tmp = force_operand (tmp, NULL);
12363 tmp = expand_simple_binop (Pmode, PLUS, tmp, addend,
12364 op0, 1, OPTAB_DIRECT);
12370 if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode))
12372 if (TARGET_MACHO && !TARGET_64BIT)
12377 rtx temp = ((reload_in_progress
12378 || ((op0 && REG_P (op0))
12380 ? op0 : gen_reg_rtx (Pmode));
12381 op1 = machopic_indirect_data_reference (op1, temp);
12382 op1 = machopic_legitimize_pic_address (op1, mode,
12383 temp == op1 ? 0 : temp);
12385 else if (MACHOPIC_INDIRECT)
12386 op1 = machopic_indirect_data_reference (op1, 0);
12394 op1 = force_reg (Pmode, op1);
12395 else if (!TARGET_64BIT || !x86_64_movabs_operand (op1, Pmode))
12397 rtx reg = !can_create_pseudo_p () ? op0 : NULL_RTX;
12398 op1 = legitimize_pic_address (op1, reg);
12407 && (PUSH_ROUNDING (GET_MODE_SIZE (mode)) != GET_MODE_SIZE (mode)
12408 || !push_operand (op0, mode))
12410 op1 = force_reg (mode, op1);
12412 if (push_operand (op0, mode)
12413 && ! general_no_elim_operand (op1, mode))
12414 op1 = copy_to_mode_reg (mode, op1);
12416 /* Force large constants in 64bit compilation into register
12417 to get them CSEed. */
12418 if (can_create_pseudo_p ()
12419 && (mode == DImode) && TARGET_64BIT
12420 && immediate_operand (op1, mode)
12421 && !x86_64_zext_immediate_operand (op1, VOIDmode)
12422 && !register_operand (op0, mode)
12424 op1 = copy_to_mode_reg (mode, op1);
12426 if (can_create_pseudo_p ()
12427 && FLOAT_MODE_P (mode)
12428 && GET_CODE (op1) == CONST_DOUBLE)
12430 /* If we are loading a floating point constant to a register,
12431 force the value to memory now, since we'll get better code
12432 out the back end. */
12434 op1 = validize_mem (force_const_mem (mode, op1));
12435 if (!register_operand (op0, mode))
12437 rtx temp = gen_reg_rtx (mode);
12438 emit_insn (gen_rtx_SET (VOIDmode, temp, op1));
12439 emit_move_insn (op0, temp);
12445 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12449 ix86_expand_vector_move (enum machine_mode mode, rtx operands[])
12451 rtx op0 = operands[0], op1 = operands[1];
12452 unsigned int align = GET_MODE_ALIGNMENT (mode);
12454 /* Force constants other than zero into memory. We do not know how
12455 the instructions used to build constants modify the upper 64 bits
12456 of the register, once we have that information we may be able
12457 to handle some of them more efficiently. */
12458 if (can_create_pseudo_p ()
12459 && register_operand (op0, mode)
12460 && (CONSTANT_P (op1)
12461 || (GET_CODE (op1) == SUBREG
12462 && CONSTANT_P (SUBREG_REG (op1))))
12463 && standard_sse_constant_p (op1) <= 0)
12464 op1 = validize_mem (force_const_mem (mode, op1));
12466 /* We need to check memory alignment for SSE mode since attribute
12467 can make operands unaligned. */
12468 if (can_create_pseudo_p ()
12469 && SSE_REG_MODE_P (mode)
12470 && ((MEM_P (op0) && (MEM_ALIGN (op0) < align))
12471 || (MEM_P (op1) && (MEM_ALIGN (op1) < align))))
12475 /* ix86_expand_vector_move_misalign() does not like constants ... */
12476 if (CONSTANT_P (op1)
12477 || (GET_CODE (op1) == SUBREG
12478 && CONSTANT_P (SUBREG_REG (op1))))
12479 op1 = validize_mem (force_const_mem (mode, op1));
12481 /* ... nor both arguments in memory. */
12482 if (!register_operand (op0, mode)
12483 && !register_operand (op1, mode))
12484 op1 = force_reg (mode, op1);
12486 tmp[0] = op0; tmp[1] = op1;
12487 ix86_expand_vector_move_misalign (mode, tmp);
12491 /* Make operand1 a register if it isn't already. */
12492 if (can_create_pseudo_p ()
12493 && !register_operand (op0, mode)
12494 && !register_operand (op1, mode))
12496 emit_move_insn (op0, force_reg (GET_MODE (op0), op1));
12500 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
12503 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
12504 straight to ix86_expand_vector_move. */
12505 /* Code generation for scalar reg-reg moves of single and double precision data:
12506 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
12510 if (x86_sse_partial_reg_dependency == true)
12515 Code generation for scalar loads of double precision data:
12516 if (x86_sse_split_regs == true)
12517 movlpd mem, reg (gas syntax)
12521 Code generation for unaligned packed loads of single precision data
12522 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
12523 if (x86_sse_unaligned_move_optimal)
12526 if (x86_sse_partial_reg_dependency == true)
12538 Code generation for unaligned packed loads of double precision data
12539 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
12540 if (x86_sse_unaligned_move_optimal)
12543 if (x86_sse_split_regs == true)
12556 ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[])
12565 switch (GET_MODE_CLASS (mode))
12567 case MODE_VECTOR_INT:
12569 switch (GET_MODE_SIZE (mode))
12572 op0 = gen_lowpart (V16QImode, op0);
12573 op1 = gen_lowpart (V16QImode, op1);
12574 emit_insn (gen_avx_movdqu (op0, op1));
12577 op0 = gen_lowpart (V32QImode, op0);
12578 op1 = gen_lowpart (V32QImode, op1);
12579 emit_insn (gen_avx_movdqu256 (op0, op1));
12582 gcc_unreachable ();
12585 case MODE_VECTOR_FLOAT:
12586 op0 = gen_lowpart (mode, op0);
12587 op1 = gen_lowpart (mode, op1);
12592 emit_insn (gen_avx_movups (op0, op1));
12595 emit_insn (gen_avx_movups256 (op0, op1));
12598 emit_insn (gen_avx_movupd (op0, op1));
12601 emit_insn (gen_avx_movupd256 (op0, op1));
12604 gcc_unreachable ();
12609 gcc_unreachable ();
12617 /* If we're optimizing for size, movups is the smallest. */
12618 if (optimize_insn_for_size_p ())
12620 op0 = gen_lowpart (V4SFmode, op0);
12621 op1 = gen_lowpart (V4SFmode, op1);
12622 emit_insn (gen_sse_movups (op0, op1));
12626 /* ??? If we have typed data, then it would appear that using
12627 movdqu is the only way to get unaligned data loaded with
12629 if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12631 op0 = gen_lowpart (V16QImode, op0);
12632 op1 = gen_lowpart (V16QImode, op1);
12633 emit_insn (gen_sse2_movdqu (op0, op1));
12637 if (TARGET_SSE2 && mode == V2DFmode)
12641 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12643 op0 = gen_lowpart (V2DFmode, op0);
12644 op1 = gen_lowpart (V2DFmode, op1);
12645 emit_insn (gen_sse2_movupd (op0, op1));
12649 /* When SSE registers are split into halves, we can avoid
12650 writing to the top half twice. */
12651 if (TARGET_SSE_SPLIT_REGS)
12653 emit_clobber (op0);
12658 /* ??? Not sure about the best option for the Intel chips.
12659 The following would seem to satisfy; the register is
12660 entirely cleared, breaking the dependency chain. We
12661 then store to the upper half, with a dependency depth
12662 of one. A rumor has it that Intel recommends two movsd
12663 followed by an unpacklpd, but this is unconfirmed. And
12664 given that the dependency depth of the unpacklpd would
12665 still be one, I'm not sure why this would be better. */
12666 zero = CONST0_RTX (V2DFmode);
12669 m = adjust_address (op1, DFmode, 0);
12670 emit_insn (gen_sse2_loadlpd (op0, zero, m));
12671 m = adjust_address (op1, DFmode, 8);
12672 emit_insn (gen_sse2_loadhpd (op0, op0, m));
12676 if (TARGET_SSE_UNALIGNED_MOVE_OPTIMAL)
12678 op0 = gen_lowpart (V4SFmode, op0);
12679 op1 = gen_lowpart (V4SFmode, op1);
12680 emit_insn (gen_sse_movups (op0, op1));
12684 if (TARGET_SSE_PARTIAL_REG_DEPENDENCY)
12685 emit_move_insn (op0, CONST0_RTX (mode));
12687 emit_clobber (op0);
12689 if (mode != V4SFmode)
12690 op0 = gen_lowpart (V4SFmode, op0);
12691 m = adjust_address (op1, V2SFmode, 0);
12692 emit_insn (gen_sse_loadlps (op0, op0, m));
12693 m = adjust_address (op1, V2SFmode, 8);
12694 emit_insn (gen_sse_loadhps (op0, op0, m));
12697 else if (MEM_P (op0))
12699 /* If we're optimizing for size, movups is the smallest. */
12700 if (optimize_insn_for_size_p ())
12702 op0 = gen_lowpart (V4SFmode, op0);
12703 op1 = gen_lowpart (V4SFmode, op1);
12704 emit_insn (gen_sse_movups (op0, op1));
12708 /* ??? Similar to above, only less clear because of quote
12709 typeless stores unquote. */
12710 if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES
12711 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
12713 op0 = gen_lowpart (V16QImode, op0);
12714 op1 = gen_lowpart (V16QImode, op1);
12715 emit_insn (gen_sse2_movdqu (op0, op1));
12719 if (TARGET_SSE2 && mode == V2DFmode)
12721 m = adjust_address (op0, DFmode, 0);
12722 emit_insn (gen_sse2_storelpd (m, op1));
12723 m = adjust_address (op0, DFmode, 8);
12724 emit_insn (gen_sse2_storehpd (m, op1));
12728 if (mode != V4SFmode)
12729 op1 = gen_lowpart (V4SFmode, op1);
12730 m = adjust_address (op0, V2SFmode, 0);
12731 emit_insn (gen_sse_storelps (m, op1));
12732 m = adjust_address (op0, V2SFmode, 8);
12733 emit_insn (gen_sse_storehps (m, op1));
12737 gcc_unreachable ();
12740 /* Expand a push in MODE. This is some mode for which we do not support
12741 proper push instructions, at least from the registers that we expect
12742 the value to live in. */
12745 ix86_expand_push (enum machine_mode mode, rtx x)
12749 tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx,
12750 GEN_INT (-GET_MODE_SIZE (mode)),
12751 stack_pointer_rtx, 1, OPTAB_DIRECT);
12752 if (tmp != stack_pointer_rtx)
12753 emit_move_insn (stack_pointer_rtx, tmp);
12755 tmp = gen_rtx_MEM (mode, stack_pointer_rtx);
12757 /* When we push an operand onto stack, it has to be aligned at least
12758 at the function argument boundary. However since we don't have
12759 the argument type, we can't determine the actual argument
12761 emit_move_insn (tmp, x);
12764 /* Helper function of ix86_fixup_binary_operands to canonicalize
12765 operand order. Returns true if the operands should be swapped. */
12768 ix86_swap_binary_operands_p (enum rtx_code code, enum machine_mode mode,
12771 rtx dst = operands[0];
12772 rtx src1 = operands[1];
12773 rtx src2 = operands[2];
12775 /* If the operation is not commutative, we can't do anything. */
12776 if (GET_RTX_CLASS (code) != RTX_COMM_ARITH)
12779 /* Highest priority is that src1 should match dst. */
12780 if (rtx_equal_p (dst, src1))
12782 if (rtx_equal_p (dst, src2))
12785 /* Next highest priority is that immediate constants come second. */
12786 if (immediate_operand (src2, mode))
12788 if (immediate_operand (src1, mode))
12791 /* Lowest priority is that memory references should come second. */
12801 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
12802 destination to use for the operation. If different from the true
12803 destination in operands[0], a copy operation will be required. */
12806 ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode,
12809 rtx dst = operands[0];
12810 rtx src1 = operands[1];
12811 rtx src2 = operands[2];
12813 /* Canonicalize operand order. */
12814 if (ix86_swap_binary_operands_p (code, mode, operands))
12818 /* It is invalid to swap operands of different modes. */
12819 gcc_assert (GET_MODE (src1) == GET_MODE (src2));
12826 /* Both source operands cannot be in memory. */
12827 if (MEM_P (src1) && MEM_P (src2))
12829 /* Optimization: Only read from memory once. */
12830 if (rtx_equal_p (src1, src2))
12832 src2 = force_reg (mode, src2);
12836 src2 = force_reg (mode, src2);
12839 /* If the destination is memory, and we do not have matching source
12840 operands, do things in registers. */
12841 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12842 dst = gen_reg_rtx (mode);
12844 /* Source 1 cannot be a constant. */
12845 if (CONSTANT_P (src1))
12846 src1 = force_reg (mode, src1);
12848 /* Source 1 cannot be a non-matching memory. */
12849 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12850 src1 = force_reg (mode, src1);
12852 operands[1] = src1;
12853 operands[2] = src2;
12857 /* Similarly, but assume that the destination has already been
12858 set up properly. */
12861 ix86_fixup_binary_operands_no_copy (enum rtx_code code,
12862 enum machine_mode mode, rtx operands[])
12864 rtx dst = ix86_fixup_binary_operands (code, mode, operands);
12865 gcc_assert (dst == operands[0]);
12868 /* Attempt to expand a binary operator. Make the expansion closer to the
12869 actual machine, then just general_operand, which will allow 3 separate
12870 memory references (one output, two input) in a single insn. */
12873 ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode,
12876 rtx src1, src2, dst, op, clob;
12878 dst = ix86_fixup_binary_operands (code, mode, operands);
12879 src1 = operands[1];
12880 src2 = operands[2];
12882 /* Emit the instruction. */
12884 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2));
12885 if (reload_in_progress)
12887 /* Reload doesn't know about the flags register, and doesn't know that
12888 it doesn't want to clobber it. We can only do this with PLUS. */
12889 gcc_assert (code == PLUS);
12894 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12895 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12898 /* Fix up the destination if needed. */
12899 if (dst != operands[0])
12900 emit_move_insn (operands[0], dst);
12903 /* Return TRUE or FALSE depending on whether the binary operator meets the
12904 appropriate constraints. */
12907 ix86_binary_operator_ok (enum rtx_code code, enum machine_mode mode,
12910 rtx dst = operands[0];
12911 rtx src1 = operands[1];
12912 rtx src2 = operands[2];
12914 /* Both source operands cannot be in memory. */
12915 if (MEM_P (src1) && MEM_P (src2))
12918 /* Canonicalize operand order for commutative operators. */
12919 if (ix86_swap_binary_operands_p (code, mode, operands))
12926 /* If the destination is memory, we must have a matching source operand. */
12927 if (MEM_P (dst) && !rtx_equal_p (dst, src1))
12930 /* Source 1 cannot be a constant. */
12931 if (CONSTANT_P (src1))
12934 /* Source 1 cannot be a non-matching memory. */
12935 if (MEM_P (src1) && !rtx_equal_p (dst, src1))
12941 /* Attempt to expand a unary operator. Make the expansion closer to the
12942 actual machine, then just general_operand, which will allow 2 separate
12943 memory references (one output, one input) in a single insn. */
12946 ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode,
12949 int matching_memory;
12950 rtx src, dst, op, clob;
12955 /* If the destination is memory, and we do not have matching source
12956 operands, do things in registers. */
12957 matching_memory = 0;
12960 if (rtx_equal_p (dst, src))
12961 matching_memory = 1;
12963 dst = gen_reg_rtx (mode);
12966 /* When source operand is memory, destination must match. */
12967 if (MEM_P (src) && !matching_memory)
12968 src = force_reg (mode, src);
12970 /* Emit the instruction. */
12972 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src));
12973 if (reload_in_progress || code == NOT)
12975 /* Reload doesn't know about the flags register, and doesn't know that
12976 it doesn't want to clobber it. */
12977 gcc_assert (code == NOT);
12982 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
12983 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
12986 /* Fix up the destination if needed. */
12987 if (dst != operands[0])
12988 emit_move_insn (operands[0], dst);
12991 /* Return TRUE or FALSE depending on whether the unary operator meets the
12992 appropriate constraints. */
12995 ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12996 enum machine_mode mode ATTRIBUTE_UNUSED,
12997 rtx operands[2] ATTRIBUTE_UNUSED)
12999 /* If one of operands is memory, source and destination must match. */
13000 if ((MEM_P (operands[0])
13001 || MEM_P (operands[1]))
13002 && ! rtx_equal_p (operands[0], operands[1]))
13007 /* Post-reload splitter for converting an SF or DFmode value in an
13008 SSE register into an unsigned SImode. */
13011 ix86_split_convert_uns_si_sse (rtx operands[])
13013 enum machine_mode vecmode;
13014 rtx value, large, zero_or_two31, input, two31, x;
13016 large = operands[1];
13017 zero_or_two31 = operands[2];
13018 input = operands[3];
13019 two31 = operands[4];
13020 vecmode = GET_MODE (large);
13021 value = gen_rtx_REG (vecmode, REGNO (operands[0]));
13023 /* Load up the value into the low element. We must ensure that the other
13024 elements are valid floats -- zero is the easiest such value. */
13027 if (vecmode == V4SFmode)
13028 emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode), input));
13030 emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode), input));
13034 input = gen_rtx_REG (vecmode, REGNO (input));
13035 emit_move_insn (value, CONST0_RTX (vecmode));
13036 if (vecmode == V4SFmode)
13037 emit_insn (gen_sse_movss (value, value, input));
13039 emit_insn (gen_sse2_movsd (value, value, input));
13042 emit_move_insn (large, two31);
13043 emit_move_insn (zero_or_two31, MEM_P (two31) ? large : two31);
13045 x = gen_rtx_fmt_ee (LE, vecmode, large, value);
13046 emit_insn (gen_rtx_SET (VOIDmode, large, x));
13048 x = gen_rtx_AND (vecmode, zero_or_two31, large);
13049 emit_insn (gen_rtx_SET (VOIDmode, zero_or_two31, x));
13051 x = gen_rtx_MINUS (vecmode, value, zero_or_two31);
13052 emit_insn (gen_rtx_SET (VOIDmode, value, x));
13054 large = gen_rtx_REG (V4SImode, REGNO (large));
13055 emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)));
13057 x = gen_rtx_REG (V4SImode, REGNO (value));
13058 if (vecmode == V4SFmode)
13059 emit_insn (gen_sse2_cvttps2dq (x, value));
13061 emit_insn (gen_sse2_cvttpd2dq (x, value));
13064 emit_insn (gen_xorv4si3 (value, value, large));
13067 /* Convert an unsigned DImode value into a DFmode, using only SSE.
13068 Expects the 64-bit DImode to be supplied in a pair of integral
13069 registers. Requires SSE2; will use SSE3 if available. For x86_32,
13070 -mfpmath=sse, !optimize_size only. */
13073 ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
13075 REAL_VALUE_TYPE bias_lo_rvt, bias_hi_rvt;
13076 rtx int_xmm, fp_xmm;
13077 rtx biases, exponents;
13080 int_xmm = gen_reg_rtx (V4SImode);
13081 if (TARGET_INTER_UNIT_MOVES)
13082 emit_insn (gen_movdi_to_sse (int_xmm, input));
13083 else if (TARGET_SSE_SPLIT_REGS)
13085 emit_clobber (int_xmm);
13086 emit_move_insn (gen_lowpart (DImode, int_xmm), input);
13090 x = gen_reg_rtx (V2DImode);
13091 ix86_expand_vector_init_one_nonzero (false, V2DImode, x, input, 0);
13092 emit_move_insn (int_xmm, gen_lowpart (V4SImode, x));
13095 x = gen_rtx_CONST_VECTOR (V4SImode,
13096 gen_rtvec (4, GEN_INT (0x43300000UL),
13097 GEN_INT (0x45300000UL),
13098 const0_rtx, const0_rtx));
13099 exponents = validize_mem (force_const_mem (V4SImode, x));
13101 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
13102 emit_insn (gen_sse2_punpckldq (int_xmm, int_xmm, exponents));
13104 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
13105 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
13106 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
13107 (0x1.0p84 + double(fp_value_hi_xmm)).
13108 Note these exponents differ by 32. */
13110 fp_xmm = copy_to_mode_reg (V2DFmode, gen_lowpart (V2DFmode, int_xmm));
13112 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
13113 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
13114 real_ldexp (&bias_lo_rvt, &dconst1, 52);
13115 real_ldexp (&bias_hi_rvt, &dconst1, 84);
13116 biases = const_double_from_real_value (bias_lo_rvt, DFmode);
13117 x = const_double_from_real_value (bias_hi_rvt, DFmode);
13118 biases = gen_rtx_CONST_VECTOR (V2DFmode, gen_rtvec (2, biases, x));
13119 biases = validize_mem (force_const_mem (V2DFmode, biases));
13120 emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));
13122 /* Add the upper and lower DFmode values together. */
13124 emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
13127 x = copy_to_mode_reg (V2DFmode, fp_xmm);
13128 emit_insn (gen_sse2_unpckhpd (fp_xmm, fp_xmm, fp_xmm));
13129 emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
13132 ix86_expand_vector_extract (false, target, fp_xmm, 0);
13135 /* Not used, but eases macroization of patterns. */
13137 ix86_expand_convert_uns_sixf_sse (rtx target ATTRIBUTE_UNUSED,
13138 rtx input ATTRIBUTE_UNUSED)
13140 gcc_unreachable ();
13143 /* Convert an unsigned SImode value into a DFmode. Only currently used
13144 for SSE, but applicable anywhere. */
13147 ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
13149 REAL_VALUE_TYPE TWO31r;
13152 x = expand_simple_binop (SImode, PLUS, input, GEN_INT (-2147483647 - 1),
13153 NULL, 1, OPTAB_DIRECT);
13155 fp = gen_reg_rtx (DFmode);
13156 emit_insn (gen_floatsidf2 (fp, x));
13158 real_ldexp (&TWO31r, &dconst1, 31);
13159 x = const_double_from_real_value (TWO31r, DFmode);
13161 x = expand_simple_binop (DFmode, PLUS, fp, x, target, 0, OPTAB_DIRECT);
13163 emit_move_insn (target, x);
13166 /* Convert a signed DImode value into a DFmode. Only used for SSE in
13167 32-bit mode; otherwise we have a direct convert instruction. */
13170 ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
13172 REAL_VALUE_TYPE TWO32r;
13173 rtx fp_lo, fp_hi, x;
13175 fp_lo = gen_reg_rtx (DFmode);
13176 fp_hi = gen_reg_rtx (DFmode);
13178 emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode, input)));
13180 real_ldexp (&TWO32r, &dconst1, 32);
13181 x = const_double_from_real_value (TWO32r, DFmode);
13182 fp_hi = expand_simple_binop (DFmode, MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);
13184 ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpart (SImode, input));
13186 x = expand_simple_binop (DFmode, PLUS, fp_hi, fp_lo, target,
13189 emit_move_insn (target, x);
13192 /* Convert an unsigned SImode value into a SFmode, using only SSE.
13193 For x86_32, -mfpmath=sse, !optimize_size only. */
13195 ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
13197 REAL_VALUE_TYPE ONE16r;
13198 rtx fp_hi, fp_lo, int_hi, int_lo, x;
13200 real_ldexp (&ONE16r, &dconst1, 16);
13201 x = const_double_from_real_value (ONE16r, SFmode);
13202 int_lo = expand_simple_binop (SImode, AND, input, GEN_INT(0xffff),
13203 NULL, 0, OPTAB_DIRECT);
13204 int_hi = expand_simple_binop (SImode, LSHIFTRT, input, GEN_INT(16),
13205 NULL, 0, OPTAB_DIRECT);
13206 fp_hi = gen_reg_rtx (SFmode);
13207 fp_lo = gen_reg_rtx (SFmode);
13208 emit_insn (gen_floatsisf2 (fp_hi, int_hi));
13209 emit_insn (gen_floatsisf2 (fp_lo, int_lo));
13210 fp_hi = expand_simple_binop (SFmode, MULT, fp_hi, x, fp_hi,
13212 fp_hi = expand_simple_binop (SFmode, PLUS, fp_hi, fp_lo, target,
13214 if (!rtx_equal_p (target, fp_hi))
13215 emit_move_insn (target, fp_hi);
13218 /* A subroutine of ix86_build_signbit_mask_vector. If VECT is true,
13219 then replicate the value for all elements of the vector
13223 ix86_build_const_vector (enum machine_mode mode, bool vect, rtx value)
13230 v = gen_rtvec (4, value, value, value, value);
13231 return gen_rtx_CONST_VECTOR (V4SImode, v);
13235 v = gen_rtvec (2, value, value);
13236 return gen_rtx_CONST_VECTOR (V2DImode, v);
13240 v = gen_rtvec (4, value, value, value, value);
13242 v = gen_rtvec (4, value, CONST0_RTX (SFmode),
13243 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13244 return gen_rtx_CONST_VECTOR (V4SFmode, v);
13248 v = gen_rtvec (2, value, value);
13250 v = gen_rtvec (2, value, CONST0_RTX (DFmode));
13251 return gen_rtx_CONST_VECTOR (V2DFmode, v);
13254 gcc_unreachable ();
13258 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
13259 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
13260 for an SSE register. If VECT is true, then replicate the mask for
13261 all elements of the vector register. If INVERT is true, then create
13262 a mask excluding the sign bit. */
13265 ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert)
13267 enum machine_mode vec_mode, imode;
13268 HOST_WIDE_INT hi, lo;
13273 /* Find the sign bit, sign extended to 2*HWI. */
13279 vec_mode = (mode == SImode) ? V4SImode : V4SFmode;
13280 lo = 0x80000000, hi = lo < 0;
13286 vec_mode = (mode == DImode) ? V2DImode : V2DFmode;
13287 if (HOST_BITS_PER_WIDE_INT >= 64)
13288 lo = (HOST_WIDE_INT)1 << shift, hi = -1;
13290 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13295 vec_mode = VOIDmode;
13296 if (HOST_BITS_PER_WIDE_INT >= 64)
13299 lo = 0, hi = (HOST_WIDE_INT)1 << shift;
13306 lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT);
13310 lo = ~lo, hi = ~hi;
13316 mask = immed_double_const (lo, hi, imode);
13318 vec = gen_rtvec (2, v, mask);
13319 v = gen_rtx_CONST_VECTOR (V2DImode, vec);
13320 v = copy_to_mode_reg (mode, gen_lowpart (mode, v));
13327 gcc_unreachable ();
13331 lo = ~lo, hi = ~hi;
13333 /* Force this value into the low part of a fp vector constant. */
13334 mask = immed_double_const (lo, hi, imode);
13335 mask = gen_lowpart (mode, mask);
13337 if (vec_mode == VOIDmode)
13338 return force_reg (mode, mask);
13340 v = ix86_build_const_vector (mode, vect, mask);
13341 return force_reg (vec_mode, v);
13344 /* Generate code for floating point ABS or NEG. */
13347 ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode,
13350 rtx mask, set, use, clob, dst, src;
13351 bool use_sse = false;
13352 bool vector_mode = VECTOR_MODE_P (mode);
13353 enum machine_mode elt_mode = mode;
13357 elt_mode = GET_MODE_INNER (mode);
13360 else if (mode == TFmode)
13362 else if (TARGET_SSE_MATH)
13363 use_sse = SSE_FLOAT_MODE_P (mode);
13365 /* NEG and ABS performed with SSE use bitwise mask operations.
13366 Create the appropriate mask now. */
13368 mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS);
13377 set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask);
13378 set = gen_rtx_SET (VOIDmode, dst, set);
13383 set = gen_rtx_fmt_e (code, mode, src);
13384 set = gen_rtx_SET (VOIDmode, dst, set);
13387 use = gen_rtx_USE (VOIDmode, mask);
13388 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
13389 emit_insn (gen_rtx_PARALLEL (VOIDmode,
13390 gen_rtvec (3, set, use, clob)));
13397 /* Expand a copysign operation. Special case operand 0 being a constant. */
13400 ix86_expand_copysign (rtx operands[])
13402 enum machine_mode mode;
13403 rtx dest, op0, op1, mask, nmask;
13405 dest = operands[0];
13409 mode = GET_MODE (dest);
13411 if (GET_CODE (op0) == CONST_DOUBLE)
13413 rtx (*copysign_insn)(rtx, rtx, rtx, rtx);
13415 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)))
13416 op0 = simplify_unary_operation (ABS, mode, op0, mode);
13418 if (mode == SFmode || mode == DFmode)
13420 enum machine_mode vmode;
13422 vmode = mode == SFmode ? V4SFmode : V2DFmode;
13424 if (op0 == CONST0_RTX (mode))
13425 op0 = CONST0_RTX (vmode);
13430 if (mode == SFmode)
13431 v = gen_rtvec (4, op0, CONST0_RTX (SFmode),
13432 CONST0_RTX (SFmode), CONST0_RTX (SFmode));
13434 v = gen_rtvec (2, op0, CONST0_RTX (DFmode));
13436 op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v));
13439 else if (op0 != CONST0_RTX (mode))
13440 op0 = force_reg (mode, op0);
13442 mask = ix86_build_signbit_mask (mode, 0, 0);
13444 if (mode == SFmode)
13445 copysign_insn = gen_copysignsf3_const;
13446 else if (mode == DFmode)
13447 copysign_insn = gen_copysigndf3_const;
13449 copysign_insn = gen_copysigntf3_const;
13451 emit_insn (copysign_insn (dest, op0, op1, mask));
13455 rtx (*copysign_insn)(rtx, rtx, rtx, rtx, rtx, rtx);
13457 nmask = ix86_build_signbit_mask (mode, 0, 1);
13458 mask = ix86_build_signbit_mask (mode, 0, 0);
13460 if (mode == SFmode)
13461 copysign_insn = gen_copysignsf3_var;
13462 else if (mode == DFmode)
13463 copysign_insn = gen_copysigndf3_var;
13465 copysign_insn = gen_copysigntf3_var;
13467 emit_insn (copysign_insn (dest, NULL_RTX, op0, op1, nmask, mask));
13471 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
13472 be a constant, and so has already been expanded into a vector constant. */
13475 ix86_split_copysign_const (rtx operands[])
13477 enum machine_mode mode, vmode;
13478 rtx dest, op0, op1, mask, x;
13480 dest = operands[0];
13483 mask = operands[3];
13485 mode = GET_MODE (dest);
13486 vmode = GET_MODE (mask);
13488 dest = simplify_gen_subreg (vmode, dest, mode, 0);
13489 x = gen_rtx_AND (vmode, dest, mask);
13490 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13492 if (op0 != CONST0_RTX (vmode))
13494 x = gen_rtx_IOR (vmode, dest, op0);
13495 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13499 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
13500 so we have to do two masks. */
13503 ix86_split_copysign_var (rtx operands[])
13505 enum machine_mode mode, vmode;
13506 rtx dest, scratch, op0, op1, mask, nmask, x;
13508 dest = operands[0];
13509 scratch = operands[1];
13512 nmask = operands[4];
13513 mask = operands[5];
13515 mode = GET_MODE (dest);
13516 vmode = GET_MODE (mask);
13518 if (rtx_equal_p (op0, op1))
13520 /* Shouldn't happen often (it's useless, obviously), but when it does
13521 we'd generate incorrect code if we continue below. */
13522 emit_move_insn (dest, op0);
13526 if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */
13528 gcc_assert (REGNO (op1) == REGNO (scratch));
13530 x = gen_rtx_AND (vmode, scratch, mask);
13531 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13534 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13535 x = gen_rtx_NOT (vmode, dest);
13536 x = gen_rtx_AND (vmode, x, op0);
13537 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13541 if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */
13543 x = gen_rtx_AND (vmode, scratch, mask);
13545 else /* alternative 2,4 */
13547 gcc_assert (REGNO (mask) == REGNO (scratch));
13548 op1 = simplify_gen_subreg (vmode, op1, mode, 0);
13549 x = gen_rtx_AND (vmode, scratch, op1);
13551 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13553 if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */
13555 dest = simplify_gen_subreg (vmode, op0, mode, 0);
13556 x = gen_rtx_AND (vmode, dest, nmask);
13558 else /* alternative 3,4 */
13560 gcc_assert (REGNO (nmask) == REGNO (dest));
13562 op0 = simplify_gen_subreg (vmode, op0, mode, 0);
13563 x = gen_rtx_AND (vmode, dest, op0);
13565 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13568 x = gen_rtx_IOR (vmode, dest, scratch);
13569 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
13572 /* Return TRUE or FALSE depending on whether the first SET in INSN
13573 has source and destination with matching CC modes, and that the
13574 CC mode is at least as constrained as REQ_MODE. */
13577 ix86_match_ccmode (rtx insn, enum machine_mode req_mode)
13580 enum machine_mode set_mode;
13582 set = PATTERN (insn);
13583 if (GET_CODE (set) == PARALLEL)
13584 set = XVECEXP (set, 0, 0);
13585 gcc_assert (GET_CODE (set) == SET);
13586 gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE);
13588 set_mode = GET_MODE (SET_DEST (set));
13592 if (req_mode != CCNOmode
13593 && (req_mode != CCmode
13594 || XEXP (SET_SRC (set), 1) != const0_rtx))
13598 if (req_mode == CCGCmode)
13602 if (req_mode == CCGOCmode || req_mode == CCNOmode)
13606 if (req_mode == CCZmode)
13617 gcc_unreachable ();
13620 return (GET_MODE (SET_SRC (set)) == set_mode);
13623 /* Generate insn patterns to do an integer compare of OPERANDS. */
13626 ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
13628 enum machine_mode cmpmode;
13631 cmpmode = SELECT_CC_MODE (code, op0, op1);
13632 flags = gen_rtx_REG (cmpmode, FLAGS_REG);
13634 /* This is very simple, but making the interface the same as in the
13635 FP case makes the rest of the code easier. */
13636 tmp = gen_rtx_COMPARE (cmpmode, op0, op1);
13637 emit_insn (gen_rtx_SET (VOIDmode, flags, tmp));
13639 /* Return the test that should be put into the flags user, i.e.
13640 the bcc, scc, or cmov instruction. */
13641 return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx);
13644 /* Figure out whether to use ordered or unordered fp comparisons.
13645 Return the appropriate mode to use. */
13648 ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED)
13650 /* ??? In order to make all comparisons reversible, we do all comparisons
13651 non-trapping when compiling for IEEE. Once gcc is able to distinguish
13652 all forms trapping and nontrapping comparisons, we can make inequality
13653 comparisons trapping again, since it results in better code when using
13654 FCOM based compares. */
13655 return TARGET_IEEE_FP ? CCFPUmode : CCFPmode;
13659 ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1)
13661 enum machine_mode mode = GET_MODE (op0);
13663 if (SCALAR_FLOAT_MODE_P (mode))
13665 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
13666 return ix86_fp_compare_mode (code);
13671 /* Only zero flag is needed. */
13672 case EQ: /* ZF=0 */
13673 case NE: /* ZF!=0 */
13675 /* Codes needing carry flag. */
13676 case GEU: /* CF=0 */
13677 case LTU: /* CF=1 */
13678 /* Detect overflow checks. They need just the carry flag. */
13679 if (GET_CODE (op0) == PLUS
13680 && rtx_equal_p (op1, XEXP (op0, 0)))
13684 case GTU: /* CF=0 & ZF=0 */
13685 case LEU: /* CF=1 | ZF=1 */
13686 /* Detect overflow checks. They need just the carry flag. */
13687 if (GET_CODE (op0) == MINUS
13688 && rtx_equal_p (op1, XEXP (op0, 0)))
13692 /* Codes possibly doable only with sign flag when
13693 comparing against zero. */
13694 case GE: /* SF=OF or SF=0 */
13695 case LT: /* SF<>OF or SF=1 */
13696 if (op1 == const0_rtx)
13699 /* For other cases Carry flag is not required. */
13701 /* Codes doable only with sign flag when comparing
13702 against zero, but we miss jump instruction for it
13703 so we need to use relational tests against overflow
13704 that thus needs to be zero. */
13705 case GT: /* ZF=0 & SF=OF */
13706 case LE: /* ZF=1 | SF<>OF */
13707 if (op1 == const0_rtx)
13711 /* strcmp pattern do (use flags) and combine may ask us for proper
13716 gcc_unreachable ();
13720 /* Return the fixed registers used for condition codes. */
13723 ix86_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
13730 /* If two condition code modes are compatible, return a condition code
13731 mode which is compatible with both. Otherwise, return
13734 static enum machine_mode
13735 ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
13740 if (GET_MODE_CLASS (m1) != MODE_CC || GET_MODE_CLASS (m2) != MODE_CC)
13743 if ((m1 == CCGCmode && m2 == CCGOCmode)
13744 || (m1 == CCGOCmode && m2 == CCGCmode))
13750 gcc_unreachable ();
13780 /* These are only compatible with themselves, which we already
13786 /* Split comparison code CODE into comparisons we can do using branch
13787 instructions. BYPASS_CODE is comparison code for branch that will
13788 branch around FIRST_CODE and SECOND_CODE. If some of branches
13789 is not required, set value to UNKNOWN.
13790 We never require more than two branches. */
13793 ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code,
13794 enum rtx_code *first_code,
13795 enum rtx_code *second_code)
13797 *first_code = code;
13798 *bypass_code = UNKNOWN;
13799 *second_code = UNKNOWN;
13801 /* The fcomi comparison sets flags as follows:
13811 case GT: /* GTU - CF=0 & ZF=0 */
13812 case GE: /* GEU - CF=0 */
13813 case ORDERED: /* PF=0 */
13814 case UNORDERED: /* PF=1 */
13815 case UNEQ: /* EQ - ZF=1 */
13816 case UNLT: /* LTU - CF=1 */
13817 case UNLE: /* LEU - CF=1 | ZF=1 */
13818 case LTGT: /* EQ - ZF=0 */
13820 case LT: /* LTU - CF=1 - fails on unordered */
13821 *first_code = UNLT;
13822 *bypass_code = UNORDERED;
13824 case LE: /* LEU - CF=1 | ZF=1 - fails on unordered */
13825 *first_code = UNLE;
13826 *bypass_code = UNORDERED;
13828 case EQ: /* EQ - ZF=1 - fails on unordered */
13829 *first_code = UNEQ;
13830 *bypass_code = UNORDERED;
13832 case NE: /* NE - ZF=0 - fails on unordered */
13833 *first_code = LTGT;
13834 *second_code = UNORDERED;
13836 case UNGE: /* GEU - CF=0 - fails on unordered */
13838 *second_code = UNORDERED;
13840 case UNGT: /* GTU - CF=0 & ZF=0 - fails on unordered */
13842 *second_code = UNORDERED;
13845 gcc_unreachable ();
13847 if (!TARGET_IEEE_FP)
13849 *second_code = UNKNOWN;
13850 *bypass_code = UNKNOWN;
13854 /* Return cost of comparison done fcom + arithmetics operations on AX.
13855 All following functions do use number of instructions as a cost metrics.
13856 In future this should be tweaked to compute bytes for optimize_size and
13857 take into account performance of various instructions on various CPUs. */
13859 ix86_fp_comparison_arithmetics_cost (enum rtx_code code)
13861 if (!TARGET_IEEE_FP)
13863 /* The cost of code output by ix86_expand_fp_compare. */
13887 gcc_unreachable ();
13891 /* Return cost of comparison done using fcomi operation.
13892 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13894 ix86_fp_comparison_fcomi_cost (enum rtx_code code)
13896 enum rtx_code bypass_code, first_code, second_code;
13897 /* Return arbitrarily high cost when instruction is not supported - this
13898 prevents gcc from using it. */
13901 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13902 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2;
13905 /* Return cost of comparison done using sahf operation.
13906 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13908 ix86_fp_comparison_sahf_cost (enum rtx_code code)
13910 enum rtx_code bypass_code, first_code, second_code;
13911 /* Return arbitrarily high cost when instruction is not preferred - this
13912 avoids gcc from using it. */
13913 if (!(TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ())))
13915 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
13916 return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3;
13919 /* Compute cost of the comparison done using any method.
13920 See ix86_fp_comparison_arithmetics_cost for the metrics. */
13922 ix86_fp_comparison_cost (enum rtx_code code)
13924 int fcomi_cost, sahf_cost, arithmetics_cost = 1024;
13927 fcomi_cost = ix86_fp_comparison_fcomi_cost (code);
13928 sahf_cost = ix86_fp_comparison_sahf_cost (code);
13930 min = arithmetics_cost = ix86_fp_comparison_arithmetics_cost (code);
13931 if (min > sahf_cost)
13933 if (min > fcomi_cost)
13938 /* Return true if we should use an FCOMI instruction for this
13942 ix86_use_fcomi_compare (enum rtx_code code ATTRIBUTE_UNUSED)
13944 enum rtx_code swapped_code = swap_condition (code);
13946 return ((ix86_fp_comparison_cost (code)
13947 == ix86_fp_comparison_fcomi_cost (code))
13948 || (ix86_fp_comparison_cost (swapped_code)
13949 == ix86_fp_comparison_fcomi_cost (swapped_code)));
13952 /* Swap, force into registers, or otherwise massage the two operands
13953 to a fp comparison. The operands are updated in place; the new
13954 comparison code is returned. */
13956 static enum rtx_code
13957 ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
13959 enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code);
13960 rtx op0 = *pop0, op1 = *pop1;
13961 enum machine_mode op_mode = GET_MODE (op0);
13962 int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode);
13964 /* All of the unordered compare instructions only work on registers.
13965 The same is true of the fcomi compare instructions. The XFmode
13966 compare instructions require registers except when comparing
13967 against zero or when converting operand 1 from fixed point to
13971 && (fpcmp_mode == CCFPUmode
13972 || (op_mode == XFmode
13973 && ! (standard_80387_constant_p (op0) == 1
13974 || standard_80387_constant_p (op1) == 1)
13975 && GET_CODE (op1) != FLOAT)
13976 || ix86_use_fcomi_compare (code)))
13978 op0 = force_reg (op_mode, op0);
13979 op1 = force_reg (op_mode, op1);
13983 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
13984 things around if they appear profitable, otherwise force op0
13985 into a register. */
13987 if (standard_80387_constant_p (op0) == 0
13989 && ! (standard_80387_constant_p (op1) == 0
13993 tmp = op0, op0 = op1, op1 = tmp;
13994 code = swap_condition (code);
13998 op0 = force_reg (op_mode, op0);
14000 if (CONSTANT_P (op1))
14002 int tmp = standard_80387_constant_p (op1);
14004 op1 = validize_mem (force_const_mem (op_mode, op1));
14008 op1 = force_reg (op_mode, op1);
14011 op1 = force_reg (op_mode, op1);
14015 /* Try to rearrange the comparison to make it cheaper. */
14016 if (ix86_fp_comparison_cost (code)
14017 > ix86_fp_comparison_cost (swap_condition (code))
14018 && (REG_P (op1) || can_create_pseudo_p ()))
14021 tmp = op0, op0 = op1, op1 = tmp;
14022 code = swap_condition (code);
14024 op0 = force_reg (op_mode, op0);
14032 /* Convert comparison codes we use to represent FP comparison to integer
14033 code that will result in proper branch. Return UNKNOWN if no such code
14037 ix86_fp_compare_code_to_integer (enum rtx_code code)
14066 /* Generate insn patterns to do a floating point compare of OPERANDS. */
14069 ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch,
14070 rtx *second_test, rtx *bypass_test)
14072 enum machine_mode fpcmp_mode, intcmp_mode;
14074 int cost = ix86_fp_comparison_cost (code);
14075 enum rtx_code bypass_code, first_code, second_code;
14077 fpcmp_mode = ix86_fp_compare_mode (code);
14078 code = ix86_prepare_fp_compare_args (code, &op0, &op1);
14081 *second_test = NULL_RTX;
14083 *bypass_test = NULL_RTX;
14085 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14087 /* Do fcomi/sahf based test when profitable. */
14088 if (ix86_fp_comparison_arithmetics_cost (code) > cost
14089 && (bypass_code == UNKNOWN || bypass_test)
14090 && (second_code == UNKNOWN || second_test))
14092 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14093 tmp = gen_rtx_SET (VOIDmode, gen_rtx_REG (fpcmp_mode, FLAGS_REG),
14099 gcc_assert (TARGET_SAHF);
14102 scratch = gen_reg_rtx (HImode);
14103 tmp2 = gen_rtx_CLOBBER (VOIDmode, scratch);
14105 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, tmp2)));
14108 /* The FP codes work out to act like unsigned. */
14109 intcmp_mode = fpcmp_mode;
14111 if (bypass_code != UNKNOWN)
14112 *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode,
14113 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14115 if (second_code != UNKNOWN)
14116 *second_test = gen_rtx_fmt_ee (second_code, VOIDmode,
14117 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14122 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
14123 tmp = gen_rtx_COMPARE (fpcmp_mode, op0, op1);
14124 tmp2 = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW);
14126 scratch = gen_reg_rtx (HImode);
14127 emit_insn (gen_rtx_SET (VOIDmode, scratch, tmp2));
14129 /* In the unordered case, we have to check C2 for NaN's, which
14130 doesn't happen to work out to anything nice combination-wise.
14131 So do some bit twiddling on the value we've got in AH to come
14132 up with an appropriate set of condition codes. */
14134 intcmp_mode = CCNOmode;
14139 if (code == GT || !TARGET_IEEE_FP)
14141 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14146 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14147 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14148 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)));
14149 intcmp_mode = CCmode;
14155 if (code == LT && TARGET_IEEE_FP)
14157 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14158 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x01)));
14159 intcmp_mode = CCmode;
14164 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x01)));
14170 if (code == GE || !TARGET_IEEE_FP)
14172 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x05)));
14177 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14178 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14185 if (code == LE && TARGET_IEEE_FP)
14187 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14188 emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx));
14189 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14190 intcmp_mode = CCmode;
14195 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x45)));
14201 if (code == EQ && TARGET_IEEE_FP)
14203 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14204 emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)));
14205 intcmp_mode = CCmode;
14210 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14217 if (code == NE && TARGET_IEEE_FP)
14219 emit_insn (gen_andqi_ext_0 (scratch, scratch, GEN_INT (0x45)));
14220 emit_insn (gen_xorqi_cc_ext_1 (scratch, scratch,
14226 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x40)));
14232 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14236 emit_insn (gen_testqi_ext_ccno_0 (scratch, GEN_INT (0x04)));
14241 gcc_unreachable ();
14245 /* Return the test that should be put into the flags user, i.e.
14246 the bcc, scc, or cmov instruction. */
14247 return gen_rtx_fmt_ee (code, VOIDmode,
14248 gen_rtx_REG (intcmp_mode, FLAGS_REG),
14253 ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test)
14256 op0 = ix86_compare_op0;
14257 op1 = ix86_compare_op1;
14260 *second_test = NULL_RTX;
14262 *bypass_test = NULL_RTX;
14264 if (ix86_compare_emitted)
14266 ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx);
14267 ix86_compare_emitted = NULL_RTX;
14269 else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0)))
14271 gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)));
14272 ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14273 second_test, bypass_test);
14276 ret = ix86_expand_int_compare (code, op0, op1);
14281 /* Return true if the CODE will result in nontrivial jump sequence. */
14283 ix86_fp_jump_nontrivial_p (enum rtx_code code)
14285 enum rtx_code bypass_code, first_code, second_code;
14288 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14289 return bypass_code != UNKNOWN || second_code != UNKNOWN;
14293 ix86_expand_branch (enum rtx_code code, rtx label)
14297 /* If we have emitted a compare insn, go straight to simple.
14298 ix86_expand_compare won't emit anything if ix86_compare_emitted
14300 if (ix86_compare_emitted)
14303 switch (GET_MODE (ix86_compare_op0))
14309 tmp = ix86_expand_compare (code, NULL, NULL);
14310 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14311 gen_rtx_LABEL_REF (VOIDmode, label),
14313 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
14322 enum rtx_code bypass_code, first_code, second_code;
14324 code = ix86_prepare_fp_compare_args (code, &ix86_compare_op0,
14325 &ix86_compare_op1);
14327 ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code);
14329 /* Check whether we will use the natural sequence with one jump. If
14330 so, we can expand jump early. Otherwise delay expansion by
14331 creating compound insn to not confuse optimizers. */
14332 if (bypass_code == UNKNOWN && second_code == UNKNOWN)
14334 ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1,
14335 gen_rtx_LABEL_REF (VOIDmode, label),
14336 pc_rtx, NULL_RTX, NULL_RTX);
14340 tmp = gen_rtx_fmt_ee (code, VOIDmode,
14341 ix86_compare_op0, ix86_compare_op1);
14342 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
14343 gen_rtx_LABEL_REF (VOIDmode, label),
14345 tmp = gen_rtx_SET (VOIDmode, pc_rtx, tmp);
14347 use_fcomi = ix86_use_fcomi_compare (code);
14348 vec = rtvec_alloc (3 + !use_fcomi);
14349 RTVEC_ELT (vec, 0) = tmp;
14351 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FPSR_REG));
14353 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCFPmode, FLAGS_REG));
14356 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (HImode));
14358 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, vec));
14367 /* Expand DImode branch into multiple compare+branch. */
14369 rtx lo[2], hi[2], label2;
14370 enum rtx_code code1, code2, code3;
14371 enum machine_mode submode;
14373 if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1))
14375 tmp = ix86_compare_op0;
14376 ix86_compare_op0 = ix86_compare_op1;
14377 ix86_compare_op1 = tmp;
14378 code = swap_condition (code);
14380 if (GET_MODE (ix86_compare_op0) == DImode)
14382 split_di (&ix86_compare_op0, 1, lo+0, hi+0);
14383 split_di (&ix86_compare_op1, 1, lo+1, hi+1);
14388 split_ti (&ix86_compare_op0, 1, lo+0, hi+0);
14389 split_ti (&ix86_compare_op1, 1, lo+1, hi+1);
14393 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
14394 avoid two branches. This costs one extra insn, so disable when
14395 optimizing for size. */
14397 if ((code == EQ || code == NE)
14398 && (!optimize_insn_for_size_p ()
14399 || hi[1] == const0_rtx || lo[1] == const0_rtx))
14404 if (hi[1] != const0_rtx)
14405 xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
14406 NULL_RTX, 0, OPTAB_WIDEN);
14409 if (lo[1] != const0_rtx)
14410 xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
14411 NULL_RTX, 0, OPTAB_WIDEN);
14413 tmp = expand_binop (submode, ior_optab, xor1, xor0,
14414 NULL_RTX, 0, OPTAB_WIDEN);
14416 ix86_compare_op0 = tmp;
14417 ix86_compare_op1 = const0_rtx;
14418 ix86_expand_branch (code, label);
14422 /* Otherwise, if we are doing less-than or greater-or-equal-than,
14423 op1 is a constant and the low word is zero, then we can just
14424 examine the high word. Similarly for low word -1 and
14425 less-or-equal-than or greater-than. */
14427 if (CONST_INT_P (hi[1]))
14430 case LT: case LTU: case GE: case GEU:
14431 if (lo[1] == const0_rtx)
14433 ix86_compare_op0 = hi[0];
14434 ix86_compare_op1 = hi[1];
14435 ix86_expand_branch (code, label);
14439 case LE: case LEU: case GT: case GTU:
14440 if (lo[1] == constm1_rtx)
14442 ix86_compare_op0 = hi[0];
14443 ix86_compare_op1 = hi[1];
14444 ix86_expand_branch (code, label);
14452 /* Otherwise, we need two or three jumps. */
14454 label2 = gen_label_rtx ();
14457 code2 = swap_condition (code);
14458 code3 = unsigned_condition (code);
14462 case LT: case GT: case LTU: case GTU:
14465 case LE: code1 = LT; code2 = GT; break;
14466 case GE: code1 = GT; code2 = LT; break;
14467 case LEU: code1 = LTU; code2 = GTU; break;
14468 case GEU: code1 = GTU; code2 = LTU; break;
14470 case EQ: code1 = UNKNOWN; code2 = NE; break;
14471 case NE: code2 = UNKNOWN; break;
14474 gcc_unreachable ();
14479 * if (hi(a) < hi(b)) goto true;
14480 * if (hi(a) > hi(b)) goto false;
14481 * if (lo(a) < lo(b)) goto true;
14485 ix86_compare_op0 = hi[0];
14486 ix86_compare_op1 = hi[1];
14488 if (code1 != UNKNOWN)
14489 ix86_expand_branch (code1, label);
14490 if (code2 != UNKNOWN)
14491 ix86_expand_branch (code2, label2);
14493 ix86_compare_op0 = lo[0];
14494 ix86_compare_op1 = lo[1];
14495 ix86_expand_branch (code3, label);
14497 if (code2 != UNKNOWN)
14498 emit_label (label2);
14503 gcc_unreachable ();
14507 /* Split branch based on floating point condition. */
14509 ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2,
14510 rtx target1, rtx target2, rtx tmp, rtx pushed)
14512 rtx second, bypass;
14513 rtx label = NULL_RTX;
14515 int bypass_probability = -1, second_probability = -1, probability = -1;
14518 if (target2 != pc_rtx)
14521 code = reverse_condition_maybe_unordered (code);
14526 condition = ix86_expand_fp_compare (code, op1, op2,
14527 tmp, &second, &bypass);
14529 /* Remove pushed operand from stack. */
14531 ix86_free_from_memory (GET_MODE (pushed));
14533 if (split_branch_probability >= 0)
14535 /* Distribute the probabilities across the jumps.
14536 Assume the BYPASS and SECOND to be always test
14538 probability = split_branch_probability;
14540 /* Value of 1 is low enough to make no need for probability
14541 to be updated. Later we may run some experiments and see
14542 if unordered values are more frequent in practice. */
14544 bypass_probability = 1;
14546 second_probability = 1;
14548 if (bypass != NULL_RTX)
14550 label = gen_label_rtx ();
14551 i = emit_jump_insn (gen_rtx_SET
14553 gen_rtx_IF_THEN_ELSE (VOIDmode,
14555 gen_rtx_LABEL_REF (VOIDmode,
14558 if (bypass_probability >= 0)
14560 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14561 GEN_INT (bypass_probability),
14564 i = emit_jump_insn (gen_rtx_SET
14566 gen_rtx_IF_THEN_ELSE (VOIDmode,
14567 condition, target1, target2)));
14568 if (probability >= 0)
14570 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14571 GEN_INT (probability),
14573 if (second != NULL_RTX)
14575 i = emit_jump_insn (gen_rtx_SET
14577 gen_rtx_IF_THEN_ELSE (VOIDmode, second, target1,
14579 if (second_probability >= 0)
14581 = gen_rtx_EXPR_LIST (REG_BR_PROB,
14582 GEN_INT (second_probability),
14585 if (label != NULL_RTX)
14586 emit_label (label);
14590 ix86_expand_setcc (enum rtx_code code, rtx dest)
14592 rtx ret, tmp, tmpreg, equiv;
14593 rtx second_test, bypass_test;
14595 if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode))
14596 return 0; /* FAIL */
14598 gcc_assert (GET_MODE (dest) == QImode);
14600 ret = ix86_expand_compare (code, &second_test, &bypass_test);
14601 PUT_MODE (ret, QImode);
14606 emit_insn (gen_rtx_SET (VOIDmode, tmp, ret));
14607 if (bypass_test || second_test)
14609 rtx test = second_test;
14611 rtx tmp2 = gen_reg_rtx (QImode);
14614 gcc_assert (!second_test);
14615 test = bypass_test;
14617 PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test)));
14619 PUT_MODE (test, QImode);
14620 emit_insn (gen_rtx_SET (VOIDmode, tmp2, test));
14623 emit_insn (gen_andqi3 (tmp, tmpreg, tmp2));
14625 emit_insn (gen_iorqi3 (tmp, tmpreg, tmp2));
14628 /* Attach a REG_EQUAL note describing the comparison result. */
14629 if (ix86_compare_op0 && ix86_compare_op1)
14631 equiv = simplify_gen_relational (code, QImode,
14632 GET_MODE (ix86_compare_op0),
14633 ix86_compare_op0, ix86_compare_op1);
14634 set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv);
14637 return 1; /* DONE */
14640 /* Expand comparison setting or clearing carry flag. Return true when
14641 successful and set pop for the operation. */
14643 ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
14645 enum machine_mode mode =
14646 GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
14648 /* Do not handle DImode compares that go through special path. */
14649 if (mode == (TARGET_64BIT ? TImode : DImode))
14652 if (SCALAR_FLOAT_MODE_P (mode))
14654 rtx second_test = NULL, bypass_test = NULL;
14655 rtx compare_op, compare_seq;
14657 gcc_assert (!DECIMAL_FLOAT_MODE_P (mode));
14659 /* Shortcut: following common codes never translate
14660 into carry flag compares. */
14661 if (code == EQ || code == NE || code == UNEQ || code == LTGT
14662 || code == ORDERED || code == UNORDERED)
14665 /* These comparisons require zero flag; swap operands so they won't. */
14666 if ((code == GT || code == UNLE || code == LE || code == UNGT)
14667 && !TARGET_IEEE_FP)
14672 code = swap_condition (code);
14675 /* Try to expand the comparison and verify that we end up with
14676 carry flag based comparison. This fails to be true only when
14677 we decide to expand comparison using arithmetic that is not
14678 too common scenario. */
14680 compare_op = ix86_expand_fp_compare (code, op0, op1, NULL_RTX,
14681 &second_test, &bypass_test);
14682 compare_seq = get_insns ();
14685 if (second_test || bypass_test)
14688 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14689 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14690 code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op));
14692 code = GET_CODE (compare_op);
14694 if (code != LTU && code != GEU)
14697 emit_insn (compare_seq);
14702 if (!INTEGRAL_MODE_P (mode))
14711 /* Convert a==0 into (unsigned)a<1. */
14714 if (op1 != const0_rtx)
14717 code = (code == EQ ? LTU : GEU);
14720 /* Convert a>b into b<a or a>=b-1. */
14723 if (CONST_INT_P (op1))
14725 op1 = gen_int_mode (INTVAL (op1) + 1, GET_MODE (op0));
14726 /* Bail out on overflow. We still can swap operands but that
14727 would force loading of the constant into register. */
14728 if (op1 == const0_rtx
14729 || !x86_64_immediate_operand (op1, GET_MODE (op1)))
14731 code = (code == GTU ? GEU : LTU);
14738 code = (code == GTU ? LTU : GEU);
14742 /* Convert a>=0 into (unsigned)a<0x80000000. */
14745 if (mode == DImode || op1 != const0_rtx)
14747 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14748 code = (code == LT ? GEU : LTU);
14752 if (mode == DImode || op1 != constm1_rtx)
14754 op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
14755 code = (code == LE ? GEU : LTU);
14761 /* Swapping operands may cause constant to appear as first operand. */
14762 if (!nonimmediate_operand (op0, VOIDmode))
14764 if (!can_create_pseudo_p ())
14766 op0 = force_reg (mode, op0);
14768 ix86_compare_op0 = op0;
14769 ix86_compare_op1 = op1;
14770 *pop = ix86_expand_compare (code, NULL, NULL);
14771 gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU);
14776 ix86_expand_int_movcc (rtx operands[])
14778 enum rtx_code code = GET_CODE (operands[1]), compare_code;
14779 rtx compare_seq, compare_op;
14780 rtx second_test, bypass_test;
14781 enum machine_mode mode = GET_MODE (operands[0]);
14782 bool sign_bit_compare_p = false;;
14785 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
14786 compare_seq = get_insns ();
14789 compare_code = GET_CODE (compare_op);
14791 if ((ix86_compare_op1 == const0_rtx && (code == GE || code == LT))
14792 || (ix86_compare_op1 == constm1_rtx && (code == GT || code == LE)))
14793 sign_bit_compare_p = true;
14795 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
14796 HImode insns, we'd be swallowed in word prefix ops. */
14798 if ((mode != HImode || TARGET_FAST_PREFIX)
14799 && (mode != (TARGET_64BIT ? TImode : DImode))
14800 && CONST_INT_P (operands[2])
14801 && CONST_INT_P (operands[3]))
14803 rtx out = operands[0];
14804 HOST_WIDE_INT ct = INTVAL (operands[2]);
14805 HOST_WIDE_INT cf = INTVAL (operands[3]);
14806 HOST_WIDE_INT diff;
14809 /* Sign bit compares are better done using shifts than we do by using
14811 if (sign_bit_compare_p
14812 || ix86_expand_carry_flag_compare (code, ix86_compare_op0,
14813 ix86_compare_op1, &compare_op))
14815 /* Detect overlap between destination and compare sources. */
14818 if (!sign_bit_compare_p)
14820 bool fpcmp = false;
14822 compare_code = GET_CODE (compare_op);
14824 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
14825 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
14828 compare_code = ix86_fp_compare_code_to_integer (compare_code);
14831 /* To simplify rest of code, restrict to the GEU case. */
14832 if (compare_code == LTU)
14834 HOST_WIDE_INT tmp = ct;
14837 compare_code = reverse_condition (compare_code);
14838 code = reverse_condition (code);
14843 PUT_CODE (compare_op,
14844 reverse_condition_maybe_unordered
14845 (GET_CODE (compare_op)));
14847 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
14851 if (reg_overlap_mentioned_p (out, ix86_compare_op0)
14852 || reg_overlap_mentioned_p (out, ix86_compare_op1))
14853 tmp = gen_reg_rtx (mode);
14855 if (mode == DImode)
14856 emit_insn (gen_x86_movdicc_0_m1_rex64 (tmp, compare_op));
14858 emit_insn (gen_x86_movsicc_0_m1 (gen_lowpart (SImode, tmp), compare_op));
14862 if (code == GT || code == GE)
14863 code = reverse_condition (code);
14866 HOST_WIDE_INT tmp = ct;
14871 tmp = emit_store_flag (tmp, code, ix86_compare_op0,
14872 ix86_compare_op1, VOIDmode, 0, -1);
14885 tmp = expand_simple_binop (mode, PLUS,
14887 copy_rtx (tmp), 1, OPTAB_DIRECT);
14898 tmp = expand_simple_binop (mode, IOR,
14900 copy_rtx (tmp), 1, OPTAB_DIRECT);
14902 else if (diff == -1 && ct)
14912 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14914 tmp = expand_simple_binop (mode, PLUS,
14915 copy_rtx (tmp), GEN_INT (cf),
14916 copy_rtx (tmp), 1, OPTAB_DIRECT);
14924 * andl cf - ct, dest
14934 tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
14937 tmp = expand_simple_binop (mode, AND,
14939 gen_int_mode (cf - ct, mode),
14940 copy_rtx (tmp), 1, OPTAB_DIRECT);
14942 tmp = expand_simple_binop (mode, PLUS,
14943 copy_rtx (tmp), GEN_INT (ct),
14944 copy_rtx (tmp), 1, OPTAB_DIRECT);
14947 if (!rtx_equal_p (tmp, out))
14948 emit_move_insn (copy_rtx (out), copy_rtx (tmp));
14950 return 1; /* DONE */
14955 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
14958 tmp = ct, ct = cf, cf = tmp;
14961 if (SCALAR_FLOAT_MODE_P (cmp_mode))
14963 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
14965 /* We may be reversing unordered compare to normal compare, that
14966 is not valid in general (we may convert non-trapping condition
14967 to trapping one), however on i386 we currently emit all
14968 comparisons unordered. */
14969 compare_code = reverse_condition_maybe_unordered (compare_code);
14970 code = reverse_condition_maybe_unordered (code);
14974 compare_code = reverse_condition (compare_code);
14975 code = reverse_condition (code);
14979 compare_code = UNKNOWN;
14980 if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT
14981 && CONST_INT_P (ix86_compare_op1))
14983 if (ix86_compare_op1 == const0_rtx
14984 && (code == LT || code == GE))
14985 compare_code = code;
14986 else if (ix86_compare_op1 == constm1_rtx)
14990 else if (code == GT)
14995 /* Optimize dest = (op0 < 0) ? -1 : cf. */
14996 if (compare_code != UNKNOWN
14997 && GET_MODE (ix86_compare_op0) == GET_MODE (out)
14998 && (cf == -1 || ct == -1))
15000 /* If lea code below could be used, only optimize
15001 if it results in a 2 insn sequence. */
15003 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
15004 || diff == 3 || diff == 5 || diff == 9)
15005 || (compare_code == LT && ct == -1)
15006 || (compare_code == GE && cf == -1))
15009 * notl op1 (if necessary)
15017 code = reverse_condition (code);
15020 out = emit_store_flag (out, code, ix86_compare_op0,
15021 ix86_compare_op1, VOIDmode, 0, -1);
15023 out = expand_simple_binop (mode, IOR,
15025 out, 1, OPTAB_DIRECT);
15026 if (out != operands[0])
15027 emit_move_insn (operands[0], out);
15029 return 1; /* DONE */
15034 if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
15035 || diff == 3 || diff == 5 || diff == 9)
15036 && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL)
15038 || x86_64_immediate_operand (GEN_INT (cf), VOIDmode)))
15044 * lea cf(dest*(ct-cf)),dest
15048 * This also catches the degenerate setcc-only case.
15054 out = emit_store_flag (out, code, ix86_compare_op0,
15055 ix86_compare_op1, VOIDmode, 0, 1);
15058 /* On x86_64 the lea instruction operates on Pmode, so we need
15059 to get arithmetics done in proper mode to match. */
15061 tmp = copy_rtx (out);
15065 out1 = copy_rtx (out);
15066 tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1));
15070 tmp = gen_rtx_PLUS (mode, tmp, out1);
15076 tmp = gen_rtx_PLUS (mode, tmp, GEN_INT (cf));
15079 if (!rtx_equal_p (tmp, out))
15082 out = force_operand (tmp, copy_rtx (out));
15084 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (out), copy_rtx (tmp)));
15086 if (!rtx_equal_p (out, operands[0]))
15087 emit_move_insn (operands[0], copy_rtx (out));
15089 return 1; /* DONE */
15093 * General case: Jumpful:
15094 * xorl dest,dest cmpl op1, op2
15095 * cmpl op1, op2 movl ct, dest
15096 * setcc dest jcc 1f
15097 * decl dest movl cf, dest
15098 * andl (cf-ct),dest 1:
15101 * Size 20. Size 14.
15103 * This is reasonably steep, but branch mispredict costs are
15104 * high on modern cpus, so consider failing only if optimizing
15108 if ((!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15109 && BRANCH_COST (optimize_insn_for_speed_p (),
15114 enum machine_mode cmp_mode = GET_MODE (ix86_compare_op0);
15119 if (SCALAR_FLOAT_MODE_P (cmp_mode))
15121 gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode));
15123 /* We may be reversing unordered compare to normal compare,
15124 that is not valid in general (we may convert non-trapping
15125 condition to trapping one), however on i386 we currently
15126 emit all comparisons unordered. */
15127 code = reverse_condition_maybe_unordered (code);
15131 code = reverse_condition (code);
15132 if (compare_code != UNKNOWN)
15133 compare_code = reverse_condition (compare_code);
15137 if (compare_code != UNKNOWN)
15139 /* notl op1 (if needed)
15144 For x < 0 (resp. x <= -1) there will be no notl,
15145 so if possible swap the constants to get rid of the
15147 True/false will be -1/0 while code below (store flag
15148 followed by decrement) is 0/-1, so the constants need
15149 to be exchanged once more. */
15151 if (compare_code == GE || !cf)
15153 code = reverse_condition (code);
15158 HOST_WIDE_INT tmp = cf;
15163 out = emit_store_flag (out, code, ix86_compare_op0,
15164 ix86_compare_op1, VOIDmode, 0, -1);
15168 out = emit_store_flag (out, code, ix86_compare_op0,
15169 ix86_compare_op1, VOIDmode, 0, 1);
15171 out = expand_simple_binop (mode, PLUS, copy_rtx (out), constm1_rtx,
15172 copy_rtx (out), 1, OPTAB_DIRECT);
15175 out = expand_simple_binop (mode, AND, copy_rtx (out),
15176 gen_int_mode (cf - ct, mode),
15177 copy_rtx (out), 1, OPTAB_DIRECT);
15179 out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct),
15180 copy_rtx (out), 1, OPTAB_DIRECT);
15181 if (!rtx_equal_p (out, operands[0]))
15182 emit_move_insn (operands[0], copy_rtx (out));
15184 return 1; /* DONE */
15188 if (!TARGET_CMOVE || (mode == QImode && TARGET_PARTIAL_REG_STALL))
15190 /* Try a few things more with specific constants and a variable. */
15193 rtx var, orig_out, out, tmp;
15195 if (BRANCH_COST (optimize_insn_for_speed_p (), false) <= 2)
15196 return 0; /* FAIL */
15198 /* If one of the two operands is an interesting constant, load a
15199 constant with the above and mask it in with a logical operation. */
15201 if (CONST_INT_P (operands[2]))
15204 if (INTVAL (operands[2]) == 0 && operands[3] != constm1_rtx)
15205 operands[3] = constm1_rtx, op = and_optab;
15206 else if (INTVAL (operands[2]) == -1 && operands[3] != const0_rtx)
15207 operands[3] = const0_rtx, op = ior_optab;
15209 return 0; /* FAIL */
15211 else if (CONST_INT_P (operands[3]))
15214 if (INTVAL (operands[3]) == 0 && operands[2] != constm1_rtx)
15215 operands[2] = constm1_rtx, op = and_optab;
15216 else if (INTVAL (operands[3]) == -1 && operands[3] != const0_rtx)
15217 operands[2] = const0_rtx, op = ior_optab;
15219 return 0; /* FAIL */
15222 return 0; /* FAIL */
15224 orig_out = operands[0];
15225 tmp = gen_reg_rtx (mode);
15228 /* Recurse to get the constant loaded. */
15229 if (ix86_expand_int_movcc (operands) == 0)
15230 return 0; /* FAIL */
15232 /* Mask in the interesting variable. */
15233 out = expand_binop (mode, op, var, tmp, orig_out, 0,
15235 if (!rtx_equal_p (out, orig_out))
15236 emit_move_insn (copy_rtx (orig_out), copy_rtx (out));
15238 return 1; /* DONE */
15242 * For comparison with above,
15252 if (! nonimmediate_operand (operands[2], mode))
15253 operands[2] = force_reg (mode, operands[2]);
15254 if (! nonimmediate_operand (operands[3], mode))
15255 operands[3] = force_reg (mode, operands[3]);
15257 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15259 rtx tmp = gen_reg_rtx (mode);
15260 emit_move_insn (tmp, operands[3]);
15263 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15265 rtx tmp = gen_reg_rtx (mode);
15266 emit_move_insn (tmp, operands[2]);
15270 if (! register_operand (operands[2], VOIDmode)
15272 || ! register_operand (operands[3], VOIDmode)))
15273 operands[2] = force_reg (mode, operands[2]);
15276 && ! register_operand (operands[3], VOIDmode))
15277 operands[3] = force_reg (mode, operands[3]);
15279 emit_insn (compare_seq);
15280 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15281 gen_rtx_IF_THEN_ELSE (mode,
15282 compare_op, operands[2],
15285 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15286 gen_rtx_IF_THEN_ELSE (mode,
15288 copy_rtx (operands[3]),
15289 copy_rtx (operands[0]))));
15291 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (operands[0]),
15292 gen_rtx_IF_THEN_ELSE (mode,
15294 copy_rtx (operands[2]),
15295 copy_rtx (operands[0]))));
15297 return 1; /* DONE */
15300 /* Swap, force into registers, or otherwise massage the two operands
15301 to an sse comparison with a mask result. Thus we differ a bit from
15302 ix86_prepare_fp_compare_args which expects to produce a flags result.
15304 The DEST operand exists to help determine whether to commute commutative
15305 operators. The POP0/POP1 operands are updated in place. The new
15306 comparison code is returned, or UNKNOWN if not implementable. */
15308 static enum rtx_code
15309 ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
15310 rtx *pop0, rtx *pop1)
15318 /* We have no LTGT as an operator. We could implement it with
15319 NE & ORDERED, but this requires an extra temporary. It's
15320 not clear that it's worth it. */
15327 /* These are supported directly. */
15334 /* For commutative operators, try to canonicalize the destination
15335 operand to be first in the comparison - this helps reload to
15336 avoid extra moves. */
15337 if (!dest || !rtx_equal_p (dest, *pop1))
15345 /* These are not supported directly. Swap the comparison operands
15346 to transform into something that is supported. */
15350 code = swap_condition (code);
15354 gcc_unreachable ();
15360 /* Detect conditional moves that exactly match min/max operational
15361 semantics. Note that this is IEEE safe, as long as we don't
15362 interchange the operands.
15364 Returns FALSE if this conditional move doesn't match a MIN/MAX,
15365 and TRUE if the operation is successful and instructions are emitted. */
15368 ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
15369 rtx cmp_op1, rtx if_true, rtx if_false)
15371 enum machine_mode mode;
15377 else if (code == UNGE)
15380 if_true = if_false;
15386 if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
15388 else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
15393 mode = GET_MODE (dest);
15395 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
15396 but MODE may be a vector mode and thus not appropriate. */
15397 if (!flag_finite_math_only || !flag_unsafe_math_optimizations)
15399 int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
15402 if_true = force_reg (mode, if_true);
15403 v = gen_rtvec (2, if_true, if_false);
15404 tmp = gen_rtx_UNSPEC (mode, v, u);
15408 code = is_min ? SMIN : SMAX;
15409 tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false);
15412 emit_insn (gen_rtx_SET (VOIDmode, dest, tmp));
15416 /* Expand an sse vector comparison. Return the register with the result. */
15419 ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
15420 rtx op_true, rtx op_false)
15422 enum machine_mode mode = GET_MODE (dest);
15425 cmp_op0 = force_reg (mode, cmp_op0);
15426 if (!nonimmediate_operand (cmp_op1, mode))
15427 cmp_op1 = force_reg (mode, cmp_op1);
15430 || reg_overlap_mentioned_p (dest, op_true)
15431 || reg_overlap_mentioned_p (dest, op_false))
15432 dest = gen_reg_rtx (mode);
15434 x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
15435 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15440 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
15441 operations. This is used for both scalar and vector conditional moves. */
15444 ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
15446 enum machine_mode mode = GET_MODE (dest);
15449 if (op_false == CONST0_RTX (mode))
15451 op_true = force_reg (mode, op_true);
15452 x = gen_rtx_AND (mode, cmp, op_true);
15453 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15455 else if (op_true == CONST0_RTX (mode))
15457 op_false = force_reg (mode, op_false);
15458 x = gen_rtx_NOT (mode, cmp);
15459 x = gen_rtx_AND (mode, x, op_false);
15460 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15462 else if (TARGET_SSE5)
15464 rtx pcmov = gen_rtx_SET (mode, dest,
15465 gen_rtx_IF_THEN_ELSE (mode, cmp,
15472 op_true = force_reg (mode, op_true);
15473 op_false = force_reg (mode, op_false);
15475 t2 = gen_reg_rtx (mode);
15477 t3 = gen_reg_rtx (mode);
15481 x = gen_rtx_AND (mode, op_true, cmp);
15482 emit_insn (gen_rtx_SET (VOIDmode, t2, x));
15484 x = gen_rtx_NOT (mode, cmp);
15485 x = gen_rtx_AND (mode, x, op_false);
15486 emit_insn (gen_rtx_SET (VOIDmode, t3, x));
15488 x = gen_rtx_IOR (mode, t3, t2);
15489 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
15493 /* Expand a floating-point conditional move. Return true if successful. */
15496 ix86_expand_fp_movcc (rtx operands[])
15498 enum machine_mode mode = GET_MODE (operands[0]);
15499 enum rtx_code code = GET_CODE (operands[1]);
15500 rtx tmp, compare_op, second_test, bypass_test;
15502 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
15504 enum machine_mode cmode;
15506 /* Since we've no cmove for sse registers, don't force bad register
15507 allocation just to gain access to it. Deny movcc when the
15508 comparison mode doesn't match the move mode. */
15509 cmode = GET_MODE (ix86_compare_op0);
15510 if (cmode == VOIDmode)
15511 cmode = GET_MODE (ix86_compare_op1);
15515 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15517 &ix86_compare_op1);
15518 if (code == UNKNOWN)
15521 if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0,
15522 ix86_compare_op1, operands[2],
15526 tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0,
15527 ix86_compare_op1, operands[2], operands[3]);
15528 ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
15532 /* The floating point conditional move instructions don't directly
15533 support conditions resulting from a signed integer comparison. */
15535 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15537 /* The floating point conditional move instructions don't directly
15538 support signed integer comparisons. */
15540 if (!fcmov_comparison_operator (compare_op, VOIDmode))
15542 gcc_assert (!second_test && !bypass_test);
15543 tmp = gen_reg_rtx (QImode);
15544 ix86_expand_setcc (code, tmp);
15546 ix86_compare_op0 = tmp;
15547 ix86_compare_op1 = const0_rtx;
15548 compare_op = ix86_expand_compare (code, &second_test, &bypass_test);
15550 if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3]))
15552 tmp = gen_reg_rtx (mode);
15553 emit_move_insn (tmp, operands[3]);
15556 if (second_test && reg_overlap_mentioned_p (operands[0], operands[2]))
15558 tmp = gen_reg_rtx (mode);
15559 emit_move_insn (tmp, operands[2]);
15563 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15564 gen_rtx_IF_THEN_ELSE (mode, compare_op,
15565 operands[2], operands[3])));
15567 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15568 gen_rtx_IF_THEN_ELSE (mode, bypass_test,
15569 operands[3], operands[0])));
15571 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
15572 gen_rtx_IF_THEN_ELSE (mode, second_test,
15573 operands[2], operands[0])));
15578 /* Expand a floating-point vector conditional move; a vcond operation
15579 rather than a movcc operation. */
15582 ix86_expand_fp_vcond (rtx operands[])
15584 enum rtx_code code = GET_CODE (operands[3]);
15587 code = ix86_prepare_sse_fp_compare_args (operands[0], code,
15588 &operands[4], &operands[5]);
15589 if (code == UNKNOWN)
15592 if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
15593 operands[5], operands[1], operands[2]))
15596 cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
15597 operands[1], operands[2]);
15598 ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
15602 /* Expand a signed/unsigned integral vector conditional move. */
15605 ix86_expand_int_vcond (rtx operands[])
15607 enum machine_mode mode = GET_MODE (operands[0]);
15608 enum rtx_code code = GET_CODE (operands[3]);
15609 bool negate = false;
15612 cop0 = operands[4];
15613 cop1 = operands[5];
15615 /* SSE5 supports all of the comparisons on all vector int types. */
15618 /* Canonicalize the comparison to EQ, GT, GTU. */
15629 code = reverse_condition (code);
15635 code = reverse_condition (code);
15641 code = swap_condition (code);
15642 x = cop0, cop0 = cop1, cop1 = x;
15646 gcc_unreachable ();
15649 /* Only SSE4.1/SSE4.2 supports V2DImode. */
15650 if (mode == V2DImode)
15655 /* SSE4.1 supports EQ. */
15656 if (!TARGET_SSE4_1)
15662 /* SSE4.2 supports GT/GTU. */
15663 if (!TARGET_SSE4_2)
15668 gcc_unreachable ();
15672 /* Unsigned parallel compare is not supported by the hardware.
15673 Play some tricks to turn this into a signed comparison
15677 cop0 = force_reg (mode, cop0);
15685 rtx (*gen_sub3) (rtx, rtx, rtx);
15687 /* Subtract (-(INT MAX) - 1) from both operands to make
15689 mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
15691 gen_sub3 = (mode == V4SImode
15692 ? gen_subv4si3 : gen_subv2di3);
15693 t1 = gen_reg_rtx (mode);
15694 emit_insn (gen_sub3 (t1, cop0, mask));
15696 t2 = gen_reg_rtx (mode);
15697 emit_insn (gen_sub3 (t2, cop1, mask));
15707 /* Perform a parallel unsigned saturating subtraction. */
15708 x = gen_reg_rtx (mode);
15709 emit_insn (gen_rtx_SET (VOIDmode, x,
15710 gen_rtx_US_MINUS (mode, cop0, cop1)));
15713 cop1 = CONST0_RTX (mode);
15719 gcc_unreachable ();
15724 x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
15725 operands[1+negate], operands[2-negate]);
15727 ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
15728 operands[2-negate]);
15732 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
15733 true if we should do zero extension, else sign extension. HIGH_P is
15734 true if we want the N/2 high elements, else the low elements. */
15737 ix86_expand_sse_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15739 enum machine_mode imode = GET_MODE (operands[1]);
15740 rtx (*unpack)(rtx, rtx, rtx);
15747 unpack = gen_vec_interleave_highv16qi;
15749 unpack = gen_vec_interleave_lowv16qi;
15753 unpack = gen_vec_interleave_highv8hi;
15755 unpack = gen_vec_interleave_lowv8hi;
15759 unpack = gen_vec_interleave_highv4si;
15761 unpack = gen_vec_interleave_lowv4si;
15764 gcc_unreachable ();
15767 dest = gen_lowpart (imode, operands[0]);
15770 se = force_reg (imode, CONST0_RTX (imode));
15772 se = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode),
15773 operands[1], pc_rtx, pc_rtx);
15775 emit_insn (unpack (dest, operands[1], se));
15778 /* This function performs the same task as ix86_expand_sse_unpack,
15779 but with SSE4.1 instructions. */
15782 ix86_expand_sse4_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15784 enum machine_mode imode = GET_MODE (operands[1]);
15785 rtx (*unpack)(rtx, rtx);
15792 unpack = gen_sse4_1_zero_extendv8qiv8hi2;
15794 unpack = gen_sse4_1_extendv8qiv8hi2;
15798 unpack = gen_sse4_1_zero_extendv4hiv4si2;
15800 unpack = gen_sse4_1_extendv4hiv4si2;
15804 unpack = gen_sse4_1_zero_extendv2siv2di2;
15806 unpack = gen_sse4_1_extendv2siv2di2;
15809 gcc_unreachable ();
15812 dest = operands[0];
15815 /* Shift higher 8 bytes to lower 8 bytes. */
15816 src = gen_reg_rtx (imode);
15817 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, src),
15818 gen_lowpart (TImode, operands[1]),
15824 emit_insn (unpack (dest, src));
15827 /* This function performs the same task as ix86_expand_sse_unpack,
15828 but with sse5 instructions. */
15831 ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
15833 enum machine_mode imode = GET_MODE (operands[1]);
15834 int pperm_bytes[16];
15836 int h = (high_p) ? 8 : 0;
15839 rtvec v = rtvec_alloc (16);
15842 rtx op0 = operands[0], op1 = operands[1];
15847 vs = rtvec_alloc (8);
15848 h2 = (high_p) ? 8 : 0;
15849 for (i = 0; i < 8; i++)
15851 pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
15852 pperm_bytes[2*i+1] = ((unsigned_p)
15854 : PPERM_SIGN | PPERM_SRC2 | i | h);
15857 for (i = 0; i < 16; i++)
15858 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15860 for (i = 0; i < 8; i++)
15861 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15863 p = gen_rtx_PARALLEL (VOIDmode, vs);
15864 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15866 emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
15868 emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
15872 vs = rtvec_alloc (4);
15873 h2 = (high_p) ? 4 : 0;
15874 for (i = 0; i < 4; i++)
15876 sign_extend = ((unsigned_p)
15878 : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
15879 pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
15880 pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
15881 pperm_bytes[4*i+2] = sign_extend;
15882 pperm_bytes[4*i+3] = sign_extend;
15885 for (i = 0; i < 16; i++)
15886 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15888 for (i = 0; i < 4; i++)
15889 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15891 p = gen_rtx_PARALLEL (VOIDmode, vs);
15892 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15894 emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
15896 emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
15900 vs = rtvec_alloc (2);
15901 h2 = (high_p) ? 2 : 0;
15902 for (i = 0; i < 2; i++)
15904 sign_extend = ((unsigned_p)
15906 : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
15907 pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
15908 pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
15909 pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
15910 pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
15911 pperm_bytes[8*i+4] = sign_extend;
15912 pperm_bytes[8*i+5] = sign_extend;
15913 pperm_bytes[8*i+6] = sign_extend;
15914 pperm_bytes[8*i+7] = sign_extend;
15917 for (i = 0; i < 16; i++)
15918 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15920 for (i = 0; i < 2; i++)
15921 RTVEC_ELT (vs, i) = GEN_INT (i + h2);
15923 p = gen_rtx_PARALLEL (VOIDmode, vs);
15924 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15926 emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
15928 emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
15932 gcc_unreachable ();
15938 /* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
15939 next narrower integer vector type */
15941 ix86_expand_sse5_pack (rtx operands[3])
15943 enum machine_mode imode = GET_MODE (operands[0]);
15944 int pperm_bytes[16];
15946 rtvec v = rtvec_alloc (16);
15948 rtx op0 = operands[0];
15949 rtx op1 = operands[1];
15950 rtx op2 = operands[2];
15955 for (i = 0; i < 8; i++)
15957 pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
15958 pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
15961 for (i = 0; i < 16; i++)
15962 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15964 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15965 emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
15969 for (i = 0; i < 4; i++)
15971 pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
15972 pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
15973 pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
15974 pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
15977 for (i = 0; i < 16; i++)
15978 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
15980 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
15981 emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
15985 for (i = 0; i < 2; i++)
15987 pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
15988 pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
15989 pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
15990 pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
15991 pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
15992 pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
15993 pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
15994 pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
15997 for (i = 0; i < 16; i++)
15998 RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
16000 x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
16001 emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
16005 gcc_unreachable ();
16011 /* Expand conditional increment or decrement using adb/sbb instructions.
16012 The default case using setcc followed by the conditional move can be
16013 done by generic code. */
16015 ix86_expand_int_addcc (rtx operands[])
16017 enum rtx_code code = GET_CODE (operands[1]);
16019 rtx val = const0_rtx;
16020 bool fpcmp = false;
16021 enum machine_mode mode = GET_MODE (operands[0]);
16023 if (operands[3] != const1_rtx
16024 && operands[3] != constm1_rtx)
16026 if (!ix86_expand_carry_flag_compare (code, ix86_compare_op0,
16027 ix86_compare_op1, &compare_op))
16029 code = GET_CODE (compare_op);
16031 if (GET_MODE (XEXP (compare_op, 0)) == CCFPmode
16032 || GET_MODE (XEXP (compare_op, 0)) == CCFPUmode)
16035 code = ix86_fp_compare_code_to_integer (code);
16042 PUT_CODE (compare_op,
16043 reverse_condition_maybe_unordered
16044 (GET_CODE (compare_op)));
16046 PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)));
16048 PUT_MODE (compare_op, mode);
16050 /* Construct either adc or sbb insn. */
16051 if ((code == LTU) == (operands[3] == constm1_rtx))
16053 switch (GET_MODE (operands[0]))
16056 emit_insn (gen_subqi3_carry (operands[0], operands[2], val, compare_op));
16059 emit_insn (gen_subhi3_carry (operands[0], operands[2], val, compare_op));
16062 emit_insn (gen_subsi3_carry (operands[0], operands[2], val, compare_op));
16065 emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16068 gcc_unreachable ();
16073 switch (GET_MODE (operands[0]))
16076 emit_insn (gen_addqi3_carry (operands[0], operands[2], val, compare_op));
16079 emit_insn (gen_addhi3_carry (operands[0], operands[2], val, compare_op));
16082 emit_insn (gen_addsi3_carry (operands[0], operands[2], val, compare_op));
16085 emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op));
16088 gcc_unreachable ();
16091 return 1; /* DONE */
16095 /* Split operands 0 and 1 into SImode parts. Similar to split_di, but
16096 works for floating pointer parameters and nonoffsetable memories.
16097 For pushes, it returns just stack offsets; the values will be saved
16098 in the right order. Maximally three parts are generated. */
16101 ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode)
16106 size = mode==XFmode ? 3 : GET_MODE_SIZE (mode) / 4;
16108 size = (GET_MODE_SIZE (mode) + 4) / 8;
16110 gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)));
16111 gcc_assert (size >= 2 && size <= 4);
16113 /* Optimize constant pool reference to immediates. This is used by fp
16114 moves, that force all constants to memory to allow combining. */
16115 if (MEM_P (operand) && MEM_READONLY_P (operand))
16117 rtx tmp = maybe_get_pool_constant (operand);
16122 if (MEM_P (operand) && !offsettable_memref_p (operand))
16124 /* The only non-offsetable memories we handle are pushes. */
16125 int ok = push_operand (operand, VOIDmode);
16129 operand = copy_rtx (operand);
16130 PUT_MODE (operand, Pmode);
16131 parts[0] = parts[1] = parts[2] = parts[3] = operand;
16135 if (GET_CODE (operand) == CONST_VECTOR)
16137 enum machine_mode imode = int_mode_for_mode (mode);
16138 /* Caution: if we looked through a constant pool memory above,
16139 the operand may actually have a different mode now. That's
16140 ok, since we want to pun this all the way back to an integer. */
16141 operand = simplify_subreg (imode, operand, GET_MODE (operand), 0);
16142 gcc_assert (operand != NULL);
16148 if (mode == DImode)
16149 split_di (&operand, 1, &parts[0], &parts[1]);
16154 if (REG_P (operand))
16156 gcc_assert (reload_completed);
16157 for (i = 0; i < size; i++)
16158 parts[i] = gen_rtx_REG (SImode, REGNO (operand) + i);
16160 else if (offsettable_memref_p (operand))
16162 operand = adjust_address (operand, SImode, 0);
16163 parts[0] = operand;
16164 for (i = 1; i < size; i++)
16165 parts[i] = adjust_address (operand, SImode, 4 * i);
16167 else if (GET_CODE (operand) == CONST_DOUBLE)
16172 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16176 real_to_target (l, &r, mode);
16177 parts[3] = gen_int_mode (l[3], SImode);
16178 parts[2] = gen_int_mode (l[2], SImode);
16181 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
16182 parts[2] = gen_int_mode (l[2], SImode);
16185 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
16188 gcc_unreachable ();
16190 parts[1] = gen_int_mode (l[1], SImode);
16191 parts[0] = gen_int_mode (l[0], SImode);
16194 gcc_unreachable ();
16199 if (mode == TImode)
16200 split_ti (&operand, 1, &parts[0], &parts[1]);
16201 if (mode == XFmode || mode == TFmode)
16203 enum machine_mode upper_mode = mode==XFmode ? SImode : DImode;
16204 if (REG_P (operand))
16206 gcc_assert (reload_completed);
16207 parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0);
16208 parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1);
16210 else if (offsettable_memref_p (operand))
16212 operand = adjust_address (operand, DImode, 0);
16213 parts[0] = operand;
16214 parts[1] = adjust_address (operand, upper_mode, 8);
16216 else if (GET_CODE (operand) == CONST_DOUBLE)
16221 REAL_VALUE_FROM_CONST_DOUBLE (r, operand);
16222 real_to_target (l, &r, mode);
16224 /* Do not use shift by 32 to avoid warning on 32bit systems. */
16225 if (HOST_BITS_PER_WIDE_INT >= 64)
16228 ((l[0] & (((HOST_WIDE_INT) 2 << 31) - 1))
16229 + ((((HOST_WIDE_INT) l[1]) << 31) << 1),
16232 parts[0] = immed_double_const (l[0], l[1], DImode);
16234 if (upper_mode == SImode)
16235 parts[1] = gen_int_mode (l[2], SImode);
16236 else if (HOST_BITS_PER_WIDE_INT >= 64)
16239 ((l[2] & (((HOST_WIDE_INT) 2 << 31) - 1))
16240 + ((((HOST_WIDE_INT) l[3]) << 31) << 1),
16243 parts[1] = immed_double_const (l[2], l[3], DImode);
16246 gcc_unreachable ();
16253 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
16254 Return false when normal moves are needed; true when all required
16255 insns have been emitted. Operands 2-4 contain the input values
16256 int the correct order; operands 5-7 contain the output values. */
16259 ix86_split_long_move (rtx operands[])
16264 int collisions = 0;
16265 enum machine_mode mode = GET_MODE (operands[0]);
16266 bool collisionparts[4];
16268 /* The DFmode expanders may ask us to move double.
16269 For 64bit target this is single move. By hiding the fact
16270 here we simplify i386.md splitters. */
16271 if (GET_MODE_SIZE (GET_MODE (operands[0])) == 8 && TARGET_64BIT)
16273 /* Optimize constant pool reference to immediates. This is used by
16274 fp moves, that force all constants to memory to allow combining. */
16276 if (MEM_P (operands[1])
16277 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
16278 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
16279 operands[1] = get_pool_constant (XEXP (operands[1], 0));
16280 if (push_operand (operands[0], VOIDmode))
16282 operands[0] = copy_rtx (operands[0]);
16283 PUT_MODE (operands[0], Pmode);
16286 operands[0] = gen_lowpart (DImode, operands[0]);
16287 operands[1] = gen_lowpart (DImode, operands[1]);
16288 emit_move_insn (operands[0], operands[1]);
16292 /* The only non-offsettable memory we handle is push. */
16293 if (push_operand (operands[0], VOIDmode))
16296 gcc_assert (!MEM_P (operands[0])
16297 || offsettable_memref_p (operands[0]));
16299 nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0]));
16300 ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0]));
16302 /* When emitting push, take care for source operands on the stack. */
16303 if (push && MEM_P (operands[1])
16304 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
16306 rtx src_base = XEXP (part[1][nparts - 1], 0);
16308 /* Compensate for the stack decrement by 4. */
16309 if (!TARGET_64BIT && nparts == 3
16310 && mode == XFmode && TARGET_128BIT_LONG_DOUBLE)
16311 src_base = plus_constant (src_base, 4);
16313 /* src_base refers to the stack pointer and is
16314 automatically decreased by emitted push. */
16315 for (i = 0; i < nparts; i++)
16316 part[1][i] = change_address (part[1][i],
16317 GET_MODE (part[1][i]), src_base);
16320 /* We need to do copy in the right order in case an address register
16321 of the source overlaps the destination. */
16322 if (REG_P (part[0][0]) && MEM_P (part[1][0]))
16326 for (i = 0; i < nparts; i++)
16329 = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0));
16330 if (collisionparts[i])
16334 /* Collision in the middle part can be handled by reordering. */
16335 if (collisions == 1 && nparts == 3 && collisionparts [1])
16337 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16338 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16340 else if (collisions == 1
16342 && (collisionparts [1] || collisionparts [2]))
16344 if (collisionparts [1])
16346 tmp = part[0][1]; part[0][1] = part[0][2]; part[0][2] = tmp;
16347 tmp = part[1][1]; part[1][1] = part[1][2]; part[1][2] = tmp;
16351 tmp = part[0][2]; part[0][2] = part[0][3]; part[0][3] = tmp;
16352 tmp = part[1][2]; part[1][2] = part[1][3]; part[1][3] = tmp;
16356 /* If there are more collisions, we can't handle it by reordering.
16357 Do an lea to the last part and use only one colliding move. */
16358 else if (collisions > 1)
16364 base = part[0][nparts - 1];
16366 /* Handle the case when the last part isn't valid for lea.
16367 Happens in 64-bit mode storing the 12-byte XFmode. */
16368 if (GET_MODE (base) != Pmode)
16369 base = gen_rtx_REG (Pmode, REGNO (base));
16371 emit_insn (gen_rtx_SET (VOIDmode, base, XEXP (part[1][0], 0)));
16372 part[1][0] = replace_equiv_address (part[1][0], base);
16373 for (i = 1; i < nparts; i++)
16375 tmp = plus_constant (base, UNITS_PER_WORD * i);
16376 part[1][i] = replace_equiv_address (part[1][i], tmp);
16387 if (TARGET_128BIT_LONG_DOUBLE && mode == XFmode)
16388 emit_insn (gen_addsi3 (stack_pointer_rtx,
16389 stack_pointer_rtx, GEN_INT (-4)));
16390 emit_move_insn (part[0][2], part[1][2]);
16392 else if (nparts == 4)
16394 emit_move_insn (part[0][3], part[1][3]);
16395 emit_move_insn (part[0][2], part[1][2]);
16400 /* In 64bit mode we don't have 32bit push available. In case this is
16401 register, it is OK - we will just use larger counterpart. We also
16402 retype memory - these comes from attempt to avoid REX prefix on
16403 moving of second half of TFmode value. */
16404 if (GET_MODE (part[1][1]) == SImode)
16406 switch (GET_CODE (part[1][1]))
16409 part[1][1] = adjust_address (part[1][1], DImode, 0);
16413 part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1]));
16417 gcc_unreachable ();
16420 if (GET_MODE (part[1][0]) == SImode)
16421 part[1][0] = part[1][1];
16424 emit_move_insn (part[0][1], part[1][1]);
16425 emit_move_insn (part[0][0], part[1][0]);
16429 /* Choose correct order to not overwrite the source before it is copied. */
16430 if ((REG_P (part[0][0])
16431 && REG_P (part[1][1])
16432 && (REGNO (part[0][0]) == REGNO (part[1][1])
16434 && REGNO (part[0][0]) == REGNO (part[1][2]))
16436 && REGNO (part[0][0]) == REGNO (part[1][3]))))
16438 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0))))
16440 for (i = 0, j = nparts - 1; i < nparts; i++, j--)
16442 operands[2 + i] = part[0][j];
16443 operands[6 + i] = part[1][j];
16448 for (i = 0; i < nparts; i++)
16450 operands[2 + i] = part[0][i];
16451 operands[6 + i] = part[1][i];
16455 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
16456 if (optimize_insn_for_size_p ())
16458 for (j = 0; j < nparts - 1; j++)
16459 if (CONST_INT_P (operands[6 + j])
16460 && operands[6 + j] != const0_rtx
16461 && REG_P (operands[2 + j]))
16462 for (i = j; i < nparts - 1; i++)
16463 if (CONST_INT_P (operands[7 + i])
16464 && INTVAL (operands[7 + i]) == INTVAL (operands[6 + j]))
16465 operands[7 + i] = operands[2 + j];
16468 for (i = 0; i < nparts; i++)
16469 emit_move_insn (operands[2 + i], operands[6 + i]);
16474 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
16475 left shift by a constant, either using a single shift or
16476 a sequence of add instructions. */
16479 ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode)
16483 emit_insn ((mode == DImode
16485 : gen_adddi3) (operand, operand, operand));
16487 else if (!optimize_insn_for_size_p ()
16488 && count * ix86_cost->add <= ix86_cost->shift_const)
16491 for (i=0; i<count; i++)
16493 emit_insn ((mode == DImode
16495 : gen_adddi3) (operand, operand, operand));
16499 emit_insn ((mode == DImode
16501 : gen_ashldi3) (operand, operand, GEN_INT (count)));
16505 ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode)
16507 rtx low[2], high[2];
16509 const int single_width = mode == DImode ? 32 : 64;
16511 if (CONST_INT_P (operands[2]))
16513 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16514 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16516 if (count >= single_width)
16518 emit_move_insn (high[0], low[1]);
16519 emit_move_insn (low[0], const0_rtx);
16521 if (count > single_width)
16522 ix86_expand_ashl_const (high[0], count - single_width, mode);
16526 if (!rtx_equal_p (operands[0], operands[1]))
16527 emit_move_insn (operands[0], operands[1]);
16528 emit_insn ((mode == DImode
16530 : gen_x86_64_shld) (high[0], low[0], GEN_INT (count)));
16531 ix86_expand_ashl_const (low[0], count, mode);
16536 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16538 if (operands[1] == const1_rtx)
16540 /* Assuming we've chosen a QImode capable registers, then 1 << N
16541 can be done with two 32/64-bit shifts, no branches, no cmoves. */
16542 if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0]))
16544 rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG);
16546 ix86_expand_clear (low[0]);
16547 ix86_expand_clear (high[0]);
16548 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width)));
16550 d = gen_lowpart (QImode, low[0]);
16551 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16552 s = gen_rtx_EQ (QImode, flags, const0_rtx);
16553 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16555 d = gen_lowpart (QImode, high[0]);
16556 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d);
16557 s = gen_rtx_NE (QImode, flags, const0_rtx);
16558 emit_insn (gen_rtx_SET (VOIDmode, d, s));
16561 /* Otherwise, we can get the same results by manually performing
16562 a bit extract operation on bit 5/6, and then performing the two
16563 shifts. The two methods of getting 0/1 into low/high are exactly
16564 the same size. Avoiding the shift in the bit extract case helps
16565 pentium4 a bit; no one else seems to care much either way. */
16570 if (TARGET_PARTIAL_REG_STALL && !optimize_insn_for_size_p ())
16571 x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]);
16573 x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]);
16574 emit_insn (gen_rtx_SET (VOIDmode, high[0], x));
16576 emit_insn ((mode == DImode
16578 : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6)));
16579 emit_insn ((mode == DImode
16581 : gen_anddi3) (high[0], high[0], GEN_INT (1)));
16582 emit_move_insn (low[0], high[0]);
16583 emit_insn ((mode == DImode
16585 : gen_xordi3) (low[0], low[0], GEN_INT (1)));
16588 emit_insn ((mode == DImode
16590 : gen_ashldi3) (low[0], low[0], operands[2]));
16591 emit_insn ((mode == DImode
16593 : gen_ashldi3) (high[0], high[0], operands[2]));
16597 if (operands[1] == constm1_rtx)
16599 /* For -1 << N, we can avoid the shld instruction, because we
16600 know that we're shifting 0...31/63 ones into a -1. */
16601 emit_move_insn (low[0], constm1_rtx);
16602 if (optimize_insn_for_size_p ())
16603 emit_move_insn (high[0], low[0]);
16605 emit_move_insn (high[0], constm1_rtx);
16609 if (!rtx_equal_p (operands[0], operands[1]))
16610 emit_move_insn (operands[0], operands[1]);
16612 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16613 emit_insn ((mode == DImode
16615 : gen_x86_64_shld) (high[0], low[0], operands[2]));
16618 emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2]));
16620 if (TARGET_CMOVE && scratch)
16622 ix86_expand_clear (scratch);
16623 emit_insn ((mode == DImode
16624 ? gen_x86_shift_adj_1
16625 : gen_x86_64_shift_adj_1) (high[0], low[0], operands[2],
16629 emit_insn ((mode == DImode
16630 ? gen_x86_shift_adj_2
16631 : gen_x86_64_shift_adj_2) (high[0], low[0], operands[2]));
16635 ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode)
16637 rtx low[2], high[2];
16639 const int single_width = mode == DImode ? 32 : 64;
16641 if (CONST_INT_P (operands[2]))
16643 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16644 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16646 if (count == single_width * 2 - 1)
16648 emit_move_insn (high[0], high[1]);
16649 emit_insn ((mode == DImode
16651 : gen_ashrdi3) (high[0], high[0],
16652 GEN_INT (single_width - 1)));
16653 emit_move_insn (low[0], high[0]);
16656 else if (count >= single_width)
16658 emit_move_insn (low[0], high[1]);
16659 emit_move_insn (high[0], low[0]);
16660 emit_insn ((mode == DImode
16662 : gen_ashrdi3) (high[0], high[0],
16663 GEN_INT (single_width - 1)));
16664 if (count > single_width)
16665 emit_insn ((mode == DImode
16667 : gen_ashrdi3) (low[0], low[0],
16668 GEN_INT (count - single_width)));
16672 if (!rtx_equal_p (operands[0], operands[1]))
16673 emit_move_insn (operands[0], operands[1]);
16674 emit_insn ((mode == DImode
16676 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16677 emit_insn ((mode == DImode
16679 : gen_ashrdi3) (high[0], high[0], GEN_INT (count)));
16684 if (!rtx_equal_p (operands[0], operands[1]))
16685 emit_move_insn (operands[0], operands[1]);
16687 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16689 emit_insn ((mode == DImode
16691 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16692 emit_insn ((mode == DImode
16694 : gen_ashrdi3) (high[0], high[0], operands[2]));
16696 if (TARGET_CMOVE && scratch)
16698 emit_move_insn (scratch, high[0]);
16699 emit_insn ((mode == DImode
16701 : gen_ashrdi3) (scratch, scratch,
16702 GEN_INT (single_width - 1)));
16703 emit_insn ((mode == DImode
16704 ? gen_x86_shift_adj_1
16705 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16709 emit_insn ((mode == DImode
16710 ? gen_x86_shift_adj_3
16711 : gen_x86_64_shift_adj_3) (low[0], high[0], operands[2]));
16716 ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode)
16718 rtx low[2], high[2];
16720 const int single_width = mode == DImode ? 32 : 64;
16722 if (CONST_INT_P (operands[2]))
16724 (mode == DImode ? split_di : split_ti) (operands, 2, low, high);
16725 count = INTVAL (operands[2]) & (single_width * 2 - 1);
16727 if (count >= single_width)
16729 emit_move_insn (low[0], high[1]);
16730 ix86_expand_clear (high[0]);
16732 if (count > single_width)
16733 emit_insn ((mode == DImode
16735 : gen_lshrdi3) (low[0], low[0],
16736 GEN_INT (count - single_width)));
16740 if (!rtx_equal_p (operands[0], operands[1]))
16741 emit_move_insn (operands[0], operands[1]);
16742 emit_insn ((mode == DImode
16744 : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count)));
16745 emit_insn ((mode == DImode
16747 : gen_lshrdi3) (high[0], high[0], GEN_INT (count)));
16752 if (!rtx_equal_p (operands[0], operands[1]))
16753 emit_move_insn (operands[0], operands[1]);
16755 (mode == DImode ? split_di : split_ti) (operands, 1, low, high);
16757 emit_insn ((mode == DImode
16759 : gen_x86_64_shrd) (low[0], high[0], operands[2]));
16760 emit_insn ((mode == DImode
16762 : gen_lshrdi3) (high[0], high[0], operands[2]));
16764 /* Heh. By reversing the arguments, we can reuse this pattern. */
16765 if (TARGET_CMOVE && scratch)
16767 ix86_expand_clear (scratch);
16768 emit_insn ((mode == DImode
16769 ? gen_x86_shift_adj_1
16770 : gen_x86_64_shift_adj_1) (low[0], high[0], operands[2],
16774 emit_insn ((mode == DImode
16775 ? gen_x86_shift_adj_2
16776 : gen_x86_64_shift_adj_2) (low[0], high[0], operands[2]));
16780 /* Predict just emitted jump instruction to be taken with probability PROB. */
16782 predict_jump (int prob)
16784 rtx insn = get_last_insn ();
16785 gcc_assert (JUMP_P (insn));
16787 = gen_rtx_EXPR_LIST (REG_BR_PROB,
16792 /* Helper function for the string operations below. Dest VARIABLE whether
16793 it is aligned to VALUE bytes. If true, jump to the label. */
16795 ix86_expand_aligntest (rtx variable, int value, bool epilogue)
16797 rtx label = gen_label_rtx ();
16798 rtx tmpcount = gen_reg_rtx (GET_MODE (variable));
16799 if (GET_MODE (variable) == DImode)
16800 emit_insn (gen_anddi3 (tmpcount, variable, GEN_INT (value)));
16802 emit_insn (gen_andsi3 (tmpcount, variable, GEN_INT (value)));
16803 emit_cmp_and_jump_insns (tmpcount, const0_rtx, EQ, 0, GET_MODE (variable),
16806 predict_jump (REG_BR_PROB_BASE * 50 / 100);
16808 predict_jump (REG_BR_PROB_BASE * 90 / 100);
16812 /* Adjust COUNTER by the VALUE. */
16814 ix86_adjust_counter (rtx countreg, HOST_WIDE_INT value)
16816 if (GET_MODE (countreg) == DImode)
16817 emit_insn (gen_adddi3 (countreg, countreg, GEN_INT (-value)));
16819 emit_insn (gen_addsi3 (countreg, countreg, GEN_INT (-value)));
16822 /* Zero extend possibly SImode EXP to Pmode register. */
16824 ix86_zero_extend_to_Pmode (rtx exp)
16827 if (GET_MODE (exp) == VOIDmode)
16828 return force_reg (Pmode, exp);
16829 if (GET_MODE (exp) == Pmode)
16830 return copy_to_mode_reg (Pmode, exp);
16831 r = gen_reg_rtx (Pmode);
16832 emit_insn (gen_zero_extendsidi2 (r, exp));
16836 /* Divide COUNTREG by SCALE. */
16838 scale_counter (rtx countreg, int scale)
16841 rtx piece_size_mask;
16845 if (CONST_INT_P (countreg))
16846 return GEN_INT (INTVAL (countreg) / scale);
16847 gcc_assert (REG_P (countreg));
16849 piece_size_mask = GEN_INT (scale - 1);
16850 sc = expand_simple_binop (GET_MODE (countreg), LSHIFTRT, countreg,
16851 GEN_INT (exact_log2 (scale)),
16852 NULL, 1, OPTAB_DIRECT);
16856 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
16857 DImode for constant loop counts. */
16859 static enum machine_mode
16860 counter_mode (rtx count_exp)
16862 if (GET_MODE (count_exp) != VOIDmode)
16863 return GET_MODE (count_exp);
16864 if (GET_CODE (count_exp) != CONST_INT)
16866 if (TARGET_64BIT && (INTVAL (count_exp) & ~0xffffffff))
16871 /* When SRCPTR is non-NULL, output simple loop to move memory
16872 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
16873 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
16874 equivalent loop to set memory by VALUE (supposed to be in MODE).
16876 The size is rounded down to whole number of chunk size moved at once.
16877 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
16881 expand_set_or_movmem_via_loop (rtx destmem, rtx srcmem,
16882 rtx destptr, rtx srcptr, rtx value,
16883 rtx count, enum machine_mode mode, int unroll,
16886 rtx out_label, top_label, iter, tmp;
16887 enum machine_mode iter_mode = counter_mode (count);
16888 rtx piece_size = GEN_INT (GET_MODE_SIZE (mode) * unroll);
16889 rtx piece_size_mask = GEN_INT (~((GET_MODE_SIZE (mode) * unroll) - 1));
16895 top_label = gen_label_rtx ();
16896 out_label = gen_label_rtx ();
16897 iter = gen_reg_rtx (iter_mode);
16899 size = expand_simple_binop (iter_mode, AND, count, piece_size_mask,
16900 NULL, 1, OPTAB_DIRECT);
16901 /* Those two should combine. */
16902 if (piece_size == const1_rtx)
16904 emit_cmp_and_jump_insns (size, const0_rtx, EQ, NULL_RTX, iter_mode,
16906 predict_jump (REG_BR_PROB_BASE * 10 / 100);
16908 emit_move_insn (iter, const0_rtx);
16910 emit_label (top_label);
16912 tmp = convert_modes (Pmode, iter_mode, iter, true);
16913 x_addr = gen_rtx_PLUS (Pmode, destptr, tmp);
16914 destmem = change_address (destmem, mode, x_addr);
16918 y_addr = gen_rtx_PLUS (Pmode, srcptr, copy_rtx (tmp));
16919 srcmem = change_address (srcmem, mode, y_addr);
16921 /* When unrolling for chips that reorder memory reads and writes,
16922 we can save registers by using single temporary.
16923 Also using 4 temporaries is overkill in 32bit mode. */
16924 if (!TARGET_64BIT && 0)
16926 for (i = 0; i < unroll; i++)
16931 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16933 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16935 emit_move_insn (destmem, srcmem);
16941 gcc_assert (unroll <= 4);
16942 for (i = 0; i < unroll; i++)
16944 tmpreg[i] = gen_reg_rtx (mode);
16948 adjust_address (copy_rtx (srcmem), mode, GET_MODE_SIZE (mode));
16950 emit_move_insn (tmpreg[i], srcmem);
16952 for (i = 0; i < unroll; i++)
16957 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16959 emit_move_insn (destmem, tmpreg[i]);
16964 for (i = 0; i < unroll; i++)
16968 adjust_address (copy_rtx (destmem), mode, GET_MODE_SIZE (mode));
16969 emit_move_insn (destmem, value);
16972 tmp = expand_simple_binop (iter_mode, PLUS, iter, piece_size, iter,
16973 true, OPTAB_LIB_WIDEN);
16975 emit_move_insn (iter, tmp);
16977 emit_cmp_and_jump_insns (iter, size, LT, NULL_RTX, iter_mode,
16979 if (expected_size != -1)
16981 expected_size /= GET_MODE_SIZE (mode) * unroll;
16982 if (expected_size == 0)
16984 else if (expected_size > REG_BR_PROB_BASE)
16985 predict_jump (REG_BR_PROB_BASE - 1);
16987 predict_jump (REG_BR_PROB_BASE - (REG_BR_PROB_BASE + expected_size / 2) / expected_size);
16990 predict_jump (REG_BR_PROB_BASE * 80 / 100);
16991 iter = ix86_zero_extend_to_Pmode (iter);
16992 tmp = expand_simple_binop (Pmode, PLUS, destptr, iter, destptr,
16993 true, OPTAB_LIB_WIDEN);
16994 if (tmp != destptr)
16995 emit_move_insn (destptr, tmp);
16998 tmp = expand_simple_binop (Pmode, PLUS, srcptr, iter, srcptr,
16999 true, OPTAB_LIB_WIDEN);
17001 emit_move_insn (srcptr, tmp);
17003 emit_label (out_label);
17006 /* Output "rep; mov" instruction.
17007 Arguments have same meaning as for previous function */
17009 expand_movmem_via_rep_mov (rtx destmem, rtx srcmem,
17010 rtx destptr, rtx srcptr,
17012 enum machine_mode mode)
17018 /* If the size is known, it is shorter to use rep movs. */
17019 if (mode == QImode && CONST_INT_P (count)
17020 && !(INTVAL (count) & 3))
17023 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17024 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17025 if (srcptr != XEXP (srcmem, 0) || GET_MODE (srcmem) != BLKmode)
17026 srcmem = adjust_automodify_address_nv (srcmem, BLKmode, srcptr, 0);
17027 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17028 if (mode != QImode)
17030 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17031 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17032 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17033 srcexp = gen_rtx_ASHIFT (Pmode, countreg,
17034 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17035 srcexp = gen_rtx_PLUS (Pmode, srcexp, srcptr);
17039 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17040 srcexp = gen_rtx_PLUS (Pmode, srcptr, countreg);
17042 if (CONST_INT_P (count))
17044 count = GEN_INT (INTVAL (count)
17045 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17046 destmem = shallow_copy_rtx (destmem);
17047 srcmem = shallow_copy_rtx (srcmem);
17048 set_mem_size (destmem, count);
17049 set_mem_size (srcmem, count);
17053 if (MEM_SIZE (destmem))
17054 set_mem_size (destmem, NULL_RTX);
17055 if (MEM_SIZE (srcmem))
17056 set_mem_size (srcmem, NULL_RTX);
17058 emit_insn (gen_rep_mov (destptr, destmem, srcptr, srcmem, countreg,
17062 /* Output "rep; stos" instruction.
17063 Arguments have same meaning as for previous function */
17065 expand_setmem_via_rep_stos (rtx destmem, rtx destptr, rtx value,
17066 rtx count, enum machine_mode mode,
17072 if (destptr != XEXP (destmem, 0) || GET_MODE (destmem) != BLKmode)
17073 destmem = adjust_automodify_address_nv (destmem, BLKmode, destptr, 0);
17074 value = force_reg (mode, gen_lowpart (mode, value));
17075 countreg = ix86_zero_extend_to_Pmode (scale_counter (count, GET_MODE_SIZE (mode)));
17076 if (mode != QImode)
17078 destexp = gen_rtx_ASHIFT (Pmode, countreg,
17079 GEN_INT (exact_log2 (GET_MODE_SIZE (mode))));
17080 destexp = gen_rtx_PLUS (Pmode, destexp, destptr);
17083 destexp = gen_rtx_PLUS (Pmode, destptr, countreg);
17084 if (orig_value == const0_rtx && CONST_INT_P (count))
17086 count = GEN_INT (INTVAL (count)
17087 & ~((HOST_WIDE_INT) GET_MODE_SIZE (mode) - 1));
17088 destmem = shallow_copy_rtx (destmem);
17089 set_mem_size (destmem, count);
17091 else if (MEM_SIZE (destmem))
17092 set_mem_size (destmem, NULL_RTX);
17093 emit_insn (gen_rep_stos (destptr, countreg, destmem, value, destexp));
17097 emit_strmov (rtx destmem, rtx srcmem,
17098 rtx destptr, rtx srcptr, enum machine_mode mode, int offset)
17100 rtx src = adjust_automodify_address_nv (srcmem, mode, srcptr, offset);
17101 rtx dest = adjust_automodify_address_nv (destmem, mode, destptr, offset);
17102 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17105 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
17107 expand_movmem_epilogue (rtx destmem, rtx srcmem,
17108 rtx destptr, rtx srcptr, rtx count, int max_size)
17111 if (CONST_INT_P (count))
17113 HOST_WIDE_INT countval = INTVAL (count);
17116 if ((countval & 0x10) && max_size > 16)
17120 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17121 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset + 8);
17124 gcc_unreachable ();
17127 if ((countval & 0x08) && max_size > 8)
17130 emit_strmov (destmem, srcmem, destptr, srcptr, DImode, offset);
17133 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17134 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset + 4);
17138 if ((countval & 0x04) && max_size > 4)
17140 emit_strmov (destmem, srcmem, destptr, srcptr, SImode, offset);
17143 if ((countval & 0x02) && max_size > 2)
17145 emit_strmov (destmem, srcmem, destptr, srcptr, HImode, offset);
17148 if ((countval & 0x01) && max_size > 1)
17150 emit_strmov (destmem, srcmem, destptr, srcptr, QImode, offset);
17157 count = expand_simple_binop (GET_MODE (count), AND, count, GEN_INT (max_size - 1),
17158 count, 1, OPTAB_DIRECT);
17159 expand_set_or_movmem_via_loop (destmem, srcmem, destptr, srcptr, NULL,
17160 count, QImode, 1, 4);
17164 /* When there are stringops, we can cheaply increase dest and src pointers.
17165 Otherwise we save code size by maintaining offset (zero is readily
17166 available from preceding rep operation) and using x86 addressing modes.
17168 if (TARGET_SINGLE_STRINGOP)
17172 rtx label = ix86_expand_aligntest (count, 4, true);
17173 src = change_address (srcmem, SImode, srcptr);
17174 dest = change_address (destmem, SImode, destptr);
17175 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17176 emit_label (label);
17177 LABEL_NUSES (label) = 1;
17181 rtx label = ix86_expand_aligntest (count, 2, true);
17182 src = change_address (srcmem, HImode, srcptr);
17183 dest = change_address (destmem, HImode, destptr);
17184 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17185 emit_label (label);
17186 LABEL_NUSES (label) = 1;
17190 rtx label = ix86_expand_aligntest (count, 1, true);
17191 src = change_address (srcmem, QImode, srcptr);
17192 dest = change_address (destmem, QImode, destptr);
17193 emit_insn (gen_strmov (destptr, dest, srcptr, src));
17194 emit_label (label);
17195 LABEL_NUSES (label) = 1;
17200 rtx offset = force_reg (Pmode, const0_rtx);
17205 rtx label = ix86_expand_aligntest (count, 4, true);
17206 src = change_address (srcmem, SImode, srcptr);
17207 dest = change_address (destmem, SImode, destptr);
17208 emit_move_insn (dest, src);
17209 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (4), NULL,
17210 true, OPTAB_LIB_WIDEN);
17212 emit_move_insn (offset, tmp);
17213 emit_label (label);
17214 LABEL_NUSES (label) = 1;
17218 rtx label = ix86_expand_aligntest (count, 2, true);
17219 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17220 src = change_address (srcmem, HImode, tmp);
17221 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17222 dest = change_address (destmem, HImode, tmp);
17223 emit_move_insn (dest, src);
17224 tmp = expand_simple_binop (Pmode, PLUS, offset, GEN_INT (2), tmp,
17225 true, OPTAB_LIB_WIDEN);
17227 emit_move_insn (offset, tmp);
17228 emit_label (label);
17229 LABEL_NUSES (label) = 1;
17233 rtx label = ix86_expand_aligntest (count, 1, true);
17234 tmp = gen_rtx_PLUS (Pmode, srcptr, offset);
17235 src = change_address (srcmem, QImode, tmp);
17236 tmp = gen_rtx_PLUS (Pmode, destptr, offset);
17237 dest = change_address (destmem, QImode, tmp);
17238 emit_move_insn (dest, src);
17239 emit_label (label);
17240 LABEL_NUSES (label) = 1;
17245 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17247 expand_setmem_epilogue_via_loop (rtx destmem, rtx destptr, rtx value,
17248 rtx count, int max_size)
17251 expand_simple_binop (counter_mode (count), AND, count,
17252 GEN_INT (max_size - 1), count, 1, OPTAB_DIRECT);
17253 expand_set_or_movmem_via_loop (destmem, NULL, destptr, NULL,
17254 gen_lowpart (QImode, value), count, QImode,
17258 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
17260 expand_setmem_epilogue (rtx destmem, rtx destptr, rtx value, rtx count, int max_size)
17264 if (CONST_INT_P (count))
17266 HOST_WIDE_INT countval = INTVAL (count);
17269 if ((countval & 0x10) && max_size > 16)
17273 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17274 emit_insn (gen_strset (destptr, dest, value));
17275 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset + 8);
17276 emit_insn (gen_strset (destptr, dest, value));
17279 gcc_unreachable ();
17282 if ((countval & 0x08) && max_size > 8)
17286 dest = adjust_automodify_address_nv (destmem, DImode, destptr, offset);
17287 emit_insn (gen_strset (destptr, dest, value));
17291 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17292 emit_insn (gen_strset (destptr, dest, value));
17293 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset + 4);
17294 emit_insn (gen_strset (destptr, dest, value));
17298 if ((countval & 0x04) && max_size > 4)
17300 dest = adjust_automodify_address_nv (destmem, SImode, destptr, offset);
17301 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17304 if ((countval & 0x02) && max_size > 2)
17306 dest = adjust_automodify_address_nv (destmem, HImode, destptr, offset);
17307 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17310 if ((countval & 0x01) && max_size > 1)
17312 dest = adjust_automodify_address_nv (destmem, QImode, destptr, offset);
17313 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17320 expand_setmem_epilogue_via_loop (destmem, destptr, value, count, max_size);
17325 rtx label = ix86_expand_aligntest (count, 16, true);
17328 dest = change_address (destmem, DImode, destptr);
17329 emit_insn (gen_strset (destptr, dest, value));
17330 emit_insn (gen_strset (destptr, dest, value));
17334 dest = change_address (destmem, SImode, destptr);
17335 emit_insn (gen_strset (destptr, dest, value));
17336 emit_insn (gen_strset (destptr, dest, value));
17337 emit_insn (gen_strset (destptr, dest, value));
17338 emit_insn (gen_strset (destptr, dest, value));
17340 emit_label (label);
17341 LABEL_NUSES (label) = 1;
17345 rtx label = ix86_expand_aligntest (count, 8, true);
17348 dest = change_address (destmem, DImode, destptr);
17349 emit_insn (gen_strset (destptr, dest, value));
17353 dest = change_address (destmem, SImode, destptr);
17354 emit_insn (gen_strset (destptr, dest, value));
17355 emit_insn (gen_strset (destptr, dest, value));
17357 emit_label (label);
17358 LABEL_NUSES (label) = 1;
17362 rtx label = ix86_expand_aligntest (count, 4, true);
17363 dest = change_address (destmem, SImode, destptr);
17364 emit_insn (gen_strset (destptr, dest, gen_lowpart (SImode, value)));
17365 emit_label (label);
17366 LABEL_NUSES (label) = 1;
17370 rtx label = ix86_expand_aligntest (count, 2, true);
17371 dest = change_address (destmem, HImode, destptr);
17372 emit_insn (gen_strset (destptr, dest, gen_lowpart (HImode, value)));
17373 emit_label (label);
17374 LABEL_NUSES (label) = 1;
17378 rtx label = ix86_expand_aligntest (count, 1, true);
17379 dest = change_address (destmem, QImode, destptr);
17380 emit_insn (gen_strset (destptr, dest, gen_lowpart (QImode, value)));
17381 emit_label (label);
17382 LABEL_NUSES (label) = 1;
17386 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
17387 DESIRED_ALIGNMENT. */
17389 expand_movmem_prologue (rtx destmem, rtx srcmem,
17390 rtx destptr, rtx srcptr, rtx count,
17391 int align, int desired_alignment)
17393 if (align <= 1 && desired_alignment > 1)
17395 rtx label = ix86_expand_aligntest (destptr, 1, false);
17396 srcmem = change_address (srcmem, QImode, srcptr);
17397 destmem = change_address (destmem, QImode, destptr);
17398 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17399 ix86_adjust_counter (count, 1);
17400 emit_label (label);
17401 LABEL_NUSES (label) = 1;
17403 if (align <= 2 && desired_alignment > 2)
17405 rtx label = ix86_expand_aligntest (destptr, 2, false);
17406 srcmem = change_address (srcmem, HImode, srcptr);
17407 destmem = change_address (destmem, HImode, destptr);
17408 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17409 ix86_adjust_counter (count, 2);
17410 emit_label (label);
17411 LABEL_NUSES (label) = 1;
17413 if (align <= 4 && desired_alignment > 4)
17415 rtx label = ix86_expand_aligntest (destptr, 4, false);
17416 srcmem = change_address (srcmem, SImode, srcptr);
17417 destmem = change_address (destmem, SImode, destptr);
17418 emit_insn (gen_strmov (destptr, destmem, srcptr, srcmem));
17419 ix86_adjust_counter (count, 4);
17420 emit_label (label);
17421 LABEL_NUSES (label) = 1;
17423 gcc_assert (desired_alignment <= 8);
17426 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
17427 ALIGN_BYTES is how many bytes need to be copied. */
17429 expand_constant_movmem_prologue (rtx dst, rtx *srcp, rtx destreg, rtx srcreg,
17430 int desired_align, int align_bytes)
17433 rtx src_size, dst_size;
17435 int src_align_bytes = get_mem_align_offset (src, desired_align * BITS_PER_UNIT);
17436 if (src_align_bytes >= 0)
17437 src_align_bytes = desired_align - src_align_bytes;
17438 src_size = MEM_SIZE (src);
17439 dst_size = MEM_SIZE (dst);
17440 if (align_bytes & 1)
17442 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17443 src = adjust_automodify_address_nv (src, QImode, srcreg, 0);
17445 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17447 if (align_bytes & 2)
17449 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17450 src = adjust_automodify_address_nv (src, HImode, srcreg, off);
17451 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17452 set_mem_align (dst, 2 * BITS_PER_UNIT);
17453 if (src_align_bytes >= 0
17454 && (src_align_bytes & 1) == (align_bytes & 1)
17455 && MEM_ALIGN (src) < 2 * BITS_PER_UNIT)
17456 set_mem_align (src, 2 * BITS_PER_UNIT);
17458 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17460 if (align_bytes & 4)
17462 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17463 src = adjust_automodify_address_nv (src, SImode, srcreg, off);
17464 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17465 set_mem_align (dst, 4 * BITS_PER_UNIT);
17466 if (src_align_bytes >= 0)
17468 unsigned int src_align = 0;
17469 if ((src_align_bytes & 3) == (align_bytes & 3))
17471 else if ((src_align_bytes & 1) == (align_bytes & 1))
17473 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17474 set_mem_align (src, src_align * BITS_PER_UNIT);
17477 emit_insn (gen_strmov (destreg, dst, srcreg, src));
17479 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17480 src = adjust_automodify_address_nv (src, BLKmode, srcreg, off);
17481 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17482 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17483 if (src_align_bytes >= 0)
17485 unsigned int src_align = 0;
17486 if ((src_align_bytes & 7) == (align_bytes & 7))
17488 else if ((src_align_bytes & 3) == (align_bytes & 3))
17490 else if ((src_align_bytes & 1) == (align_bytes & 1))
17492 if (src_align > (unsigned int) desired_align)
17493 src_align = desired_align;
17494 if (MEM_ALIGN (src) < src_align * BITS_PER_UNIT)
17495 set_mem_align (src, src_align * BITS_PER_UNIT);
17498 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17500 set_mem_size (dst, GEN_INT (INTVAL (src_size) - align_bytes));
17505 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
17506 DESIRED_ALIGNMENT. */
17508 expand_setmem_prologue (rtx destmem, rtx destptr, rtx value, rtx count,
17509 int align, int desired_alignment)
17511 if (align <= 1 && desired_alignment > 1)
17513 rtx label = ix86_expand_aligntest (destptr, 1, false);
17514 destmem = change_address (destmem, QImode, destptr);
17515 emit_insn (gen_strset (destptr, destmem, gen_lowpart (QImode, value)));
17516 ix86_adjust_counter (count, 1);
17517 emit_label (label);
17518 LABEL_NUSES (label) = 1;
17520 if (align <= 2 && desired_alignment > 2)
17522 rtx label = ix86_expand_aligntest (destptr, 2, false);
17523 destmem = change_address (destmem, HImode, destptr);
17524 emit_insn (gen_strset (destptr, destmem, gen_lowpart (HImode, value)));
17525 ix86_adjust_counter (count, 2);
17526 emit_label (label);
17527 LABEL_NUSES (label) = 1;
17529 if (align <= 4 && desired_alignment > 4)
17531 rtx label = ix86_expand_aligntest (destptr, 4, false);
17532 destmem = change_address (destmem, SImode, destptr);
17533 emit_insn (gen_strset (destptr, destmem, gen_lowpart (SImode, value)));
17534 ix86_adjust_counter (count, 4);
17535 emit_label (label);
17536 LABEL_NUSES (label) = 1;
17538 gcc_assert (desired_alignment <= 8);
17541 /* Set enough from DST to align DST known to by aligned by ALIGN to
17542 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
17544 expand_constant_setmem_prologue (rtx dst, rtx destreg, rtx value,
17545 int desired_align, int align_bytes)
17548 rtx dst_size = MEM_SIZE (dst);
17549 if (align_bytes & 1)
17551 dst = adjust_automodify_address_nv (dst, QImode, destreg, 0);
17553 emit_insn (gen_strset (destreg, dst,
17554 gen_lowpart (QImode, value)));
17556 if (align_bytes & 2)
17558 dst = adjust_automodify_address_nv (dst, HImode, destreg, off);
17559 if (MEM_ALIGN (dst) < 2 * BITS_PER_UNIT)
17560 set_mem_align (dst, 2 * BITS_PER_UNIT);
17562 emit_insn (gen_strset (destreg, dst,
17563 gen_lowpart (HImode, value)));
17565 if (align_bytes & 4)
17567 dst = adjust_automodify_address_nv (dst, SImode, destreg, off);
17568 if (MEM_ALIGN (dst) < 4 * BITS_PER_UNIT)
17569 set_mem_align (dst, 4 * BITS_PER_UNIT);
17571 emit_insn (gen_strset (destreg, dst,
17572 gen_lowpart (SImode, value)));
17574 dst = adjust_automodify_address_nv (dst, BLKmode, destreg, off);
17575 if (MEM_ALIGN (dst) < (unsigned int) desired_align * BITS_PER_UNIT)
17576 set_mem_align (dst, desired_align * BITS_PER_UNIT);
17578 set_mem_size (dst, GEN_INT (INTVAL (dst_size) - align_bytes));
17582 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
17583 static enum stringop_alg
17584 decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, bool memset,
17585 int *dynamic_check)
17587 const struct stringop_algs * algs;
17588 bool optimize_for_speed;
17589 /* Algorithms using the rep prefix want at least edi and ecx;
17590 additionally, memset wants eax and memcpy wants esi. Don't
17591 consider such algorithms if the user has appropriated those
17592 registers for their own purposes. */
17593 bool rep_prefix_usable = !(fixed_regs[CX_REG] || fixed_regs[DI_REG]
17595 ? fixed_regs[AX_REG] : fixed_regs[SI_REG]));
17597 #define ALG_USABLE_P(alg) (rep_prefix_usable \
17598 || (alg != rep_prefix_1_byte \
17599 && alg != rep_prefix_4_byte \
17600 && alg != rep_prefix_8_byte))
17601 const struct processor_costs *cost;
17603 /* Even if the string operation call is cold, we still might spend a lot
17604 of time processing large blocks. */
17605 if (optimize_function_for_size_p (cfun)
17606 || (optimize_insn_for_size_p ()
17607 && expected_size != -1 && expected_size < 256))
17608 optimize_for_speed = false;
17610 optimize_for_speed = true;
17612 cost = optimize_for_speed ? ix86_cost : &ix86_size_cost;
17614 *dynamic_check = -1;
17616 algs = &cost->memset[TARGET_64BIT != 0];
17618 algs = &cost->memcpy[TARGET_64BIT != 0];
17619 if (stringop_alg != no_stringop && ALG_USABLE_P (stringop_alg))
17620 return stringop_alg;
17621 /* rep; movq or rep; movl is the smallest variant. */
17622 else if (!optimize_for_speed)
17624 if (!count || (count & 3))
17625 return rep_prefix_usable ? rep_prefix_1_byte : loop_1_byte;
17627 return rep_prefix_usable ? rep_prefix_4_byte : loop;
17629 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
17631 else if (expected_size != -1 && expected_size < 4)
17632 return loop_1_byte;
17633 else if (expected_size != -1)
17636 enum stringop_alg alg = libcall;
17637 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17639 /* We get here if the algorithms that were not libcall-based
17640 were rep-prefix based and we are unable to use rep prefixes
17641 based on global register usage. Break out of the loop and
17642 use the heuristic below. */
17643 if (algs->size[i].max == 0)
17645 if (algs->size[i].max >= expected_size || algs->size[i].max == -1)
17647 enum stringop_alg candidate = algs->size[i].alg;
17649 if (candidate != libcall && ALG_USABLE_P (candidate))
17651 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
17652 last non-libcall inline algorithm. */
17653 if (TARGET_INLINE_ALL_STRINGOPS)
17655 /* When the current size is best to be copied by a libcall,
17656 but we are still forced to inline, run the heuristic below
17657 that will pick code for medium sized blocks. */
17658 if (alg != libcall)
17662 else if (ALG_USABLE_P (candidate))
17666 gcc_assert (TARGET_INLINE_ALL_STRINGOPS || !rep_prefix_usable);
17668 /* When asked to inline the call anyway, try to pick meaningful choice.
17669 We look for maximal size of block that is faster to copy by hand and
17670 take blocks of at most of that size guessing that average size will
17671 be roughly half of the block.
17673 If this turns out to be bad, we might simply specify the preferred
17674 choice in ix86_costs. */
17675 if ((TARGET_INLINE_ALL_STRINGOPS || TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17676 && (algs->unknown_size == libcall || !ALG_USABLE_P (algs->unknown_size)))
17679 enum stringop_alg alg;
17681 bool any_alg_usable_p = true;
17683 for (i = 0; i < NAX_STRINGOP_ALGS; i++)
17685 enum stringop_alg candidate = algs->size[i].alg;
17686 any_alg_usable_p = any_alg_usable_p && ALG_USABLE_P (candidate);
17688 if (candidate != libcall && candidate
17689 && ALG_USABLE_P (candidate))
17690 max = algs->size[i].max;
17692 /* If there aren't any usable algorithms, then recursing on
17693 smaller sizes isn't going to find anything. Just return the
17694 simple byte-at-a-time copy loop. */
17695 if (!any_alg_usable_p)
17697 /* Pick something reasonable. */
17698 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17699 *dynamic_check = 128;
17700 return loop_1_byte;
17704 alg = decide_alg (count, max / 2, memset, dynamic_check);
17705 gcc_assert (*dynamic_check == -1);
17706 gcc_assert (alg != libcall);
17707 if (TARGET_INLINE_STRINGOPS_DYNAMICALLY)
17708 *dynamic_check = max;
17711 return ALG_USABLE_P (algs->unknown_size) ? algs->unknown_size : libcall;
17712 #undef ALG_USABLE_P
17715 /* Decide on alignment. We know that the operand is already aligned to ALIGN
17716 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
17718 decide_alignment (int align,
17719 enum stringop_alg alg,
17722 int desired_align = 0;
17726 gcc_unreachable ();
17728 case unrolled_loop:
17729 desired_align = GET_MODE_SIZE (Pmode);
17731 case rep_prefix_8_byte:
17734 case rep_prefix_4_byte:
17735 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17736 copying whole cacheline at once. */
17737 if (TARGET_PENTIUMPRO)
17742 case rep_prefix_1_byte:
17743 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
17744 copying whole cacheline at once. */
17745 if (TARGET_PENTIUMPRO)
17759 if (desired_align < align)
17760 desired_align = align;
17761 if (expected_size != -1 && expected_size < 4)
17762 desired_align = align;
17763 return desired_align;
17766 /* Return the smallest power of 2 greater than VAL. */
17768 smallest_pow2_greater_than (int val)
17776 /* Expand string move (memcpy) operation. Use i386 string operations when
17777 profitable. expand_setmem contains similar code. The code depends upon
17778 architecture, block size and alignment, but always has the same
17781 1) Prologue guard: Conditional that jumps up to epilogues for small
17782 blocks that can be handled by epilogue alone. This is faster but
17783 also needed for correctness, since prologue assume the block is larger
17784 than the desired alignment.
17786 Optional dynamic check for size and libcall for large
17787 blocks is emitted here too, with -minline-stringops-dynamically.
17789 2) Prologue: copy first few bytes in order to get destination aligned
17790 to DESIRED_ALIGN. It is emitted only when ALIGN is less than
17791 DESIRED_ALIGN and and up to DESIRED_ALIGN - ALIGN bytes can be copied.
17792 We emit either a jump tree on power of two sized blocks, or a byte loop.
17794 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
17795 with specified algorithm.
17797 4) Epilogue: code copying tail of the block that is too small to be
17798 handled by main body (or up to size guarded by prologue guard). */
17801 ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp,
17802 rtx expected_align_exp, rtx expected_size_exp)
17808 rtx jump_around_label = NULL;
17809 HOST_WIDE_INT align = 1;
17810 unsigned HOST_WIDE_INT count = 0;
17811 HOST_WIDE_INT expected_size = -1;
17812 int size_needed = 0, epilogue_size_needed;
17813 int desired_align = 0, align_bytes = 0;
17814 enum stringop_alg alg;
17816 bool need_zero_guard = false;
17818 if (CONST_INT_P (align_exp))
17819 align = INTVAL (align_exp);
17820 /* i386 can do misaligned access on reasonably increased cost. */
17821 if (CONST_INT_P (expected_align_exp)
17822 && INTVAL (expected_align_exp) > align)
17823 align = INTVAL (expected_align_exp);
17824 /* ALIGN is the minimum of destination and source alignment, but we care here
17825 just about destination alignment. */
17826 else if (MEM_ALIGN (dst) > (unsigned HOST_WIDE_INT) align * BITS_PER_UNIT)
17827 align = MEM_ALIGN (dst) / BITS_PER_UNIT;
17829 if (CONST_INT_P (count_exp))
17830 count = expected_size = INTVAL (count_exp);
17831 if (CONST_INT_P (expected_size_exp) && count == 0)
17832 expected_size = INTVAL (expected_size_exp);
17834 /* Make sure we don't need to care about overflow later on. */
17835 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
17838 /* Step 0: Decide on preferred algorithm, desired alignment and
17839 size of chunks to be copied by main loop. */
17841 alg = decide_alg (count, expected_size, false, &dynamic_check);
17842 desired_align = decide_alignment (align, alg, expected_size);
17844 if (!TARGET_ALIGN_STRINGOPS)
17845 align = desired_align;
17847 if (alg == libcall)
17849 gcc_assert (alg != no_stringop);
17851 count_exp = copy_to_mode_reg (GET_MODE (count_exp), count_exp);
17852 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
17853 srcreg = copy_to_mode_reg (Pmode, XEXP (src, 0));
17858 gcc_unreachable ();
17860 need_zero_guard = true;
17861 size_needed = GET_MODE_SIZE (Pmode);
17863 case unrolled_loop:
17864 need_zero_guard = true;
17865 size_needed = GET_MODE_SIZE (Pmode) * (TARGET_64BIT ? 4 : 2);
17867 case rep_prefix_8_byte:
17870 case rep_prefix_4_byte:
17873 case rep_prefix_1_byte:
17877 need_zero_guard = true;
17882 epilogue_size_needed = size_needed;
17884 /* Step 1: Prologue guard. */
17886 /* Alignment code needs count to be in register. */
17887 if (CONST_INT_P (count_exp) && desired_align > align)
17889 if (INTVAL (count_exp) > desired_align
17890 && INTVAL (count_exp) > size_needed)
17893 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
17894 if (align_bytes <= 0)
17897 align_bytes = desired_align - align_bytes;
17899 if (align_bytes == 0)
17900 count_exp = force_reg (counter_mode (count_exp), count_exp);
17902 gcc_assert (desired_align >= 1 && align >= 1);
17904 /* Ensure that alignment prologue won't copy past end of block. */
17905 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
17907 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
17908 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
17909 Make sure it is power of 2. */
17910 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
17914 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
17916 /* If main algorithm works on QImode, no epilogue is needed.
17917 For small sizes just don't align anything. */
17918 if (size_needed == 1)
17919 desired_align = align;
17926 label = gen_label_rtx ();
17927 emit_cmp_and_jump_insns (count_exp,
17928 GEN_INT (epilogue_size_needed),
17929 LTU, 0, counter_mode (count_exp), 1, label);
17930 if (expected_size == -1 || expected_size < epilogue_size_needed)
17931 predict_jump (REG_BR_PROB_BASE * 60 / 100);
17933 predict_jump (REG_BR_PROB_BASE * 20 / 100);
17937 /* Emit code to decide on runtime whether library call or inline should be
17939 if (dynamic_check != -1)
17941 if (CONST_INT_P (count_exp))
17943 if (UINTVAL (count_exp) >= (unsigned HOST_WIDE_INT)dynamic_check)
17945 emit_block_move_via_libcall (dst, src, count_exp, false);
17946 count_exp = const0_rtx;
17952 rtx hot_label = gen_label_rtx ();
17953 jump_around_label = gen_label_rtx ();
17954 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
17955 LEU, 0, GET_MODE (count_exp), 1, hot_label);
17956 predict_jump (REG_BR_PROB_BASE * 90 / 100);
17957 emit_block_move_via_libcall (dst, src, count_exp, false);
17958 emit_jump (jump_around_label);
17959 emit_label (hot_label);
17963 /* Step 2: Alignment prologue. */
17965 if (desired_align > align)
17967 if (align_bytes == 0)
17969 /* Except for the first move in epilogue, we no longer know
17970 constant offset in aliasing info. It don't seems to worth
17971 the pain to maintain it for the first move, so throw away
17973 src = change_address (src, BLKmode, srcreg);
17974 dst = change_address (dst, BLKmode, destreg);
17975 expand_movmem_prologue (dst, src, destreg, srcreg, count_exp, align,
17980 /* If we know how many bytes need to be stored before dst is
17981 sufficiently aligned, maintain aliasing info accurately. */
17982 dst = expand_constant_movmem_prologue (dst, &src, destreg, srcreg,
17983 desired_align, align_bytes);
17984 count_exp = plus_constant (count_exp, -align_bytes);
17985 count -= align_bytes;
17987 if (need_zero_guard
17988 && (count < (unsigned HOST_WIDE_INT) size_needed
17989 || (align_bytes == 0
17990 && count < ((unsigned HOST_WIDE_INT) size_needed
17991 + desired_align - align))))
17993 /* It is possible that we copied enough so the main loop will not
17995 gcc_assert (size_needed > 1);
17996 if (label == NULL_RTX)
17997 label = gen_label_rtx ();
17998 emit_cmp_and_jump_insns (count_exp,
17999 GEN_INT (size_needed),
18000 LTU, 0, counter_mode (count_exp), 1, label);
18001 if (expected_size == -1
18002 || expected_size < (desired_align - align) / 2 + size_needed)
18003 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18005 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18008 if (label && size_needed == 1)
18010 emit_label (label);
18011 LABEL_NUSES (label) = 1;
18013 epilogue_size_needed = 1;
18015 else if (label == NULL_RTX)
18016 epilogue_size_needed = size_needed;
18018 /* Step 3: Main loop. */
18024 gcc_unreachable ();
18026 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18027 count_exp, QImode, 1, expected_size);
18030 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18031 count_exp, Pmode, 1, expected_size);
18033 case unrolled_loop:
18034 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
18035 registers for 4 temporaries anyway. */
18036 expand_set_or_movmem_via_loop (dst, src, destreg, srcreg, NULL,
18037 count_exp, Pmode, TARGET_64BIT ? 4 : 2,
18040 case rep_prefix_8_byte:
18041 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18044 case rep_prefix_4_byte:
18045 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18048 case rep_prefix_1_byte:
18049 expand_movmem_via_rep_mov (dst, src, destreg, srcreg, count_exp,
18053 /* Adjust properly the offset of src and dest memory for aliasing. */
18054 if (CONST_INT_P (count_exp))
18056 src = adjust_automodify_address_nv (src, BLKmode, srcreg,
18057 (count / size_needed) * size_needed);
18058 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18059 (count / size_needed) * size_needed);
18063 src = change_address (src, BLKmode, srcreg);
18064 dst = change_address (dst, BLKmode, destreg);
18067 /* Step 4: Epilogue to copy the remaining bytes. */
18071 /* When the main loop is done, COUNT_EXP might hold original count,
18072 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18073 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18074 bytes. Compensate if needed. */
18076 if (size_needed < epilogue_size_needed)
18079 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18080 GEN_INT (size_needed - 1), count_exp, 1,
18082 if (tmp != count_exp)
18083 emit_move_insn (count_exp, tmp);
18085 emit_label (label);
18086 LABEL_NUSES (label) = 1;
18089 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18090 expand_movmem_epilogue (dst, src, destreg, srcreg, count_exp,
18091 epilogue_size_needed);
18092 if (jump_around_label)
18093 emit_label (jump_around_label);
18097 /* Helper function for memcpy. For QImode value 0xXY produce
18098 0xXYXYXYXY of wide specified by MODE. This is essentially
18099 a * 0x10101010, but we can do slightly better than
18100 synth_mult by unwinding the sequence by hand on CPUs with
18103 promote_duplicated_reg (enum machine_mode mode, rtx val)
18105 enum machine_mode valmode = GET_MODE (val);
18107 int nops = mode == DImode ? 3 : 2;
18109 gcc_assert (mode == SImode || mode == DImode);
18110 if (val == const0_rtx)
18111 return copy_to_mode_reg (mode, const0_rtx);
18112 if (CONST_INT_P (val))
18114 HOST_WIDE_INT v = INTVAL (val) & 255;
18118 if (mode == DImode)
18119 v |= (v << 16) << 16;
18120 return copy_to_mode_reg (mode, gen_int_mode (v, mode));
18123 if (valmode == VOIDmode)
18125 if (valmode != QImode)
18126 val = gen_lowpart (QImode, val);
18127 if (mode == QImode)
18129 if (!TARGET_PARTIAL_REG_STALL)
18131 if (ix86_cost->mult_init[mode == DImode ? 3 : 2]
18132 + ix86_cost->mult_bit * (mode == DImode ? 8 : 4)
18133 <= (ix86_cost->shift_const + ix86_cost->add) * nops
18134 + (COSTS_N_INSNS (TARGET_PARTIAL_REG_STALL == 0)))
18136 rtx reg = convert_modes (mode, QImode, val, true);
18137 tmp = promote_duplicated_reg (mode, const1_rtx);
18138 return expand_simple_binop (mode, MULT, reg, tmp, NULL, 1,
18143 rtx reg = convert_modes (mode, QImode, val, true);
18145 if (!TARGET_PARTIAL_REG_STALL)
18146 if (mode == SImode)
18147 emit_insn (gen_movsi_insv_1 (reg, reg));
18149 emit_insn (gen_movdi_insv_1_rex64 (reg, reg));
18152 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
18153 NULL, 1, OPTAB_DIRECT);
18155 expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18157 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (16),
18158 NULL, 1, OPTAB_DIRECT);
18159 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18160 if (mode == SImode)
18162 tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (32),
18163 NULL, 1, OPTAB_DIRECT);
18164 reg = expand_simple_binop (mode, IOR, reg, tmp, reg, 1, OPTAB_DIRECT);
18169 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
18170 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
18171 alignment from ALIGN to DESIRED_ALIGN. */
18173 promote_duplicated_reg_to_size (rtx val, int size_needed, int desired_align, int align)
18178 && (size_needed > 4 || (desired_align > align && desired_align > 4)))
18179 promoted_val = promote_duplicated_reg (DImode, val);
18180 else if (size_needed > 2 || (desired_align > align && desired_align > 2))
18181 promoted_val = promote_duplicated_reg (SImode, val);
18182 else if (size_needed > 1 || (desired_align > align && desired_align > 1))
18183 promoted_val = promote_duplicated_reg (HImode, val);
18185 promoted_val = val;
18187 return promoted_val;
18190 /* Expand string clear operation (bzero). Use i386 string operations when
18191 profitable. See expand_movmem comment for explanation of individual
18192 steps performed. */
18194 ix86_expand_setmem (rtx dst, rtx count_exp, rtx val_exp, rtx align_exp,
18195 rtx expected_align_exp, rtx expected_size_exp)
18200 rtx jump_around_label = NULL;
18201 HOST_WIDE_INT align = 1;
18202 unsigned HOST_WIDE_INT count = 0;
18203 HOST_WIDE_INT expected_size = -1;
18204 int size_needed = 0, epilogue_size_needed;
18205 int desired_align = 0, align_bytes = 0;
18206 enum stringop_alg alg;
18207 rtx promoted_val = NULL;
18208 bool force_loopy_epilogue = false;
18210 bool need_zero_guard = false;
18212 if (CONST_INT_P (align_exp))
18213 align = INTVAL (align_exp);
18214 /* i386 can do misaligned access on reasonably increased cost. */
18215 if (CONST_INT_P (expected_align_exp)
18216 && INTVAL (expected_align_exp) > align)
18217 align = INTVAL (expected_align_exp);
18218 if (CONST_INT_P (count_exp))
18219 count = expected_size = INTVAL (count_exp);
18220 if (CONST_INT_P (expected_size_exp) && count == 0)
18221 expected_size = INTVAL (expected_size_exp);
18223 /* Make sure we don't need to care about overflow later on. */
18224 if (count > ((unsigned HOST_WIDE_INT) 1 << 30))
18227 /* Step 0: Decide on preferred algorithm, desired alignment and
18228 size of chunks to be copied by main loop. */
18230 alg = decide_alg (count, expected_size, true, &dynamic_check);
18231 desired_align = decide_alignment (align, alg, expected_size);
18233 if (!TARGET_ALIGN_STRINGOPS)
18234 align = desired_align;
18236 if (alg == libcall)
18238 gcc_assert (alg != no_stringop);
18240 count_exp = copy_to_mode_reg (counter_mode (count_exp), count_exp);
18241 destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0));
18246 gcc_unreachable ();
18248 need_zero_guard = true;
18249 size_needed = GET_MODE_SIZE (Pmode);
18251 case unrolled_loop:
18252 need_zero_guard = true;
18253 size_needed = GET_MODE_SIZE (Pmode) * 4;
18255 case rep_prefix_8_byte:
18258 case rep_prefix_4_byte:
18261 case rep_prefix_1_byte:
18265 need_zero_guard = true;
18269 epilogue_size_needed = size_needed;
18271 /* Step 1: Prologue guard. */
18273 /* Alignment code needs count to be in register. */
18274 if (CONST_INT_P (count_exp) && desired_align > align)
18276 if (INTVAL (count_exp) > desired_align
18277 && INTVAL (count_exp) > size_needed)
18280 = get_mem_align_offset (dst, desired_align * BITS_PER_UNIT);
18281 if (align_bytes <= 0)
18284 align_bytes = desired_align - align_bytes;
18286 if (align_bytes == 0)
18288 enum machine_mode mode = SImode;
18289 if (TARGET_64BIT && (count & ~0xffffffff))
18291 count_exp = force_reg (mode, count_exp);
18294 /* Do the cheap promotion to allow better CSE across the
18295 main loop and epilogue (ie one load of the big constant in the
18296 front of all code. */
18297 if (CONST_INT_P (val_exp))
18298 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18299 desired_align, align);
18300 /* Ensure that alignment prologue won't copy past end of block. */
18301 if (size_needed > 1 || (desired_align > 1 && desired_align > align))
18303 epilogue_size_needed = MAX (size_needed - 1, desired_align - align);
18304 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
18305 Make sure it is power of 2. */
18306 epilogue_size_needed = smallest_pow2_greater_than (epilogue_size_needed);
18308 /* To improve performance of small blocks, we jump around the VAL
18309 promoting mode. This mean that if the promoted VAL is not constant,
18310 we might not use it in the epilogue and have to use byte
18312 if (epilogue_size_needed > 2 && !promoted_val)
18313 force_loopy_epilogue = true;
18316 if (count < (unsigned HOST_WIDE_INT)epilogue_size_needed)
18318 /* If main algorithm works on QImode, no epilogue is needed.
18319 For small sizes just don't align anything. */
18320 if (size_needed == 1)
18321 desired_align = align;
18328 label = gen_label_rtx ();
18329 emit_cmp_and_jump_insns (count_exp,
18330 GEN_INT (epilogue_size_needed),
18331 LTU, 0, counter_mode (count_exp), 1, label);
18332 if (expected_size == -1 || expected_size <= epilogue_size_needed)
18333 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18335 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18338 if (dynamic_check != -1)
18340 rtx hot_label = gen_label_rtx ();
18341 jump_around_label = gen_label_rtx ();
18342 emit_cmp_and_jump_insns (count_exp, GEN_INT (dynamic_check - 1),
18343 LEU, 0, counter_mode (count_exp), 1, hot_label);
18344 predict_jump (REG_BR_PROB_BASE * 90 / 100);
18345 set_storage_via_libcall (dst, count_exp, val_exp, false);
18346 emit_jump (jump_around_label);
18347 emit_label (hot_label);
18350 /* Step 2: Alignment prologue. */
18352 /* Do the expensive promotion once we branched off the small blocks. */
18354 promoted_val = promote_duplicated_reg_to_size (val_exp, size_needed,
18355 desired_align, align);
18356 gcc_assert (desired_align >= 1 && align >= 1);
18358 if (desired_align > align)
18360 if (align_bytes == 0)
18362 /* Except for the first move in epilogue, we no longer know
18363 constant offset in aliasing info. It don't seems to worth
18364 the pain to maintain it for the first move, so throw away
18366 dst = change_address (dst, BLKmode, destreg);
18367 expand_setmem_prologue (dst, destreg, promoted_val, count_exp, align,
18372 /* If we know how many bytes need to be stored before dst is
18373 sufficiently aligned, maintain aliasing info accurately. */
18374 dst = expand_constant_setmem_prologue (dst, destreg, promoted_val,
18375 desired_align, align_bytes);
18376 count_exp = plus_constant (count_exp, -align_bytes);
18377 count -= align_bytes;
18379 if (need_zero_guard
18380 && (count < (unsigned HOST_WIDE_INT) size_needed
18381 || (align_bytes == 0
18382 && count < ((unsigned HOST_WIDE_INT) size_needed
18383 + desired_align - align))))
18385 /* It is possible that we copied enough so the main loop will not
18387 gcc_assert (size_needed > 1);
18388 if (label == NULL_RTX)
18389 label = gen_label_rtx ();
18390 emit_cmp_and_jump_insns (count_exp,
18391 GEN_INT (size_needed),
18392 LTU, 0, counter_mode (count_exp), 1, label);
18393 if (expected_size == -1
18394 || expected_size < (desired_align - align) / 2 + size_needed)
18395 predict_jump (REG_BR_PROB_BASE * 20 / 100);
18397 predict_jump (REG_BR_PROB_BASE * 60 / 100);
18400 if (label && size_needed == 1)
18402 emit_label (label);
18403 LABEL_NUSES (label) = 1;
18405 promoted_val = val_exp;
18406 epilogue_size_needed = 1;
18408 else if (label == NULL_RTX)
18409 epilogue_size_needed = size_needed;
18411 /* Step 3: Main loop. */
18417 gcc_unreachable ();
18419 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18420 count_exp, QImode, 1, expected_size);
18423 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18424 count_exp, Pmode, 1, expected_size);
18426 case unrolled_loop:
18427 expand_set_or_movmem_via_loop (dst, NULL, destreg, NULL, promoted_val,
18428 count_exp, Pmode, 4, expected_size);
18430 case rep_prefix_8_byte:
18431 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18434 case rep_prefix_4_byte:
18435 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18438 case rep_prefix_1_byte:
18439 expand_setmem_via_rep_stos (dst, destreg, promoted_val, count_exp,
18443 /* Adjust properly the offset of src and dest memory for aliasing. */
18444 if (CONST_INT_P (count_exp))
18445 dst = adjust_automodify_address_nv (dst, BLKmode, destreg,
18446 (count / size_needed) * size_needed);
18448 dst = change_address (dst, BLKmode, destreg);
18450 /* Step 4: Epilogue to copy the remaining bytes. */
18454 /* When the main loop is done, COUNT_EXP might hold original count,
18455 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
18456 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
18457 bytes. Compensate if needed. */
18459 if (size_needed < epilogue_size_needed)
18462 expand_simple_binop (counter_mode (count_exp), AND, count_exp,
18463 GEN_INT (size_needed - 1), count_exp, 1,
18465 if (tmp != count_exp)
18466 emit_move_insn (count_exp, tmp);
18468 emit_label (label);
18469 LABEL_NUSES (label) = 1;
18472 if (count_exp != const0_rtx && epilogue_size_needed > 1)
18474 if (force_loopy_epilogue)
18475 expand_setmem_epilogue_via_loop (dst, destreg, val_exp, count_exp,
18476 epilogue_size_needed);
18478 expand_setmem_epilogue (dst, destreg, promoted_val, count_exp,
18479 epilogue_size_needed);
18481 if (jump_around_label)
18482 emit_label (jump_around_label);
18486 /* Expand the appropriate insns for doing strlen if not just doing
18489 out = result, initialized with the start address
18490 align_rtx = alignment of the address.
18491 scratch = scratch register, initialized with the startaddress when
18492 not aligned, otherwise undefined
18494 This is just the body. It needs the initializations mentioned above and
18495 some address computing at the end. These things are done in i386.md. */
18498 ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx)
18502 rtx align_2_label = NULL_RTX;
18503 rtx align_3_label = NULL_RTX;
18504 rtx align_4_label = gen_label_rtx ();
18505 rtx end_0_label = gen_label_rtx ();
18507 rtx tmpreg = gen_reg_rtx (SImode);
18508 rtx scratch = gen_reg_rtx (SImode);
18512 if (CONST_INT_P (align_rtx))
18513 align = INTVAL (align_rtx);
18515 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
18517 /* Is there a known alignment and is it less than 4? */
18520 rtx scratch1 = gen_reg_rtx (Pmode);
18521 emit_move_insn (scratch1, out);
18522 /* Is there a known alignment and is it not 2? */
18525 align_3_label = gen_label_rtx (); /* Label when aligned to 3-byte */
18526 align_2_label = gen_label_rtx (); /* Label when aligned to 2-byte */
18528 /* Leave just the 3 lower bits. */
18529 align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (3),
18530 NULL_RTX, 0, OPTAB_WIDEN);
18532 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18533 Pmode, 1, align_4_label);
18534 emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL,
18535 Pmode, 1, align_2_label);
18536 emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL,
18537 Pmode, 1, align_3_label);
18541 /* Since the alignment is 2, we have to check 2 or 0 bytes;
18542 check if is aligned to 4 - byte. */
18544 align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx,
18545 NULL_RTX, 0, OPTAB_WIDEN);
18547 emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL,
18548 Pmode, 1, align_4_label);
18551 mem = change_address (src, QImode, out);
18553 /* Now compare the bytes. */
18555 /* Compare the first n unaligned byte on a byte per byte basis. */
18556 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL,
18557 QImode, 1, end_0_label);
18559 /* Increment the address. */
18560 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18562 /* Not needed with an alignment of 2 */
18565 emit_label (align_2_label);
18567 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18570 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18572 emit_label (align_3_label);
18575 emit_cmp_and_jump_insns (mem, const0_rtx, EQ, NULL, QImode, 1,
18578 emit_insn ((*ix86_gen_add3) (out, out, const1_rtx));
18581 /* Generate loop to check 4 bytes at a time. It is not a good idea to
18582 align this loop. It gives only huge programs, but does not help to
18584 emit_label (align_4_label);
18586 mem = change_address (src, SImode, out);
18587 emit_move_insn (scratch, mem);
18588 emit_insn ((*ix86_gen_add3) (out, out, GEN_INT (4)));
18590 /* This formula yields a nonzero result iff one of the bytes is zero.
18591 This saves three branches inside loop and many cycles. */
18593 emit_insn (gen_addsi3 (tmpreg, scratch, GEN_INT (-0x01010101)));
18594 emit_insn (gen_one_cmplsi2 (scratch, scratch));
18595 emit_insn (gen_andsi3 (tmpreg, tmpreg, scratch));
18596 emit_insn (gen_andsi3 (tmpreg, tmpreg,
18597 gen_int_mode (0x80808080, SImode)));
18598 emit_cmp_and_jump_insns (tmpreg, const0_rtx, EQ, 0, SImode, 1,
18603 rtx reg = gen_reg_rtx (SImode);
18604 rtx reg2 = gen_reg_rtx (Pmode);
18605 emit_move_insn (reg, tmpreg);
18606 emit_insn (gen_lshrsi3 (reg, reg, GEN_INT (16)));
18608 /* If zero is not in the first two bytes, move two bytes forward. */
18609 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18610 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18611 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18612 emit_insn (gen_rtx_SET (VOIDmode, tmpreg,
18613 gen_rtx_IF_THEN_ELSE (SImode, tmp,
18616 /* Emit lea manually to avoid clobbering of flags. */
18617 emit_insn (gen_rtx_SET (SImode, reg2,
18618 gen_rtx_PLUS (Pmode, out, const2_rtx)));
18620 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18621 tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
18622 emit_insn (gen_rtx_SET (VOIDmode, out,
18623 gen_rtx_IF_THEN_ELSE (Pmode, tmp,
18630 rtx end_2_label = gen_label_rtx ();
18631 /* Is zero in the first two bytes? */
18633 emit_insn (gen_testsi_ccno_1 (tmpreg, GEN_INT (0x8080)));
18634 tmp = gen_rtx_REG (CCNOmode, FLAGS_REG);
18635 tmp = gen_rtx_NE (VOIDmode, tmp, const0_rtx);
18636 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
18637 gen_rtx_LABEL_REF (VOIDmode, end_2_label),
18639 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
18640 JUMP_LABEL (tmp) = end_2_label;
18642 /* Not in the first two. Move two bytes forward. */
18643 emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16)));
18644 emit_insn ((*ix86_gen_add3) (out, out, const2_rtx));
18646 emit_label (end_2_label);
18650 /* Avoid branch in fixing the byte. */
18651 tmpreg = gen_lowpart (QImode, tmpreg);
18652 emit_insn (gen_addqi3_cc (tmpreg, tmpreg, tmpreg));
18653 cmp = gen_rtx_LTU (Pmode, gen_rtx_REG (CCmode, FLAGS_REG), const0_rtx);
18654 emit_insn ((*ix86_gen_sub3_carry) (out, out, GEN_INT (3), cmp));
18656 emit_label (end_0_label);
18659 /* Expand strlen. */
18662 ix86_expand_strlen (rtx out, rtx src, rtx eoschar, rtx align)
18664 rtx addr, scratch1, scratch2, scratch3, scratch4;
18666 /* The generic case of strlen expander is long. Avoid it's
18667 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
18669 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18670 && !TARGET_INLINE_ALL_STRINGOPS
18671 && !optimize_insn_for_size_p ()
18672 && (!CONST_INT_P (align) || INTVAL (align) < 4))
18675 addr = force_reg (Pmode, XEXP (src, 0));
18676 scratch1 = gen_reg_rtx (Pmode);
18678 if (TARGET_UNROLL_STRLEN && eoschar == const0_rtx && optimize > 1
18679 && !optimize_insn_for_size_p ())
18681 /* Well it seems that some optimizer does not combine a call like
18682 foo(strlen(bar), strlen(bar));
18683 when the move and the subtraction is done here. It does calculate
18684 the length just once when these instructions are done inside of
18685 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
18686 often used and I use one fewer register for the lifetime of
18687 output_strlen_unroll() this is better. */
18689 emit_move_insn (out, addr);
18691 ix86_expand_strlensi_unroll_1 (out, src, align);
18693 /* strlensi_unroll_1 returns the address of the zero at the end of
18694 the string, like memchr(), so compute the length by subtracting
18695 the start address. */
18696 emit_insn ((*ix86_gen_sub3) (out, out, addr));
18702 /* Can't use this if the user has appropriated eax, ecx, or edi. */
18703 if (fixed_regs[AX_REG] || fixed_regs[CX_REG] || fixed_regs[DI_REG])
18706 scratch2 = gen_reg_rtx (Pmode);
18707 scratch3 = gen_reg_rtx (Pmode);
18708 scratch4 = force_reg (Pmode, constm1_rtx);
18710 emit_move_insn (scratch3, addr);
18711 eoschar = force_reg (QImode, eoschar);
18713 src = replace_equiv_address_nv (src, scratch3);
18715 /* If .md starts supporting :P, this can be done in .md. */
18716 unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (4, src, eoschar, align,
18717 scratch4), UNSPEC_SCAS);
18718 emit_insn (gen_strlenqi_1 (scratch1, scratch3, unspec));
18719 emit_insn ((*ix86_gen_one_cmpl2) (scratch2, scratch1));
18720 emit_insn ((*ix86_gen_add3) (out, scratch2, constm1_rtx));
18725 /* For given symbol (function) construct code to compute address of it's PLT
18726 entry in large x86-64 PIC model. */
18728 construct_plt_address (rtx symbol)
18730 rtx tmp = gen_reg_rtx (Pmode);
18731 rtx unspec = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol), UNSPEC_PLTOFF);
18733 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
18734 gcc_assert (ix86_cmodel == CM_LARGE_PIC);
18736 emit_move_insn (tmp, gen_rtx_CONST (Pmode, unspec));
18737 emit_insn (gen_adddi3 (tmp, tmp, pic_offset_table_rtx));
18742 ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
18744 rtx pop, int sibcall)
18746 rtx use = NULL, call;
18748 if (pop == const0_rtx)
18750 gcc_assert (!TARGET_64BIT || !pop);
18752 if (TARGET_MACHO && !TARGET_64BIT)
18755 if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
18756 fnaddr = machopic_indirect_call_target (fnaddr);
18761 /* Static functions and indirect calls don't need the pic register. */
18762 if (flag_pic && (!TARGET_64BIT || ix86_cmodel == CM_LARGE_PIC)
18763 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18764 && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
18765 use_reg (&use, pic_offset_table_rtx);
18768 if (TARGET_64BIT && INTVAL (callarg2) >= 0)
18770 rtx al = gen_rtx_REG (QImode, AX_REG);
18771 emit_move_insn (al, callarg2);
18772 use_reg (&use, al);
18775 if (ix86_cmodel == CM_LARGE_PIC
18776 && GET_CODE (fnaddr) == MEM
18777 && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
18778 && !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
18779 fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
18781 ? !sibcall_insn_operand (XEXP (fnaddr, 0), Pmode)
18782 : !call_insn_operand (XEXP (fnaddr, 0), Pmode))
18784 fnaddr = copy_to_mode_reg (Pmode, XEXP (fnaddr, 0));
18785 fnaddr = gen_rtx_MEM (QImode, fnaddr);
18788 call = gen_rtx_CALL (VOIDmode, fnaddr, callarg1);
18790 call = gen_rtx_SET (VOIDmode, retval, call);
18793 pop = gen_rtx_PLUS (Pmode, stack_pointer_rtx, pop);
18794 pop = gen_rtx_SET (VOIDmode, stack_pointer_rtx, pop);
18795 call = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, call, pop));
18798 && ix86_cfun_abi () == MS_ABI
18799 && (!callarg2 || INTVAL (callarg2) != -2))
18801 /* We need to represent that SI and DI registers are clobbered
18803 static int clobbered_registers[] = {
18804 XMM6_REG, XMM7_REG, XMM8_REG,
18805 XMM9_REG, XMM10_REG, XMM11_REG,
18806 XMM12_REG, XMM13_REG, XMM14_REG,
18807 XMM15_REG, SI_REG, DI_REG
18810 rtx vec[ARRAY_SIZE (clobbered_registers) + 2];
18811 rtx unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx),
18812 UNSPEC_MS_TO_SYSV_CALL);
18816 for (i = 0; i < ARRAY_SIZE (clobbered_registers); i++)
18817 vec[i + 2] = gen_rtx_CLOBBER (SSE_REGNO_P (clobbered_registers[i])
18820 (SSE_REGNO_P (clobbered_registers[i])
18822 clobbered_registers[i]));
18824 call = gen_rtx_PARALLEL (VOIDmode,
18825 gen_rtvec_v (ARRAY_SIZE (clobbered_registers)
18829 call = emit_call_insn (call);
18831 CALL_INSN_FUNCTION_USAGE (call) = use;
18835 /* Clear stack slot assignments remembered from previous functions.
18836 This is called from INIT_EXPANDERS once before RTL is emitted for each
18839 static struct machine_function *
18840 ix86_init_machine_status (void)
18842 struct machine_function *f;
18844 f = GGC_CNEW (struct machine_function);
18845 f->use_fast_prologue_epilogue_nregs = -1;
18846 f->tls_descriptor_call_expanded_p = 0;
18847 f->call_abi = DEFAULT_ABI;
18852 /* Return a MEM corresponding to a stack slot with mode MODE.
18853 Allocate a new slot if necessary.
18855 The RTL for a function can have several slots available: N is
18856 which slot to use. */
18859 assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n)
18861 struct stack_local_entry *s;
18863 gcc_assert (n < MAX_386_STACK_LOCALS);
18865 /* Virtual slot is valid only before vregs are instantiated. */
18866 gcc_assert ((n == SLOT_VIRTUAL) == !virtuals_instantiated);
18868 for (s = ix86_stack_locals; s; s = s->next)
18869 if (s->mode == mode && s->n == n)
18870 return copy_rtx (s->rtl);
18872 s = (struct stack_local_entry *)
18873 ggc_alloc (sizeof (struct stack_local_entry));
18876 s->rtl = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
18878 s->next = ix86_stack_locals;
18879 ix86_stack_locals = s;
18883 /* Construct the SYMBOL_REF for the tls_get_addr function. */
18885 static GTY(()) rtx ix86_tls_symbol;
18887 ix86_tls_get_addr (void)
18890 if (!ix86_tls_symbol)
18892 ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode,
18893 (TARGET_ANY_GNU_TLS
18895 ? "___tls_get_addr"
18896 : "__tls_get_addr");
18899 return ix86_tls_symbol;
18902 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
18904 static GTY(()) rtx ix86_tls_module_base_symbol;
18906 ix86_tls_module_base (void)
18909 if (!ix86_tls_module_base_symbol)
18911 ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode,
18912 "_TLS_MODULE_BASE_");
18913 SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol)
18914 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT;
18917 return ix86_tls_module_base_symbol;
18920 /* Calculate the length of the memory address in the instruction
18921 encoding. Does not include the one-byte modrm, opcode, or prefix. */
18924 memory_address_length (rtx addr)
18926 struct ix86_address parts;
18927 rtx base, index, disp;
18931 if (GET_CODE (addr) == PRE_DEC
18932 || GET_CODE (addr) == POST_INC
18933 || GET_CODE (addr) == PRE_MODIFY
18934 || GET_CODE (addr) == POST_MODIFY)
18937 ok = ix86_decompose_address (addr, &parts);
18940 if (parts.base && GET_CODE (parts.base) == SUBREG)
18941 parts.base = SUBREG_REG (parts.base);
18942 if (parts.index && GET_CODE (parts.index) == SUBREG)
18943 parts.index = SUBREG_REG (parts.index);
18946 index = parts.index;
18951 - esp as the base always wants an index,
18952 - ebp as the base always wants a displacement. */
18954 /* Register Indirect. */
18955 if (base && !index && !disp)
18957 /* esp (for its index) and ebp (for its displacement) need
18958 the two-byte modrm form. */
18959 if (addr == stack_pointer_rtx
18960 || addr == arg_pointer_rtx
18961 || addr == frame_pointer_rtx
18962 || addr == hard_frame_pointer_rtx)
18966 /* Direct Addressing. */
18967 else if (disp && !base && !index)
18972 /* Find the length of the displacement constant. */
18975 if (base && satisfies_constraint_K (disp))
18980 /* ebp always wants a displacement. */
18981 else if (base == hard_frame_pointer_rtx)
18984 /* An index requires the two-byte modrm form.... */
18986 /* ...like esp, which always wants an index. */
18987 || base == stack_pointer_rtx
18988 || base == arg_pointer_rtx
18989 || base == frame_pointer_rtx)
18996 /* Compute default value for "length_immediate" attribute. When SHORTFORM
18997 is set, expect that insn have 8bit immediate alternative. */
18999 ix86_attr_length_immediate_default (rtx insn, int shortform)
19003 extract_insn_cached (insn);
19004 for (i = recog_data.n_operands - 1; i >= 0; --i)
19005 if (CONSTANT_P (recog_data.operand[i]))
19008 if (shortform && satisfies_constraint_K (recog_data.operand[i]))
19012 switch (get_attr_mode (insn))
19023 /* Immediates for DImode instructions are encoded as 32bit sign extended values. */
19028 fatal_insn ("unknown insn mode", insn);
19034 /* Compute default value for "length_address" attribute. */
19036 ix86_attr_length_address_default (rtx insn)
19040 if (get_attr_type (insn) == TYPE_LEA)
19042 rtx set = PATTERN (insn);
19044 if (GET_CODE (set) == PARALLEL)
19045 set = XVECEXP (set, 0, 0);
19047 gcc_assert (GET_CODE (set) == SET);
19049 return memory_address_length (SET_SRC (set));
19052 extract_insn_cached (insn);
19053 for (i = recog_data.n_operands - 1; i >= 0; --i)
19054 if (MEM_P (recog_data.operand[i]))
19056 return memory_address_length (XEXP (recog_data.operand[i], 0));
19062 /* Compute default value for "length_vex" attribute. It includes
19063 2 or 3 byte VEX prefix and 1 opcode byte. */
19066 ix86_attr_length_vex_default (rtx insn, int has_0f_opcode,
19071 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
19072 byte VEX prefix. */
19073 if (!has_0f_opcode || has_vex_w)
19076 /* We can always use 2 byte VEX prefix in 32bit. */
19080 extract_insn_cached (insn);
19082 for (i = recog_data.n_operands - 1; i >= 0; --i)
19083 if (REG_P (recog_data.operand[i]))
19085 /* REX.W bit uses 3 byte VEX prefix. */
19086 if (GET_MODE (recog_data.operand[i]) == DImode)
19091 /* REX.X or REX.B bits use 3 byte VEX prefix. */
19092 if (MEM_P (recog_data.operand[i])
19093 && x86_extended_reg_mentioned_p (recog_data.operand[i]))
19100 /* Return the maximum number of instructions a cpu can issue. */
19103 ix86_issue_rate (void)
19107 case PROCESSOR_PENTIUM:
19111 case PROCESSOR_PENTIUMPRO:
19112 case PROCESSOR_PENTIUM4:
19113 case PROCESSOR_ATHLON:
19115 case PROCESSOR_AMDFAM10:
19116 case PROCESSOR_NOCONA:
19117 case PROCESSOR_GENERIC32:
19118 case PROCESSOR_GENERIC64:
19121 case PROCESSOR_CORE2:
19129 /* A subroutine of ix86_adjust_cost -- return true iff INSN reads flags set
19130 by DEP_INSN and nothing set by DEP_INSN. */
19133 ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19137 /* Simplify the test for uninteresting insns. */
19138 if (insn_type != TYPE_SETCC
19139 && insn_type != TYPE_ICMOV
19140 && insn_type != TYPE_FCMOV
19141 && insn_type != TYPE_IBR)
19144 if ((set = single_set (dep_insn)) != 0)
19146 set = SET_DEST (set);
19149 else if (GET_CODE (PATTERN (dep_insn)) == PARALLEL
19150 && XVECLEN (PATTERN (dep_insn), 0) == 2
19151 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 0)) == SET
19152 && GET_CODE (XVECEXP (PATTERN (dep_insn), 0, 1)) == SET)
19154 set = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19155 set2 = SET_DEST (XVECEXP (PATTERN (dep_insn), 0, 0));
19160 if (!REG_P (set) || REGNO (set) != FLAGS_REG)
19163 /* This test is true if the dependent insn reads the flags but
19164 not any other potentially set register. */
19165 if (!reg_overlap_mentioned_p (set, PATTERN (insn)))
19168 if (set2 && reg_overlap_mentioned_p (set2, PATTERN (insn)))
19174 /* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
19175 address with operands set by DEP_INSN. */
19178 ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
19182 if (insn_type == TYPE_LEA
19185 addr = PATTERN (insn);
19187 if (GET_CODE (addr) == PARALLEL)
19188 addr = XVECEXP (addr, 0, 0);
19190 gcc_assert (GET_CODE (addr) == SET);
19192 addr = SET_SRC (addr);
19197 extract_insn_cached (insn);
19198 for (i = recog_data.n_operands - 1; i >= 0; --i)
19199 if (MEM_P (recog_data.operand[i]))
19201 addr = XEXP (recog_data.operand[i], 0);
19208 return modified_in_p (addr, dep_insn);
19212 ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
19214 enum attr_type insn_type, dep_insn_type;
19215 enum attr_memory memory;
19217 int dep_insn_code_number;
19219 /* Anti and output dependencies have zero cost on all CPUs. */
19220 if (REG_NOTE_KIND (link) != 0)
19223 dep_insn_code_number = recog_memoized (dep_insn);
19225 /* If we can't recognize the insns, we can't really do anything. */
19226 if (dep_insn_code_number < 0 || recog_memoized (insn) < 0)
19229 insn_type = get_attr_type (insn);
19230 dep_insn_type = get_attr_type (dep_insn);
19234 case PROCESSOR_PENTIUM:
19235 /* Address Generation Interlock adds a cycle of latency. */
19236 if (ix86_agi_dependent (insn, dep_insn, insn_type))
19239 /* ??? Compares pair with jump/setcc. */
19240 if (ix86_flags_dependent (insn, dep_insn, insn_type))
19243 /* Floating point stores require value to be ready one cycle earlier. */
19244 if (insn_type == TYPE_FMOV
19245 && get_attr_memory (insn) == MEMORY_STORE
19246 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19250 case PROCESSOR_PENTIUMPRO:
19251 memory = get_attr_memory (insn);
19253 /* INT->FP conversion is expensive. */
19254 if (get_attr_fp_int_src (dep_insn))
19257 /* There is one cycle extra latency between an FP op and a store. */
19258 if (insn_type == TYPE_FMOV
19259 && (set = single_set (dep_insn)) != NULL_RTX
19260 && (set2 = single_set (insn)) != NULL_RTX
19261 && rtx_equal_p (SET_DEST (set), SET_SRC (set2))
19262 && MEM_P (SET_DEST (set2)))
19265 /* Show ability of reorder buffer to hide latency of load by executing
19266 in parallel with previous instruction in case
19267 previous instruction is not needed to compute the address. */
19268 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19269 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19271 /* Claim moves to take one cycle, as core can issue one load
19272 at time and the next load can start cycle later. */
19273 if (dep_insn_type == TYPE_IMOV
19274 || dep_insn_type == TYPE_FMOV)
19282 memory = get_attr_memory (insn);
19284 /* The esp dependency is resolved before the instruction is really
19286 if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
19287 && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
19290 /* INT->FP conversion is expensive. */
19291 if (get_attr_fp_int_src (dep_insn))
19294 /* Show ability of reorder buffer to hide latency of load by executing
19295 in parallel with previous instruction in case
19296 previous instruction is not needed to compute the address. */
19297 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19298 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19300 /* Claim moves to take one cycle, as core can issue one load
19301 at time and the next load can start cycle later. */
19302 if (dep_insn_type == TYPE_IMOV
19303 || dep_insn_type == TYPE_FMOV)
19312 case PROCESSOR_ATHLON:
19314 case PROCESSOR_AMDFAM10:
19315 case PROCESSOR_GENERIC32:
19316 case PROCESSOR_GENERIC64:
19317 memory = get_attr_memory (insn);
19319 /* Show ability of reorder buffer to hide latency of load by executing
19320 in parallel with previous instruction in case
19321 previous instruction is not needed to compute the address. */
19322 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
19323 && !ix86_agi_dependent (insn, dep_insn, insn_type))
19325 enum attr_unit unit = get_attr_unit (insn);
19328 /* Because of the difference between the length of integer and
19329 floating unit pipeline preparation stages, the memory operands
19330 for floating point are cheaper.
19332 ??? For Athlon it the difference is most probably 2. */
19333 if (unit == UNIT_INTEGER || unit == UNIT_UNKNOWN)
19336 loadcost = TARGET_ATHLON ? 2 : 0;
19338 if (cost >= loadcost)
19351 /* How many alternative schedules to try. This should be as wide as the
19352 scheduling freedom in the DFA, but no wider. Making this value too
19353 large results extra work for the scheduler. */
19356 ia32_multipass_dfa_lookahead (void)
19360 case PROCESSOR_PENTIUM:
19363 case PROCESSOR_PENTIUMPRO:
19373 /* Compute the alignment given to a constant that is being placed in memory.
19374 EXP is the constant and ALIGN is the alignment that the object would
19376 The value of this function is used instead of that alignment to align
19380 ix86_constant_alignment (tree exp, int align)
19382 if (TREE_CODE (exp) == REAL_CST || TREE_CODE (exp) == VECTOR_CST
19383 || TREE_CODE (exp) == INTEGER_CST)
19385 if (TYPE_MODE (TREE_TYPE (exp)) == DFmode && align < 64)
19387 else if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (exp))) && align < 128)
19390 else if (!optimize_size && TREE_CODE (exp) == STRING_CST
19391 && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD)
19392 return BITS_PER_WORD;
19397 /* Compute the alignment for a static variable.
19398 TYPE is the data type, and ALIGN is the alignment that
19399 the object would ordinarily have. The value of this function is used
19400 instead of that alignment to align the object. */
19403 ix86_data_alignment (tree type, int align)
19405 int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
19407 if (AGGREGATE_TYPE_P (type)
19408 && TYPE_SIZE (type)
19409 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19410 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align
19411 || TREE_INT_CST_HIGH (TYPE_SIZE (type)))
19412 && align < max_align)
19415 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19416 to 16byte boundary. */
19419 if (AGGREGATE_TYPE_P (type)
19420 && TYPE_SIZE (type)
19421 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19422 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 128
19423 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19427 if (TREE_CODE (type) == ARRAY_TYPE)
19429 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19431 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19434 else if (TREE_CODE (type) == COMPLEX_TYPE)
19437 if (TYPE_MODE (type) == DCmode && align < 64)
19439 if ((TYPE_MODE (type) == XCmode
19440 || TYPE_MODE (type) == TCmode) && align < 128)
19443 else if ((TREE_CODE (type) == RECORD_TYPE
19444 || TREE_CODE (type) == UNION_TYPE
19445 || TREE_CODE (type) == QUAL_UNION_TYPE)
19446 && TYPE_FIELDS (type))
19448 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19450 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19453 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19454 || TREE_CODE (type) == INTEGER_TYPE)
19456 if (TYPE_MODE (type) == DFmode && align < 64)
19458 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19465 /* Compute the alignment for a local variable or a stack slot. EXP is
19466 the data type or decl itself, MODE is the widest mode available and
19467 ALIGN is the alignment that the object would ordinarily have. The
19468 value of this macro is used instead of that alignment to align the
19472 ix86_local_alignment (tree exp, enum machine_mode mode,
19473 unsigned int align)
19477 if (exp && DECL_P (exp))
19479 type = TREE_TYPE (exp);
19488 /* Don't do dynamic stack realignment for long long objects with
19489 -mpreferred-stack-boundary=2. */
19492 && ix86_preferred_stack_boundary < 64
19493 && (mode == DImode || (type && TYPE_MODE (type) == DImode))
19494 && (!type || !TYPE_USER_ALIGN (type))
19495 && (!decl || !DECL_USER_ALIGN (decl)))
19498 /* If TYPE is NULL, we are allocating a stack slot for caller-save
19499 register in MODE. We will return the largest alignment of XF
19503 if (mode == XFmode && align < GET_MODE_ALIGNMENT (DFmode))
19504 align = GET_MODE_ALIGNMENT (DFmode);
19508 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
19509 to 16byte boundary. */
19512 if (AGGREGATE_TYPE_P (type)
19513 && TYPE_SIZE (type)
19514 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
19515 && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 16
19516 || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 128)
19519 if (TREE_CODE (type) == ARRAY_TYPE)
19521 if (TYPE_MODE (TREE_TYPE (type)) == DFmode && align < 64)
19523 if (ALIGN_MODE_128 (TYPE_MODE (TREE_TYPE (type))) && align < 128)
19526 else if (TREE_CODE (type) == COMPLEX_TYPE)
19528 if (TYPE_MODE (type) == DCmode && align < 64)
19530 if ((TYPE_MODE (type) == XCmode
19531 || TYPE_MODE (type) == TCmode) && align < 128)
19534 else if ((TREE_CODE (type) == RECORD_TYPE
19535 || TREE_CODE (type) == UNION_TYPE
19536 || TREE_CODE (type) == QUAL_UNION_TYPE)
19537 && TYPE_FIELDS (type))
19539 if (DECL_MODE (TYPE_FIELDS (type)) == DFmode && align < 64)
19541 if (ALIGN_MODE_128 (DECL_MODE (TYPE_FIELDS (type))) && align < 128)
19544 else if (TREE_CODE (type) == REAL_TYPE || TREE_CODE (type) == VECTOR_TYPE
19545 || TREE_CODE (type) == INTEGER_TYPE)
19548 if (TYPE_MODE (type) == DFmode && align < 64)
19550 if (ALIGN_MODE_128 (TYPE_MODE (type)) && align < 128)
19556 /* Compute the minimum required alignment for dynamic stack realignment
19557 purposes for a local variable, parameter or a stack slot. EXP is
19558 the data type or decl itself, MODE is its mode and ALIGN is the
19559 alignment that the object would ordinarily have. */
19562 ix86_minimum_alignment (tree exp, enum machine_mode mode,
19563 unsigned int align)
19567 if (TARGET_64BIT || align != 64 || ix86_preferred_stack_boundary >= 64)
19570 if (exp && DECL_P (exp))
19572 type = TREE_TYPE (exp);
19581 /* Don't do dynamic stack realignment for long long objects with
19582 -mpreferred-stack-boundary=2. */
19583 if ((mode == DImode || (type && TYPE_MODE (type) == DImode))
19584 && (!type || !TYPE_USER_ALIGN (type))
19585 && (!decl || !DECL_USER_ALIGN (decl)))
19591 /* Emit RTL insns to initialize the variable parts of a trampoline.
19592 FNADDR is an RTX for the address of the function's pure code.
19593 CXT is an RTX for the static chain value for the function. */
19595 x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
19599 /* Compute offset from the end of the jmp to the target function. */
19600 rtx disp = expand_binop (SImode, sub_optab, fnaddr,
19601 plus_constant (tramp, 10),
19602 NULL_RTX, 1, OPTAB_DIRECT);
19603 emit_move_insn (gen_rtx_MEM (QImode, tramp),
19604 gen_int_mode (0xb9, QImode));
19605 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 1)), cxt);
19606 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, 5)),
19607 gen_int_mode (0xe9, QImode));
19608 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 6)), disp);
19613 /* Try to load address using shorter movl instead of movabs.
19614 We may want to support movq for kernel mode, but kernel does not use
19615 trampolines at the moment. */
19616 if (x86_64_zext_immediate_operand (fnaddr, VOIDmode))
19618 fnaddr = copy_to_mode_reg (DImode, fnaddr);
19619 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19620 gen_int_mode (0xbb41, HImode));
19621 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, offset + 2)),
19622 gen_lowpart (SImode, fnaddr));
19627 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19628 gen_int_mode (0xbb49, HImode));
19629 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19633 /* Load static chain using movabs to r10. */
19634 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19635 gen_int_mode (0xba49, HImode));
19636 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, offset + 2)),
19639 /* Jump to the r11 */
19640 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)),
19641 gen_int_mode (0xff49, HImode));
19642 emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)),
19643 gen_int_mode (0xe3, QImode));
19645 gcc_assert (offset <= TRAMPOLINE_SIZE);
19648 #ifdef ENABLE_EXECUTE_STACK
19649 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
19650 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
19654 /* Codes for all the SSE/MMX builtins. */
19657 IX86_BUILTIN_ADDPS,
19658 IX86_BUILTIN_ADDSS,
19659 IX86_BUILTIN_DIVPS,
19660 IX86_BUILTIN_DIVSS,
19661 IX86_BUILTIN_MULPS,
19662 IX86_BUILTIN_MULSS,
19663 IX86_BUILTIN_SUBPS,
19664 IX86_BUILTIN_SUBSS,
19666 IX86_BUILTIN_CMPEQPS,
19667 IX86_BUILTIN_CMPLTPS,
19668 IX86_BUILTIN_CMPLEPS,
19669 IX86_BUILTIN_CMPGTPS,
19670 IX86_BUILTIN_CMPGEPS,
19671 IX86_BUILTIN_CMPNEQPS,
19672 IX86_BUILTIN_CMPNLTPS,
19673 IX86_BUILTIN_CMPNLEPS,
19674 IX86_BUILTIN_CMPNGTPS,
19675 IX86_BUILTIN_CMPNGEPS,
19676 IX86_BUILTIN_CMPORDPS,
19677 IX86_BUILTIN_CMPUNORDPS,
19678 IX86_BUILTIN_CMPEQSS,
19679 IX86_BUILTIN_CMPLTSS,
19680 IX86_BUILTIN_CMPLESS,
19681 IX86_BUILTIN_CMPNEQSS,
19682 IX86_BUILTIN_CMPNLTSS,
19683 IX86_BUILTIN_CMPNLESS,
19684 IX86_BUILTIN_CMPNGTSS,
19685 IX86_BUILTIN_CMPNGESS,
19686 IX86_BUILTIN_CMPORDSS,
19687 IX86_BUILTIN_CMPUNORDSS,
19689 IX86_BUILTIN_COMIEQSS,
19690 IX86_BUILTIN_COMILTSS,
19691 IX86_BUILTIN_COMILESS,
19692 IX86_BUILTIN_COMIGTSS,
19693 IX86_BUILTIN_COMIGESS,
19694 IX86_BUILTIN_COMINEQSS,
19695 IX86_BUILTIN_UCOMIEQSS,
19696 IX86_BUILTIN_UCOMILTSS,
19697 IX86_BUILTIN_UCOMILESS,
19698 IX86_BUILTIN_UCOMIGTSS,
19699 IX86_BUILTIN_UCOMIGESS,
19700 IX86_BUILTIN_UCOMINEQSS,
19702 IX86_BUILTIN_CVTPI2PS,
19703 IX86_BUILTIN_CVTPS2PI,
19704 IX86_BUILTIN_CVTSI2SS,
19705 IX86_BUILTIN_CVTSI642SS,
19706 IX86_BUILTIN_CVTSS2SI,
19707 IX86_BUILTIN_CVTSS2SI64,
19708 IX86_BUILTIN_CVTTPS2PI,
19709 IX86_BUILTIN_CVTTSS2SI,
19710 IX86_BUILTIN_CVTTSS2SI64,
19712 IX86_BUILTIN_MAXPS,
19713 IX86_BUILTIN_MAXSS,
19714 IX86_BUILTIN_MINPS,
19715 IX86_BUILTIN_MINSS,
19717 IX86_BUILTIN_LOADUPS,
19718 IX86_BUILTIN_STOREUPS,
19719 IX86_BUILTIN_MOVSS,
19721 IX86_BUILTIN_MOVHLPS,
19722 IX86_BUILTIN_MOVLHPS,
19723 IX86_BUILTIN_LOADHPS,
19724 IX86_BUILTIN_LOADLPS,
19725 IX86_BUILTIN_STOREHPS,
19726 IX86_BUILTIN_STORELPS,
19728 IX86_BUILTIN_MASKMOVQ,
19729 IX86_BUILTIN_MOVMSKPS,
19730 IX86_BUILTIN_PMOVMSKB,
19732 IX86_BUILTIN_MOVNTPS,
19733 IX86_BUILTIN_MOVNTQ,
19735 IX86_BUILTIN_LOADDQU,
19736 IX86_BUILTIN_STOREDQU,
19738 IX86_BUILTIN_PACKSSWB,
19739 IX86_BUILTIN_PACKSSDW,
19740 IX86_BUILTIN_PACKUSWB,
19742 IX86_BUILTIN_PADDB,
19743 IX86_BUILTIN_PADDW,
19744 IX86_BUILTIN_PADDD,
19745 IX86_BUILTIN_PADDQ,
19746 IX86_BUILTIN_PADDSB,
19747 IX86_BUILTIN_PADDSW,
19748 IX86_BUILTIN_PADDUSB,
19749 IX86_BUILTIN_PADDUSW,
19750 IX86_BUILTIN_PSUBB,
19751 IX86_BUILTIN_PSUBW,
19752 IX86_BUILTIN_PSUBD,
19753 IX86_BUILTIN_PSUBQ,
19754 IX86_BUILTIN_PSUBSB,
19755 IX86_BUILTIN_PSUBSW,
19756 IX86_BUILTIN_PSUBUSB,
19757 IX86_BUILTIN_PSUBUSW,
19760 IX86_BUILTIN_PANDN,
19764 IX86_BUILTIN_PAVGB,
19765 IX86_BUILTIN_PAVGW,
19767 IX86_BUILTIN_PCMPEQB,
19768 IX86_BUILTIN_PCMPEQW,
19769 IX86_BUILTIN_PCMPEQD,
19770 IX86_BUILTIN_PCMPGTB,
19771 IX86_BUILTIN_PCMPGTW,
19772 IX86_BUILTIN_PCMPGTD,
19774 IX86_BUILTIN_PMADDWD,
19776 IX86_BUILTIN_PMAXSW,
19777 IX86_BUILTIN_PMAXUB,
19778 IX86_BUILTIN_PMINSW,
19779 IX86_BUILTIN_PMINUB,
19781 IX86_BUILTIN_PMULHUW,
19782 IX86_BUILTIN_PMULHW,
19783 IX86_BUILTIN_PMULLW,
19785 IX86_BUILTIN_PSADBW,
19786 IX86_BUILTIN_PSHUFW,
19788 IX86_BUILTIN_PSLLW,
19789 IX86_BUILTIN_PSLLD,
19790 IX86_BUILTIN_PSLLQ,
19791 IX86_BUILTIN_PSRAW,
19792 IX86_BUILTIN_PSRAD,
19793 IX86_BUILTIN_PSRLW,
19794 IX86_BUILTIN_PSRLD,
19795 IX86_BUILTIN_PSRLQ,
19796 IX86_BUILTIN_PSLLWI,
19797 IX86_BUILTIN_PSLLDI,
19798 IX86_BUILTIN_PSLLQI,
19799 IX86_BUILTIN_PSRAWI,
19800 IX86_BUILTIN_PSRADI,
19801 IX86_BUILTIN_PSRLWI,
19802 IX86_BUILTIN_PSRLDI,
19803 IX86_BUILTIN_PSRLQI,
19805 IX86_BUILTIN_PUNPCKHBW,
19806 IX86_BUILTIN_PUNPCKHWD,
19807 IX86_BUILTIN_PUNPCKHDQ,
19808 IX86_BUILTIN_PUNPCKLBW,
19809 IX86_BUILTIN_PUNPCKLWD,
19810 IX86_BUILTIN_PUNPCKLDQ,
19812 IX86_BUILTIN_SHUFPS,
19814 IX86_BUILTIN_RCPPS,
19815 IX86_BUILTIN_RCPSS,
19816 IX86_BUILTIN_RSQRTPS,
19817 IX86_BUILTIN_RSQRTPS_NR,
19818 IX86_BUILTIN_RSQRTSS,
19819 IX86_BUILTIN_RSQRTF,
19820 IX86_BUILTIN_SQRTPS,
19821 IX86_BUILTIN_SQRTPS_NR,
19822 IX86_BUILTIN_SQRTSS,
19824 IX86_BUILTIN_UNPCKHPS,
19825 IX86_BUILTIN_UNPCKLPS,
19827 IX86_BUILTIN_ANDPS,
19828 IX86_BUILTIN_ANDNPS,
19830 IX86_BUILTIN_XORPS,
19833 IX86_BUILTIN_LDMXCSR,
19834 IX86_BUILTIN_STMXCSR,
19835 IX86_BUILTIN_SFENCE,
19837 /* 3DNow! Original */
19838 IX86_BUILTIN_FEMMS,
19839 IX86_BUILTIN_PAVGUSB,
19840 IX86_BUILTIN_PF2ID,
19841 IX86_BUILTIN_PFACC,
19842 IX86_BUILTIN_PFADD,
19843 IX86_BUILTIN_PFCMPEQ,
19844 IX86_BUILTIN_PFCMPGE,
19845 IX86_BUILTIN_PFCMPGT,
19846 IX86_BUILTIN_PFMAX,
19847 IX86_BUILTIN_PFMIN,
19848 IX86_BUILTIN_PFMUL,
19849 IX86_BUILTIN_PFRCP,
19850 IX86_BUILTIN_PFRCPIT1,
19851 IX86_BUILTIN_PFRCPIT2,
19852 IX86_BUILTIN_PFRSQIT1,
19853 IX86_BUILTIN_PFRSQRT,
19854 IX86_BUILTIN_PFSUB,
19855 IX86_BUILTIN_PFSUBR,
19856 IX86_BUILTIN_PI2FD,
19857 IX86_BUILTIN_PMULHRW,
19859 /* 3DNow! Athlon Extensions */
19860 IX86_BUILTIN_PF2IW,
19861 IX86_BUILTIN_PFNACC,
19862 IX86_BUILTIN_PFPNACC,
19863 IX86_BUILTIN_PI2FW,
19864 IX86_BUILTIN_PSWAPDSI,
19865 IX86_BUILTIN_PSWAPDSF,
19868 IX86_BUILTIN_ADDPD,
19869 IX86_BUILTIN_ADDSD,
19870 IX86_BUILTIN_DIVPD,
19871 IX86_BUILTIN_DIVSD,
19872 IX86_BUILTIN_MULPD,
19873 IX86_BUILTIN_MULSD,
19874 IX86_BUILTIN_SUBPD,
19875 IX86_BUILTIN_SUBSD,
19877 IX86_BUILTIN_CMPEQPD,
19878 IX86_BUILTIN_CMPLTPD,
19879 IX86_BUILTIN_CMPLEPD,
19880 IX86_BUILTIN_CMPGTPD,
19881 IX86_BUILTIN_CMPGEPD,
19882 IX86_BUILTIN_CMPNEQPD,
19883 IX86_BUILTIN_CMPNLTPD,
19884 IX86_BUILTIN_CMPNLEPD,
19885 IX86_BUILTIN_CMPNGTPD,
19886 IX86_BUILTIN_CMPNGEPD,
19887 IX86_BUILTIN_CMPORDPD,
19888 IX86_BUILTIN_CMPUNORDPD,
19889 IX86_BUILTIN_CMPEQSD,
19890 IX86_BUILTIN_CMPLTSD,
19891 IX86_BUILTIN_CMPLESD,
19892 IX86_BUILTIN_CMPNEQSD,
19893 IX86_BUILTIN_CMPNLTSD,
19894 IX86_BUILTIN_CMPNLESD,
19895 IX86_BUILTIN_CMPORDSD,
19896 IX86_BUILTIN_CMPUNORDSD,
19898 IX86_BUILTIN_COMIEQSD,
19899 IX86_BUILTIN_COMILTSD,
19900 IX86_BUILTIN_COMILESD,
19901 IX86_BUILTIN_COMIGTSD,
19902 IX86_BUILTIN_COMIGESD,
19903 IX86_BUILTIN_COMINEQSD,
19904 IX86_BUILTIN_UCOMIEQSD,
19905 IX86_BUILTIN_UCOMILTSD,
19906 IX86_BUILTIN_UCOMILESD,
19907 IX86_BUILTIN_UCOMIGTSD,
19908 IX86_BUILTIN_UCOMIGESD,
19909 IX86_BUILTIN_UCOMINEQSD,
19911 IX86_BUILTIN_MAXPD,
19912 IX86_BUILTIN_MAXSD,
19913 IX86_BUILTIN_MINPD,
19914 IX86_BUILTIN_MINSD,
19916 IX86_BUILTIN_ANDPD,
19917 IX86_BUILTIN_ANDNPD,
19919 IX86_BUILTIN_XORPD,
19921 IX86_BUILTIN_SQRTPD,
19922 IX86_BUILTIN_SQRTSD,
19924 IX86_BUILTIN_UNPCKHPD,
19925 IX86_BUILTIN_UNPCKLPD,
19927 IX86_BUILTIN_SHUFPD,
19929 IX86_BUILTIN_LOADUPD,
19930 IX86_BUILTIN_STOREUPD,
19931 IX86_BUILTIN_MOVSD,
19933 IX86_BUILTIN_LOADHPD,
19934 IX86_BUILTIN_LOADLPD,
19936 IX86_BUILTIN_CVTDQ2PD,
19937 IX86_BUILTIN_CVTDQ2PS,
19939 IX86_BUILTIN_CVTPD2DQ,
19940 IX86_BUILTIN_CVTPD2PI,
19941 IX86_BUILTIN_CVTPD2PS,
19942 IX86_BUILTIN_CVTTPD2DQ,
19943 IX86_BUILTIN_CVTTPD2PI,
19945 IX86_BUILTIN_CVTPI2PD,
19946 IX86_BUILTIN_CVTSI2SD,
19947 IX86_BUILTIN_CVTSI642SD,
19949 IX86_BUILTIN_CVTSD2SI,
19950 IX86_BUILTIN_CVTSD2SI64,
19951 IX86_BUILTIN_CVTSD2SS,
19952 IX86_BUILTIN_CVTSS2SD,
19953 IX86_BUILTIN_CVTTSD2SI,
19954 IX86_BUILTIN_CVTTSD2SI64,
19956 IX86_BUILTIN_CVTPS2DQ,
19957 IX86_BUILTIN_CVTPS2PD,
19958 IX86_BUILTIN_CVTTPS2DQ,
19960 IX86_BUILTIN_MOVNTI,
19961 IX86_BUILTIN_MOVNTPD,
19962 IX86_BUILTIN_MOVNTDQ,
19964 IX86_BUILTIN_MOVQ128,
19967 IX86_BUILTIN_MASKMOVDQU,
19968 IX86_BUILTIN_MOVMSKPD,
19969 IX86_BUILTIN_PMOVMSKB128,
19971 IX86_BUILTIN_PACKSSWB128,
19972 IX86_BUILTIN_PACKSSDW128,
19973 IX86_BUILTIN_PACKUSWB128,
19975 IX86_BUILTIN_PADDB128,
19976 IX86_BUILTIN_PADDW128,
19977 IX86_BUILTIN_PADDD128,
19978 IX86_BUILTIN_PADDQ128,
19979 IX86_BUILTIN_PADDSB128,
19980 IX86_BUILTIN_PADDSW128,
19981 IX86_BUILTIN_PADDUSB128,
19982 IX86_BUILTIN_PADDUSW128,
19983 IX86_BUILTIN_PSUBB128,
19984 IX86_BUILTIN_PSUBW128,
19985 IX86_BUILTIN_PSUBD128,
19986 IX86_BUILTIN_PSUBQ128,
19987 IX86_BUILTIN_PSUBSB128,
19988 IX86_BUILTIN_PSUBSW128,
19989 IX86_BUILTIN_PSUBUSB128,
19990 IX86_BUILTIN_PSUBUSW128,
19992 IX86_BUILTIN_PAND128,
19993 IX86_BUILTIN_PANDN128,
19994 IX86_BUILTIN_POR128,
19995 IX86_BUILTIN_PXOR128,
19997 IX86_BUILTIN_PAVGB128,
19998 IX86_BUILTIN_PAVGW128,
20000 IX86_BUILTIN_PCMPEQB128,
20001 IX86_BUILTIN_PCMPEQW128,
20002 IX86_BUILTIN_PCMPEQD128,
20003 IX86_BUILTIN_PCMPGTB128,
20004 IX86_BUILTIN_PCMPGTW128,
20005 IX86_BUILTIN_PCMPGTD128,
20007 IX86_BUILTIN_PMADDWD128,
20009 IX86_BUILTIN_PMAXSW128,
20010 IX86_BUILTIN_PMAXUB128,
20011 IX86_BUILTIN_PMINSW128,
20012 IX86_BUILTIN_PMINUB128,
20014 IX86_BUILTIN_PMULUDQ,
20015 IX86_BUILTIN_PMULUDQ128,
20016 IX86_BUILTIN_PMULHUW128,
20017 IX86_BUILTIN_PMULHW128,
20018 IX86_BUILTIN_PMULLW128,
20020 IX86_BUILTIN_PSADBW128,
20021 IX86_BUILTIN_PSHUFHW,
20022 IX86_BUILTIN_PSHUFLW,
20023 IX86_BUILTIN_PSHUFD,
20025 IX86_BUILTIN_PSLLDQI128,
20026 IX86_BUILTIN_PSLLWI128,
20027 IX86_BUILTIN_PSLLDI128,
20028 IX86_BUILTIN_PSLLQI128,
20029 IX86_BUILTIN_PSRAWI128,
20030 IX86_BUILTIN_PSRADI128,
20031 IX86_BUILTIN_PSRLDQI128,
20032 IX86_BUILTIN_PSRLWI128,
20033 IX86_BUILTIN_PSRLDI128,
20034 IX86_BUILTIN_PSRLQI128,
20036 IX86_BUILTIN_PSLLDQ128,
20037 IX86_BUILTIN_PSLLW128,
20038 IX86_BUILTIN_PSLLD128,
20039 IX86_BUILTIN_PSLLQ128,
20040 IX86_BUILTIN_PSRAW128,
20041 IX86_BUILTIN_PSRAD128,
20042 IX86_BUILTIN_PSRLW128,
20043 IX86_BUILTIN_PSRLD128,
20044 IX86_BUILTIN_PSRLQ128,
20046 IX86_BUILTIN_PUNPCKHBW128,
20047 IX86_BUILTIN_PUNPCKHWD128,
20048 IX86_BUILTIN_PUNPCKHDQ128,
20049 IX86_BUILTIN_PUNPCKHQDQ128,
20050 IX86_BUILTIN_PUNPCKLBW128,
20051 IX86_BUILTIN_PUNPCKLWD128,
20052 IX86_BUILTIN_PUNPCKLDQ128,
20053 IX86_BUILTIN_PUNPCKLQDQ128,
20055 IX86_BUILTIN_CLFLUSH,
20056 IX86_BUILTIN_MFENCE,
20057 IX86_BUILTIN_LFENCE,
20060 IX86_BUILTIN_ADDSUBPS,
20061 IX86_BUILTIN_HADDPS,
20062 IX86_BUILTIN_HSUBPS,
20063 IX86_BUILTIN_MOVSHDUP,
20064 IX86_BUILTIN_MOVSLDUP,
20065 IX86_BUILTIN_ADDSUBPD,
20066 IX86_BUILTIN_HADDPD,
20067 IX86_BUILTIN_HSUBPD,
20068 IX86_BUILTIN_LDDQU,
20070 IX86_BUILTIN_MONITOR,
20071 IX86_BUILTIN_MWAIT,
20074 IX86_BUILTIN_PHADDW,
20075 IX86_BUILTIN_PHADDD,
20076 IX86_BUILTIN_PHADDSW,
20077 IX86_BUILTIN_PHSUBW,
20078 IX86_BUILTIN_PHSUBD,
20079 IX86_BUILTIN_PHSUBSW,
20080 IX86_BUILTIN_PMADDUBSW,
20081 IX86_BUILTIN_PMULHRSW,
20082 IX86_BUILTIN_PSHUFB,
20083 IX86_BUILTIN_PSIGNB,
20084 IX86_BUILTIN_PSIGNW,
20085 IX86_BUILTIN_PSIGND,
20086 IX86_BUILTIN_PALIGNR,
20087 IX86_BUILTIN_PABSB,
20088 IX86_BUILTIN_PABSW,
20089 IX86_BUILTIN_PABSD,
20091 IX86_BUILTIN_PHADDW128,
20092 IX86_BUILTIN_PHADDD128,
20093 IX86_BUILTIN_PHADDSW128,
20094 IX86_BUILTIN_PHSUBW128,
20095 IX86_BUILTIN_PHSUBD128,
20096 IX86_BUILTIN_PHSUBSW128,
20097 IX86_BUILTIN_PMADDUBSW128,
20098 IX86_BUILTIN_PMULHRSW128,
20099 IX86_BUILTIN_PSHUFB128,
20100 IX86_BUILTIN_PSIGNB128,
20101 IX86_BUILTIN_PSIGNW128,
20102 IX86_BUILTIN_PSIGND128,
20103 IX86_BUILTIN_PALIGNR128,
20104 IX86_BUILTIN_PABSB128,
20105 IX86_BUILTIN_PABSW128,
20106 IX86_BUILTIN_PABSD128,
20108 /* AMDFAM10 - SSE4A New Instructions. */
20109 IX86_BUILTIN_MOVNTSD,
20110 IX86_BUILTIN_MOVNTSS,
20111 IX86_BUILTIN_EXTRQI,
20112 IX86_BUILTIN_EXTRQ,
20113 IX86_BUILTIN_INSERTQI,
20114 IX86_BUILTIN_INSERTQ,
20117 IX86_BUILTIN_BLENDPD,
20118 IX86_BUILTIN_BLENDPS,
20119 IX86_BUILTIN_BLENDVPD,
20120 IX86_BUILTIN_BLENDVPS,
20121 IX86_BUILTIN_PBLENDVB128,
20122 IX86_BUILTIN_PBLENDW128,
20127 IX86_BUILTIN_INSERTPS128,
20129 IX86_BUILTIN_MOVNTDQA,
20130 IX86_BUILTIN_MPSADBW128,
20131 IX86_BUILTIN_PACKUSDW128,
20132 IX86_BUILTIN_PCMPEQQ,
20133 IX86_BUILTIN_PHMINPOSUW128,
20135 IX86_BUILTIN_PMAXSB128,
20136 IX86_BUILTIN_PMAXSD128,
20137 IX86_BUILTIN_PMAXUD128,
20138 IX86_BUILTIN_PMAXUW128,
20140 IX86_BUILTIN_PMINSB128,
20141 IX86_BUILTIN_PMINSD128,
20142 IX86_BUILTIN_PMINUD128,
20143 IX86_BUILTIN_PMINUW128,
20145 IX86_BUILTIN_PMOVSXBW128,
20146 IX86_BUILTIN_PMOVSXBD128,
20147 IX86_BUILTIN_PMOVSXBQ128,
20148 IX86_BUILTIN_PMOVSXWD128,
20149 IX86_BUILTIN_PMOVSXWQ128,
20150 IX86_BUILTIN_PMOVSXDQ128,
20152 IX86_BUILTIN_PMOVZXBW128,
20153 IX86_BUILTIN_PMOVZXBD128,
20154 IX86_BUILTIN_PMOVZXBQ128,
20155 IX86_BUILTIN_PMOVZXWD128,
20156 IX86_BUILTIN_PMOVZXWQ128,
20157 IX86_BUILTIN_PMOVZXDQ128,
20159 IX86_BUILTIN_PMULDQ128,
20160 IX86_BUILTIN_PMULLD128,
20162 IX86_BUILTIN_ROUNDPD,
20163 IX86_BUILTIN_ROUNDPS,
20164 IX86_BUILTIN_ROUNDSD,
20165 IX86_BUILTIN_ROUNDSS,
20167 IX86_BUILTIN_PTESTZ,
20168 IX86_BUILTIN_PTESTC,
20169 IX86_BUILTIN_PTESTNZC,
20171 IX86_BUILTIN_VEC_INIT_V2SI,
20172 IX86_BUILTIN_VEC_INIT_V4HI,
20173 IX86_BUILTIN_VEC_INIT_V8QI,
20174 IX86_BUILTIN_VEC_EXT_V2DF,
20175 IX86_BUILTIN_VEC_EXT_V2DI,
20176 IX86_BUILTIN_VEC_EXT_V4SF,
20177 IX86_BUILTIN_VEC_EXT_V4SI,
20178 IX86_BUILTIN_VEC_EXT_V8HI,
20179 IX86_BUILTIN_VEC_EXT_V2SI,
20180 IX86_BUILTIN_VEC_EXT_V4HI,
20181 IX86_BUILTIN_VEC_EXT_V16QI,
20182 IX86_BUILTIN_VEC_SET_V2DI,
20183 IX86_BUILTIN_VEC_SET_V4SF,
20184 IX86_BUILTIN_VEC_SET_V4SI,
20185 IX86_BUILTIN_VEC_SET_V8HI,
20186 IX86_BUILTIN_VEC_SET_V4HI,
20187 IX86_BUILTIN_VEC_SET_V16QI,
20189 IX86_BUILTIN_VEC_PACK_SFIX,
20192 IX86_BUILTIN_CRC32QI,
20193 IX86_BUILTIN_CRC32HI,
20194 IX86_BUILTIN_CRC32SI,
20195 IX86_BUILTIN_CRC32DI,
20197 IX86_BUILTIN_PCMPESTRI128,
20198 IX86_BUILTIN_PCMPESTRM128,
20199 IX86_BUILTIN_PCMPESTRA128,
20200 IX86_BUILTIN_PCMPESTRC128,
20201 IX86_BUILTIN_PCMPESTRO128,
20202 IX86_BUILTIN_PCMPESTRS128,
20203 IX86_BUILTIN_PCMPESTRZ128,
20204 IX86_BUILTIN_PCMPISTRI128,
20205 IX86_BUILTIN_PCMPISTRM128,
20206 IX86_BUILTIN_PCMPISTRA128,
20207 IX86_BUILTIN_PCMPISTRC128,
20208 IX86_BUILTIN_PCMPISTRO128,
20209 IX86_BUILTIN_PCMPISTRS128,
20210 IX86_BUILTIN_PCMPISTRZ128,
20212 IX86_BUILTIN_PCMPGTQ,
20214 /* AES instructions */
20215 IX86_BUILTIN_AESENC128,
20216 IX86_BUILTIN_AESENCLAST128,
20217 IX86_BUILTIN_AESDEC128,
20218 IX86_BUILTIN_AESDECLAST128,
20219 IX86_BUILTIN_AESIMC128,
20220 IX86_BUILTIN_AESKEYGENASSIST128,
20222 /* PCLMUL instruction */
20223 IX86_BUILTIN_PCLMULQDQ128,
20226 IX86_BUILTIN_ADDPD256,
20227 IX86_BUILTIN_ADDPS256,
20228 IX86_BUILTIN_ADDSUBPD256,
20229 IX86_BUILTIN_ADDSUBPS256,
20230 IX86_BUILTIN_ANDPD256,
20231 IX86_BUILTIN_ANDPS256,
20232 IX86_BUILTIN_ANDNPD256,
20233 IX86_BUILTIN_ANDNPS256,
20234 IX86_BUILTIN_BLENDPD256,
20235 IX86_BUILTIN_BLENDPS256,
20236 IX86_BUILTIN_BLENDVPD256,
20237 IX86_BUILTIN_BLENDVPS256,
20238 IX86_BUILTIN_DIVPD256,
20239 IX86_BUILTIN_DIVPS256,
20240 IX86_BUILTIN_DPPS256,
20241 IX86_BUILTIN_HADDPD256,
20242 IX86_BUILTIN_HADDPS256,
20243 IX86_BUILTIN_HSUBPD256,
20244 IX86_BUILTIN_HSUBPS256,
20245 IX86_BUILTIN_MAXPD256,
20246 IX86_BUILTIN_MAXPS256,
20247 IX86_BUILTIN_MINPD256,
20248 IX86_BUILTIN_MINPS256,
20249 IX86_BUILTIN_MULPD256,
20250 IX86_BUILTIN_MULPS256,
20251 IX86_BUILTIN_ORPD256,
20252 IX86_BUILTIN_ORPS256,
20253 IX86_BUILTIN_SHUFPD256,
20254 IX86_BUILTIN_SHUFPS256,
20255 IX86_BUILTIN_SUBPD256,
20256 IX86_BUILTIN_SUBPS256,
20257 IX86_BUILTIN_XORPD256,
20258 IX86_BUILTIN_XORPS256,
20259 IX86_BUILTIN_CMPSD,
20260 IX86_BUILTIN_CMPSS,
20261 IX86_BUILTIN_CMPPD,
20262 IX86_BUILTIN_CMPPS,
20263 IX86_BUILTIN_CMPPD256,
20264 IX86_BUILTIN_CMPPS256,
20265 IX86_BUILTIN_CVTDQ2PD256,
20266 IX86_BUILTIN_CVTDQ2PS256,
20267 IX86_BUILTIN_CVTPD2PS256,
20268 IX86_BUILTIN_CVTPS2DQ256,
20269 IX86_BUILTIN_CVTPS2PD256,
20270 IX86_BUILTIN_CVTTPD2DQ256,
20271 IX86_BUILTIN_CVTPD2DQ256,
20272 IX86_BUILTIN_CVTTPS2DQ256,
20273 IX86_BUILTIN_EXTRACTF128PD256,
20274 IX86_BUILTIN_EXTRACTF128PS256,
20275 IX86_BUILTIN_EXTRACTF128SI256,
20276 IX86_BUILTIN_VZEROALL,
20277 IX86_BUILTIN_VZEROUPPER,
20278 IX86_BUILTIN_VZEROUPPER_REX64,
20279 IX86_BUILTIN_VPERMILVARPD,
20280 IX86_BUILTIN_VPERMILVARPS,
20281 IX86_BUILTIN_VPERMILVARPD256,
20282 IX86_BUILTIN_VPERMILVARPS256,
20283 IX86_BUILTIN_VPERMILPD,
20284 IX86_BUILTIN_VPERMILPS,
20285 IX86_BUILTIN_VPERMILPD256,
20286 IX86_BUILTIN_VPERMILPS256,
20287 IX86_BUILTIN_VPERM2F128PD256,
20288 IX86_BUILTIN_VPERM2F128PS256,
20289 IX86_BUILTIN_VPERM2F128SI256,
20290 IX86_BUILTIN_VBROADCASTSS,
20291 IX86_BUILTIN_VBROADCASTSD256,
20292 IX86_BUILTIN_VBROADCASTSS256,
20293 IX86_BUILTIN_VBROADCASTPD256,
20294 IX86_BUILTIN_VBROADCASTPS256,
20295 IX86_BUILTIN_VINSERTF128PD256,
20296 IX86_BUILTIN_VINSERTF128PS256,
20297 IX86_BUILTIN_VINSERTF128SI256,
20298 IX86_BUILTIN_LOADUPD256,
20299 IX86_BUILTIN_LOADUPS256,
20300 IX86_BUILTIN_STOREUPD256,
20301 IX86_BUILTIN_STOREUPS256,
20302 IX86_BUILTIN_LDDQU256,
20303 IX86_BUILTIN_MOVNTDQ256,
20304 IX86_BUILTIN_MOVNTPD256,
20305 IX86_BUILTIN_MOVNTPS256,
20306 IX86_BUILTIN_LOADDQU256,
20307 IX86_BUILTIN_STOREDQU256,
20308 IX86_BUILTIN_MASKLOADPD,
20309 IX86_BUILTIN_MASKLOADPS,
20310 IX86_BUILTIN_MASKSTOREPD,
20311 IX86_BUILTIN_MASKSTOREPS,
20312 IX86_BUILTIN_MASKLOADPD256,
20313 IX86_BUILTIN_MASKLOADPS256,
20314 IX86_BUILTIN_MASKSTOREPD256,
20315 IX86_BUILTIN_MASKSTOREPS256,
20316 IX86_BUILTIN_MOVSHDUP256,
20317 IX86_BUILTIN_MOVSLDUP256,
20318 IX86_BUILTIN_MOVDDUP256,
20320 IX86_BUILTIN_SQRTPD256,
20321 IX86_BUILTIN_SQRTPS256,
20322 IX86_BUILTIN_SQRTPS_NR256,
20323 IX86_BUILTIN_RSQRTPS256,
20324 IX86_BUILTIN_RSQRTPS_NR256,
20326 IX86_BUILTIN_RCPPS256,
20328 IX86_BUILTIN_ROUNDPD256,
20329 IX86_BUILTIN_ROUNDPS256,
20331 IX86_BUILTIN_UNPCKHPD256,
20332 IX86_BUILTIN_UNPCKLPD256,
20333 IX86_BUILTIN_UNPCKHPS256,
20334 IX86_BUILTIN_UNPCKLPS256,
20336 IX86_BUILTIN_SI256_SI,
20337 IX86_BUILTIN_PS256_PS,
20338 IX86_BUILTIN_PD256_PD,
20339 IX86_BUILTIN_SI_SI256,
20340 IX86_BUILTIN_PS_PS256,
20341 IX86_BUILTIN_PD_PD256,
20343 IX86_BUILTIN_VTESTZPD,
20344 IX86_BUILTIN_VTESTCPD,
20345 IX86_BUILTIN_VTESTNZCPD,
20346 IX86_BUILTIN_VTESTZPS,
20347 IX86_BUILTIN_VTESTCPS,
20348 IX86_BUILTIN_VTESTNZCPS,
20349 IX86_BUILTIN_VTESTZPD256,
20350 IX86_BUILTIN_VTESTCPD256,
20351 IX86_BUILTIN_VTESTNZCPD256,
20352 IX86_BUILTIN_VTESTZPS256,
20353 IX86_BUILTIN_VTESTCPS256,
20354 IX86_BUILTIN_VTESTNZCPS256,
20355 IX86_BUILTIN_PTESTZ256,
20356 IX86_BUILTIN_PTESTC256,
20357 IX86_BUILTIN_PTESTNZC256,
20359 IX86_BUILTIN_MOVMSKPD256,
20360 IX86_BUILTIN_MOVMSKPS256,
20362 /* TFmode support builtins. */
20364 IX86_BUILTIN_FABSQ,
20365 IX86_BUILTIN_COPYSIGNQ,
20367 /* SSE5 instructions */
20368 IX86_BUILTIN_FMADDSS,
20369 IX86_BUILTIN_FMADDSD,
20370 IX86_BUILTIN_FMADDPS,
20371 IX86_BUILTIN_FMADDPD,
20372 IX86_BUILTIN_FMSUBSS,
20373 IX86_BUILTIN_FMSUBSD,
20374 IX86_BUILTIN_FMSUBPS,
20375 IX86_BUILTIN_FMSUBPD,
20376 IX86_BUILTIN_FNMADDSS,
20377 IX86_BUILTIN_FNMADDSD,
20378 IX86_BUILTIN_FNMADDPS,
20379 IX86_BUILTIN_FNMADDPD,
20380 IX86_BUILTIN_FNMSUBSS,
20381 IX86_BUILTIN_FNMSUBSD,
20382 IX86_BUILTIN_FNMSUBPS,
20383 IX86_BUILTIN_FNMSUBPD,
20384 IX86_BUILTIN_PCMOV,
20385 IX86_BUILTIN_PCMOV_V2DI,
20386 IX86_BUILTIN_PCMOV_V4SI,
20387 IX86_BUILTIN_PCMOV_V8HI,
20388 IX86_BUILTIN_PCMOV_V16QI,
20389 IX86_BUILTIN_PCMOV_V4SF,
20390 IX86_BUILTIN_PCMOV_V2DF,
20391 IX86_BUILTIN_PPERM,
20392 IX86_BUILTIN_PERMPS,
20393 IX86_BUILTIN_PERMPD,
20394 IX86_BUILTIN_PMACSSWW,
20395 IX86_BUILTIN_PMACSWW,
20396 IX86_BUILTIN_PMACSSWD,
20397 IX86_BUILTIN_PMACSWD,
20398 IX86_BUILTIN_PMACSSDD,
20399 IX86_BUILTIN_PMACSDD,
20400 IX86_BUILTIN_PMACSSDQL,
20401 IX86_BUILTIN_PMACSSDQH,
20402 IX86_BUILTIN_PMACSDQL,
20403 IX86_BUILTIN_PMACSDQH,
20404 IX86_BUILTIN_PMADCSSWD,
20405 IX86_BUILTIN_PMADCSWD,
20406 IX86_BUILTIN_PHADDBW,
20407 IX86_BUILTIN_PHADDBD,
20408 IX86_BUILTIN_PHADDBQ,
20409 IX86_BUILTIN_PHADDWD,
20410 IX86_BUILTIN_PHADDWQ,
20411 IX86_BUILTIN_PHADDDQ,
20412 IX86_BUILTIN_PHADDUBW,
20413 IX86_BUILTIN_PHADDUBD,
20414 IX86_BUILTIN_PHADDUBQ,
20415 IX86_BUILTIN_PHADDUWD,
20416 IX86_BUILTIN_PHADDUWQ,
20417 IX86_BUILTIN_PHADDUDQ,
20418 IX86_BUILTIN_PHSUBBW,
20419 IX86_BUILTIN_PHSUBWD,
20420 IX86_BUILTIN_PHSUBDQ,
20421 IX86_BUILTIN_PROTB,
20422 IX86_BUILTIN_PROTW,
20423 IX86_BUILTIN_PROTD,
20424 IX86_BUILTIN_PROTQ,
20425 IX86_BUILTIN_PROTB_IMM,
20426 IX86_BUILTIN_PROTW_IMM,
20427 IX86_BUILTIN_PROTD_IMM,
20428 IX86_BUILTIN_PROTQ_IMM,
20429 IX86_BUILTIN_PSHLB,
20430 IX86_BUILTIN_PSHLW,
20431 IX86_BUILTIN_PSHLD,
20432 IX86_BUILTIN_PSHLQ,
20433 IX86_BUILTIN_PSHAB,
20434 IX86_BUILTIN_PSHAW,
20435 IX86_BUILTIN_PSHAD,
20436 IX86_BUILTIN_PSHAQ,
20437 IX86_BUILTIN_FRCZSS,
20438 IX86_BUILTIN_FRCZSD,
20439 IX86_BUILTIN_FRCZPS,
20440 IX86_BUILTIN_FRCZPD,
20441 IX86_BUILTIN_CVTPH2PS,
20442 IX86_BUILTIN_CVTPS2PH,
20444 IX86_BUILTIN_COMEQSS,
20445 IX86_BUILTIN_COMNESS,
20446 IX86_BUILTIN_COMLTSS,
20447 IX86_BUILTIN_COMLESS,
20448 IX86_BUILTIN_COMGTSS,
20449 IX86_BUILTIN_COMGESS,
20450 IX86_BUILTIN_COMUEQSS,
20451 IX86_BUILTIN_COMUNESS,
20452 IX86_BUILTIN_COMULTSS,
20453 IX86_BUILTIN_COMULESS,
20454 IX86_BUILTIN_COMUGTSS,
20455 IX86_BUILTIN_COMUGESS,
20456 IX86_BUILTIN_COMORDSS,
20457 IX86_BUILTIN_COMUNORDSS,
20458 IX86_BUILTIN_COMFALSESS,
20459 IX86_BUILTIN_COMTRUESS,
20461 IX86_BUILTIN_COMEQSD,
20462 IX86_BUILTIN_COMNESD,
20463 IX86_BUILTIN_COMLTSD,
20464 IX86_BUILTIN_COMLESD,
20465 IX86_BUILTIN_COMGTSD,
20466 IX86_BUILTIN_COMGESD,
20467 IX86_BUILTIN_COMUEQSD,
20468 IX86_BUILTIN_COMUNESD,
20469 IX86_BUILTIN_COMULTSD,
20470 IX86_BUILTIN_COMULESD,
20471 IX86_BUILTIN_COMUGTSD,
20472 IX86_BUILTIN_COMUGESD,
20473 IX86_BUILTIN_COMORDSD,
20474 IX86_BUILTIN_COMUNORDSD,
20475 IX86_BUILTIN_COMFALSESD,
20476 IX86_BUILTIN_COMTRUESD,
20478 IX86_BUILTIN_COMEQPS,
20479 IX86_BUILTIN_COMNEPS,
20480 IX86_BUILTIN_COMLTPS,
20481 IX86_BUILTIN_COMLEPS,
20482 IX86_BUILTIN_COMGTPS,
20483 IX86_BUILTIN_COMGEPS,
20484 IX86_BUILTIN_COMUEQPS,
20485 IX86_BUILTIN_COMUNEPS,
20486 IX86_BUILTIN_COMULTPS,
20487 IX86_BUILTIN_COMULEPS,
20488 IX86_BUILTIN_COMUGTPS,
20489 IX86_BUILTIN_COMUGEPS,
20490 IX86_BUILTIN_COMORDPS,
20491 IX86_BUILTIN_COMUNORDPS,
20492 IX86_BUILTIN_COMFALSEPS,
20493 IX86_BUILTIN_COMTRUEPS,
20495 IX86_BUILTIN_COMEQPD,
20496 IX86_BUILTIN_COMNEPD,
20497 IX86_BUILTIN_COMLTPD,
20498 IX86_BUILTIN_COMLEPD,
20499 IX86_BUILTIN_COMGTPD,
20500 IX86_BUILTIN_COMGEPD,
20501 IX86_BUILTIN_COMUEQPD,
20502 IX86_BUILTIN_COMUNEPD,
20503 IX86_BUILTIN_COMULTPD,
20504 IX86_BUILTIN_COMULEPD,
20505 IX86_BUILTIN_COMUGTPD,
20506 IX86_BUILTIN_COMUGEPD,
20507 IX86_BUILTIN_COMORDPD,
20508 IX86_BUILTIN_COMUNORDPD,
20509 IX86_BUILTIN_COMFALSEPD,
20510 IX86_BUILTIN_COMTRUEPD,
20512 IX86_BUILTIN_PCOMEQUB,
20513 IX86_BUILTIN_PCOMNEUB,
20514 IX86_BUILTIN_PCOMLTUB,
20515 IX86_BUILTIN_PCOMLEUB,
20516 IX86_BUILTIN_PCOMGTUB,
20517 IX86_BUILTIN_PCOMGEUB,
20518 IX86_BUILTIN_PCOMFALSEUB,
20519 IX86_BUILTIN_PCOMTRUEUB,
20520 IX86_BUILTIN_PCOMEQUW,
20521 IX86_BUILTIN_PCOMNEUW,
20522 IX86_BUILTIN_PCOMLTUW,
20523 IX86_BUILTIN_PCOMLEUW,
20524 IX86_BUILTIN_PCOMGTUW,
20525 IX86_BUILTIN_PCOMGEUW,
20526 IX86_BUILTIN_PCOMFALSEUW,
20527 IX86_BUILTIN_PCOMTRUEUW,
20528 IX86_BUILTIN_PCOMEQUD,
20529 IX86_BUILTIN_PCOMNEUD,
20530 IX86_BUILTIN_PCOMLTUD,
20531 IX86_BUILTIN_PCOMLEUD,
20532 IX86_BUILTIN_PCOMGTUD,
20533 IX86_BUILTIN_PCOMGEUD,
20534 IX86_BUILTIN_PCOMFALSEUD,
20535 IX86_BUILTIN_PCOMTRUEUD,
20536 IX86_BUILTIN_PCOMEQUQ,
20537 IX86_BUILTIN_PCOMNEUQ,
20538 IX86_BUILTIN_PCOMLTUQ,
20539 IX86_BUILTIN_PCOMLEUQ,
20540 IX86_BUILTIN_PCOMGTUQ,
20541 IX86_BUILTIN_PCOMGEUQ,
20542 IX86_BUILTIN_PCOMFALSEUQ,
20543 IX86_BUILTIN_PCOMTRUEUQ,
20545 IX86_BUILTIN_PCOMEQB,
20546 IX86_BUILTIN_PCOMNEB,
20547 IX86_BUILTIN_PCOMLTB,
20548 IX86_BUILTIN_PCOMLEB,
20549 IX86_BUILTIN_PCOMGTB,
20550 IX86_BUILTIN_PCOMGEB,
20551 IX86_BUILTIN_PCOMFALSEB,
20552 IX86_BUILTIN_PCOMTRUEB,
20553 IX86_BUILTIN_PCOMEQW,
20554 IX86_BUILTIN_PCOMNEW,
20555 IX86_BUILTIN_PCOMLTW,
20556 IX86_BUILTIN_PCOMLEW,
20557 IX86_BUILTIN_PCOMGTW,
20558 IX86_BUILTIN_PCOMGEW,
20559 IX86_BUILTIN_PCOMFALSEW,
20560 IX86_BUILTIN_PCOMTRUEW,
20561 IX86_BUILTIN_PCOMEQD,
20562 IX86_BUILTIN_PCOMNED,
20563 IX86_BUILTIN_PCOMLTD,
20564 IX86_BUILTIN_PCOMLED,
20565 IX86_BUILTIN_PCOMGTD,
20566 IX86_BUILTIN_PCOMGED,
20567 IX86_BUILTIN_PCOMFALSED,
20568 IX86_BUILTIN_PCOMTRUED,
20569 IX86_BUILTIN_PCOMEQQ,
20570 IX86_BUILTIN_PCOMNEQ,
20571 IX86_BUILTIN_PCOMLTQ,
20572 IX86_BUILTIN_PCOMLEQ,
20573 IX86_BUILTIN_PCOMGTQ,
20574 IX86_BUILTIN_PCOMGEQ,
20575 IX86_BUILTIN_PCOMFALSEQ,
20576 IX86_BUILTIN_PCOMTRUEQ,
20581 /* Table for the ix86 builtin decls. */
20582 static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
20584 /* Table of all of the builtin functions that are possible with different ISA's
20585 but are waiting to be built until a function is declared to use that
20587 struct builtin_isa GTY(())
20589 tree type; /* builtin type to use in the declaration */
20590 const char *name; /* function name */
20591 int isa; /* isa_flags this builtin is defined for */
20592 bool const_p; /* true if the declaration is constant */
20595 static GTY(()) struct builtin_isa ix86_builtins_isa[(int) IX86_BUILTIN_MAX];
20598 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
20599 * of which isa_flags to use in the ix86_builtins_isa array. Stores the
20600 * function decl in the ix86_builtins array. Returns the function decl or
20601 * NULL_TREE, if the builtin was not added.
20603 * If the front end has a special hook for builtin functions, delay adding
20604 * builtin functions that aren't in the current ISA until the ISA is changed
20605 * with function specific optimization. Doing so, can save about 300K for the
20606 * default compiler. When the builtin is expanded, check at that time whether
20609 * If the front end doesn't have a special hook, record all builtins, even if
20610 * it isn't an instruction set in the current ISA in case the user uses
20611 * function specific options for a different ISA, so that we don't get scope
20612 * errors if a builtin is added in the middle of a function scope. */
20615 def_builtin (int mask, const char *name, tree type, enum ix86_builtins code)
20617 tree decl = NULL_TREE;
20619 if (!(mask & OPTION_MASK_ISA_64BIT) || TARGET_64BIT)
20621 ix86_builtins_isa[(int) code].isa = mask;
20623 mask &= ~OPTION_MASK_ISA_64BIT;
20624 if ((mask & ix86_isa_flags) != 0
20625 || (lang_hooks.builtin_function
20626 == lang_hooks.builtin_function_ext_scope))
20629 decl = add_builtin_function (name, type, code, BUILT_IN_MD, NULL,
20631 ix86_builtins[(int) code] = decl;
20632 ix86_builtins_isa[(int) code].type = NULL_TREE;
20636 ix86_builtins[(int) code] = NULL_TREE;
20637 ix86_builtins_isa[(int) code].const_p = false;
20638 ix86_builtins_isa[(int) code].type = type;
20639 ix86_builtins_isa[(int) code].name = name;
20646 /* Like def_builtin, but also marks the function decl "const". */
20649 def_builtin_const (int mask, const char *name, tree type,
20650 enum ix86_builtins code)
20652 tree decl = def_builtin (mask, name, type, code);
20654 TREE_READONLY (decl) = 1;
20656 ix86_builtins_isa[(int) code].const_p = true;
20661 /* Add any new builtin functions for a given ISA that may not have been
20662 declared. This saves a bit of space compared to adding all of the
20663 declarations to the tree, even if we didn't use them. */
20666 ix86_add_new_builtins (int isa)
20671 for (i = 0; i < (int)IX86_BUILTIN_MAX; i++)
20673 if ((ix86_builtins_isa[i].isa & isa) != 0
20674 && ix86_builtins_isa[i].type != NULL_TREE)
20676 decl = add_builtin_function_ext_scope (ix86_builtins_isa[i].name,
20677 ix86_builtins_isa[i].type,
20678 i, BUILT_IN_MD, NULL,
20681 ix86_builtins[i] = decl;
20682 ix86_builtins_isa[i].type = NULL_TREE;
20683 if (ix86_builtins_isa[i].const_p)
20684 TREE_READONLY (decl) = 1;
20689 /* Bits for builtin_description.flag. */
20691 /* Set when we don't support the comparison natively, and should
20692 swap_comparison in order to support it. */
20693 #define BUILTIN_DESC_SWAP_OPERANDS 1
20695 struct builtin_description
20697 const unsigned int mask;
20698 const enum insn_code icode;
20699 const char *const name;
20700 const enum ix86_builtins code;
20701 const enum rtx_code comparison;
20705 static const struct builtin_description bdesc_comi[] =
20707 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
20708 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
20709 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
20710 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
20711 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
20712 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
20713 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
20714 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
20715 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
20716 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
20717 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
20718 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
20719 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
20720 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
20721 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
20722 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
20723 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
20724 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
20725 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
20726 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
20727 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
20728 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
20729 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
20730 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
20733 static const struct builtin_description bdesc_pcmpestr[] =
20736 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
20737 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
20738 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
20739 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
20740 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
20741 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
20742 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
20745 static const struct builtin_description bdesc_pcmpistr[] =
20748 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
20749 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
20750 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
20751 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
20752 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
20753 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
20754 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
20757 /* Special builtin types */
20758 enum ix86_special_builtin_type
20760 SPECIAL_FTYPE_UNKNOWN,
20762 V32QI_FTYPE_PCCHAR,
20763 V16QI_FTYPE_PCCHAR,
20765 V8SF_FTYPE_PCFLOAT,
20767 V4DF_FTYPE_PCDOUBLE,
20768 V4SF_FTYPE_PCFLOAT,
20769 V2DF_FTYPE_PCDOUBLE,
20770 V8SF_FTYPE_PCV8SF_V8SF,
20771 V4DF_FTYPE_PCV4DF_V4DF,
20772 V4SF_FTYPE_V4SF_PCV2SF,
20773 V4SF_FTYPE_PCV4SF_V4SF,
20774 V2DF_FTYPE_V2DF_PCDOUBLE,
20775 V2DF_FTYPE_PCV2DF_V2DF,
20777 VOID_FTYPE_PV2SF_V4SF,
20778 VOID_FTYPE_PV4DI_V4DI,
20779 VOID_FTYPE_PV2DI_V2DI,
20780 VOID_FTYPE_PCHAR_V32QI,
20781 VOID_FTYPE_PCHAR_V16QI,
20782 VOID_FTYPE_PFLOAT_V8SF,
20783 VOID_FTYPE_PFLOAT_V4SF,
20784 VOID_FTYPE_PDOUBLE_V4DF,
20785 VOID_FTYPE_PDOUBLE_V2DF,
20787 VOID_FTYPE_PINT_INT,
20788 VOID_FTYPE_PV8SF_V8SF_V8SF,
20789 VOID_FTYPE_PV4DF_V4DF_V4DF,
20790 VOID_FTYPE_PV4SF_V4SF_V4SF,
20791 VOID_FTYPE_PV2DF_V2DF_V2DF
20794 /* Builtin types */
20795 enum ix86_builtin_type
20798 FLOAT128_FTYPE_FLOAT128,
20800 FLOAT128_FTYPE_FLOAT128_FLOAT128,
20801 INT_FTYPE_V8SF_V8SF_PTEST,
20802 INT_FTYPE_V4DI_V4DI_PTEST,
20803 INT_FTYPE_V4DF_V4DF_PTEST,
20804 INT_FTYPE_V4SF_V4SF_PTEST,
20805 INT_FTYPE_V2DI_V2DI_PTEST,
20806 INT_FTYPE_V2DF_V2DF_PTEST,
20838 V4SF_FTYPE_V4SF_VEC_MERGE,
20847 V2DF_FTYPE_V2DF_VEC_MERGE,
20858 V16QI_FTYPE_V16QI_V16QI,
20859 V16QI_FTYPE_V8HI_V8HI,
20860 V8QI_FTYPE_V8QI_V8QI,
20861 V8QI_FTYPE_V4HI_V4HI,
20862 V8HI_FTYPE_V8HI_V8HI,
20863 V8HI_FTYPE_V8HI_V8HI_COUNT,
20864 V8HI_FTYPE_V16QI_V16QI,
20865 V8HI_FTYPE_V4SI_V4SI,
20866 V8HI_FTYPE_V8HI_SI_COUNT,
20867 V8SF_FTYPE_V8SF_V8SF,
20868 V8SF_FTYPE_V8SF_V8SI,
20869 V4SI_FTYPE_V4SI_V4SI,
20870 V4SI_FTYPE_V4SI_V4SI_COUNT,
20871 V4SI_FTYPE_V8HI_V8HI,
20872 V4SI_FTYPE_V4SF_V4SF,
20873 V4SI_FTYPE_V2DF_V2DF,
20874 V4SI_FTYPE_V4SI_SI_COUNT,
20875 V4HI_FTYPE_V4HI_V4HI,
20876 V4HI_FTYPE_V4HI_V4HI_COUNT,
20877 V4HI_FTYPE_V8QI_V8QI,
20878 V4HI_FTYPE_V2SI_V2SI,
20879 V4HI_FTYPE_V4HI_SI_COUNT,
20880 V4DF_FTYPE_V4DF_V4DF,
20881 V4DF_FTYPE_V4DF_V4DI,
20882 V4SF_FTYPE_V4SF_V4SF,
20883 V4SF_FTYPE_V4SF_V4SF_SWAP,
20884 V4SF_FTYPE_V4SF_V4SI,
20885 V4SF_FTYPE_V4SF_V2SI,
20886 V4SF_FTYPE_V4SF_V2DF,
20887 V4SF_FTYPE_V4SF_DI,
20888 V4SF_FTYPE_V4SF_SI,
20889 V2DI_FTYPE_V2DI_V2DI,
20890 V2DI_FTYPE_V2DI_V2DI_COUNT,
20891 V2DI_FTYPE_V16QI_V16QI,
20892 V2DI_FTYPE_V4SI_V4SI,
20893 V2DI_FTYPE_V2DI_V16QI,
20894 V2DI_FTYPE_V2DF_V2DF,
20895 V2DI_FTYPE_V2DI_SI_COUNT,
20896 V2SI_FTYPE_V2SI_V2SI,
20897 V2SI_FTYPE_V2SI_V2SI_COUNT,
20898 V2SI_FTYPE_V4HI_V4HI,
20899 V2SI_FTYPE_V2SF_V2SF,
20900 V2SI_FTYPE_V2SI_SI_COUNT,
20901 V2DF_FTYPE_V2DF_V2DF,
20902 V2DF_FTYPE_V2DF_V2DF_SWAP,
20903 V2DF_FTYPE_V2DF_V4SF,
20904 V2DF_FTYPE_V2DF_V2DI,
20905 V2DF_FTYPE_V2DF_DI,
20906 V2DF_FTYPE_V2DF_SI,
20907 V2SF_FTYPE_V2SF_V2SF,
20908 V1DI_FTYPE_V1DI_V1DI,
20909 V1DI_FTYPE_V1DI_V1DI_COUNT,
20910 V1DI_FTYPE_V8QI_V8QI,
20911 V1DI_FTYPE_V2SI_V2SI,
20912 V1DI_FTYPE_V1DI_SI_COUNT,
20913 UINT64_FTYPE_UINT64_UINT64,
20914 UINT_FTYPE_UINT_UINT,
20915 UINT_FTYPE_UINT_USHORT,
20916 UINT_FTYPE_UINT_UCHAR,
20917 V8HI_FTYPE_V8HI_INT,
20918 V4SI_FTYPE_V4SI_INT,
20919 V4HI_FTYPE_V4HI_INT,
20920 V8SF_FTYPE_V8SF_INT,
20921 V4SI_FTYPE_V8SI_INT,
20922 V4SF_FTYPE_V8SF_INT,
20923 V2DF_FTYPE_V4DF_INT,
20924 V4DF_FTYPE_V4DF_INT,
20925 V4SF_FTYPE_V4SF_INT,
20926 V2DI_FTYPE_V2DI_INT,
20927 V2DI2TI_FTYPE_V2DI_INT,
20928 V2DF_FTYPE_V2DF_INT,
20929 V16QI_FTYPE_V16QI_V16QI_V16QI,
20930 V8SF_FTYPE_V8SF_V8SF_V8SF,
20931 V4DF_FTYPE_V4DF_V4DF_V4DF,
20932 V4SF_FTYPE_V4SF_V4SF_V4SF,
20933 V2DF_FTYPE_V2DF_V2DF_V2DF,
20934 V16QI_FTYPE_V16QI_V16QI_INT,
20935 V8SI_FTYPE_V8SI_V8SI_INT,
20936 V8SI_FTYPE_V8SI_V4SI_INT,
20937 V8HI_FTYPE_V8HI_V8HI_INT,
20938 V8SF_FTYPE_V8SF_V8SF_INT,
20939 V8SF_FTYPE_V8SF_V4SF_INT,
20940 V4SI_FTYPE_V4SI_V4SI_INT,
20941 V4DF_FTYPE_V4DF_V4DF_INT,
20942 V4DF_FTYPE_V4DF_V2DF_INT,
20943 V4SF_FTYPE_V4SF_V4SF_INT,
20944 V2DI_FTYPE_V2DI_V2DI_INT,
20945 V2DI2TI_FTYPE_V2DI_V2DI_INT,
20946 V1DI2DI_FTYPE_V1DI_V1DI_INT,
20947 V2DF_FTYPE_V2DF_V2DF_INT,
20948 V2DI_FTYPE_V2DI_UINT_UINT,
20949 V2DI_FTYPE_V2DI_V2DI_UINT_UINT
20952 /* Special builtins with variable number of arguments. */
20953 static const struct builtin_description bdesc_special_args[] =
20956 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20959 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
20962 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20963 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
20964 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
20966 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20967 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
20968 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20969 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
20971 /* SSE or 3DNow!A */
20972 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20973 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntdi, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PDI_DI },
20976 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20977 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
20978 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20979 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
20980 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20981 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
20982 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntsi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
20983 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
20984 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20986 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20987 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
20990 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
20993 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
20996 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
20997 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
21000 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
21001 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, 0, IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
21002 { OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_64BIT, CODE_FOR_avx_vzeroupper_rex64, 0, IX86_BUILTIN_VZEROUPPER_REX64, UNKNOWN, (int) VOID_FTYPE_VOID },
21004 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
21005 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastsd256, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21006 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastss256, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21007 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_pd256, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
21008 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_ps256, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
21010 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
21011 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
21012 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21013 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21014 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21015 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
21016 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
21018 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
21019 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
21020 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
21022 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
21023 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
21024 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
21025 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
21026 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
21027 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
21028 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
21029 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
21032 /* Builtins with variable number of arguments. */
21033 static const struct builtin_description bdesc_args[] =
21036 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21037 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21038 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21039 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21040 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21041 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21043 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21044 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21045 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21046 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21047 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21048 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21049 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21050 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21052 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21053 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21055 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21056 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21057 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21058 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21060 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21061 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21062 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21063 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21064 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21065 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21067 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21068 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21069 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21070 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21071 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
21072 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
21074 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21075 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
21076 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
21078 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
21080 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21081 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21082 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21083 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21084 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21085 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21087 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21088 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21089 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
21090 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21091 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21092 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
21094 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
21095 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
21096 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
21097 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
21100 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21101 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21102 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21103 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21105 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21106 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21107 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21108 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21109 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21110 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
21111 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21112 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21113 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21114 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21115 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21116 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21117 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21118 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21119 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21122 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
21123 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
21124 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21125 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
21126 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21127 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
21130 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
21131 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21132 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21133 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21134 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21135 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21136 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21137 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21138 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21139 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
21140 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
21141 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
21143 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21145 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21146 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21147 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21148 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21149 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21150 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21151 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21152 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21154 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21155 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21156 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21157 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21158 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21159 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21160 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21161 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21162 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21163 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21164 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
21165 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21166 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
21167 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
21168 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
21169 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21170 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
21171 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
21172 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
21173 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21174 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
21175 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
21177 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21178 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21179 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21180 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21182 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21183 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21184 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21185 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21187 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21188 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21189 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21190 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpckhps, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21191 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21193 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
21194 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
21195 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
21197 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
21199 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21200 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21201 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
21203 /* SSE MMX or 3Dnow!A */
21204 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21205 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21206 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21208 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21209 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21210 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21211 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21213 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
21214 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
21216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
21219 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21221 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
21222 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
21223 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
21224 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
21225 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2ps, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
21227 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21228 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21229 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
21230 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
21231 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
21233 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
21235 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21236 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
21237 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21238 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
21240 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21241 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
21242 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttps2dq, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
21244 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21245 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21246 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21247 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21248 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21249 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21250 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21251 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21253 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21254 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21255 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21256 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21257 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
21258 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21259 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21260 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21261 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21262 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21263 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
21264 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21265 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
21266 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
21267 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
21268 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21269 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
21270 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
21271 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
21272 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
21274 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21275 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21276 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21277 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21279 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21280 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21281 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21282 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21284 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21285 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpckhpd_exp, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21286 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_unpcklpd_exp, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21288 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
21290 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21291 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21292 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21293 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21294 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21295 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21296 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21297 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21300 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21308 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21309 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
21311 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21313 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21314 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21326 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21327 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21328 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhbw, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21332 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhwd, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhdq, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckhqdq, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklbw, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklwd, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpckldq, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_punpcklqdq, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
21344 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
21347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
21348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
21352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
21353 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
21354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
21355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
21357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21358 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21359 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21360 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21361 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21362 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21363 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_INT },
21366 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21367 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21368 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
21369 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21370 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21371 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
21373 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
21374 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
21375 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
21376 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
21378 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
21379 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21380 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
21382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
21384 { OPTION_MASK_ISA_SSE2, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
21385 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
21387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21390 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21391 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
21394 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
21395 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
21397 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21398 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21399 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21400 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21401 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
21402 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
21405 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
21406 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
21407 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21408 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
21409 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
21410 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
21412 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21413 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21414 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21415 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21416 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21417 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21418 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21419 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21420 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21421 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21422 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21423 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21424 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
21425 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
21426 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21427 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21428 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21429 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21430 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21431 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
21432 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21433 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
21434 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21435 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
21438 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI2TI_FTYPE_V2DI_V2DI_INT },
21439 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI2DI_FTYPE_V1DI_V1DI_INT },
21442 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21443 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21444 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
21445 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
21446 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21447 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21448 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21449 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
21450 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
21451 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
21453 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21454 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21455 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21456 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21457 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21458 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21459 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
21460 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
21461 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
21462 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
21463 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
21464 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
21465 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
21467 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
21468 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21469 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21470 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21471 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21472 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21473 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
21474 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21475 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21476 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
21477 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
21478 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
21480 /* SSE4.1 and SSE5 */
21481 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21482 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21483 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21484 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21486 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21487 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21488 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
21491 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21492 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
21493 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
21494 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
21495 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
21498 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
21499 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
21500 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
21501 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21504 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
21505 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
21507 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21508 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21509 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21510 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
21513 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
21516 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21517 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21518 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21519 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21520 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21521 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21522 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21523 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21524 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21525 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21526 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21527 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21528 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21529 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21530 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21531 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21532 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21533 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21534 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21535 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21536 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21537 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21538 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21539 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21540 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21541 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21543 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
21544 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
21545 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
21546 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
21548 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21549 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21550 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
21551 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
21552 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21553 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21554 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21555 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpsdv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21556 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpssv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21557 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
21558 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
21559 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppdv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21560 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmppsv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21561 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
21562 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
21563 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
21564 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2pd256, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
21565 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtdq2ps256, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
21566 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
21567 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21568 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
21569 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttpd2dq256, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21570 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
21571 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvttps2dq256, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
21572 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
21573 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
21574 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
21575 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
21576 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
21577 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21578 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21579 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
21580 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
21581 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
21583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21585 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21587 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
21588 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21589 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21590 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21591 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21593 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
21595 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
21596 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
21598 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21599 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
21600 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21601 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
21603 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
21604 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
21605 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
21606 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si_si256, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
21607 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps_ps256, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
21608 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd_pd256, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
21610 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21611 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21612 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
21613 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21614 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21615 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
21616 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21617 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21618 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
21619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21621 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
21622 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
21626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
21627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
21631 enum multi_arg_type {
21641 MULTI_ARG_3_PERMPS,
21642 MULTI_ARG_3_PERMPD,
21649 MULTI_ARG_2_DI_IMM,
21650 MULTI_ARG_2_SI_IMM,
21651 MULTI_ARG_2_HI_IMM,
21652 MULTI_ARG_2_QI_IMM,
21653 MULTI_ARG_2_SF_CMP,
21654 MULTI_ARG_2_DF_CMP,
21655 MULTI_ARG_2_DI_CMP,
21656 MULTI_ARG_2_SI_CMP,
21657 MULTI_ARG_2_HI_CMP,
21658 MULTI_ARG_2_QI_CMP,
21681 static const struct builtin_description bdesc_multi_arg[] =
21683 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, 0, (int)MULTI_ARG_3_SF },
21684 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, 0, (int)MULTI_ARG_3_DF },
21685 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, 0, (int)MULTI_ARG_3_SF },
21686 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, 0, (int)MULTI_ARG_3_DF },
21687 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, 0, (int)MULTI_ARG_3_SF },
21688 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, 0, (int)MULTI_ARG_3_DF },
21689 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, 0, (int)MULTI_ARG_3_SF },
21690 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, 0, (int)MULTI_ARG_3_DF },
21691 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, 0, (int)MULTI_ARG_3_SF },
21692 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, 0, (int)MULTI_ARG_3_DF },
21693 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, 0, (int)MULTI_ARG_3_SF },
21694 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, 0, (int)MULTI_ARG_3_DF },
21695 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, 0, (int)MULTI_ARG_3_SF },
21696 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, 0, (int)MULTI_ARG_3_DF },
21697 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, 0, (int)MULTI_ARG_3_SF },
21698 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, 0, (int)MULTI_ARG_3_DF },
21699 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, 0, (int)MULTI_ARG_3_DI },
21700 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, 0, (int)MULTI_ARG_3_DI },
21701 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, 0, (int)MULTI_ARG_3_SI },
21702 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, 0, (int)MULTI_ARG_3_HI },
21703 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,0, (int)MULTI_ARG_3_QI },
21704 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, 0, (int)MULTI_ARG_3_DF },
21705 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, 0, (int)MULTI_ARG_3_SF },
21706 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, 0, (int)MULTI_ARG_3_QI },
21707 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, 0, (int)MULTI_ARG_3_PERMPS },
21708 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, 0, (int)MULTI_ARG_3_PERMPD },
21709 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, 0, (int)MULTI_ARG_3_HI },
21710 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, 0, (int)MULTI_ARG_3_HI },
21711 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21712 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, 0, (int)MULTI_ARG_3_HI_SI },
21713 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, 0, (int)MULTI_ARG_3_SI },
21714 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, 0, (int)MULTI_ARG_3_SI },
21715 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21716 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21717 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, 0, (int)MULTI_ARG_3_SI_DI },
21718 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, 0, (int)MULTI_ARG_3_SI_DI },
21719 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, 0, (int)MULTI_ARG_3_HI_SI },
21720 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, 0, (int)MULTI_ARG_3_HI_SI },
21721 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, 0, (int)MULTI_ARG_2_DI },
21722 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, 0, (int)MULTI_ARG_2_SI },
21723 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, 0, (int)MULTI_ARG_2_HI },
21724 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, 0, (int)MULTI_ARG_2_QI },
21725 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, 0, (int)MULTI_ARG_2_DI_IMM },
21726 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, 0, (int)MULTI_ARG_2_SI_IMM },
21727 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, 0, (int)MULTI_ARG_2_HI_IMM },
21728 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, 0, (int)MULTI_ARG_2_QI_IMM },
21729 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, 0, (int)MULTI_ARG_2_DI },
21730 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, 0, (int)MULTI_ARG_2_SI },
21731 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, 0, (int)MULTI_ARG_2_HI },
21732 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, 0, (int)MULTI_ARG_2_QI },
21733 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, 0, (int)MULTI_ARG_2_DI },
21734 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, 0, (int)MULTI_ARG_2_SI },
21735 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, 0, (int)MULTI_ARG_2_HI },
21736 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, 0, (int)MULTI_ARG_2_QI },
21737 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, 0, (int)MULTI_ARG_2_SF },
21738 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, 0, (int)MULTI_ARG_2_DF },
21739 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, 0, (int)MULTI_ARG_1_SF },
21740 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, 0, (int)MULTI_ARG_1_DF },
21741 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, 0, (int)MULTI_ARG_1_PH2PS },
21742 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, 0, (int)MULTI_ARG_1_PS2PH },
21743 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, 0, (int)MULTI_ARG_1_QI_HI },
21744 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, 0, (int)MULTI_ARG_1_QI_SI },
21745 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, 0, (int)MULTI_ARG_1_QI_DI },
21746 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, 0, (int)MULTI_ARG_1_HI_SI },
21747 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, 0, (int)MULTI_ARG_1_HI_DI },
21748 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, 0, (int)MULTI_ARG_1_SI_DI },
21749 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, 0, (int)MULTI_ARG_1_QI_HI },
21750 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, 0, (int)MULTI_ARG_1_QI_SI },
21751 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, 0, (int)MULTI_ARG_1_QI_DI },
21752 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, 0, (int)MULTI_ARG_1_HI_SI },
21753 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, 0, (int)MULTI_ARG_1_HI_DI },
21754 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, 0, (int)MULTI_ARG_1_SI_DI },
21755 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, 0, (int)MULTI_ARG_1_QI_HI },
21756 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, 0, (int)MULTI_ARG_1_HI_SI },
21757 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, 0, (int)MULTI_ARG_1_SI_DI },
21759 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
21760 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21761 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
21762 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
21763 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
21764 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
21765 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
21766 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21767 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21768 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21769 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21770 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21771 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21772 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21773 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21774 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21776 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
21777 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21778 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
21779 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
21780 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
21781 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
21782 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
21783 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21784 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21785 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21786 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21787 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21788 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21789 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21790 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21791 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21793 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
21794 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21795 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
21796 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
21797 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
21798 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
21799 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
21800 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
21801 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21802 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
21803 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
21804 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
21805 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
21806 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
21807 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
21808 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
21810 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
21811 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21812 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
21813 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
21814 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
21815 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
21816 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
21817 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
21818 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21819 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
21820 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
21821 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
21822 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
21823 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
21824 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
21825 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
21827 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
21828 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21829 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
21830 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
21831 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
21832 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
21833 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
21835 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
21836 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21837 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
21838 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
21839 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
21840 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
21841 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
21843 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
21844 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21845 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
21846 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
21847 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
21848 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
21849 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
21851 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21852 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21853 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
21854 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
21855 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
21856 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
21857 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
21859 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
21860 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21861 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
21862 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
21863 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
21864 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
21865 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
21867 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
21868 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21869 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
21870 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
21871 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
21872 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
21873 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
21875 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
21876 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21877 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
21878 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
21879 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
21880 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
21881 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
21883 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
21884 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21885 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
21886 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
21887 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
21888 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
21889 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
21891 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
21892 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
21893 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
21894 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
21895 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
21896 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
21897 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
21898 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
21900 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21901 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21902 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21903 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21904 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
21905 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
21906 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
21907 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
21909 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21910 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21911 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21912 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21913 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
21914 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
21915 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
21916 { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
21919 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
21920 in the current target ISA to allow the user to compile particular modules
21921 with different target specific options that differ from the command line
21924 ix86_init_mmx_sse_builtins (void)
21926 const struct builtin_description * d;
21929 tree V16QI_type_node = build_vector_type_for_mode (char_type_node, V16QImode);
21930 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
21931 tree V1DI_type_node
21932 = build_vector_type_for_mode (long_long_integer_type_node, V1DImode);
21933 tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
21934 tree V2DI_type_node
21935 = build_vector_type_for_mode (long_long_integer_type_node, V2DImode);
21936 tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode);
21937 tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode);
21938 tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode);
21939 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
21940 tree V8QI_type_node = build_vector_type_for_mode (char_type_node, V8QImode);
21941 tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode);
21943 tree pchar_type_node = build_pointer_type (char_type_node);
21944 tree pcchar_type_node
21945 = build_pointer_type (build_type_variant (char_type_node, 1, 0));
21946 tree pfloat_type_node = build_pointer_type (float_type_node);
21947 tree pcfloat_type_node
21948 = build_pointer_type (build_type_variant (float_type_node, 1, 0));
21949 tree pv2sf_type_node = build_pointer_type (V2SF_type_node);
21950 tree pcv2sf_type_node
21951 = build_pointer_type (build_type_variant (V2SF_type_node, 1, 0));
21952 tree pv2di_type_node = build_pointer_type (V2DI_type_node);
21953 tree pdi_type_node = build_pointer_type (long_long_unsigned_type_node);
21956 tree int_ftype_v4sf_v4sf
21957 = build_function_type_list (integer_type_node,
21958 V4SF_type_node, V4SF_type_node, NULL_TREE);
21959 tree v4si_ftype_v4sf_v4sf
21960 = build_function_type_list (V4SI_type_node,
21961 V4SF_type_node, V4SF_type_node, NULL_TREE);
21962 /* MMX/SSE/integer conversions. */
21963 tree int_ftype_v4sf
21964 = build_function_type_list (integer_type_node,
21965 V4SF_type_node, NULL_TREE);
21966 tree int64_ftype_v4sf
21967 = build_function_type_list (long_long_integer_type_node,
21968 V4SF_type_node, NULL_TREE);
21969 tree int_ftype_v8qi
21970 = build_function_type_list (integer_type_node, V8QI_type_node, NULL_TREE);
21971 tree v4sf_ftype_v4sf_int
21972 = build_function_type_list (V4SF_type_node,
21973 V4SF_type_node, integer_type_node, NULL_TREE);
21974 tree v4sf_ftype_v4sf_int64
21975 = build_function_type_list (V4SF_type_node,
21976 V4SF_type_node, long_long_integer_type_node,
21978 tree v4sf_ftype_v4sf_v2si
21979 = build_function_type_list (V4SF_type_node,
21980 V4SF_type_node, V2SI_type_node, NULL_TREE);
21982 /* Miscellaneous. */
21983 tree v8qi_ftype_v4hi_v4hi
21984 = build_function_type_list (V8QI_type_node,
21985 V4HI_type_node, V4HI_type_node, NULL_TREE);
21986 tree v4hi_ftype_v2si_v2si
21987 = build_function_type_list (V4HI_type_node,
21988 V2SI_type_node, V2SI_type_node, NULL_TREE);
21989 tree v4sf_ftype_v4sf_v4sf_int
21990 = build_function_type_list (V4SF_type_node,
21991 V4SF_type_node, V4SF_type_node,
21992 integer_type_node, NULL_TREE);
21993 tree v2si_ftype_v4hi_v4hi
21994 = build_function_type_list (V2SI_type_node,
21995 V4HI_type_node, V4HI_type_node, NULL_TREE);
21996 tree v4hi_ftype_v4hi_int
21997 = build_function_type_list (V4HI_type_node,
21998 V4HI_type_node, integer_type_node, NULL_TREE);
21999 tree v2si_ftype_v2si_int
22000 = build_function_type_list (V2SI_type_node,
22001 V2SI_type_node, integer_type_node, NULL_TREE);
22002 tree v1di_ftype_v1di_int
22003 = build_function_type_list (V1DI_type_node,
22004 V1DI_type_node, integer_type_node, NULL_TREE);
22006 tree void_ftype_void
22007 = build_function_type (void_type_node, void_list_node);
22008 tree void_ftype_unsigned
22009 = build_function_type_list (void_type_node, unsigned_type_node, NULL_TREE);
22010 tree void_ftype_unsigned_unsigned
22011 = build_function_type_list (void_type_node, unsigned_type_node,
22012 unsigned_type_node, NULL_TREE);
22013 tree void_ftype_pcvoid_unsigned_unsigned
22014 = build_function_type_list (void_type_node, const_ptr_type_node,
22015 unsigned_type_node, unsigned_type_node,
22017 tree unsigned_ftype_void
22018 = build_function_type (unsigned_type_node, void_list_node);
22019 tree v2si_ftype_v4sf
22020 = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE);
22021 /* Loads/stores. */
22022 tree void_ftype_v8qi_v8qi_pchar
22023 = build_function_type_list (void_type_node,
22024 V8QI_type_node, V8QI_type_node,
22025 pchar_type_node, NULL_TREE);
22026 tree v4sf_ftype_pcfloat
22027 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
22028 tree v4sf_ftype_v4sf_pcv2sf
22029 = build_function_type_list (V4SF_type_node,
22030 V4SF_type_node, pcv2sf_type_node, NULL_TREE);
22031 tree void_ftype_pv2sf_v4sf
22032 = build_function_type_list (void_type_node,
22033 pv2sf_type_node, V4SF_type_node, NULL_TREE);
22034 tree void_ftype_pfloat_v4sf
22035 = build_function_type_list (void_type_node,
22036 pfloat_type_node, V4SF_type_node, NULL_TREE);
22037 tree void_ftype_pdi_di
22038 = build_function_type_list (void_type_node,
22039 pdi_type_node, long_long_unsigned_type_node,
22041 tree void_ftype_pv2di_v2di
22042 = build_function_type_list (void_type_node,
22043 pv2di_type_node, V2DI_type_node, NULL_TREE);
22044 /* Normal vector unops. */
22045 tree v4sf_ftype_v4sf
22046 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
22047 tree v16qi_ftype_v16qi
22048 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
22049 tree v8hi_ftype_v8hi
22050 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
22051 tree v4si_ftype_v4si
22052 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
22053 tree v8qi_ftype_v8qi
22054 = build_function_type_list (V8QI_type_node, V8QI_type_node, NULL_TREE);
22055 tree v4hi_ftype_v4hi
22056 = build_function_type_list (V4HI_type_node, V4HI_type_node, NULL_TREE);
22058 /* Normal vector binops. */
22059 tree v4sf_ftype_v4sf_v4sf
22060 = build_function_type_list (V4SF_type_node,
22061 V4SF_type_node, V4SF_type_node, NULL_TREE);
22062 tree v8qi_ftype_v8qi_v8qi
22063 = build_function_type_list (V8QI_type_node,
22064 V8QI_type_node, V8QI_type_node, NULL_TREE);
22065 tree v4hi_ftype_v4hi_v4hi
22066 = build_function_type_list (V4HI_type_node,
22067 V4HI_type_node, V4HI_type_node, NULL_TREE);
22068 tree v2si_ftype_v2si_v2si
22069 = build_function_type_list (V2SI_type_node,
22070 V2SI_type_node, V2SI_type_node, NULL_TREE);
22071 tree v1di_ftype_v1di_v1di
22072 = build_function_type_list (V1DI_type_node,
22073 V1DI_type_node, V1DI_type_node, NULL_TREE);
22074 tree v1di_ftype_v1di_v1di_int
22075 = build_function_type_list (V1DI_type_node,
22076 V1DI_type_node, V1DI_type_node,
22077 integer_type_node, NULL_TREE);
22078 tree v2si_ftype_v2sf
22079 = build_function_type_list (V2SI_type_node, V2SF_type_node, NULL_TREE);
22080 tree v2sf_ftype_v2si
22081 = build_function_type_list (V2SF_type_node, V2SI_type_node, NULL_TREE);
22082 tree v2si_ftype_v2si
22083 = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE);
22084 tree v2sf_ftype_v2sf
22085 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
22086 tree v2sf_ftype_v2sf_v2sf
22087 = build_function_type_list (V2SF_type_node,
22088 V2SF_type_node, V2SF_type_node, NULL_TREE);
22089 tree v2si_ftype_v2sf_v2sf
22090 = build_function_type_list (V2SI_type_node,
22091 V2SF_type_node, V2SF_type_node, NULL_TREE);
22092 tree pint_type_node = build_pointer_type (integer_type_node);
22093 tree pdouble_type_node = build_pointer_type (double_type_node);
22094 tree pcdouble_type_node = build_pointer_type (
22095 build_type_variant (double_type_node, 1, 0));
22096 tree int_ftype_v2df_v2df
22097 = build_function_type_list (integer_type_node,
22098 V2DF_type_node, V2DF_type_node, NULL_TREE);
22100 tree void_ftype_pcvoid
22101 = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE);
22102 tree v4sf_ftype_v4si
22103 = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE);
22104 tree v4si_ftype_v4sf
22105 = build_function_type_list (V4SI_type_node, V4SF_type_node, NULL_TREE);
22106 tree v2df_ftype_v4si
22107 = build_function_type_list (V2DF_type_node, V4SI_type_node, NULL_TREE);
22108 tree v4si_ftype_v2df
22109 = build_function_type_list (V4SI_type_node, V2DF_type_node, NULL_TREE);
22110 tree v4si_ftype_v2df_v2df
22111 = build_function_type_list (V4SI_type_node,
22112 V2DF_type_node, V2DF_type_node, NULL_TREE);
22113 tree v2si_ftype_v2df
22114 = build_function_type_list (V2SI_type_node, V2DF_type_node, NULL_TREE);
22115 tree v4sf_ftype_v2df
22116 = build_function_type_list (V4SF_type_node, V2DF_type_node, NULL_TREE);
22117 tree v2df_ftype_v2si
22118 = build_function_type_list (V2DF_type_node, V2SI_type_node, NULL_TREE);
22119 tree v2df_ftype_v4sf
22120 = build_function_type_list (V2DF_type_node, V4SF_type_node, NULL_TREE);
22121 tree int_ftype_v2df
22122 = build_function_type_list (integer_type_node, V2DF_type_node, NULL_TREE);
22123 tree int64_ftype_v2df
22124 = build_function_type_list (long_long_integer_type_node,
22125 V2DF_type_node, NULL_TREE);
22126 tree v2df_ftype_v2df_int
22127 = build_function_type_list (V2DF_type_node,
22128 V2DF_type_node, integer_type_node, NULL_TREE);
22129 tree v2df_ftype_v2df_int64
22130 = build_function_type_list (V2DF_type_node,
22131 V2DF_type_node, long_long_integer_type_node,
22133 tree v4sf_ftype_v4sf_v2df
22134 = build_function_type_list (V4SF_type_node,
22135 V4SF_type_node, V2DF_type_node, NULL_TREE);
22136 tree v2df_ftype_v2df_v4sf
22137 = build_function_type_list (V2DF_type_node,
22138 V2DF_type_node, V4SF_type_node, NULL_TREE);
22139 tree v2df_ftype_v2df_v2df_int
22140 = build_function_type_list (V2DF_type_node,
22141 V2DF_type_node, V2DF_type_node,
22144 tree v2df_ftype_v2df_pcdouble
22145 = build_function_type_list (V2DF_type_node,
22146 V2DF_type_node, pcdouble_type_node, NULL_TREE);
22147 tree void_ftype_pdouble_v2df
22148 = build_function_type_list (void_type_node,
22149 pdouble_type_node, V2DF_type_node, NULL_TREE);
22150 tree void_ftype_pint_int
22151 = build_function_type_list (void_type_node,
22152 pint_type_node, integer_type_node, NULL_TREE);
22153 tree void_ftype_v16qi_v16qi_pchar
22154 = build_function_type_list (void_type_node,
22155 V16QI_type_node, V16QI_type_node,
22156 pchar_type_node, NULL_TREE);
22157 tree v2df_ftype_pcdouble
22158 = build_function_type_list (V2DF_type_node, pcdouble_type_node, NULL_TREE);
22159 tree v2df_ftype_v2df_v2df
22160 = build_function_type_list (V2DF_type_node,
22161 V2DF_type_node, V2DF_type_node, NULL_TREE);
22162 tree v16qi_ftype_v16qi_v16qi
22163 = build_function_type_list (V16QI_type_node,
22164 V16QI_type_node, V16QI_type_node, NULL_TREE);
22165 tree v8hi_ftype_v8hi_v8hi
22166 = build_function_type_list (V8HI_type_node,
22167 V8HI_type_node, V8HI_type_node, NULL_TREE);
22168 tree v4si_ftype_v4si_v4si
22169 = build_function_type_list (V4SI_type_node,
22170 V4SI_type_node, V4SI_type_node, NULL_TREE);
22171 tree v2di_ftype_v2di_v2di
22172 = build_function_type_list (V2DI_type_node,
22173 V2DI_type_node, V2DI_type_node, NULL_TREE);
22174 tree v2di_ftype_v2df_v2df
22175 = build_function_type_list (V2DI_type_node,
22176 V2DF_type_node, V2DF_type_node, NULL_TREE);
22177 tree v2df_ftype_v2df
22178 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
22179 tree v2di_ftype_v2di_int
22180 = build_function_type_list (V2DI_type_node,
22181 V2DI_type_node, integer_type_node, NULL_TREE);
22182 tree v2di_ftype_v2di_v2di_int
22183 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22184 V2DI_type_node, integer_type_node, NULL_TREE);
22185 tree v4si_ftype_v4si_int
22186 = build_function_type_list (V4SI_type_node,
22187 V4SI_type_node, integer_type_node, NULL_TREE);
22188 tree v8hi_ftype_v8hi_int
22189 = build_function_type_list (V8HI_type_node,
22190 V8HI_type_node, integer_type_node, NULL_TREE);
22191 tree v4si_ftype_v8hi_v8hi
22192 = build_function_type_list (V4SI_type_node,
22193 V8HI_type_node, V8HI_type_node, NULL_TREE);
22194 tree v1di_ftype_v8qi_v8qi
22195 = build_function_type_list (V1DI_type_node,
22196 V8QI_type_node, V8QI_type_node, NULL_TREE);
22197 tree v1di_ftype_v2si_v2si
22198 = build_function_type_list (V1DI_type_node,
22199 V2SI_type_node, V2SI_type_node, NULL_TREE);
22200 tree v2di_ftype_v16qi_v16qi
22201 = build_function_type_list (V2DI_type_node,
22202 V16QI_type_node, V16QI_type_node, NULL_TREE);
22203 tree v2di_ftype_v4si_v4si
22204 = build_function_type_list (V2DI_type_node,
22205 V4SI_type_node, V4SI_type_node, NULL_TREE);
22206 tree int_ftype_v16qi
22207 = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE);
22208 tree v16qi_ftype_pcchar
22209 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
22210 tree void_ftype_pchar_v16qi
22211 = build_function_type_list (void_type_node,
22212 pchar_type_node, V16QI_type_node, NULL_TREE);
22214 tree v2di_ftype_v2di_unsigned_unsigned
22215 = build_function_type_list (V2DI_type_node, V2DI_type_node,
22216 unsigned_type_node, unsigned_type_node,
22218 tree v2di_ftype_v2di_v2di_unsigned_unsigned
22219 = build_function_type_list (V2DI_type_node, V2DI_type_node, V2DI_type_node,
22220 unsigned_type_node, unsigned_type_node,
22222 tree v2di_ftype_v2di_v16qi
22223 = build_function_type_list (V2DI_type_node, V2DI_type_node, V16QI_type_node,
22225 tree v2df_ftype_v2df_v2df_v2df
22226 = build_function_type_list (V2DF_type_node,
22227 V2DF_type_node, V2DF_type_node,
22228 V2DF_type_node, NULL_TREE);
22229 tree v4sf_ftype_v4sf_v4sf_v4sf
22230 = build_function_type_list (V4SF_type_node,
22231 V4SF_type_node, V4SF_type_node,
22232 V4SF_type_node, NULL_TREE);
22233 tree v8hi_ftype_v16qi
22234 = build_function_type_list (V8HI_type_node, V16QI_type_node,
22236 tree v4si_ftype_v16qi
22237 = build_function_type_list (V4SI_type_node, V16QI_type_node,
22239 tree v2di_ftype_v16qi
22240 = build_function_type_list (V2DI_type_node, V16QI_type_node,
22242 tree v4si_ftype_v8hi
22243 = build_function_type_list (V4SI_type_node, V8HI_type_node,
22245 tree v2di_ftype_v8hi
22246 = build_function_type_list (V2DI_type_node, V8HI_type_node,
22248 tree v2di_ftype_v4si
22249 = build_function_type_list (V2DI_type_node, V4SI_type_node,
22251 tree v2di_ftype_pv2di
22252 = build_function_type_list (V2DI_type_node, pv2di_type_node,
22254 tree v16qi_ftype_v16qi_v16qi_int
22255 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22256 V16QI_type_node, integer_type_node,
22258 tree v16qi_ftype_v16qi_v16qi_v16qi
22259 = build_function_type_list (V16QI_type_node, V16QI_type_node,
22260 V16QI_type_node, V16QI_type_node,
22262 tree v8hi_ftype_v8hi_v8hi_int
22263 = build_function_type_list (V8HI_type_node, V8HI_type_node,
22264 V8HI_type_node, integer_type_node,
22266 tree v4si_ftype_v4si_v4si_int
22267 = build_function_type_list (V4SI_type_node, V4SI_type_node,
22268 V4SI_type_node, integer_type_node,
22270 tree int_ftype_v2di_v2di
22271 = build_function_type_list (integer_type_node,
22272 V2DI_type_node, V2DI_type_node,
22274 tree int_ftype_v16qi_int_v16qi_int_int
22275 = build_function_type_list (integer_type_node,
22282 tree v16qi_ftype_v16qi_int_v16qi_int_int
22283 = build_function_type_list (V16QI_type_node,
22290 tree int_ftype_v16qi_v16qi_int
22291 = build_function_type_list (integer_type_node,
22297 /* SSE5 instructions */
22298 tree v2di_ftype_v2di_v2di_v2di
22299 = build_function_type_list (V2DI_type_node,
22305 tree v4si_ftype_v4si_v4si_v4si
22306 = build_function_type_list (V4SI_type_node,
22312 tree v4si_ftype_v4si_v4si_v2di
22313 = build_function_type_list (V4SI_type_node,
22319 tree v8hi_ftype_v8hi_v8hi_v8hi
22320 = build_function_type_list (V8HI_type_node,
22326 tree v8hi_ftype_v8hi_v8hi_v4si
22327 = build_function_type_list (V8HI_type_node,
22333 tree v2df_ftype_v2df_v2df_v16qi
22334 = build_function_type_list (V2DF_type_node,
22340 tree v4sf_ftype_v4sf_v4sf_v16qi
22341 = build_function_type_list (V4SF_type_node,
22347 tree v2di_ftype_v2di_si
22348 = build_function_type_list (V2DI_type_node,
22353 tree v4si_ftype_v4si_si
22354 = build_function_type_list (V4SI_type_node,
22359 tree v8hi_ftype_v8hi_si
22360 = build_function_type_list (V8HI_type_node,
22365 tree v16qi_ftype_v16qi_si
22366 = build_function_type_list (V16QI_type_node,
22370 tree v4sf_ftype_v4hi
22371 = build_function_type_list (V4SF_type_node,
22375 tree v4hi_ftype_v4sf
22376 = build_function_type_list (V4HI_type_node,
22380 tree v2di_ftype_v2di
22381 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
22383 tree v16qi_ftype_v8hi_v8hi
22384 = build_function_type_list (V16QI_type_node,
22385 V8HI_type_node, V8HI_type_node,
22387 tree v8hi_ftype_v4si_v4si
22388 = build_function_type_list (V8HI_type_node,
22389 V4SI_type_node, V4SI_type_node,
22391 tree v8hi_ftype_v16qi_v16qi
22392 = build_function_type_list (V8HI_type_node,
22393 V16QI_type_node, V16QI_type_node,
22395 tree v4hi_ftype_v8qi_v8qi
22396 = build_function_type_list (V4HI_type_node,
22397 V8QI_type_node, V8QI_type_node,
22399 tree unsigned_ftype_unsigned_uchar
22400 = build_function_type_list (unsigned_type_node,
22401 unsigned_type_node,
22402 unsigned_char_type_node,
22404 tree unsigned_ftype_unsigned_ushort
22405 = build_function_type_list (unsigned_type_node,
22406 unsigned_type_node,
22407 short_unsigned_type_node,
22409 tree unsigned_ftype_unsigned_unsigned
22410 = build_function_type_list (unsigned_type_node,
22411 unsigned_type_node,
22412 unsigned_type_node,
22414 tree uint64_ftype_uint64_uint64
22415 = build_function_type_list (long_long_unsigned_type_node,
22416 long_long_unsigned_type_node,
22417 long_long_unsigned_type_node,
22419 tree float_ftype_float
22420 = build_function_type_list (float_type_node,
22425 tree V32QI_type_node = build_vector_type_for_mode (char_type_node,
22427 tree V8SI_type_node = build_vector_type_for_mode (intSI_type_node,
22429 tree V8SF_type_node = build_vector_type_for_mode (float_type_node,
22431 tree V4DI_type_node = build_vector_type_for_mode (long_long_integer_type_node,
22433 tree V4DF_type_node = build_vector_type_for_mode (double_type_node,
22435 tree v8sf_ftype_v8sf
22436 = build_function_type_list (V8SF_type_node,
22439 tree v8si_ftype_v8sf
22440 = build_function_type_list (V8SI_type_node,
22443 tree v8sf_ftype_v8si
22444 = build_function_type_list (V8SF_type_node,
22447 tree v4si_ftype_v4df
22448 = build_function_type_list (V4SI_type_node,
22451 tree v4df_ftype_v4df
22452 = build_function_type_list (V4DF_type_node,
22455 tree v4df_ftype_v4si
22456 = build_function_type_list (V4DF_type_node,
22459 tree v4df_ftype_v4sf
22460 = build_function_type_list (V4DF_type_node,
22463 tree v4sf_ftype_v4df
22464 = build_function_type_list (V4SF_type_node,
22467 tree v8sf_ftype_v8sf_v8sf
22468 = build_function_type_list (V8SF_type_node,
22469 V8SF_type_node, V8SF_type_node,
22471 tree v4df_ftype_v4df_v4df
22472 = build_function_type_list (V4DF_type_node,
22473 V4DF_type_node, V4DF_type_node,
22475 tree v8sf_ftype_v8sf_int
22476 = build_function_type_list (V8SF_type_node,
22477 V8SF_type_node, integer_type_node,
22479 tree v4si_ftype_v8si_int
22480 = build_function_type_list (V4SI_type_node,
22481 V8SI_type_node, integer_type_node,
22483 tree v4df_ftype_v4df_int
22484 = build_function_type_list (V4DF_type_node,
22485 V4DF_type_node, integer_type_node,
22487 tree v4sf_ftype_v8sf_int
22488 = build_function_type_list (V4SF_type_node,
22489 V8SF_type_node, integer_type_node,
22491 tree v2df_ftype_v4df_int
22492 = build_function_type_list (V2DF_type_node,
22493 V4DF_type_node, integer_type_node,
22495 tree v8sf_ftype_v8sf_v8sf_int
22496 = build_function_type_list (V8SF_type_node,
22497 V8SF_type_node, V8SF_type_node,
22500 tree v8sf_ftype_v8sf_v8sf_v8sf
22501 = build_function_type_list (V8SF_type_node,
22502 V8SF_type_node, V8SF_type_node,
22505 tree v4df_ftype_v4df_v4df_v4df
22506 = build_function_type_list (V4DF_type_node,
22507 V4DF_type_node, V4DF_type_node,
22510 tree v8si_ftype_v8si_v8si_int
22511 = build_function_type_list (V8SI_type_node,
22512 V8SI_type_node, V8SI_type_node,
22515 tree v4df_ftype_v4df_v4df_int
22516 = build_function_type_list (V4DF_type_node,
22517 V4DF_type_node, V4DF_type_node,
22520 tree v8sf_ftype_pcfloat
22521 = build_function_type_list (V8SF_type_node,
22524 tree v4df_ftype_pcdouble
22525 = build_function_type_list (V4DF_type_node,
22526 pcdouble_type_node,
22528 tree pcv4sf_type_node
22529 = build_pointer_type (build_type_variant (V4SF_type_node, 1, 0));
22530 tree pcv2df_type_node
22531 = build_pointer_type (build_type_variant (V2DF_type_node, 1, 0));
22532 tree v8sf_ftype_pcv4sf
22533 = build_function_type_list (V8SF_type_node,
22536 tree v4df_ftype_pcv2df
22537 = build_function_type_list (V4DF_type_node,
22540 tree v32qi_ftype_pcchar
22541 = build_function_type_list (V32QI_type_node,
22544 tree void_ftype_pchar_v32qi
22545 = build_function_type_list (void_type_node,
22546 pchar_type_node, V32QI_type_node,
22548 tree v8si_ftype_v8si_v4si_int
22549 = build_function_type_list (V8SI_type_node,
22550 V8SI_type_node, V4SI_type_node,
22553 tree pv4di_type_node = build_pointer_type (V4DI_type_node);
22554 tree void_ftype_pv4di_v4di
22555 = build_function_type_list (void_type_node,
22556 pv4di_type_node, V4DI_type_node,
22558 tree v8sf_ftype_v8sf_v4sf_int
22559 = build_function_type_list (V8SF_type_node,
22560 V8SF_type_node, V4SF_type_node,
22563 tree v4df_ftype_v4df_v2df_int
22564 = build_function_type_list (V4DF_type_node,
22565 V4DF_type_node, V2DF_type_node,
22568 tree void_ftype_pfloat_v8sf
22569 = build_function_type_list (void_type_node,
22570 pfloat_type_node, V8SF_type_node,
22572 tree void_ftype_pdouble_v4df
22573 = build_function_type_list (void_type_node,
22574 pdouble_type_node, V4DF_type_node,
22576 tree pv8sf_type_node = build_pointer_type (V8SF_type_node);
22577 tree pv4sf_type_node = build_pointer_type (V4SF_type_node);
22578 tree pv4df_type_node = build_pointer_type (V4DF_type_node);
22579 tree pv2df_type_node = build_pointer_type (V2DF_type_node);
22580 tree pcv8sf_type_node
22581 = build_pointer_type (build_type_variant (V8SF_type_node, 1, 0));
22582 tree pcv4df_type_node
22583 = build_pointer_type (build_type_variant (V4DF_type_node, 1, 0));
22584 tree v8sf_ftype_pcv8sf_v8sf
22585 = build_function_type_list (V8SF_type_node,
22586 pcv8sf_type_node, V8SF_type_node,
22588 tree v4df_ftype_pcv4df_v4df
22589 = build_function_type_list (V4DF_type_node,
22590 pcv4df_type_node, V4DF_type_node,
22592 tree v4sf_ftype_pcv4sf_v4sf
22593 = build_function_type_list (V4SF_type_node,
22594 pcv4sf_type_node, V4SF_type_node,
22596 tree v2df_ftype_pcv2df_v2df
22597 = build_function_type_list (V2DF_type_node,
22598 pcv2df_type_node, V2DF_type_node,
22600 tree void_ftype_pv8sf_v8sf_v8sf
22601 = build_function_type_list (void_type_node,
22602 pv8sf_type_node, V8SF_type_node,
22605 tree void_ftype_pv4df_v4df_v4df
22606 = build_function_type_list (void_type_node,
22607 pv4df_type_node, V4DF_type_node,
22610 tree void_ftype_pv4sf_v4sf_v4sf
22611 = build_function_type_list (void_type_node,
22612 pv4sf_type_node, V4SF_type_node,
22615 tree void_ftype_pv2df_v2df_v2df
22616 = build_function_type_list (void_type_node,
22617 pv2df_type_node, V2DF_type_node,
22620 tree v4df_ftype_v2df
22621 = build_function_type_list (V4DF_type_node,
22624 tree v8sf_ftype_v4sf
22625 = build_function_type_list (V8SF_type_node,
22628 tree v8si_ftype_v4si
22629 = build_function_type_list (V8SI_type_node,
22632 tree v2df_ftype_v4df
22633 = build_function_type_list (V2DF_type_node,
22636 tree v4sf_ftype_v8sf
22637 = build_function_type_list (V4SF_type_node,
22640 tree v4si_ftype_v8si
22641 = build_function_type_list (V4SI_type_node,
22644 tree int_ftype_v4df
22645 = build_function_type_list (integer_type_node,
22648 tree int_ftype_v8sf
22649 = build_function_type_list (integer_type_node,
22652 tree int_ftype_v8sf_v8sf
22653 = build_function_type_list (integer_type_node,
22654 V8SF_type_node, V8SF_type_node,
22656 tree int_ftype_v4di_v4di
22657 = build_function_type_list (integer_type_node,
22658 V4DI_type_node, V4DI_type_node,
22660 tree int_ftype_v4df_v4df
22661 = build_function_type_list (integer_type_node,
22662 V4DF_type_node, V4DF_type_node,
22664 tree v8sf_ftype_v8sf_v8si
22665 = build_function_type_list (V8SF_type_node,
22666 V8SF_type_node, V8SI_type_node,
22668 tree v4df_ftype_v4df_v4di
22669 = build_function_type_list (V4DF_type_node,
22670 V4DF_type_node, V4DI_type_node,
22672 tree v4sf_ftype_v4sf_v4si
22673 = build_function_type_list (V4SF_type_node,
22674 V4SF_type_node, V4SI_type_node, NULL_TREE);
22675 tree v2df_ftype_v2df_v2di
22676 = build_function_type_list (V2DF_type_node,
22677 V2DF_type_node, V2DI_type_node, NULL_TREE);
22681 /* Add all special builtins with variable number of operands. */
22682 for (i = 0, d = bdesc_special_args;
22683 i < ARRAY_SIZE (bdesc_special_args);
22691 switch ((enum ix86_special_builtin_type) d->flag)
22693 case VOID_FTYPE_VOID:
22694 type = void_ftype_void;
22696 case V32QI_FTYPE_PCCHAR:
22697 type = v32qi_ftype_pcchar;
22699 case V16QI_FTYPE_PCCHAR:
22700 type = v16qi_ftype_pcchar;
22702 case V8SF_FTYPE_PCV4SF:
22703 type = v8sf_ftype_pcv4sf;
22705 case V8SF_FTYPE_PCFLOAT:
22706 type = v8sf_ftype_pcfloat;
22708 case V4DF_FTYPE_PCV2DF:
22709 type = v4df_ftype_pcv2df;
22711 case V4DF_FTYPE_PCDOUBLE:
22712 type = v4df_ftype_pcdouble;
22714 case V4SF_FTYPE_PCFLOAT:
22715 type = v4sf_ftype_pcfloat;
22717 case V2DI_FTYPE_PV2DI:
22718 type = v2di_ftype_pv2di;
22720 case V2DF_FTYPE_PCDOUBLE:
22721 type = v2df_ftype_pcdouble;
22723 case V8SF_FTYPE_PCV8SF_V8SF:
22724 type = v8sf_ftype_pcv8sf_v8sf;
22726 case V4DF_FTYPE_PCV4DF_V4DF:
22727 type = v4df_ftype_pcv4df_v4df;
22729 case V4SF_FTYPE_V4SF_PCV2SF:
22730 type = v4sf_ftype_v4sf_pcv2sf;
22732 case V4SF_FTYPE_PCV4SF_V4SF:
22733 type = v4sf_ftype_pcv4sf_v4sf;
22735 case V2DF_FTYPE_V2DF_PCDOUBLE:
22736 type = v2df_ftype_v2df_pcdouble;
22738 case V2DF_FTYPE_PCV2DF_V2DF:
22739 type = v2df_ftype_pcv2df_v2df;
22741 case VOID_FTYPE_PV2SF_V4SF:
22742 type = void_ftype_pv2sf_v4sf;
22744 case VOID_FTYPE_PV4DI_V4DI:
22745 type = void_ftype_pv4di_v4di;
22747 case VOID_FTYPE_PV2DI_V2DI:
22748 type = void_ftype_pv2di_v2di;
22750 case VOID_FTYPE_PCHAR_V32QI:
22751 type = void_ftype_pchar_v32qi;
22753 case VOID_FTYPE_PCHAR_V16QI:
22754 type = void_ftype_pchar_v16qi;
22756 case VOID_FTYPE_PFLOAT_V8SF:
22757 type = void_ftype_pfloat_v8sf;
22759 case VOID_FTYPE_PFLOAT_V4SF:
22760 type = void_ftype_pfloat_v4sf;
22762 case VOID_FTYPE_PDOUBLE_V4DF:
22763 type = void_ftype_pdouble_v4df;
22765 case VOID_FTYPE_PDOUBLE_V2DF:
22766 type = void_ftype_pdouble_v2df;
22768 case VOID_FTYPE_PDI_DI:
22769 type = void_ftype_pdi_di;
22771 case VOID_FTYPE_PINT_INT:
22772 type = void_ftype_pint_int;
22774 case VOID_FTYPE_PV8SF_V8SF_V8SF:
22775 type = void_ftype_pv8sf_v8sf_v8sf;
22777 case VOID_FTYPE_PV4DF_V4DF_V4DF:
22778 type = void_ftype_pv4df_v4df_v4df;
22780 case VOID_FTYPE_PV4SF_V4SF_V4SF:
22781 type = void_ftype_pv4sf_v4sf_v4sf;
22783 case VOID_FTYPE_PV2DF_V2DF_V2DF:
22784 type = void_ftype_pv2df_v2df_v2df;
22787 gcc_unreachable ();
22790 def_builtin (d->mask, d->name, type, d->code);
22793 /* Add all builtins with variable number of operands. */
22794 for (i = 0, d = bdesc_args;
22795 i < ARRAY_SIZE (bdesc_args);
22803 switch ((enum ix86_builtin_type) d->flag)
22805 case FLOAT_FTYPE_FLOAT:
22806 type = float_ftype_float;
22808 case INT_FTYPE_V8SF_V8SF_PTEST:
22809 type = int_ftype_v8sf_v8sf;
22811 case INT_FTYPE_V4DI_V4DI_PTEST:
22812 type = int_ftype_v4di_v4di;
22814 case INT_FTYPE_V4DF_V4DF_PTEST:
22815 type = int_ftype_v4df_v4df;
22817 case INT_FTYPE_V4SF_V4SF_PTEST:
22818 type = int_ftype_v4sf_v4sf;
22820 case INT_FTYPE_V2DI_V2DI_PTEST:
22821 type = int_ftype_v2di_v2di;
22823 case INT_FTYPE_V2DF_V2DF_PTEST:
22824 type = int_ftype_v2df_v2df;
22826 case INT64_FTYPE_V4SF:
22827 type = int64_ftype_v4sf;
22829 case INT64_FTYPE_V2DF:
22830 type = int64_ftype_v2df;
22832 case INT_FTYPE_V16QI:
22833 type = int_ftype_v16qi;
22835 case INT_FTYPE_V8QI:
22836 type = int_ftype_v8qi;
22838 case INT_FTYPE_V8SF:
22839 type = int_ftype_v8sf;
22841 case INT_FTYPE_V4DF:
22842 type = int_ftype_v4df;
22844 case INT_FTYPE_V4SF:
22845 type = int_ftype_v4sf;
22847 case INT_FTYPE_V2DF:
22848 type = int_ftype_v2df;
22850 case V16QI_FTYPE_V16QI:
22851 type = v16qi_ftype_v16qi;
22853 case V8SI_FTYPE_V8SF:
22854 type = v8si_ftype_v8sf;
22856 case V8SI_FTYPE_V4SI:
22857 type = v8si_ftype_v4si;
22859 case V8HI_FTYPE_V8HI:
22860 type = v8hi_ftype_v8hi;
22862 case V8HI_FTYPE_V16QI:
22863 type = v8hi_ftype_v16qi;
22865 case V8QI_FTYPE_V8QI:
22866 type = v8qi_ftype_v8qi;
22868 case V8SF_FTYPE_V8SF:
22869 type = v8sf_ftype_v8sf;
22871 case V8SF_FTYPE_V8SI:
22872 type = v8sf_ftype_v8si;
22874 case V8SF_FTYPE_V4SF:
22875 type = v8sf_ftype_v4sf;
22877 case V4SI_FTYPE_V4DF:
22878 type = v4si_ftype_v4df;
22880 case V4SI_FTYPE_V4SI:
22881 type = v4si_ftype_v4si;
22883 case V4SI_FTYPE_V16QI:
22884 type = v4si_ftype_v16qi;
22886 case V4SI_FTYPE_V8SI:
22887 type = v4si_ftype_v8si;
22889 case V4SI_FTYPE_V8HI:
22890 type = v4si_ftype_v8hi;
22892 case V4SI_FTYPE_V4SF:
22893 type = v4si_ftype_v4sf;
22895 case V4SI_FTYPE_V2DF:
22896 type = v4si_ftype_v2df;
22898 case V4HI_FTYPE_V4HI:
22899 type = v4hi_ftype_v4hi;
22901 case V4DF_FTYPE_V4DF:
22902 type = v4df_ftype_v4df;
22904 case V4DF_FTYPE_V4SI:
22905 type = v4df_ftype_v4si;
22907 case V4DF_FTYPE_V4SF:
22908 type = v4df_ftype_v4sf;
22910 case V4DF_FTYPE_V2DF:
22911 type = v4df_ftype_v2df;
22913 case V4SF_FTYPE_V4SF:
22914 case V4SF_FTYPE_V4SF_VEC_MERGE:
22915 type = v4sf_ftype_v4sf;
22917 case V4SF_FTYPE_V8SF:
22918 type = v4sf_ftype_v8sf;
22920 case V4SF_FTYPE_V4SI:
22921 type = v4sf_ftype_v4si;
22923 case V4SF_FTYPE_V4DF:
22924 type = v4sf_ftype_v4df;
22926 case V4SF_FTYPE_V2DF:
22927 type = v4sf_ftype_v2df;
22929 case V2DI_FTYPE_V2DI:
22930 type = v2di_ftype_v2di;
22932 case V2DI_FTYPE_V16QI:
22933 type = v2di_ftype_v16qi;
22935 case V2DI_FTYPE_V8HI:
22936 type = v2di_ftype_v8hi;
22938 case V2DI_FTYPE_V4SI:
22939 type = v2di_ftype_v4si;
22941 case V2SI_FTYPE_V2SI:
22942 type = v2si_ftype_v2si;
22944 case V2SI_FTYPE_V4SF:
22945 type = v2si_ftype_v4sf;
22947 case V2SI_FTYPE_V2DF:
22948 type = v2si_ftype_v2df;
22950 case V2SI_FTYPE_V2SF:
22951 type = v2si_ftype_v2sf;
22953 case V2DF_FTYPE_V4DF:
22954 type = v2df_ftype_v4df;
22956 case V2DF_FTYPE_V4SF:
22957 type = v2df_ftype_v4sf;
22959 case V2DF_FTYPE_V2DF:
22960 case V2DF_FTYPE_V2DF_VEC_MERGE:
22961 type = v2df_ftype_v2df;
22963 case V2DF_FTYPE_V2SI:
22964 type = v2df_ftype_v2si;
22966 case V2DF_FTYPE_V4SI:
22967 type = v2df_ftype_v4si;
22969 case V2SF_FTYPE_V2SF:
22970 type = v2sf_ftype_v2sf;
22972 case V2SF_FTYPE_V2SI:
22973 type = v2sf_ftype_v2si;
22975 case V16QI_FTYPE_V16QI_V16QI:
22976 type = v16qi_ftype_v16qi_v16qi;
22978 case V16QI_FTYPE_V8HI_V8HI:
22979 type = v16qi_ftype_v8hi_v8hi;
22981 case V8QI_FTYPE_V8QI_V8QI:
22982 type = v8qi_ftype_v8qi_v8qi;
22984 case V8QI_FTYPE_V4HI_V4HI:
22985 type = v8qi_ftype_v4hi_v4hi;
22987 case V8HI_FTYPE_V8HI_V8HI:
22988 case V8HI_FTYPE_V8HI_V8HI_COUNT:
22989 type = v8hi_ftype_v8hi_v8hi;
22991 case V8HI_FTYPE_V16QI_V16QI:
22992 type = v8hi_ftype_v16qi_v16qi;
22994 case V8HI_FTYPE_V4SI_V4SI:
22995 type = v8hi_ftype_v4si_v4si;
22997 case V8HI_FTYPE_V8HI_SI_COUNT:
22998 type = v8hi_ftype_v8hi_int;
23000 case V8SF_FTYPE_V8SF_V8SF:
23001 type = v8sf_ftype_v8sf_v8sf;
23003 case V8SF_FTYPE_V8SF_V8SI:
23004 type = v8sf_ftype_v8sf_v8si;
23006 case V4SI_FTYPE_V4SI_V4SI:
23007 case V4SI_FTYPE_V4SI_V4SI_COUNT:
23008 type = v4si_ftype_v4si_v4si;
23010 case V4SI_FTYPE_V8HI_V8HI:
23011 type = v4si_ftype_v8hi_v8hi;
23013 case V4SI_FTYPE_V4SF_V4SF:
23014 type = v4si_ftype_v4sf_v4sf;
23016 case V4SI_FTYPE_V2DF_V2DF:
23017 type = v4si_ftype_v2df_v2df;
23019 case V4SI_FTYPE_V4SI_SI_COUNT:
23020 type = v4si_ftype_v4si_int;
23022 case V4HI_FTYPE_V4HI_V4HI:
23023 case V4HI_FTYPE_V4HI_V4HI_COUNT:
23024 type = v4hi_ftype_v4hi_v4hi;
23026 case V4HI_FTYPE_V8QI_V8QI:
23027 type = v4hi_ftype_v8qi_v8qi;
23029 case V4HI_FTYPE_V2SI_V2SI:
23030 type = v4hi_ftype_v2si_v2si;
23032 case V4HI_FTYPE_V4HI_SI_COUNT:
23033 type = v4hi_ftype_v4hi_int;
23035 case V4DF_FTYPE_V4DF_V4DF:
23036 type = v4df_ftype_v4df_v4df;
23038 case V4DF_FTYPE_V4DF_V4DI:
23039 type = v4df_ftype_v4df_v4di;
23041 case V4SF_FTYPE_V4SF_V4SF:
23042 case V4SF_FTYPE_V4SF_V4SF_SWAP:
23043 type = v4sf_ftype_v4sf_v4sf;
23045 case V4SF_FTYPE_V4SF_V4SI:
23046 type = v4sf_ftype_v4sf_v4si;
23048 case V4SF_FTYPE_V4SF_V2SI:
23049 type = v4sf_ftype_v4sf_v2si;
23051 case V4SF_FTYPE_V4SF_V2DF:
23052 type = v4sf_ftype_v4sf_v2df;
23054 case V4SF_FTYPE_V4SF_DI:
23055 type = v4sf_ftype_v4sf_int64;
23057 case V4SF_FTYPE_V4SF_SI:
23058 type = v4sf_ftype_v4sf_int;
23060 case V2DI_FTYPE_V2DI_V2DI:
23061 case V2DI_FTYPE_V2DI_V2DI_COUNT:
23062 type = v2di_ftype_v2di_v2di;
23064 case V2DI_FTYPE_V16QI_V16QI:
23065 type = v2di_ftype_v16qi_v16qi;
23067 case V2DI_FTYPE_V4SI_V4SI:
23068 type = v2di_ftype_v4si_v4si;
23070 case V2DI_FTYPE_V2DI_V16QI:
23071 type = v2di_ftype_v2di_v16qi;
23073 case V2DI_FTYPE_V2DF_V2DF:
23074 type = v2di_ftype_v2df_v2df;
23076 case V2DI_FTYPE_V2DI_SI_COUNT:
23077 type = v2di_ftype_v2di_int;
23079 case V2SI_FTYPE_V2SI_V2SI:
23080 case V2SI_FTYPE_V2SI_V2SI_COUNT:
23081 type = v2si_ftype_v2si_v2si;
23083 case V2SI_FTYPE_V4HI_V4HI:
23084 type = v2si_ftype_v4hi_v4hi;
23086 case V2SI_FTYPE_V2SF_V2SF:
23087 type = v2si_ftype_v2sf_v2sf;
23089 case V2SI_FTYPE_V2SI_SI_COUNT:
23090 type = v2si_ftype_v2si_int;
23092 case V2DF_FTYPE_V2DF_V2DF:
23093 case V2DF_FTYPE_V2DF_V2DF_SWAP:
23094 type = v2df_ftype_v2df_v2df;
23096 case V2DF_FTYPE_V2DF_V4SF:
23097 type = v2df_ftype_v2df_v4sf;
23099 case V2DF_FTYPE_V2DF_V2DI:
23100 type = v2df_ftype_v2df_v2di;
23102 case V2DF_FTYPE_V2DF_DI:
23103 type = v2df_ftype_v2df_int64;
23105 case V2DF_FTYPE_V2DF_SI:
23106 type = v2df_ftype_v2df_int;
23108 case V2SF_FTYPE_V2SF_V2SF:
23109 type = v2sf_ftype_v2sf_v2sf;
23111 case V1DI_FTYPE_V1DI_V1DI:
23112 case V1DI_FTYPE_V1DI_V1DI_COUNT:
23113 type = v1di_ftype_v1di_v1di;
23115 case V1DI_FTYPE_V8QI_V8QI:
23116 type = v1di_ftype_v8qi_v8qi;
23118 case V1DI_FTYPE_V2SI_V2SI:
23119 type = v1di_ftype_v2si_v2si;
23121 case V1DI_FTYPE_V1DI_SI_COUNT:
23122 type = v1di_ftype_v1di_int;
23124 case UINT64_FTYPE_UINT64_UINT64:
23125 type = uint64_ftype_uint64_uint64;
23127 case UINT_FTYPE_UINT_UINT:
23128 type = unsigned_ftype_unsigned_unsigned;
23130 case UINT_FTYPE_UINT_USHORT:
23131 type = unsigned_ftype_unsigned_ushort;
23133 case UINT_FTYPE_UINT_UCHAR:
23134 type = unsigned_ftype_unsigned_uchar;
23136 case V8HI_FTYPE_V8HI_INT:
23137 type = v8hi_ftype_v8hi_int;
23139 case V8SF_FTYPE_V8SF_INT:
23140 type = v8sf_ftype_v8sf_int;
23142 case V4SI_FTYPE_V4SI_INT:
23143 type = v4si_ftype_v4si_int;
23145 case V4SI_FTYPE_V8SI_INT:
23146 type = v4si_ftype_v8si_int;
23148 case V4HI_FTYPE_V4HI_INT:
23149 type = v4hi_ftype_v4hi_int;
23151 case V4DF_FTYPE_V4DF_INT:
23152 type = v4df_ftype_v4df_int;
23154 case V4SF_FTYPE_V4SF_INT:
23155 type = v4sf_ftype_v4sf_int;
23157 case V4SF_FTYPE_V8SF_INT:
23158 type = v4sf_ftype_v8sf_int;
23160 case V2DI_FTYPE_V2DI_INT:
23161 case V2DI2TI_FTYPE_V2DI_INT:
23162 type = v2di_ftype_v2di_int;
23164 case V2DF_FTYPE_V2DF_INT:
23165 type = v2df_ftype_v2df_int;
23167 case V2DF_FTYPE_V4DF_INT:
23168 type = v2df_ftype_v4df_int;
23170 case V16QI_FTYPE_V16QI_V16QI_V16QI:
23171 type = v16qi_ftype_v16qi_v16qi_v16qi;
23173 case V8SF_FTYPE_V8SF_V8SF_V8SF:
23174 type = v8sf_ftype_v8sf_v8sf_v8sf;
23176 case V4DF_FTYPE_V4DF_V4DF_V4DF:
23177 type = v4df_ftype_v4df_v4df_v4df;
23179 case V4SF_FTYPE_V4SF_V4SF_V4SF:
23180 type = v4sf_ftype_v4sf_v4sf_v4sf;
23182 case V2DF_FTYPE_V2DF_V2DF_V2DF:
23183 type = v2df_ftype_v2df_v2df_v2df;
23185 case V16QI_FTYPE_V16QI_V16QI_INT:
23186 type = v16qi_ftype_v16qi_v16qi_int;
23188 case V8SI_FTYPE_V8SI_V8SI_INT:
23189 type = v8si_ftype_v8si_v8si_int;
23191 case V8SI_FTYPE_V8SI_V4SI_INT:
23192 type = v8si_ftype_v8si_v4si_int;
23194 case V8HI_FTYPE_V8HI_V8HI_INT:
23195 type = v8hi_ftype_v8hi_v8hi_int;
23197 case V8SF_FTYPE_V8SF_V8SF_INT:
23198 type = v8sf_ftype_v8sf_v8sf_int;
23200 case V8SF_FTYPE_V8SF_V4SF_INT:
23201 type = v8sf_ftype_v8sf_v4sf_int;
23203 case V4SI_FTYPE_V4SI_V4SI_INT:
23204 type = v4si_ftype_v4si_v4si_int;
23206 case V4DF_FTYPE_V4DF_V4DF_INT:
23207 type = v4df_ftype_v4df_v4df_int;
23209 case V4DF_FTYPE_V4DF_V2DF_INT:
23210 type = v4df_ftype_v4df_v2df_int;
23212 case V4SF_FTYPE_V4SF_V4SF_INT:
23213 type = v4sf_ftype_v4sf_v4sf_int;
23215 case V2DI_FTYPE_V2DI_V2DI_INT:
23216 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
23217 type = v2di_ftype_v2di_v2di_int;
23219 case V2DF_FTYPE_V2DF_V2DF_INT:
23220 type = v2df_ftype_v2df_v2df_int;
23222 case V2DI_FTYPE_V2DI_UINT_UINT:
23223 type = v2di_ftype_v2di_unsigned_unsigned;
23225 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
23226 type = v2di_ftype_v2di_v2di_unsigned_unsigned;
23228 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
23229 type = v1di_ftype_v1di_v1di_int;
23232 gcc_unreachable ();
23235 def_builtin_const (d->mask, d->name, type, d->code);
23238 /* pcmpestr[im] insns. */
23239 for (i = 0, d = bdesc_pcmpestr;
23240 i < ARRAY_SIZE (bdesc_pcmpestr);
23243 if (d->code == IX86_BUILTIN_PCMPESTRM128)
23244 ftype = v16qi_ftype_v16qi_int_v16qi_int_int;
23246 ftype = int_ftype_v16qi_int_v16qi_int_int;
23247 def_builtin_const (d->mask, d->name, ftype, d->code);
23250 /* pcmpistr[im] insns. */
23251 for (i = 0, d = bdesc_pcmpistr;
23252 i < ARRAY_SIZE (bdesc_pcmpistr);
23255 if (d->code == IX86_BUILTIN_PCMPISTRM128)
23256 ftype = v16qi_ftype_v16qi_v16qi_int;
23258 ftype = int_ftype_v16qi_v16qi_int;
23259 def_builtin_const (d->mask, d->name, ftype, d->code);
23262 /* comi/ucomi insns. */
23263 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
23264 if (d->mask == OPTION_MASK_ISA_SSE2)
23265 def_builtin_const (d->mask, d->name, int_ftype_v2df_v2df, d->code);
23267 def_builtin_const (d->mask, d->name, int_ftype_v4sf_v4sf, d->code);
23270 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr", void_ftype_unsigned, IX86_BUILTIN_LDMXCSR);
23271 def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr", unsigned_ftype_void, IX86_BUILTIN_STMXCSR);
23273 /* SSE or 3DNow!A */
23274 def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ);
23277 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU);
23279 def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH);
23280 x86_mfence = def_builtin (OPTION_MASK_ISA_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE);
23283 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_monitor", void_ftype_pcvoid_unsigned_unsigned, IX86_BUILTIN_MONITOR);
23284 def_builtin (OPTION_MASK_ISA_SSE3, "__builtin_ia32_mwait", void_ftype_unsigned_unsigned, IX86_BUILTIN_MWAIT);
23287 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenc128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENC128);
23288 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesenclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESENCLAST128);
23289 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdec128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDEC128);
23290 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesdeclast128", v2di_ftype_v2di_v2di, IX86_BUILTIN_AESDECLAST128);
23291 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aesimc128", v2di_ftype_v2di, IX86_BUILTIN_AESIMC128);
23292 def_builtin_const (OPTION_MASK_ISA_AES, "__builtin_ia32_aeskeygenassist128", v2di_ftype_v2di_int, IX86_BUILTIN_AESKEYGENASSIST128);
23295 def_builtin_const (OPTION_MASK_ISA_PCLMUL, "__builtin_ia32_pclmulqdq128", v2di_ftype_v2di_v2di_int, IX86_BUILTIN_PCLMULQDQ128);
23298 def_builtin (OPTION_MASK_ISA_AVX, "__builtin_ia32_vzeroupper", void_ftype_void,
23299 TARGET_64BIT ? IX86_BUILTIN_VZEROUPPER_REX64 : IX86_BUILTIN_VZEROUPPER);
23301 /* Access to the vec_init patterns. */
23302 ftype = build_function_type_list (V2SI_type_node, integer_type_node,
23303 integer_type_node, NULL_TREE);
23304 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v2si", ftype, IX86_BUILTIN_VEC_INIT_V2SI);
23306 ftype = build_function_type_list (V4HI_type_node, short_integer_type_node,
23307 short_integer_type_node,
23308 short_integer_type_node,
23309 short_integer_type_node, NULL_TREE);
23310 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v4hi", ftype, IX86_BUILTIN_VEC_INIT_V4HI);
23312 ftype = build_function_type_list (V8QI_type_node, char_type_node,
23313 char_type_node, char_type_node,
23314 char_type_node, char_type_node,
23315 char_type_node, char_type_node,
23316 char_type_node, NULL_TREE);
23317 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_init_v8qi", ftype, IX86_BUILTIN_VEC_INIT_V8QI);
23319 /* Access to the vec_extract patterns. */
23320 ftype = build_function_type_list (double_type_node, V2DF_type_node,
23321 integer_type_node, NULL_TREE);
23322 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2df", ftype, IX86_BUILTIN_VEC_EXT_V2DF);
23324 ftype = build_function_type_list (long_long_integer_type_node,
23325 V2DI_type_node, integer_type_node,
23327 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v2di", ftype, IX86_BUILTIN_VEC_EXT_V2DI);
23329 ftype = build_function_type_list (float_type_node, V4SF_type_node,
23330 integer_type_node, NULL_TREE);
23331 def_builtin_const (OPTION_MASK_ISA_SSE, "__builtin_ia32_vec_ext_v4sf", ftype, IX86_BUILTIN_VEC_EXT_V4SF);
23333 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
23334 integer_type_node, NULL_TREE);
23335 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v4si", ftype, IX86_BUILTIN_VEC_EXT_V4SI);
23337 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
23338 integer_type_node, NULL_TREE);
23339 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v8hi", ftype, IX86_BUILTIN_VEC_EXT_V8HI);
23341 ftype = build_function_type_list (intHI_type_node, V4HI_type_node,
23342 integer_type_node, NULL_TREE);
23343 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", ftype, IX86_BUILTIN_VEC_EXT_V4HI);
23345 ftype = build_function_type_list (intSI_type_node, V2SI_type_node,
23346 integer_type_node, NULL_TREE);
23347 def_builtin_const (OPTION_MASK_ISA_MMX, "__builtin_ia32_vec_ext_v2si", ftype, IX86_BUILTIN_VEC_EXT_V2SI);
23349 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
23350 integer_type_node, NULL_TREE);
23351 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_ext_v16qi", ftype, IX86_BUILTIN_VEC_EXT_V16QI);
23353 /* Access to the vec_set patterns. */
23354 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
23356 integer_type_node, NULL_TREE);
23357 def_builtin_const (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_64BIT, "__builtin_ia32_vec_set_v2di", ftype, IX86_BUILTIN_VEC_SET_V2DI);
23359 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
23361 integer_type_node, NULL_TREE);
23362 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4sf", ftype, IX86_BUILTIN_VEC_SET_V4SF);
23364 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
23366 integer_type_node, NULL_TREE);
23367 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v4si", ftype, IX86_BUILTIN_VEC_SET_V4SI);
23369 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
23371 integer_type_node, NULL_TREE);
23372 def_builtin_const (OPTION_MASK_ISA_SSE2, "__builtin_ia32_vec_set_v8hi", ftype, IX86_BUILTIN_VEC_SET_V8HI);
23374 ftype = build_function_type_list (V4HI_type_node, V4HI_type_node,
23376 integer_type_node, NULL_TREE);
23377 def_builtin_const (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, "__builtin_ia32_vec_set_v4hi", ftype, IX86_BUILTIN_VEC_SET_V4HI);
23379 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
23381 integer_type_node, NULL_TREE);
23382 def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
23384 /* Add SSE5 multi-arg argument instructions */
23385 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
23387 tree mtype = NULL_TREE;
23392 switch ((enum multi_arg_type)d->flag)
23394 case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
23395 case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
23396 case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
23397 case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
23398 case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
23399 case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
23400 case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
23401 case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
23402 case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
23403 case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
23404 case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
23405 case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
23406 case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
23407 case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
23408 case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
23409 case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
23410 case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
23411 case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
23412 case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
23413 case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
23414 case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
23415 case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
23416 case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
23417 case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
23418 case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
23419 case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
23420 case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
23421 case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
23422 case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
23423 case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
23424 case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
23425 case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
23426 case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
23427 case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
23428 case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
23429 case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
23430 case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
23431 case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
23432 case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
23433 case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
23434 case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
23435 case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
23436 case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
23437 case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
23438 case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
23439 case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
23440 case MULTI_ARG_UNKNOWN:
23442 gcc_unreachable ();
23446 def_builtin_const (d->mask, d->name, mtype, d->code);
23450 /* Internal method for ix86_init_builtins. */
23453 ix86_init_builtins_va_builtins_abi (void)
23455 tree ms_va_ref, sysv_va_ref;
23456 tree fnvoid_va_end_ms, fnvoid_va_end_sysv;
23457 tree fnvoid_va_start_ms, fnvoid_va_start_sysv;
23458 tree fnvoid_va_copy_ms, fnvoid_va_copy_sysv;
23459 tree fnattr_ms = NULL_TREE, fnattr_sysv = NULL_TREE;
23463 fnattr_ms = build_tree_list (get_identifier ("ms_abi"), NULL_TREE);
23464 fnattr_sysv = build_tree_list (get_identifier ("sysv_abi"), NULL_TREE);
23465 ms_va_ref = build_reference_type (ms_va_list_type_node);
23467 build_pointer_type (TREE_TYPE (sysv_va_list_type_node));
23470 build_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23471 fnvoid_va_start_ms =
23472 build_varargs_function_type_list (void_type_node, ms_va_ref, NULL_TREE);
23473 fnvoid_va_end_sysv =
23474 build_function_type_list (void_type_node, sysv_va_ref, NULL_TREE);
23475 fnvoid_va_start_sysv =
23476 build_varargs_function_type_list (void_type_node, sysv_va_ref,
23478 fnvoid_va_copy_ms =
23479 build_function_type_list (void_type_node, ms_va_ref, ms_va_list_type_node,
23481 fnvoid_va_copy_sysv =
23482 build_function_type_list (void_type_node, sysv_va_ref,
23483 sysv_va_ref, NULL_TREE);
23485 add_builtin_function ("__builtin_ms_va_start", fnvoid_va_start_ms,
23486 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_ms);
23487 add_builtin_function ("__builtin_ms_va_end", fnvoid_va_end_ms,
23488 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_ms);
23489 add_builtin_function ("__builtin_ms_va_copy", fnvoid_va_copy_ms,
23490 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_ms);
23491 add_builtin_function ("__builtin_sysv_va_start", fnvoid_va_start_sysv,
23492 BUILT_IN_VA_START, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23493 add_builtin_function ("__builtin_sysv_va_end", fnvoid_va_end_sysv,
23494 BUILT_IN_VA_END, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23495 add_builtin_function ("__builtin_sysv_va_copy", fnvoid_va_copy_sysv,
23496 BUILT_IN_VA_COPY, BUILT_IN_NORMAL, NULL, fnattr_sysv);
23500 ix86_init_builtins (void)
23502 tree float128_type_node = make_node (REAL_TYPE);
23505 /* The __float80 type. */
23506 if (TYPE_MODE (long_double_type_node) == XFmode)
23507 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
23511 /* The __float80 type. */
23512 tree float80_type_node = make_node (REAL_TYPE);
23514 TYPE_PRECISION (float80_type_node) = 80;
23515 layout_type (float80_type_node);
23516 (*lang_hooks.types.register_builtin_type) (float80_type_node,
23520 /* The __float128 type. */
23521 TYPE_PRECISION (float128_type_node) = 128;
23522 layout_type (float128_type_node);
23523 (*lang_hooks.types.register_builtin_type) (float128_type_node,
23526 /* TFmode support builtins. */
23527 ftype = build_function_type (float128_type_node, void_list_node);
23528 decl = add_builtin_function ("__builtin_infq", ftype,
23529 IX86_BUILTIN_INFQ, BUILT_IN_MD,
23531 ix86_builtins[(int) IX86_BUILTIN_INFQ] = decl;
23533 /* We will expand them to normal call if SSE2 isn't available since
23534 they are used by libgcc. */
23535 ftype = build_function_type_list (float128_type_node,
23536 float128_type_node,
23538 decl = add_builtin_function ("__builtin_fabsq", ftype,
23539 IX86_BUILTIN_FABSQ, BUILT_IN_MD,
23540 "__fabstf2", NULL_TREE);
23541 ix86_builtins[(int) IX86_BUILTIN_FABSQ] = decl;
23542 TREE_READONLY (decl) = 1;
23544 ftype = build_function_type_list (float128_type_node,
23545 float128_type_node,
23546 float128_type_node,
23548 decl = add_builtin_function ("__builtin_copysignq", ftype,
23549 IX86_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
23550 "__copysigntf3", NULL_TREE);
23551 ix86_builtins[(int) IX86_BUILTIN_COPYSIGNQ] = decl;
23552 TREE_READONLY (decl) = 1;
23554 ix86_init_mmx_sse_builtins ();
23556 ix86_init_builtins_va_builtins_abi ();
23559 /* Errors in the source file can cause expand_expr to return const0_rtx
23560 where we expect a vector. To avoid crashing, use one of the vector
23561 clear instructions. */
23563 safe_vector_operand (rtx x, enum machine_mode mode)
23565 if (x == const0_rtx)
23566 x = CONST0_RTX (mode);
23570 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
23573 ix86_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
23576 tree arg0 = CALL_EXPR_ARG (exp, 0);
23577 tree arg1 = CALL_EXPR_ARG (exp, 1);
23578 rtx op0 = expand_normal (arg0);
23579 rtx op1 = expand_normal (arg1);
23580 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23581 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23582 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
23584 if (VECTOR_MODE_P (mode0))
23585 op0 = safe_vector_operand (op0, mode0);
23586 if (VECTOR_MODE_P (mode1))
23587 op1 = safe_vector_operand (op1, mode1);
23589 if (optimize || !target
23590 || GET_MODE (target) != tmode
23591 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23592 target = gen_reg_rtx (tmode);
23594 if (GET_MODE (op1) == SImode && mode1 == TImode)
23596 rtx x = gen_reg_rtx (V4SImode);
23597 emit_insn (gen_sse2_loadd (x, op1));
23598 op1 = gen_lowpart (TImode, x);
23601 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
23602 op0 = copy_to_mode_reg (mode0, op0);
23603 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
23604 op1 = copy_to_mode_reg (mode1, op1);
23606 pat = GEN_FCN (icode) (target, op0, op1);
23615 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
23618 ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
23619 enum multi_arg_type m_type,
23620 enum insn_code sub_code)
23625 bool comparison_p = false;
23627 bool last_arg_constant = false;
23628 int num_memory = 0;
23631 enum machine_mode mode;
23634 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23638 case MULTI_ARG_3_SF:
23639 case MULTI_ARG_3_DF:
23640 case MULTI_ARG_3_DI:
23641 case MULTI_ARG_3_SI:
23642 case MULTI_ARG_3_SI_DI:
23643 case MULTI_ARG_3_HI:
23644 case MULTI_ARG_3_HI_SI:
23645 case MULTI_ARG_3_QI:
23646 case MULTI_ARG_3_PERMPS:
23647 case MULTI_ARG_3_PERMPD:
23651 case MULTI_ARG_2_SF:
23652 case MULTI_ARG_2_DF:
23653 case MULTI_ARG_2_DI:
23654 case MULTI_ARG_2_SI:
23655 case MULTI_ARG_2_HI:
23656 case MULTI_ARG_2_QI:
23660 case MULTI_ARG_2_DI_IMM:
23661 case MULTI_ARG_2_SI_IMM:
23662 case MULTI_ARG_2_HI_IMM:
23663 case MULTI_ARG_2_QI_IMM:
23665 last_arg_constant = true;
23668 case MULTI_ARG_1_SF:
23669 case MULTI_ARG_1_DF:
23670 case MULTI_ARG_1_DI:
23671 case MULTI_ARG_1_SI:
23672 case MULTI_ARG_1_HI:
23673 case MULTI_ARG_1_QI:
23674 case MULTI_ARG_1_SI_DI:
23675 case MULTI_ARG_1_HI_DI:
23676 case MULTI_ARG_1_HI_SI:
23677 case MULTI_ARG_1_QI_DI:
23678 case MULTI_ARG_1_QI_SI:
23679 case MULTI_ARG_1_QI_HI:
23680 case MULTI_ARG_1_PH2PS:
23681 case MULTI_ARG_1_PS2PH:
23685 case MULTI_ARG_2_SF_CMP:
23686 case MULTI_ARG_2_DF_CMP:
23687 case MULTI_ARG_2_DI_CMP:
23688 case MULTI_ARG_2_SI_CMP:
23689 case MULTI_ARG_2_HI_CMP:
23690 case MULTI_ARG_2_QI_CMP:
23692 comparison_p = true;
23695 case MULTI_ARG_2_SF_TF:
23696 case MULTI_ARG_2_DF_TF:
23697 case MULTI_ARG_2_DI_TF:
23698 case MULTI_ARG_2_SI_TF:
23699 case MULTI_ARG_2_HI_TF:
23700 case MULTI_ARG_2_QI_TF:
23705 case MULTI_ARG_UNKNOWN:
23707 gcc_unreachable ();
23710 if (optimize || !target
23711 || GET_MODE (target) != tmode
23712 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23713 target = gen_reg_rtx (tmode);
23715 gcc_assert (nargs <= 4);
23717 for (i = 0; i < nargs; i++)
23719 tree arg = CALL_EXPR_ARG (exp, i);
23720 rtx op = expand_normal (arg);
23721 int adjust = (comparison_p) ? 1 : 0;
23722 enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
23724 if (last_arg_constant && i == nargs-1)
23726 if (GET_CODE (op) != CONST_INT)
23728 error ("last argument must be an immediate");
23729 return gen_reg_rtx (tmode);
23734 if (VECTOR_MODE_P (mode))
23735 op = safe_vector_operand (op, mode);
23737 /* If we aren't optimizing, only allow one memory operand to be
23739 if (memory_operand (op, mode))
23742 gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
23745 || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
23747 op = force_reg (mode, op);
23751 args[i].mode = mode;
23757 pat = GEN_FCN (icode) (target, args[0].op);
23762 pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
23763 GEN_INT ((int)sub_code));
23764 else if (! comparison_p)
23765 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
23768 rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
23772 pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
23777 pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
23781 gcc_unreachable ();
23791 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
23792 insns with vec_merge. */
23795 ix86_expand_unop_vec_merge_builtin (enum insn_code icode, tree exp,
23799 tree arg0 = CALL_EXPR_ARG (exp, 0);
23800 rtx op1, op0 = expand_normal (arg0);
23801 enum machine_mode tmode = insn_data[icode].operand[0].mode;
23802 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
23804 if (optimize || !target
23805 || GET_MODE (target) != tmode
23806 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
23807 target = gen_reg_rtx (tmode);
23809 if (VECTOR_MODE_P (mode0))
23810 op0 = safe_vector_operand (op0, mode0);
23812 if ((optimize && !register_operand (op0, mode0))
23813 || ! (*insn_data[icode].operand[1].predicate) (op0, mode0))
23814 op0 = copy_to_mode_reg (mode0, op0);
23817 if (! (*insn_data[icode].operand[2].predicate) (op1, mode0))
23818 op1 = copy_to_mode_reg (mode0, op1);
23820 pat = GEN_FCN (icode) (target, op0, op1);
23827 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
23830 ix86_expand_sse_compare (const struct builtin_description *d,
23831 tree exp, rtx target, bool swap)
23834 tree arg0 = CALL_EXPR_ARG (exp, 0);
23835 tree arg1 = CALL_EXPR_ARG (exp, 1);
23836 rtx op0 = expand_normal (arg0);
23837 rtx op1 = expand_normal (arg1);
23839 enum machine_mode tmode = insn_data[d->icode].operand[0].mode;
23840 enum machine_mode mode0 = insn_data[d->icode].operand[1].mode;
23841 enum machine_mode mode1 = insn_data[d->icode].operand[2].mode;
23842 enum rtx_code comparison = d->comparison;
23844 if (VECTOR_MODE_P (mode0))
23845 op0 = safe_vector_operand (op0, mode0);
23846 if (VECTOR_MODE_P (mode1))
23847 op1 = safe_vector_operand (op1, mode1);
23849 /* Swap operands if we have a comparison that isn't available in
23853 rtx tmp = gen_reg_rtx (mode1);
23854 emit_move_insn (tmp, op1);
23859 if (optimize || !target
23860 || GET_MODE (target) != tmode
23861 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode))
23862 target = gen_reg_rtx (tmode);
23864 if ((optimize && !register_operand (op0, mode0))
23865 || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0))
23866 op0 = copy_to_mode_reg (mode0, op0);
23867 if ((optimize && !register_operand (op1, mode1))
23868 || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1))
23869 op1 = copy_to_mode_reg (mode1, op1);
23871 op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1);
23872 pat = GEN_FCN (d->icode) (target, op0, op1, op2);
23879 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
23882 ix86_expand_sse_comi (const struct builtin_description *d, tree exp,
23886 tree arg0 = CALL_EXPR_ARG (exp, 0);
23887 tree arg1 = CALL_EXPR_ARG (exp, 1);
23888 rtx op0 = expand_normal (arg0);
23889 rtx op1 = expand_normal (arg1);
23890 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23891 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23892 enum rtx_code comparison = d->comparison;
23894 if (VECTOR_MODE_P (mode0))
23895 op0 = safe_vector_operand (op0, mode0);
23896 if (VECTOR_MODE_P (mode1))
23897 op1 = safe_vector_operand (op1, mode1);
23899 /* Swap operands if we have a comparison that isn't available in
23901 if (d->flag & BUILTIN_DESC_SWAP_OPERANDS)
23908 target = gen_reg_rtx (SImode);
23909 emit_move_insn (target, const0_rtx);
23910 target = gen_rtx_SUBREG (QImode, target, 0);
23912 if ((optimize && !register_operand (op0, mode0))
23913 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23914 op0 = copy_to_mode_reg (mode0, op0);
23915 if ((optimize && !register_operand (op1, mode1))
23916 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23917 op1 = copy_to_mode_reg (mode1, op1);
23919 pat = GEN_FCN (d->icode) (op0, op1);
23923 emit_insn (gen_rtx_SET (VOIDmode,
23924 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23925 gen_rtx_fmt_ee (comparison, QImode,
23929 return SUBREG_REG (target);
23932 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
23935 ix86_expand_sse_ptest (const struct builtin_description *d, tree exp,
23939 tree arg0 = CALL_EXPR_ARG (exp, 0);
23940 tree arg1 = CALL_EXPR_ARG (exp, 1);
23941 rtx op0 = expand_normal (arg0);
23942 rtx op1 = expand_normal (arg1);
23943 enum machine_mode mode0 = insn_data[d->icode].operand[0].mode;
23944 enum machine_mode mode1 = insn_data[d->icode].operand[1].mode;
23945 enum rtx_code comparison = d->comparison;
23947 if (VECTOR_MODE_P (mode0))
23948 op0 = safe_vector_operand (op0, mode0);
23949 if (VECTOR_MODE_P (mode1))
23950 op1 = safe_vector_operand (op1, mode1);
23952 target = gen_reg_rtx (SImode);
23953 emit_move_insn (target, const0_rtx);
23954 target = gen_rtx_SUBREG (QImode, target, 0);
23956 if ((optimize && !register_operand (op0, mode0))
23957 || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0))
23958 op0 = copy_to_mode_reg (mode0, op0);
23959 if ((optimize && !register_operand (op1, mode1))
23960 || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1))
23961 op1 = copy_to_mode_reg (mode1, op1);
23963 pat = GEN_FCN (d->icode) (op0, op1);
23967 emit_insn (gen_rtx_SET (VOIDmode,
23968 gen_rtx_STRICT_LOW_PART (VOIDmode, target),
23969 gen_rtx_fmt_ee (comparison, QImode,
23973 return SUBREG_REG (target);
23976 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
23979 ix86_expand_sse_pcmpestr (const struct builtin_description *d,
23980 tree exp, rtx target)
23983 tree arg0 = CALL_EXPR_ARG (exp, 0);
23984 tree arg1 = CALL_EXPR_ARG (exp, 1);
23985 tree arg2 = CALL_EXPR_ARG (exp, 2);
23986 tree arg3 = CALL_EXPR_ARG (exp, 3);
23987 tree arg4 = CALL_EXPR_ARG (exp, 4);
23988 rtx scratch0, scratch1;
23989 rtx op0 = expand_normal (arg0);
23990 rtx op1 = expand_normal (arg1);
23991 rtx op2 = expand_normal (arg2);
23992 rtx op3 = expand_normal (arg3);
23993 rtx op4 = expand_normal (arg4);
23994 enum machine_mode tmode0, tmode1, modev2, modei3, modev4, modei5, modeimm;
23996 tmode0 = insn_data[d->icode].operand[0].mode;
23997 tmode1 = insn_data[d->icode].operand[1].mode;
23998 modev2 = insn_data[d->icode].operand[2].mode;
23999 modei3 = insn_data[d->icode].operand[3].mode;
24000 modev4 = insn_data[d->icode].operand[4].mode;
24001 modei5 = insn_data[d->icode].operand[5].mode;
24002 modeimm = insn_data[d->icode].operand[6].mode;
24004 if (VECTOR_MODE_P (modev2))
24005 op0 = safe_vector_operand (op0, modev2);
24006 if (VECTOR_MODE_P (modev4))
24007 op2 = safe_vector_operand (op2, modev4);
24009 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24010 op0 = copy_to_mode_reg (modev2, op0);
24011 if (! (*insn_data[d->icode].operand[3].predicate) (op1, modei3))
24012 op1 = copy_to_mode_reg (modei3, op1);
24013 if ((optimize && !register_operand (op2, modev4))
24014 || !(*insn_data[d->icode].operand[4].predicate) (op2, modev4))
24015 op2 = copy_to_mode_reg (modev4, op2);
24016 if (! (*insn_data[d->icode].operand[5].predicate) (op3, modei5))
24017 op3 = copy_to_mode_reg (modei5, op3);
24019 if (! (*insn_data[d->icode].operand[6].predicate) (op4, modeimm))
24021 error ("the fifth argument must be a 8-bit immediate");
24025 if (d->code == IX86_BUILTIN_PCMPESTRI128)
24027 if (optimize || !target
24028 || GET_MODE (target) != tmode0
24029 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24030 target = gen_reg_rtx (tmode0);
24032 scratch1 = gen_reg_rtx (tmode1);
24034 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2, op3, op4);
24036 else if (d->code == IX86_BUILTIN_PCMPESTRM128)
24038 if (optimize || !target
24039 || GET_MODE (target) != tmode1
24040 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24041 target = gen_reg_rtx (tmode1);
24043 scratch0 = gen_reg_rtx (tmode0);
24045 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2, op3, op4);
24049 gcc_assert (d->flag);
24051 scratch0 = gen_reg_rtx (tmode0);
24052 scratch1 = gen_reg_rtx (tmode1);
24054 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2, op3, op4);
24064 target = gen_reg_rtx (SImode);
24065 emit_move_insn (target, const0_rtx);
24066 target = gen_rtx_SUBREG (QImode, target, 0);
24069 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24070 gen_rtx_fmt_ee (EQ, QImode,
24071 gen_rtx_REG ((enum machine_mode) d->flag,
24074 return SUBREG_REG (target);
24081 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
24084 ix86_expand_sse_pcmpistr (const struct builtin_description *d,
24085 tree exp, rtx target)
24088 tree arg0 = CALL_EXPR_ARG (exp, 0);
24089 tree arg1 = CALL_EXPR_ARG (exp, 1);
24090 tree arg2 = CALL_EXPR_ARG (exp, 2);
24091 rtx scratch0, scratch1;
24092 rtx op0 = expand_normal (arg0);
24093 rtx op1 = expand_normal (arg1);
24094 rtx op2 = expand_normal (arg2);
24095 enum machine_mode tmode0, tmode1, modev2, modev3, modeimm;
24097 tmode0 = insn_data[d->icode].operand[0].mode;
24098 tmode1 = insn_data[d->icode].operand[1].mode;
24099 modev2 = insn_data[d->icode].operand[2].mode;
24100 modev3 = insn_data[d->icode].operand[3].mode;
24101 modeimm = insn_data[d->icode].operand[4].mode;
24103 if (VECTOR_MODE_P (modev2))
24104 op0 = safe_vector_operand (op0, modev2);
24105 if (VECTOR_MODE_P (modev3))
24106 op1 = safe_vector_operand (op1, modev3);
24108 if (! (*insn_data[d->icode].operand[2].predicate) (op0, modev2))
24109 op0 = copy_to_mode_reg (modev2, op0);
24110 if ((optimize && !register_operand (op1, modev3))
24111 || !(*insn_data[d->icode].operand[3].predicate) (op1, modev3))
24112 op1 = copy_to_mode_reg (modev3, op1);
24114 if (! (*insn_data[d->icode].operand[4].predicate) (op2, modeimm))
24116 error ("the third argument must be a 8-bit immediate");
24120 if (d->code == IX86_BUILTIN_PCMPISTRI128)
24122 if (optimize || !target
24123 || GET_MODE (target) != tmode0
24124 || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode0))
24125 target = gen_reg_rtx (tmode0);
24127 scratch1 = gen_reg_rtx (tmode1);
24129 pat = GEN_FCN (d->icode) (target, scratch1, op0, op1, op2);
24131 else if (d->code == IX86_BUILTIN_PCMPISTRM128)
24133 if (optimize || !target
24134 || GET_MODE (target) != tmode1
24135 || ! (*insn_data[d->icode].operand[1].predicate) (target, tmode1))
24136 target = gen_reg_rtx (tmode1);
24138 scratch0 = gen_reg_rtx (tmode0);
24140 pat = GEN_FCN (d->icode) (scratch0, target, op0, op1, op2);
24144 gcc_assert (d->flag);
24146 scratch0 = gen_reg_rtx (tmode0);
24147 scratch1 = gen_reg_rtx (tmode1);
24149 pat = GEN_FCN (d->icode) (scratch0, scratch1, op0, op1, op2);
24159 target = gen_reg_rtx (SImode);
24160 emit_move_insn (target, const0_rtx);
24161 target = gen_rtx_SUBREG (QImode, target, 0);
24164 (gen_rtx_SET (VOIDmode, gen_rtx_STRICT_LOW_PART (VOIDmode, target),
24165 gen_rtx_fmt_ee (EQ, QImode,
24166 gen_rtx_REG ((enum machine_mode) d->flag,
24169 return SUBREG_REG (target);
24175 /* Subroutine of ix86_expand_builtin to take care of insns with
24176 variable number of operands. */
24179 ix86_expand_args_builtin (const struct builtin_description *d,
24180 tree exp, rtx target)
24182 rtx pat, real_target;
24183 unsigned int i, nargs;
24184 unsigned int nargs_constant = 0;
24185 int num_memory = 0;
24189 enum machine_mode mode;
24191 bool last_arg_count = false;
24192 enum insn_code icode = d->icode;
24193 const struct insn_data *insn_p = &insn_data[icode];
24194 enum machine_mode tmode = insn_p->operand[0].mode;
24195 enum machine_mode rmode = VOIDmode;
24197 enum rtx_code comparison = d->comparison;
24199 switch ((enum ix86_builtin_type) d->flag)
24201 case INT_FTYPE_V8SF_V8SF_PTEST:
24202 case INT_FTYPE_V4DI_V4DI_PTEST:
24203 case INT_FTYPE_V4DF_V4DF_PTEST:
24204 case INT_FTYPE_V4SF_V4SF_PTEST:
24205 case INT_FTYPE_V2DI_V2DI_PTEST:
24206 case INT_FTYPE_V2DF_V2DF_PTEST:
24207 return ix86_expand_sse_ptest (d, exp, target);
24208 case FLOAT128_FTYPE_FLOAT128:
24209 case FLOAT_FTYPE_FLOAT:
24210 case INT64_FTYPE_V4SF:
24211 case INT64_FTYPE_V2DF:
24212 case INT_FTYPE_V16QI:
24213 case INT_FTYPE_V8QI:
24214 case INT_FTYPE_V8SF:
24215 case INT_FTYPE_V4DF:
24216 case INT_FTYPE_V4SF:
24217 case INT_FTYPE_V2DF:
24218 case V16QI_FTYPE_V16QI:
24219 case V8SI_FTYPE_V8SF:
24220 case V8SI_FTYPE_V4SI:
24221 case V8HI_FTYPE_V8HI:
24222 case V8HI_FTYPE_V16QI:
24223 case V8QI_FTYPE_V8QI:
24224 case V8SF_FTYPE_V8SF:
24225 case V8SF_FTYPE_V8SI:
24226 case V8SF_FTYPE_V4SF:
24227 case V4SI_FTYPE_V4SI:
24228 case V4SI_FTYPE_V16QI:
24229 case V4SI_FTYPE_V4SF:
24230 case V4SI_FTYPE_V8SI:
24231 case V4SI_FTYPE_V8HI:
24232 case V4SI_FTYPE_V4DF:
24233 case V4SI_FTYPE_V2DF:
24234 case V4HI_FTYPE_V4HI:
24235 case V4DF_FTYPE_V4DF:
24236 case V4DF_FTYPE_V4SI:
24237 case V4DF_FTYPE_V4SF:
24238 case V4DF_FTYPE_V2DF:
24239 case V4SF_FTYPE_V4SF:
24240 case V4SF_FTYPE_V4SI:
24241 case V4SF_FTYPE_V8SF:
24242 case V4SF_FTYPE_V4DF:
24243 case V4SF_FTYPE_V2DF:
24244 case V2DI_FTYPE_V2DI:
24245 case V2DI_FTYPE_V16QI:
24246 case V2DI_FTYPE_V8HI:
24247 case V2DI_FTYPE_V4SI:
24248 case V2DF_FTYPE_V2DF:
24249 case V2DF_FTYPE_V4SI:
24250 case V2DF_FTYPE_V4DF:
24251 case V2DF_FTYPE_V4SF:
24252 case V2DF_FTYPE_V2SI:
24253 case V2SI_FTYPE_V2SI:
24254 case V2SI_FTYPE_V4SF:
24255 case V2SI_FTYPE_V2SF:
24256 case V2SI_FTYPE_V2DF:
24257 case V2SF_FTYPE_V2SF:
24258 case V2SF_FTYPE_V2SI:
24261 case V4SF_FTYPE_V4SF_VEC_MERGE:
24262 case V2DF_FTYPE_V2DF_VEC_MERGE:
24263 return ix86_expand_unop_vec_merge_builtin (icode, exp, target);
24264 case FLOAT128_FTYPE_FLOAT128_FLOAT128:
24265 case V16QI_FTYPE_V16QI_V16QI:
24266 case V16QI_FTYPE_V8HI_V8HI:
24267 case V8QI_FTYPE_V8QI_V8QI:
24268 case V8QI_FTYPE_V4HI_V4HI:
24269 case V8HI_FTYPE_V8HI_V8HI:
24270 case V8HI_FTYPE_V16QI_V16QI:
24271 case V8HI_FTYPE_V4SI_V4SI:
24272 case V8SF_FTYPE_V8SF_V8SF:
24273 case V8SF_FTYPE_V8SF_V8SI:
24274 case V4SI_FTYPE_V4SI_V4SI:
24275 case V4SI_FTYPE_V8HI_V8HI:
24276 case V4SI_FTYPE_V4SF_V4SF:
24277 case V4SI_FTYPE_V2DF_V2DF:
24278 case V4HI_FTYPE_V4HI_V4HI:
24279 case V4HI_FTYPE_V8QI_V8QI:
24280 case V4HI_FTYPE_V2SI_V2SI:
24281 case V4DF_FTYPE_V4DF_V4DF:
24282 case V4DF_FTYPE_V4DF_V4DI:
24283 case V4SF_FTYPE_V4SF_V4SF:
24284 case V4SF_FTYPE_V4SF_V4SI:
24285 case V4SF_FTYPE_V4SF_V2SI:
24286 case V4SF_FTYPE_V4SF_V2DF:
24287 case V4SF_FTYPE_V4SF_DI:
24288 case V4SF_FTYPE_V4SF_SI:
24289 case V2DI_FTYPE_V2DI_V2DI:
24290 case V2DI_FTYPE_V16QI_V16QI:
24291 case V2DI_FTYPE_V4SI_V4SI:
24292 case V2DI_FTYPE_V2DI_V16QI:
24293 case V2DI_FTYPE_V2DF_V2DF:
24294 case V2SI_FTYPE_V2SI_V2SI:
24295 case V2SI_FTYPE_V4HI_V4HI:
24296 case V2SI_FTYPE_V2SF_V2SF:
24297 case V2DF_FTYPE_V2DF_V2DF:
24298 case V2DF_FTYPE_V2DF_V4SF:
24299 case V2DF_FTYPE_V2DF_V2DI:
24300 case V2DF_FTYPE_V2DF_DI:
24301 case V2DF_FTYPE_V2DF_SI:
24302 case V2SF_FTYPE_V2SF_V2SF:
24303 case V1DI_FTYPE_V1DI_V1DI:
24304 case V1DI_FTYPE_V8QI_V8QI:
24305 case V1DI_FTYPE_V2SI_V2SI:
24306 if (comparison == UNKNOWN)
24307 return ix86_expand_binop_builtin (icode, exp, target);
24310 case V4SF_FTYPE_V4SF_V4SF_SWAP:
24311 case V2DF_FTYPE_V2DF_V2DF_SWAP:
24312 gcc_assert (comparison != UNKNOWN);
24316 case V8HI_FTYPE_V8HI_V8HI_COUNT:
24317 case V8HI_FTYPE_V8HI_SI_COUNT:
24318 case V4SI_FTYPE_V4SI_V4SI_COUNT:
24319 case V4SI_FTYPE_V4SI_SI_COUNT:
24320 case V4HI_FTYPE_V4HI_V4HI_COUNT:
24321 case V4HI_FTYPE_V4HI_SI_COUNT:
24322 case V2DI_FTYPE_V2DI_V2DI_COUNT:
24323 case V2DI_FTYPE_V2DI_SI_COUNT:
24324 case V2SI_FTYPE_V2SI_V2SI_COUNT:
24325 case V2SI_FTYPE_V2SI_SI_COUNT:
24326 case V1DI_FTYPE_V1DI_V1DI_COUNT:
24327 case V1DI_FTYPE_V1DI_SI_COUNT:
24329 last_arg_count = true;
24331 case UINT64_FTYPE_UINT64_UINT64:
24332 case UINT_FTYPE_UINT_UINT:
24333 case UINT_FTYPE_UINT_USHORT:
24334 case UINT_FTYPE_UINT_UCHAR:
24337 case V2DI2TI_FTYPE_V2DI_INT:
24340 nargs_constant = 1;
24342 case V8HI_FTYPE_V8HI_INT:
24343 case V8SF_FTYPE_V8SF_INT:
24344 case V4SI_FTYPE_V4SI_INT:
24345 case V4SI_FTYPE_V8SI_INT:
24346 case V4HI_FTYPE_V4HI_INT:
24347 case V4DF_FTYPE_V4DF_INT:
24348 case V4SF_FTYPE_V4SF_INT:
24349 case V4SF_FTYPE_V8SF_INT:
24350 case V2DI_FTYPE_V2DI_INT:
24351 case V2DF_FTYPE_V2DF_INT:
24352 case V2DF_FTYPE_V4DF_INT:
24354 nargs_constant = 1;
24356 case V16QI_FTYPE_V16QI_V16QI_V16QI:
24357 case V8SF_FTYPE_V8SF_V8SF_V8SF:
24358 case V4DF_FTYPE_V4DF_V4DF_V4DF:
24359 case V4SF_FTYPE_V4SF_V4SF_V4SF:
24360 case V2DF_FTYPE_V2DF_V2DF_V2DF:
24363 case V16QI_FTYPE_V16QI_V16QI_INT:
24364 case V8HI_FTYPE_V8HI_V8HI_INT:
24365 case V8SI_FTYPE_V8SI_V8SI_INT:
24366 case V8SI_FTYPE_V8SI_V4SI_INT:
24367 case V8SF_FTYPE_V8SF_V8SF_INT:
24368 case V8SF_FTYPE_V8SF_V4SF_INT:
24369 case V4SI_FTYPE_V4SI_V4SI_INT:
24370 case V4DF_FTYPE_V4DF_V4DF_INT:
24371 case V4DF_FTYPE_V4DF_V2DF_INT:
24372 case V4SF_FTYPE_V4SF_V4SF_INT:
24373 case V2DI_FTYPE_V2DI_V2DI_INT:
24374 case V2DF_FTYPE_V2DF_V2DF_INT:
24376 nargs_constant = 1;
24378 case V2DI2TI_FTYPE_V2DI_V2DI_INT:
24381 nargs_constant = 1;
24383 case V1DI2DI_FTYPE_V1DI_V1DI_INT:
24386 nargs_constant = 1;
24388 case V2DI_FTYPE_V2DI_UINT_UINT:
24390 nargs_constant = 2;
24392 case V2DI_FTYPE_V2DI_V2DI_UINT_UINT:
24394 nargs_constant = 2;
24397 gcc_unreachable ();
24400 gcc_assert (nargs <= ARRAY_SIZE (args));
24402 if (comparison != UNKNOWN)
24404 gcc_assert (nargs == 2);
24405 return ix86_expand_sse_compare (d, exp, target, swap);
24408 if (rmode == VOIDmode || rmode == tmode)
24412 || GET_MODE (target) != tmode
24413 || ! (*insn_p->operand[0].predicate) (target, tmode))
24414 target = gen_reg_rtx (tmode);
24415 real_target = target;
24419 target = gen_reg_rtx (rmode);
24420 real_target = simplify_gen_subreg (tmode, target, rmode, 0);
24423 for (i = 0; i < nargs; i++)
24425 tree arg = CALL_EXPR_ARG (exp, i);
24426 rtx op = expand_normal (arg);
24427 enum machine_mode mode = insn_p->operand[i + 1].mode;
24428 bool match = (*insn_p->operand[i + 1].predicate) (op, mode);
24430 if (last_arg_count && (i + 1) == nargs)
24432 /* SIMD shift insns take either an 8-bit immediate or
24433 register as count. But builtin functions take int as
24434 count. If count doesn't match, we put it in register. */
24437 op = simplify_gen_subreg (SImode, op, GET_MODE (op), 0);
24438 if (!(*insn_p->operand[i + 1].predicate) (op, mode))
24439 op = copy_to_reg (op);
24442 else if ((nargs - i) <= nargs_constant)
24447 case CODE_FOR_sse4_1_roundpd:
24448 case CODE_FOR_sse4_1_roundps:
24449 case CODE_FOR_sse4_1_roundsd:
24450 case CODE_FOR_sse4_1_roundss:
24451 case CODE_FOR_sse4_1_blendps:
24452 case CODE_FOR_avx_blendpd256:
24453 case CODE_FOR_avx_vpermilv4df:
24454 case CODE_FOR_avx_roundpd256:
24455 case CODE_FOR_avx_roundps256:
24456 error ("the last argument must be a 4-bit immediate");
24459 case CODE_FOR_sse4_1_blendpd:
24460 case CODE_FOR_avx_vpermilv2df:
24461 error ("the last argument must be a 2-bit immediate");
24464 case CODE_FOR_avx_vextractf128v4df:
24465 case CODE_FOR_avx_vextractf128v8sf:
24466 case CODE_FOR_avx_vextractf128v8si:
24467 case CODE_FOR_avx_vinsertf128v4df:
24468 case CODE_FOR_avx_vinsertf128v8sf:
24469 case CODE_FOR_avx_vinsertf128v8si:
24470 error ("the last argument must be a 1-bit immediate");
24473 case CODE_FOR_avx_cmpsdv2df3:
24474 case CODE_FOR_avx_cmpssv4sf3:
24475 case CODE_FOR_avx_cmppdv2df3:
24476 case CODE_FOR_avx_cmppsv4sf3:
24477 case CODE_FOR_avx_cmppdv4df3:
24478 case CODE_FOR_avx_cmppsv8sf3:
24479 error ("the last argument must be a 5-bit immediate");
24483 switch (nargs_constant)
24486 if ((nargs - i) == nargs_constant)
24488 error ("the next to last argument must be an 8-bit immediate");
24492 error ("the last argument must be an 8-bit immediate");
24495 gcc_unreachable ();
24502 if (VECTOR_MODE_P (mode))
24503 op = safe_vector_operand (op, mode);
24505 /* If we aren't optimizing, only allow one memory operand to
24507 if (memory_operand (op, mode))
24510 if (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
24512 if (optimize || !match || num_memory > 1)
24513 op = copy_to_mode_reg (mode, op);
24517 op = copy_to_reg (op);
24518 op = simplify_gen_subreg (mode, op, GET_MODE (op), 0);
24523 args[i].mode = mode;
24529 pat = GEN_FCN (icode) (real_target, args[0].op);
24532 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op);
24535 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24539 pat = GEN_FCN (icode) (real_target, args[0].op, args[1].op,
24540 args[2].op, args[3].op);
24543 gcc_unreachable ();
24553 /* Subroutine of ix86_expand_builtin to take care of special insns
24554 with variable number of operands. */
24557 ix86_expand_special_args_builtin (const struct builtin_description *d,
24558 tree exp, rtx target)
24562 unsigned int i, nargs, arg_adjust, memory;
24566 enum machine_mode mode;
24568 enum insn_code icode = d->icode;
24569 bool last_arg_constant = false;
24570 const struct insn_data *insn_p = &insn_data[icode];
24571 enum machine_mode tmode = insn_p->operand[0].mode;
24572 enum { load, store } klass;
24574 switch ((enum ix86_special_builtin_type) d->flag)
24576 case VOID_FTYPE_VOID:
24577 emit_insn (GEN_FCN (icode) (target));
24579 case V2DI_FTYPE_PV2DI:
24580 case V32QI_FTYPE_PCCHAR:
24581 case V16QI_FTYPE_PCCHAR:
24582 case V8SF_FTYPE_PCV4SF:
24583 case V8SF_FTYPE_PCFLOAT:
24584 case V4SF_FTYPE_PCFLOAT:
24585 case V4DF_FTYPE_PCV2DF:
24586 case V4DF_FTYPE_PCDOUBLE:
24587 case V2DF_FTYPE_PCDOUBLE:
24592 case VOID_FTYPE_PV2SF_V4SF:
24593 case VOID_FTYPE_PV4DI_V4DI:
24594 case VOID_FTYPE_PV2DI_V2DI:
24595 case VOID_FTYPE_PCHAR_V32QI:
24596 case VOID_FTYPE_PCHAR_V16QI:
24597 case VOID_FTYPE_PFLOAT_V8SF:
24598 case VOID_FTYPE_PFLOAT_V4SF:
24599 case VOID_FTYPE_PDOUBLE_V4DF:
24600 case VOID_FTYPE_PDOUBLE_V2DF:
24601 case VOID_FTYPE_PDI_DI:
24602 case VOID_FTYPE_PINT_INT:
24605 /* Reserve memory operand for target. */
24606 memory = ARRAY_SIZE (args);
24608 case V4SF_FTYPE_V4SF_PCV2SF:
24609 case V2DF_FTYPE_V2DF_PCDOUBLE:
24614 case V8SF_FTYPE_PCV8SF_V8SF:
24615 case V4DF_FTYPE_PCV4DF_V4DF:
24616 case V4SF_FTYPE_PCV4SF_V4SF:
24617 case V2DF_FTYPE_PCV2DF_V2DF:
24622 case VOID_FTYPE_PV8SF_V8SF_V8SF:
24623 case VOID_FTYPE_PV4DF_V4DF_V4DF:
24624 case VOID_FTYPE_PV4SF_V4SF_V4SF:
24625 case VOID_FTYPE_PV2DF_V2DF_V2DF:
24628 /* Reserve memory operand for target. */
24629 memory = ARRAY_SIZE (args);
24632 gcc_unreachable ();
24635 gcc_assert (nargs <= ARRAY_SIZE (args));
24637 if (klass == store)
24639 arg = CALL_EXPR_ARG (exp, 0);
24640 op = expand_normal (arg);
24641 gcc_assert (target == 0);
24642 target = gen_rtx_MEM (tmode, copy_to_mode_reg (Pmode, op));
24650 || GET_MODE (target) != tmode
24651 || ! (*insn_p->operand[0].predicate) (target, tmode))
24652 target = gen_reg_rtx (tmode);
24655 for (i = 0; i < nargs; i++)
24657 enum machine_mode mode = insn_p->operand[i + 1].mode;
24660 arg = CALL_EXPR_ARG (exp, i + arg_adjust);
24661 op = expand_normal (arg);
24662 match = (*insn_p->operand[i + 1].predicate) (op, mode);
24664 if (last_arg_constant && (i + 1) == nargs)
24670 error ("the last argument must be an 8-bit immediate");
24678 /* This must be the memory operand. */
24679 op = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, op));
24680 gcc_assert (GET_MODE (op) == mode
24681 || GET_MODE (op) == VOIDmode);
24685 /* This must be register. */
24686 if (VECTOR_MODE_P (mode))
24687 op = safe_vector_operand (op, mode);
24689 gcc_assert (GET_MODE (op) == mode
24690 || GET_MODE (op) == VOIDmode);
24691 op = copy_to_mode_reg (mode, op);
24696 args[i].mode = mode;
24702 pat = GEN_FCN (icode) (target, args[0].op);
24705 pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
24708 gcc_unreachable ();
24714 return klass == store ? 0 : target;
24717 /* Return the integer constant in ARG. Constrain it to be in the range
24718 of the subparts of VEC_TYPE; issue an error if not. */
24721 get_element_number (tree vec_type, tree arg)
24723 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
24725 if (!host_integerp (arg, 1)
24726 || (elt = tree_low_cst (arg, 1), elt > max))
24728 error ("selector must be an integer constant in the range 0..%wi", max);
24735 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24736 ix86_expand_vector_init. We DO have language-level syntax for this, in
24737 the form of (type){ init-list }. Except that since we can't place emms
24738 instructions from inside the compiler, we can't allow the use of MMX
24739 registers unless the user explicitly asks for it. So we do *not* define
24740 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
24741 we have builtins invoked by mmintrin.h that gives us license to emit
24742 these sorts of instructions. */
24745 ix86_expand_vec_init_builtin (tree type, tree exp, rtx target)
24747 enum machine_mode tmode = TYPE_MODE (type);
24748 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
24749 int i, n_elt = GET_MODE_NUNITS (tmode);
24750 rtvec v = rtvec_alloc (n_elt);
24752 gcc_assert (VECTOR_MODE_P (tmode));
24753 gcc_assert (call_expr_nargs (exp) == n_elt);
24755 for (i = 0; i < n_elt; ++i)
24757 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
24758 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
24761 if (!target || !register_operand (target, tmode))
24762 target = gen_reg_rtx (tmode);
24764 ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v));
24768 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24769 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
24770 had a language-level syntax for referencing vector elements. */
24773 ix86_expand_vec_ext_builtin (tree exp, rtx target)
24775 enum machine_mode tmode, mode0;
24780 arg0 = CALL_EXPR_ARG (exp, 0);
24781 arg1 = CALL_EXPR_ARG (exp, 1);
24783 op0 = expand_normal (arg0);
24784 elt = get_element_number (TREE_TYPE (arg0), arg1);
24786 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24787 mode0 = TYPE_MODE (TREE_TYPE (arg0));
24788 gcc_assert (VECTOR_MODE_P (mode0));
24790 op0 = force_reg (mode0, op0);
24792 if (optimize || !target || !register_operand (target, tmode))
24793 target = gen_reg_rtx (tmode);
24795 ix86_expand_vector_extract (true, target, op0, elt);
24800 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
24801 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
24802 a language-level syntax for referencing vector elements. */
24805 ix86_expand_vec_set_builtin (tree exp)
24807 enum machine_mode tmode, mode1;
24808 tree arg0, arg1, arg2;
24810 rtx op0, op1, target;
24812 arg0 = CALL_EXPR_ARG (exp, 0);
24813 arg1 = CALL_EXPR_ARG (exp, 1);
24814 arg2 = CALL_EXPR_ARG (exp, 2);
24816 tmode = TYPE_MODE (TREE_TYPE (arg0));
24817 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
24818 gcc_assert (VECTOR_MODE_P (tmode));
24820 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
24821 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
24822 elt = get_element_number (TREE_TYPE (arg0), arg2);
24824 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
24825 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
24827 op0 = force_reg (tmode, op0);
24828 op1 = force_reg (mode1, op1);
24830 /* OP0 is the source of these builtin functions and shouldn't be
24831 modified. Create a copy, use it and return it as target. */
24832 target = gen_reg_rtx (tmode);
24833 emit_move_insn (target, op0);
24834 ix86_expand_vector_set (true, target, op1, elt);
24839 /* Expand an expression EXP that calls a built-in function,
24840 with result going to TARGET if that's convenient
24841 (and in mode MODE if that's convenient).
24842 SUBTARGET may be used as the target for computing one of EXP's operands.
24843 IGNORE is nonzero if the value is to be ignored. */
24846 ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
24847 enum machine_mode mode ATTRIBUTE_UNUSED,
24848 int ignore ATTRIBUTE_UNUSED)
24850 const struct builtin_description *d;
24852 enum insn_code icode;
24853 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
24854 tree arg0, arg1, arg2;
24855 rtx op0, op1, op2, pat;
24856 enum machine_mode mode0, mode1, mode2;
24857 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
24859 /* Determine whether the builtin function is available under the current ISA.
24860 Originally the builtin was not created if it wasn't applicable to the
24861 current ISA based on the command line switches. With function specific
24862 options, we need to check in the context of the function making the call
24863 whether it is supported. */
24864 if (ix86_builtins_isa[fcode].isa
24865 && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
24867 char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
24868 NULL, NULL, false);
24871 error ("%qE needs unknown isa option", fndecl);
24874 gcc_assert (opts != NULL);
24875 error ("%qE needs isa option %s", fndecl, opts);
24883 case IX86_BUILTIN_MASKMOVQ:
24884 case IX86_BUILTIN_MASKMOVDQU:
24885 icode = (fcode == IX86_BUILTIN_MASKMOVQ
24886 ? CODE_FOR_mmx_maskmovq
24887 : CODE_FOR_sse2_maskmovdqu);
24888 /* Note the arg order is different from the operand order. */
24889 arg1 = CALL_EXPR_ARG (exp, 0);
24890 arg2 = CALL_EXPR_ARG (exp, 1);
24891 arg0 = CALL_EXPR_ARG (exp, 2);
24892 op0 = expand_normal (arg0);
24893 op1 = expand_normal (arg1);
24894 op2 = expand_normal (arg2);
24895 mode0 = insn_data[icode].operand[0].mode;
24896 mode1 = insn_data[icode].operand[1].mode;
24897 mode2 = insn_data[icode].operand[2].mode;
24899 op0 = force_reg (Pmode, op0);
24900 op0 = gen_rtx_MEM (mode1, op0);
24902 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
24903 op0 = copy_to_mode_reg (mode0, op0);
24904 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
24905 op1 = copy_to_mode_reg (mode1, op1);
24906 if (! (*insn_data[icode].operand[2].predicate) (op2, mode2))
24907 op2 = copy_to_mode_reg (mode2, op2);
24908 pat = GEN_FCN (icode) (op0, op1, op2);
24914 case IX86_BUILTIN_LDMXCSR:
24915 op0 = expand_normal (CALL_EXPR_ARG (exp, 0));
24916 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24917 emit_move_insn (target, op0);
24918 emit_insn (gen_sse_ldmxcsr (target));
24921 case IX86_BUILTIN_STMXCSR:
24922 target = assign_386_stack_local (SImode, SLOT_VIRTUAL);
24923 emit_insn (gen_sse_stmxcsr (target));
24924 return copy_to_mode_reg (SImode, target);
24926 case IX86_BUILTIN_CLFLUSH:
24927 arg0 = CALL_EXPR_ARG (exp, 0);
24928 op0 = expand_normal (arg0);
24929 icode = CODE_FOR_sse2_clflush;
24930 if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode))
24931 op0 = copy_to_mode_reg (Pmode, op0);
24933 emit_insn (gen_sse2_clflush (op0));
24936 case IX86_BUILTIN_MONITOR:
24937 arg0 = CALL_EXPR_ARG (exp, 0);
24938 arg1 = CALL_EXPR_ARG (exp, 1);
24939 arg2 = CALL_EXPR_ARG (exp, 2);
24940 op0 = expand_normal (arg0);
24941 op1 = expand_normal (arg1);
24942 op2 = expand_normal (arg2);
24944 op0 = copy_to_mode_reg (Pmode, op0);
24946 op1 = copy_to_mode_reg (SImode, op1);
24948 op2 = copy_to_mode_reg (SImode, op2);
24949 emit_insn ((*ix86_gen_monitor) (op0, op1, op2));
24952 case IX86_BUILTIN_MWAIT:
24953 arg0 = CALL_EXPR_ARG (exp, 0);
24954 arg1 = CALL_EXPR_ARG (exp, 1);
24955 op0 = expand_normal (arg0);
24956 op1 = expand_normal (arg1);
24958 op0 = copy_to_mode_reg (SImode, op0);
24960 op1 = copy_to_mode_reg (SImode, op1);
24961 emit_insn (gen_sse3_mwait (op0, op1));
24964 case IX86_BUILTIN_VEC_INIT_V2SI:
24965 case IX86_BUILTIN_VEC_INIT_V4HI:
24966 case IX86_BUILTIN_VEC_INIT_V8QI:
24967 return ix86_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
24969 case IX86_BUILTIN_VEC_EXT_V2DF:
24970 case IX86_BUILTIN_VEC_EXT_V2DI:
24971 case IX86_BUILTIN_VEC_EXT_V4SF:
24972 case IX86_BUILTIN_VEC_EXT_V4SI:
24973 case IX86_BUILTIN_VEC_EXT_V8HI:
24974 case IX86_BUILTIN_VEC_EXT_V2SI:
24975 case IX86_BUILTIN_VEC_EXT_V4HI:
24976 case IX86_BUILTIN_VEC_EXT_V16QI:
24977 return ix86_expand_vec_ext_builtin (exp, target);
24979 case IX86_BUILTIN_VEC_SET_V2DI:
24980 case IX86_BUILTIN_VEC_SET_V4SF:
24981 case IX86_BUILTIN_VEC_SET_V4SI:
24982 case IX86_BUILTIN_VEC_SET_V8HI:
24983 case IX86_BUILTIN_VEC_SET_V4HI:
24984 case IX86_BUILTIN_VEC_SET_V16QI:
24985 return ix86_expand_vec_set_builtin (exp);
24987 case IX86_BUILTIN_INFQ:
24989 REAL_VALUE_TYPE inf;
24993 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, mode);
24995 tmp = validize_mem (force_const_mem (mode, tmp));
24998 target = gen_reg_rtx (mode);
25000 emit_move_insn (target, tmp);
25008 for (i = 0, d = bdesc_special_args;
25009 i < ARRAY_SIZE (bdesc_special_args);
25011 if (d->code == fcode)
25012 return ix86_expand_special_args_builtin (d, exp, target);
25014 for (i = 0, d = bdesc_args;
25015 i < ARRAY_SIZE (bdesc_args);
25017 if (d->code == fcode)
25020 case IX86_BUILTIN_FABSQ:
25021 case IX86_BUILTIN_COPYSIGNQ:
25023 /* Emit a normal call if SSE2 isn't available. */
25024 return expand_call (exp, target, ignore);
25026 return ix86_expand_args_builtin (d, exp, target);
25029 for (i = 0, d = bdesc_comi; i < ARRAY_SIZE (bdesc_comi); i++, d++)
25030 if (d->code == fcode)
25031 return ix86_expand_sse_comi (d, exp, target);
25033 for (i = 0, d = bdesc_pcmpestr;
25034 i < ARRAY_SIZE (bdesc_pcmpestr);
25036 if (d->code == fcode)
25037 return ix86_expand_sse_pcmpestr (d, exp, target);
25039 for (i = 0, d = bdesc_pcmpistr;
25040 i < ARRAY_SIZE (bdesc_pcmpistr);
25042 if (d->code == fcode)
25043 return ix86_expand_sse_pcmpistr (d, exp, target);
25045 for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
25046 if (d->code == fcode)
25047 return ix86_expand_multi_arg_builtin (d->icode, exp, target,
25048 (enum multi_arg_type)d->flag,
25051 gcc_unreachable ();
25054 /* Returns a function decl for a vectorized version of the builtin function
25055 with builtin function code FN and the result vector type TYPE, or NULL_TREE
25056 if it is not available. */
25059 ix86_builtin_vectorized_function (unsigned int fn, tree type_out,
25062 enum machine_mode in_mode, out_mode;
25065 if (TREE_CODE (type_out) != VECTOR_TYPE
25066 || TREE_CODE (type_in) != VECTOR_TYPE)
25069 out_mode = TYPE_MODE (TREE_TYPE (type_out));
25070 out_n = TYPE_VECTOR_SUBPARTS (type_out);
25071 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25072 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25076 case BUILT_IN_SQRT:
25077 if (out_mode == DFmode && out_n == 2
25078 && in_mode == DFmode && in_n == 2)
25079 return ix86_builtins[IX86_BUILTIN_SQRTPD];
25082 case BUILT_IN_SQRTF:
25083 if (out_mode == SFmode && out_n == 4
25084 && in_mode == SFmode && in_n == 4)
25085 return ix86_builtins[IX86_BUILTIN_SQRTPS_NR];
25088 case BUILT_IN_LRINT:
25089 if (out_mode == SImode && out_n == 4
25090 && in_mode == DFmode && in_n == 2)
25091 return ix86_builtins[IX86_BUILTIN_VEC_PACK_SFIX];
25094 case BUILT_IN_LRINTF:
25095 if (out_mode == SImode && out_n == 4
25096 && in_mode == SFmode && in_n == 4)
25097 return ix86_builtins[IX86_BUILTIN_CVTPS2DQ];
25104 /* Dispatch to a handler for a vectorization library. */
25105 if (ix86_veclib_handler)
25106 return (*ix86_veclib_handler)(fn, type_out, type_in);
25111 /* Handler for an SVML-style interface to
25112 a library with vectorized intrinsics. */
25115 ix86_veclibabi_svml (enum built_in_function fn, tree type_out, tree type_in)
25118 tree fntype, new_fndecl, args;
25121 enum machine_mode el_mode, in_mode;
25124 /* The SVML is suitable for unsafe math only. */
25125 if (!flag_unsafe_math_optimizations)
25128 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25129 n = TYPE_VECTOR_SUBPARTS (type_out);
25130 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25131 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25132 if (el_mode != in_mode
25140 case BUILT_IN_LOG10:
25142 case BUILT_IN_TANH:
25144 case BUILT_IN_ATAN:
25145 case BUILT_IN_ATAN2:
25146 case BUILT_IN_ATANH:
25147 case BUILT_IN_CBRT:
25148 case BUILT_IN_SINH:
25150 case BUILT_IN_ASINH:
25151 case BUILT_IN_ASIN:
25152 case BUILT_IN_COSH:
25154 case BUILT_IN_ACOSH:
25155 case BUILT_IN_ACOS:
25156 if (el_mode != DFmode || n != 2)
25160 case BUILT_IN_EXPF:
25161 case BUILT_IN_LOGF:
25162 case BUILT_IN_LOG10F:
25163 case BUILT_IN_POWF:
25164 case BUILT_IN_TANHF:
25165 case BUILT_IN_TANF:
25166 case BUILT_IN_ATANF:
25167 case BUILT_IN_ATAN2F:
25168 case BUILT_IN_ATANHF:
25169 case BUILT_IN_CBRTF:
25170 case BUILT_IN_SINHF:
25171 case BUILT_IN_SINF:
25172 case BUILT_IN_ASINHF:
25173 case BUILT_IN_ASINF:
25174 case BUILT_IN_COSHF:
25175 case BUILT_IN_COSF:
25176 case BUILT_IN_ACOSHF:
25177 case BUILT_IN_ACOSF:
25178 if (el_mode != SFmode || n != 4)
25186 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25188 if (fn == BUILT_IN_LOGF)
25189 strcpy (name, "vmlsLn4");
25190 else if (fn == BUILT_IN_LOG)
25191 strcpy (name, "vmldLn2");
25194 sprintf (name, "vmls%s", bname+10);
25195 name[strlen (name)-1] = '4';
25198 sprintf (name, "vmld%s2", bname+10);
25200 /* Convert to uppercase. */
25204 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25205 args = TREE_CHAIN (args))
25209 fntype = build_function_type_list (type_out, type_in, NULL);
25211 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25213 /* Build a function declaration for the vectorized function. */
25214 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25215 TREE_PUBLIC (new_fndecl) = 1;
25216 DECL_EXTERNAL (new_fndecl) = 1;
25217 DECL_IS_NOVOPS (new_fndecl) = 1;
25218 TREE_READONLY (new_fndecl) = 1;
25223 /* Handler for an ACML-style interface to
25224 a library with vectorized intrinsics. */
25227 ix86_veclibabi_acml (enum built_in_function fn, tree type_out, tree type_in)
25229 char name[20] = "__vr.._";
25230 tree fntype, new_fndecl, args;
25233 enum machine_mode el_mode, in_mode;
25236 /* The ACML is 64bits only and suitable for unsafe math only as
25237 it does not correctly support parts of IEEE with the required
25238 precision such as denormals. */
25240 || !flag_unsafe_math_optimizations)
25243 el_mode = TYPE_MODE (TREE_TYPE (type_out));
25244 n = TYPE_VECTOR_SUBPARTS (type_out);
25245 in_mode = TYPE_MODE (TREE_TYPE (type_in));
25246 in_n = TYPE_VECTOR_SUBPARTS (type_in);
25247 if (el_mode != in_mode
25257 case BUILT_IN_LOG2:
25258 case BUILT_IN_LOG10:
25261 if (el_mode != DFmode
25266 case BUILT_IN_SINF:
25267 case BUILT_IN_COSF:
25268 case BUILT_IN_EXPF:
25269 case BUILT_IN_POWF:
25270 case BUILT_IN_LOGF:
25271 case BUILT_IN_LOG2F:
25272 case BUILT_IN_LOG10F:
25275 if (el_mode != SFmode
25284 bname = IDENTIFIER_POINTER (DECL_NAME (implicit_built_in_decls[fn]));
25285 sprintf (name + 7, "%s", bname+10);
25288 for (args = DECL_ARGUMENTS (implicit_built_in_decls[fn]); args;
25289 args = TREE_CHAIN (args))
25293 fntype = build_function_type_list (type_out, type_in, NULL);
25295 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
25297 /* Build a function declaration for the vectorized function. */
25298 new_fndecl = build_decl (FUNCTION_DECL, get_identifier (name), fntype);
25299 TREE_PUBLIC (new_fndecl) = 1;
25300 DECL_EXTERNAL (new_fndecl) = 1;
25301 DECL_IS_NOVOPS (new_fndecl) = 1;
25302 TREE_READONLY (new_fndecl) = 1;
25308 /* Returns a decl of a function that implements conversion of an integer vector
25309 into a floating-point vector, or vice-versa. TYPE is the type of the integer
25310 side of the conversion.
25311 Return NULL_TREE if it is not available. */
25314 ix86_vectorize_builtin_conversion (unsigned int code, tree type)
25316 if (!TARGET_SSE2 || TREE_CODE (type) != VECTOR_TYPE
25317 /* There are only conversions from/to signed integers. */
25318 || TYPE_UNSIGNED (TREE_TYPE (type)))
25324 switch (TYPE_MODE (type))
25327 return ix86_builtins[IX86_BUILTIN_CVTDQ2PS];
25332 case FIX_TRUNC_EXPR:
25333 switch (TYPE_MODE (type))
25336 return ix86_builtins[IX86_BUILTIN_CVTTPS2DQ];
25346 /* Returns a code for a target-specific builtin that implements
25347 reciprocal of the function, or NULL_TREE if not available. */
25350 ix86_builtin_reciprocal (unsigned int fn, bool md_fn,
25351 bool sqrt ATTRIBUTE_UNUSED)
25353 if (! (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
25354 && flag_finite_math_only && !flag_trapping_math
25355 && flag_unsafe_math_optimizations))
25359 /* Machine dependent builtins. */
25362 /* Vectorized version of sqrt to rsqrt conversion. */
25363 case IX86_BUILTIN_SQRTPS_NR:
25364 return ix86_builtins[IX86_BUILTIN_RSQRTPS_NR];
25370 /* Normal builtins. */
25373 /* Sqrt to rsqrt conversion. */
25374 case BUILT_IN_SQRTF:
25375 return ix86_builtins[IX86_BUILTIN_RSQRTF];
25382 /* Store OPERAND to the memory after reload is completed. This means
25383 that we can't easily use assign_stack_local. */
25385 ix86_force_to_memory (enum machine_mode mode, rtx operand)
25389 gcc_assert (reload_completed);
25390 if (!TARGET_64BIT_MS_ABI && TARGET_RED_ZONE)
25392 result = gen_rtx_MEM (mode,
25393 gen_rtx_PLUS (Pmode,
25395 GEN_INT (-RED_ZONE_SIZE)));
25396 emit_move_insn (result, operand);
25398 else if ((TARGET_64BIT_MS_ABI || !TARGET_RED_ZONE) && TARGET_64BIT)
25404 operand = gen_lowpart (DImode, operand);
25408 gen_rtx_SET (VOIDmode,
25409 gen_rtx_MEM (DImode,
25410 gen_rtx_PRE_DEC (DImode,
25411 stack_pointer_rtx)),
25415 gcc_unreachable ();
25417 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25426 split_di (&operand, 1, operands, operands + 1);
25428 gen_rtx_SET (VOIDmode,
25429 gen_rtx_MEM (SImode,
25430 gen_rtx_PRE_DEC (Pmode,
25431 stack_pointer_rtx)),
25434 gen_rtx_SET (VOIDmode,
25435 gen_rtx_MEM (SImode,
25436 gen_rtx_PRE_DEC (Pmode,
25437 stack_pointer_rtx)),
25442 /* Store HImodes as SImodes. */
25443 operand = gen_lowpart (SImode, operand);
25447 gen_rtx_SET (VOIDmode,
25448 gen_rtx_MEM (GET_MODE (operand),
25449 gen_rtx_PRE_DEC (SImode,
25450 stack_pointer_rtx)),
25454 gcc_unreachable ();
25456 result = gen_rtx_MEM (mode, stack_pointer_rtx);
25461 /* Free operand from the memory. */
25463 ix86_free_from_memory (enum machine_mode mode)
25465 if (!TARGET_RED_ZONE || TARGET_64BIT_MS_ABI)
25469 if (mode == DImode || TARGET_64BIT)
25473 /* Use LEA to deallocate stack space. In peephole2 it will be converted
25474 to pop or add instruction if registers are available. */
25475 emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
25476 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25481 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
25482 QImode must go into class Q_REGS.
25483 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
25484 movdf to do mem-to-mem moves through integer regs. */
25486 ix86_preferred_reload_class (rtx x, enum reg_class regclass)
25488 enum machine_mode mode = GET_MODE (x);
25490 /* We're only allowed to return a subclass of CLASS. Many of the
25491 following checks fail for NO_REGS, so eliminate that early. */
25492 if (regclass == NO_REGS)
25495 /* All classes can load zeros. */
25496 if (x == CONST0_RTX (mode))
25499 /* Force constants into memory if we are loading a (nonzero) constant into
25500 an MMX or SSE register. This is because there are no MMX/SSE instructions
25501 to load from a constant. */
25503 && (MAYBE_MMX_CLASS_P (regclass) || MAYBE_SSE_CLASS_P (regclass)))
25506 /* Prefer SSE regs only, if we can use them for math. */
25507 if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode))
25508 return SSE_CLASS_P (regclass) ? regclass : NO_REGS;
25510 /* Floating-point constants need more complex checks. */
25511 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
25513 /* General regs can load everything. */
25514 if (reg_class_subset_p (regclass, GENERAL_REGS))
25517 /* Floats can load 0 and 1 plus some others. Note that we eliminated
25518 zero above. We only want to wind up preferring 80387 registers if
25519 we plan on doing computation with them. */
25521 && standard_80387_constant_p (x))
25523 /* Limit class to non-sse. */
25524 if (regclass == FLOAT_SSE_REGS)
25526 if (regclass == FP_TOP_SSE_REGS)
25528 if (regclass == FP_SECOND_SSE_REGS)
25529 return FP_SECOND_REG;
25530 if (regclass == FLOAT_INT_REGS || regclass == FLOAT_REGS)
25537 /* Generally when we see PLUS here, it's the function invariant
25538 (plus soft-fp const_int). Which can only be computed into general
25540 if (GET_CODE (x) == PLUS)
25541 return reg_class_subset_p (regclass, GENERAL_REGS) ? regclass : NO_REGS;
25543 /* QImode constants are easy to load, but non-constant QImode data
25544 must go into Q_REGS. */
25545 if (GET_MODE (x) == QImode && !CONSTANT_P (x))
25547 if (reg_class_subset_p (regclass, Q_REGS))
25549 if (reg_class_subset_p (Q_REGS, regclass))
25557 /* Discourage putting floating-point values in SSE registers unless
25558 SSE math is being used, and likewise for the 387 registers. */
25560 ix86_preferred_output_reload_class (rtx x, enum reg_class regclass)
25562 enum machine_mode mode = GET_MODE (x);
25564 /* Restrict the output reload class to the register bank that we are doing
25565 math on. If we would like not to return a subset of CLASS, reject this
25566 alternative: if reload cannot do this, it will still use its choice. */
25567 mode = GET_MODE (x);
25568 if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode))
25569 return MAYBE_SSE_CLASS_P (regclass) ? SSE_REGS : NO_REGS;
25571 if (X87_FLOAT_MODE_P (mode))
25573 if (regclass == FP_TOP_SSE_REGS)
25575 else if (regclass == FP_SECOND_SSE_REGS)
25576 return FP_SECOND_REG;
25578 return FLOAT_CLASS_P (regclass) ? regclass : NO_REGS;
25584 static enum reg_class
25585 ix86_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
25586 enum machine_mode mode,
25587 secondary_reload_info *sri ATTRIBUTE_UNUSED)
25589 /* QImode spills from non-QI registers require
25590 intermediate register on 32bit targets. */
25591 if (!in_p && mode == QImode && !TARGET_64BIT
25592 && (rclass == GENERAL_REGS
25593 || rclass == LEGACY_REGS
25594 || rclass == INDEX_REGS))
25603 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
25604 regno = true_regnum (x);
25606 /* Return Q_REGS if the operand is in memory. */
25614 /* If we are copying between general and FP registers, we need a memory
25615 location. The same is true for SSE and MMX registers.
25617 To optimize register_move_cost performance, allow inline variant.
25619 The macro can't work reliably when one of the CLASSES is class containing
25620 registers from multiple units (SSE, MMX, integer). We avoid this by never
25621 combining those units in single alternative in the machine description.
25622 Ensure that this constraint holds to avoid unexpected surprises.
25624 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
25625 enforce these sanity checks. */
25628 inline_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25629 enum machine_mode mode, int strict)
25631 if (MAYBE_FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class1)
25632 || MAYBE_FLOAT_CLASS_P (class2) != FLOAT_CLASS_P (class2)
25633 || MAYBE_SSE_CLASS_P (class1) != SSE_CLASS_P (class1)
25634 || MAYBE_SSE_CLASS_P (class2) != SSE_CLASS_P (class2)
25635 || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1)
25636 || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2))
25638 gcc_assert (!strict);
25642 if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2))
25645 /* ??? This is a lie. We do have moves between mmx/general, and for
25646 mmx/sse2. But by saying we need secondary memory we discourage the
25647 register allocator from using the mmx registers unless needed. */
25648 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2))
25651 if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25653 /* SSE1 doesn't have any direct moves from other classes. */
25657 /* If the target says that inter-unit moves are more expensive
25658 than moving through memory, then don't generate them. */
25659 if (!TARGET_INTER_UNIT_MOVES)
25662 /* Between SSE and general, we have moves no larger than word size. */
25663 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
25671 ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2,
25672 enum machine_mode mode, int strict)
25674 return inline_secondary_memory_needed (class1, class2, mode, strict);
25677 /* Return true if the registers in CLASS cannot represent the change from
25678 modes FROM to TO. */
25681 ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
25682 enum reg_class regclass)
25687 /* x87 registers can't do subreg at all, as all values are reformatted
25688 to extended precision. */
25689 if (MAYBE_FLOAT_CLASS_P (regclass))
25692 if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
25694 /* Vector registers do not support QI or HImode loads. If we don't
25695 disallow a change to these modes, reload will assume it's ok to
25696 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
25697 the vec_dupv4hi pattern. */
25698 if (GET_MODE_SIZE (from) < 4)
25701 /* Vector registers do not support subreg with nonzero offsets, which
25702 are otherwise valid for integer registers. Since we can't see
25703 whether we have a nonzero offset from here, prohibit all
25704 nonparadoxical subregs changing size. */
25705 if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
25712 /* Return the cost of moving data of mode M between a
25713 register and memory. A value of 2 is the default; this cost is
25714 relative to those in `REGISTER_MOVE_COST'.
25716 This function is used extensively by register_move_cost that is used to
25717 build tables at startup. Make it inline in this case.
25718 When IN is 2, return maximum of in and out move cost.
25720 If moving between registers and memory is more expensive than
25721 between two registers, you should define this macro to express the
25724 Model also increased moving costs of QImode registers in non
25728 inline_memory_move_cost (enum machine_mode mode, enum reg_class regclass,
25732 if (FLOAT_CLASS_P (regclass))
25750 return MAX (ix86_cost->fp_load [index], ix86_cost->fp_store [index]);
25751 return in ? ix86_cost->fp_load [index] : ix86_cost->fp_store [index];
25753 if (SSE_CLASS_P (regclass))
25756 switch (GET_MODE_SIZE (mode))
25771 return MAX (ix86_cost->sse_load [index], ix86_cost->sse_store [index]);
25772 return in ? ix86_cost->sse_load [index] : ix86_cost->sse_store [index];
25774 if (MMX_CLASS_P (regclass))
25777 switch (GET_MODE_SIZE (mode))
25789 return MAX (ix86_cost->mmx_load [index], ix86_cost->mmx_store [index]);
25790 return in ? ix86_cost->mmx_load [index] : ix86_cost->mmx_store [index];
25792 switch (GET_MODE_SIZE (mode))
25795 if (Q_CLASS_P (regclass) || TARGET_64BIT)
25798 return ix86_cost->int_store[0];
25799 if (TARGET_PARTIAL_REG_DEPENDENCY
25800 && optimize_function_for_speed_p (cfun))
25801 cost = ix86_cost->movzbl_load;
25803 cost = ix86_cost->int_load[0];
25805 return MAX (cost, ix86_cost->int_store[0]);
25811 return MAX (ix86_cost->movzbl_load, ix86_cost->int_store[0] + 4);
25813 return ix86_cost->movzbl_load;
25815 return ix86_cost->int_store[0] + 4;
25820 return MAX (ix86_cost->int_load[1], ix86_cost->int_store[1]);
25821 return in ? ix86_cost->int_load[1] : ix86_cost->int_store[1];
25823 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
25824 if (mode == TFmode)
25827 cost = MAX (ix86_cost->int_load[2] , ix86_cost->int_store[2]);
25829 cost = ix86_cost->int_load[2];
25831 cost = ix86_cost->int_store[2];
25832 return (cost * (((int) GET_MODE_SIZE (mode)
25833 + UNITS_PER_WORD - 1) / UNITS_PER_WORD));
25838 ix86_memory_move_cost (enum machine_mode mode, enum reg_class regclass, int in)
25840 return inline_memory_move_cost (mode, regclass, in);
25844 /* Return the cost of moving data from a register in class CLASS1 to
25845 one in class CLASS2.
25847 It is not required that the cost always equal 2 when FROM is the same as TO;
25848 on some machines it is expensive to move between registers if they are not
25849 general registers. */
25852 ix86_register_move_cost (enum machine_mode mode, enum reg_class class1,
25853 enum reg_class class2)
25855 /* In case we require secondary memory, compute cost of the store followed
25856 by load. In order to avoid bad register allocation choices, we need
25857 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
25859 if (inline_secondary_memory_needed (class1, class2, mode, 0))
25863 cost += inline_memory_move_cost (mode, class1, 2);
25864 cost += inline_memory_move_cost (mode, class2, 2);
25866 /* In case of copying from general_purpose_register we may emit multiple
25867 stores followed by single load causing memory size mismatch stall.
25868 Count this as arbitrarily high cost of 20. */
25869 if (CLASS_MAX_NREGS (class1, mode) > CLASS_MAX_NREGS (class2, mode))
25872 /* In the case of FP/MMX moves, the registers actually overlap, and we
25873 have to switch modes in order to treat them differently. */
25874 if ((MMX_CLASS_P (class1) && MAYBE_FLOAT_CLASS_P (class2))
25875 || (MMX_CLASS_P (class2) && MAYBE_FLOAT_CLASS_P (class1)))
25881 /* Moves between SSE/MMX and integer unit are expensive. */
25882 if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)
25883 || SSE_CLASS_P (class1) != SSE_CLASS_P (class2))
25885 /* ??? By keeping returned value relatively high, we limit the number
25886 of moves between integer and MMX/SSE registers for all targets.
25887 Additionally, high value prevents problem with x86_modes_tieable_p(),
25888 where integer modes in MMX/SSE registers are not tieable
25889 because of missing QImode and HImode moves to, from or between
25890 MMX/SSE registers. */
25891 return MAX (8, ix86_cost->mmxsse_to_integer);
25893 if (MAYBE_FLOAT_CLASS_P (class1))
25894 return ix86_cost->fp_move;
25895 if (MAYBE_SSE_CLASS_P (class1))
25896 return ix86_cost->sse_move;
25897 if (MAYBE_MMX_CLASS_P (class1))
25898 return ix86_cost->mmx_move;
25902 /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */
25905 ix86_hard_regno_mode_ok (int regno, enum machine_mode mode)
25907 /* Flags and only flags can only hold CCmode values. */
25908 if (CC_REGNO_P (regno))
25909 return GET_MODE_CLASS (mode) == MODE_CC;
25910 if (GET_MODE_CLASS (mode) == MODE_CC
25911 || GET_MODE_CLASS (mode) == MODE_RANDOM
25912 || GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
25914 if (FP_REGNO_P (regno))
25915 return VALID_FP_MODE_P (mode);
25916 if (SSE_REGNO_P (regno))
25918 /* We implement the move patterns for all vector modes into and
25919 out of SSE registers, even when no operation instructions
25920 are available. OImode move is available only when AVX is
25922 return ((TARGET_AVX && mode == OImode)
25923 || VALID_AVX256_REG_MODE (mode)
25924 || VALID_SSE_REG_MODE (mode)
25925 || VALID_SSE2_REG_MODE (mode)
25926 || VALID_MMX_REG_MODE (mode)
25927 || VALID_MMX_REG_MODE_3DNOW (mode));
25929 if (MMX_REGNO_P (regno))
25931 /* We implement the move patterns for 3DNOW modes even in MMX mode,
25932 so if the register is available at all, then we can move data of
25933 the given mode into or out of it. */
25934 return (VALID_MMX_REG_MODE (mode)
25935 || VALID_MMX_REG_MODE_3DNOW (mode));
25938 if (mode == QImode)
25940 /* Take care for QImode values - they can be in non-QI regs,
25941 but then they do cause partial register stalls. */
25942 if (regno <= BX_REG || TARGET_64BIT)
25944 if (!TARGET_PARTIAL_REG_STALL)
25946 return reload_in_progress || reload_completed;
25948 /* We handle both integer and floats in the general purpose registers. */
25949 else if (VALID_INT_MODE_P (mode))
25951 else if (VALID_FP_MODE_P (mode))
25953 else if (VALID_DFP_MODE_P (mode))
25955 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
25956 on to use that value in smaller contexts, this can easily force a
25957 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
25958 supporting DImode, allow it. */
25959 else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode))
25965 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
25966 tieable integer mode. */
25969 ix86_tieable_integer_mode_p (enum machine_mode mode)
25978 return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL;
25981 return TARGET_64BIT;
25988 /* Return true if MODE1 is accessible in a register that can hold MODE2
25989 without copying. That is, all register classes that can hold MODE2
25990 can also hold MODE1. */
25993 ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
25995 if (mode1 == mode2)
25998 if (ix86_tieable_integer_mode_p (mode1)
25999 && ix86_tieable_integer_mode_p (mode2))
26002 /* MODE2 being XFmode implies fp stack or general regs, which means we
26003 can tie any smaller floating point modes to it. Note that we do not
26004 tie this with TFmode. */
26005 if (mode2 == XFmode)
26006 return mode1 == SFmode || mode1 == DFmode;
26008 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
26009 that we can tie it with SFmode. */
26010 if (mode2 == DFmode)
26011 return mode1 == SFmode;
26013 /* If MODE2 is only appropriate for an SSE register, then tie with
26014 any other mode acceptable to SSE registers. */
26015 if (GET_MODE_SIZE (mode2) == 16
26016 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
26017 return (GET_MODE_SIZE (mode1) == 16
26018 && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
26020 /* If MODE2 is appropriate for an MMX register, then tie
26021 with any other mode acceptable to MMX registers. */
26022 if (GET_MODE_SIZE (mode2) == 8
26023 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2))
26024 return (GET_MODE_SIZE (mode1) == 8
26025 && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1));
26030 /* Compute a (partial) cost for rtx X. Return true if the complete
26031 cost has been computed, and false if subexpressions should be
26032 scanned. In either case, *TOTAL contains the cost result. */
26035 ix86_rtx_costs (rtx x, int code, int outer_code_i, int *total, bool speed)
26037 enum rtx_code outer_code = (enum rtx_code) outer_code_i;
26038 enum machine_mode mode = GET_MODE (x);
26039 const struct processor_costs *cost = speed ? ix86_cost : &ix86_size_cost;
26047 if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode))
26049 else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode))
26051 else if (flag_pic && SYMBOLIC_CONST (x)
26053 || (!GET_CODE (x) != LABEL_REF
26054 && (GET_CODE (x) != SYMBOL_REF
26055 || !SYMBOL_REF_LOCAL_P (x)))))
26062 if (mode == VOIDmode)
26065 switch (standard_80387_constant_p (x))
26070 default: /* Other constants */
26075 /* Start with (MEM (SYMBOL_REF)), since that's where
26076 it'll probably end up. Add a penalty for size. */
26077 *total = (COSTS_N_INSNS (1)
26078 + (flag_pic != 0 && !TARGET_64BIT)
26079 + (mode == SFmode ? 0 : mode == DFmode ? 1 : 2));
26085 /* The zero extensions is often completely free on x86_64, so make
26086 it as cheap as possible. */
26087 if (TARGET_64BIT && mode == DImode
26088 && GET_MODE (XEXP (x, 0)) == SImode)
26090 else if (TARGET_ZERO_EXTEND_WITH_AND)
26091 *total = cost->add;
26093 *total = cost->movzx;
26097 *total = cost->movsx;
26101 if (CONST_INT_P (XEXP (x, 1))
26102 && (GET_MODE (XEXP (x, 0)) != DImode || TARGET_64BIT))
26104 HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26107 *total = cost->add;
26110 if ((value == 2 || value == 3)
26111 && cost->lea <= cost->shift_const)
26113 *total = cost->lea;
26123 if (!TARGET_64BIT && GET_MODE (XEXP (x, 0)) == DImode)
26125 if (CONST_INT_P (XEXP (x, 1)))
26127 if (INTVAL (XEXP (x, 1)) > 32)
26128 *total = cost->shift_const + COSTS_N_INSNS (2);
26130 *total = cost->shift_const * 2;
26134 if (GET_CODE (XEXP (x, 1)) == AND)
26135 *total = cost->shift_var * 2;
26137 *total = cost->shift_var * 6 + COSTS_N_INSNS (2);
26142 if (CONST_INT_P (XEXP (x, 1)))
26143 *total = cost->shift_const;
26145 *total = cost->shift_var;
26150 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26152 /* ??? SSE scalar cost should be used here. */
26153 *total = cost->fmul;
26156 else if (X87_FLOAT_MODE_P (mode))
26158 *total = cost->fmul;
26161 else if (FLOAT_MODE_P (mode))
26163 /* ??? SSE vector cost should be used here. */
26164 *total = cost->fmul;
26169 rtx op0 = XEXP (x, 0);
26170 rtx op1 = XEXP (x, 1);
26172 if (CONST_INT_P (XEXP (x, 1)))
26174 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
26175 for (nbits = 0; value != 0; value &= value - 1)
26179 /* This is arbitrary. */
26182 /* Compute costs correctly for widening multiplication. */
26183 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
26184 && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2
26185 == GET_MODE_SIZE (mode))
26187 int is_mulwiden = 0;
26188 enum machine_mode inner_mode = GET_MODE (op0);
26190 if (GET_CODE (op0) == GET_CODE (op1))
26191 is_mulwiden = 1, op1 = XEXP (op1, 0);
26192 else if (CONST_INT_P (op1))
26194 if (GET_CODE (op0) == SIGN_EXTEND)
26195 is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode)
26198 is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode));
26202 op0 = XEXP (op0, 0), mode = GET_MODE (op0);
26205 *total = (cost->mult_init[MODE_INDEX (mode)]
26206 + nbits * cost->mult_bit
26207 + rtx_cost (op0, outer_code, speed) + rtx_cost (op1, outer_code, speed));
26216 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26217 /* ??? SSE cost should be used here. */
26218 *total = cost->fdiv;
26219 else if (X87_FLOAT_MODE_P (mode))
26220 *total = cost->fdiv;
26221 else if (FLOAT_MODE_P (mode))
26222 /* ??? SSE vector cost should be used here. */
26223 *total = cost->fdiv;
26225 *total = cost->divide[MODE_INDEX (mode)];
26229 if (GET_MODE_CLASS (mode) == MODE_INT
26230 && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode))
26232 if (GET_CODE (XEXP (x, 0)) == PLUS
26233 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
26234 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
26235 && CONSTANT_P (XEXP (x, 1)))
26237 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1));
26238 if (val == 2 || val == 4 || val == 8)
26240 *total = cost->lea;
26241 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26242 *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0),
26243 outer_code, speed);
26244 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26248 else if (GET_CODE (XEXP (x, 0)) == MULT
26249 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
26251 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1));
26252 if (val == 2 || val == 4 || val == 8)
26254 *total = cost->lea;
26255 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26256 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26260 else if (GET_CODE (XEXP (x, 0)) == PLUS)
26262 *total = cost->lea;
26263 *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed);
26264 *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code, speed);
26265 *total += rtx_cost (XEXP (x, 1), outer_code, speed);
26272 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26274 /* ??? SSE cost should be used here. */
26275 *total = cost->fadd;
26278 else if (X87_FLOAT_MODE_P (mode))
26280 *total = cost->fadd;
26283 else if (FLOAT_MODE_P (mode))
26285 /* ??? SSE vector cost should be used here. */
26286 *total = cost->fadd;
26294 if (!TARGET_64BIT && mode == DImode)
26296 *total = (cost->add * 2
26297 + (rtx_cost (XEXP (x, 0), outer_code, speed)
26298 << (GET_MODE (XEXP (x, 0)) != DImode))
26299 + (rtx_cost (XEXP (x, 1), outer_code, speed)
26300 << (GET_MODE (XEXP (x, 1)) != DImode)));
26306 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26308 /* ??? SSE cost should be used here. */
26309 *total = cost->fchs;
26312 else if (X87_FLOAT_MODE_P (mode))
26314 *total = cost->fchs;
26317 else if (FLOAT_MODE_P (mode))
26319 /* ??? SSE vector cost should be used here. */
26320 *total = cost->fchs;
26326 if (!TARGET_64BIT && mode == DImode)
26327 *total = cost->add * 2;
26329 *total = cost->add;
26333 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT
26334 && XEXP (XEXP (x, 0), 1) == const1_rtx
26335 && CONST_INT_P (XEXP (XEXP (x, 0), 2))
26336 && XEXP (x, 1) == const0_rtx)
26338 /* This kind of construct is implemented using test[bwl].
26339 Treat it as if we had an AND. */
26340 *total = (cost->add
26341 + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code, speed)
26342 + rtx_cost (const1_rtx, outer_code, speed));
26348 if (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))
26353 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26354 /* ??? SSE cost should be used here. */
26355 *total = cost->fabs;
26356 else if (X87_FLOAT_MODE_P (mode))
26357 *total = cost->fabs;
26358 else if (FLOAT_MODE_P (mode))
26359 /* ??? SSE vector cost should be used here. */
26360 *total = cost->fabs;
26364 if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH)
26365 /* ??? SSE cost should be used here. */
26366 *total = cost->fsqrt;
26367 else if (X87_FLOAT_MODE_P (mode))
26368 *total = cost->fsqrt;
26369 else if (FLOAT_MODE_P (mode))
26370 /* ??? SSE vector cost should be used here. */
26371 *total = cost->fsqrt;
26375 if (XINT (x, 1) == UNSPEC_TP)
26386 static int current_machopic_label_num;
26388 /* Given a symbol name and its associated stub, write out the
26389 definition of the stub. */
26392 machopic_output_stub (FILE *file, const char *symb, const char *stub)
26394 unsigned int length;
26395 char *binder_name, *symbol_name, lazy_ptr_name[32];
26396 int label = ++current_machopic_label_num;
26398 /* For 64-bit we shouldn't get here. */
26399 gcc_assert (!TARGET_64BIT);
26401 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
26402 symb = (*targetm.strip_name_encoding) (symb);
26404 length = strlen (stub);
26405 binder_name = XALLOCAVEC (char, length + 32);
26406 GEN_BINDER_NAME_FOR_STUB (binder_name, stub, length);
26408 length = strlen (symb);
26409 symbol_name = XALLOCAVEC (char, length + 32);
26410 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
26412 sprintf (lazy_ptr_name, "L%d$lz", label);
26415 switch_to_section (darwin_sections[machopic_picsymbol_stub_section]);
26417 switch_to_section (darwin_sections[machopic_symbol_stub_section]);
26419 fprintf (file, "%s:\n", stub);
26420 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26424 fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label);
26425 fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label);
26426 fprintf (file, "\tjmp\t*%%edx\n");
26429 fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name);
26431 fprintf (file, "%s:\n", binder_name);
26435 fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label);
26436 fprintf (file, "\tpushl\t%%eax\n");
26439 fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name);
26441 fprintf (file, "\tjmp\tdyld_stub_binding_helper\n");
26443 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
26444 fprintf (file, "%s:\n", lazy_ptr_name);
26445 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
26446 fprintf (file, "\t.long %s\n", binder_name);
26450 darwin_x86_file_end (void)
26452 darwin_file_end ();
26455 #endif /* TARGET_MACHO */
26457 /* Order the registers for register allocator. */
26460 x86_order_regs_for_local_alloc (void)
26465 /* First allocate the local general purpose registers. */
26466 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26467 if (GENERAL_REGNO_P (i) && call_used_regs[i])
26468 reg_alloc_order [pos++] = i;
26470 /* Global general purpose registers. */
26471 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
26472 if (GENERAL_REGNO_P (i) && !call_used_regs[i])
26473 reg_alloc_order [pos++] = i;
26475 /* x87 registers come first in case we are doing FP math
26477 if (!TARGET_SSE_MATH)
26478 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26479 reg_alloc_order [pos++] = i;
26481 /* SSE registers. */
26482 for (i = FIRST_SSE_REG; i <= LAST_SSE_REG; i++)
26483 reg_alloc_order [pos++] = i;
26484 for (i = FIRST_REX_SSE_REG; i <= LAST_REX_SSE_REG; i++)
26485 reg_alloc_order [pos++] = i;
26487 /* x87 registers. */
26488 if (TARGET_SSE_MATH)
26489 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++)
26490 reg_alloc_order [pos++] = i;
26492 for (i = FIRST_MMX_REG; i <= LAST_MMX_REG; i++)
26493 reg_alloc_order [pos++] = i;
26495 /* Initialize the rest of array as we do not allocate some registers
26497 while (pos < FIRST_PSEUDO_REGISTER)
26498 reg_alloc_order [pos++] = 0;
26501 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
26502 struct attribute_spec.handler. */
26504 ix86_handle_abi_attribute (tree *node, tree name,
26505 tree args ATTRIBUTE_UNUSED,
26506 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26508 if (TREE_CODE (*node) != FUNCTION_TYPE
26509 && TREE_CODE (*node) != METHOD_TYPE
26510 && TREE_CODE (*node) != FIELD_DECL
26511 && TREE_CODE (*node) != TYPE_DECL)
26513 warning (OPT_Wattributes, "%qs attribute only applies to functions",
26514 IDENTIFIER_POINTER (name));
26515 *no_add_attrs = true;
26520 warning (OPT_Wattributes, "%qs attribute only available for 64-bit",
26521 IDENTIFIER_POINTER (name));
26522 *no_add_attrs = true;
26526 /* Can combine regparm with all attributes but fastcall. */
26527 if (is_attribute_p ("ms_abi", name))
26529 if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (*node)))
26531 error ("ms_abi and sysv_abi attributes are not compatible");
26536 else if (is_attribute_p ("sysv_abi", name))
26538 if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (*node)))
26540 error ("ms_abi and sysv_abi attributes are not compatible");
26549 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
26550 struct attribute_spec.handler. */
26552 ix86_handle_struct_attribute (tree *node, tree name,
26553 tree args ATTRIBUTE_UNUSED,
26554 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
26557 if (DECL_P (*node))
26559 if (TREE_CODE (*node) == TYPE_DECL)
26560 type = &TREE_TYPE (*node);
26565 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
26566 || TREE_CODE (*type) == UNION_TYPE)))
26568 warning (OPT_Wattributes, "%qs attribute ignored",
26569 IDENTIFIER_POINTER (name));
26570 *no_add_attrs = true;
26573 else if ((is_attribute_p ("ms_struct", name)
26574 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
26575 || ((is_attribute_p ("gcc_struct", name)
26576 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
26578 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
26579 IDENTIFIER_POINTER (name));
26580 *no_add_attrs = true;
26587 ix86_ms_bitfield_layout_p (const_tree record_type)
26589 return (TARGET_MS_BITFIELD_LAYOUT &&
26590 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
26591 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
26594 /* Returns an expression indicating where the this parameter is
26595 located on entry to the FUNCTION. */
26598 x86_this_parameter (tree function)
26600 tree type = TREE_TYPE (function);
26601 bool aggr = aggregate_value_p (TREE_TYPE (type), type) != 0;
26606 const int *parm_regs;
26608 if (ix86_function_type_abi (type) == MS_ABI)
26609 parm_regs = x86_64_ms_abi_int_parameter_registers;
26611 parm_regs = x86_64_int_parameter_registers;
26612 return gen_rtx_REG (DImode, parm_regs[aggr]);
26615 nregs = ix86_function_regparm (type, function);
26617 if (nregs > 0 && !stdarg_p (type))
26621 if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
26622 regno = aggr ? DX_REG : CX_REG;
26630 return gen_rtx_MEM (SImode,
26631 plus_constant (stack_pointer_rtx, 4));
26634 return gen_rtx_REG (SImode, regno);
26637 return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, aggr ? 8 : 4));
26640 /* Determine whether x86_output_mi_thunk can succeed. */
26643 x86_can_output_mi_thunk (const_tree thunk ATTRIBUTE_UNUSED,
26644 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
26645 HOST_WIDE_INT vcall_offset, const_tree function)
26647 /* 64-bit can handle anything. */
26651 /* For 32-bit, everything's fine if we have one free register. */
26652 if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
26655 /* Need a free register for vcall_offset. */
26659 /* Need a free register for GOT references. */
26660 if (flag_pic && !(*targetm.binds_local_p) (function))
26663 /* Otherwise ok. */
26667 /* Output the assembler code for a thunk function. THUNK_DECL is the
26668 declaration for the thunk function itself, FUNCTION is the decl for
26669 the target function. DELTA is an immediate constant offset to be
26670 added to THIS. If VCALL_OFFSET is nonzero, the word at
26671 *(*this + vcall_offset) should be added to THIS. */
26674 x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
26675 tree thunk ATTRIBUTE_UNUSED, HOST_WIDE_INT delta,
26676 HOST_WIDE_INT vcall_offset, tree function)
26679 rtx this_param = x86_this_parameter (function);
26682 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
26683 pull it in now and let DELTA benefit. */
26684 if (REG_P (this_param))
26685 this_reg = this_param;
26686 else if (vcall_offset)
26688 /* Put the this parameter into %eax. */
26689 xops[0] = this_param;
26690 xops[1] = this_reg = gen_rtx_REG (Pmode, AX_REG);
26691 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26694 this_reg = NULL_RTX;
26696 /* Adjust the this parameter by a fixed constant. */
26699 xops[0] = GEN_INT (delta);
26700 xops[1] = this_reg ? this_reg : this_param;
26703 if (!x86_64_general_operand (xops[0], DImode))
26705 tmp = gen_rtx_REG (DImode, R10_REG);
26707 output_asm_insn ("mov{q}\t{%1, %0|%0, %1}", xops);
26709 xops[1] = this_param;
26711 output_asm_insn ("add{q}\t{%0, %1|%1, %0}", xops);
26714 output_asm_insn ("add{l}\t{%0, %1|%1, %0}", xops);
26717 /* Adjust the this parameter by a value stored in the vtable. */
26721 tmp = gen_rtx_REG (DImode, R10_REG);
26724 int tmp_regno = CX_REG;
26725 if (lookup_attribute ("fastcall",
26726 TYPE_ATTRIBUTES (TREE_TYPE (function))))
26727 tmp_regno = AX_REG;
26728 tmp = gen_rtx_REG (SImode, tmp_regno);
26731 xops[0] = gen_rtx_MEM (Pmode, this_reg);
26733 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26735 /* Adjust the this parameter. */
26736 xops[0] = gen_rtx_MEM (Pmode, plus_constant (tmp, vcall_offset));
26737 if (TARGET_64BIT && !memory_operand (xops[0], Pmode))
26739 rtx tmp2 = gen_rtx_REG (DImode, R11_REG);
26740 xops[0] = GEN_INT (vcall_offset);
26742 output_asm_insn ("mov{q}\t{%0, %1|%1, %0}", xops);
26743 xops[0] = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, tmp, tmp2));
26745 xops[1] = this_reg;
26746 output_asm_insn ("add%z1\t{%0, %1|%1, %0}", xops);
26749 /* If necessary, drop THIS back to its stack slot. */
26750 if (this_reg && this_reg != this_param)
26752 xops[0] = this_reg;
26753 xops[1] = this_param;
26754 output_asm_insn ("mov%z1\t{%0, %1|%1, %0}", xops);
26757 xops[0] = XEXP (DECL_RTL (function), 0);
26760 if (!flag_pic || (*targetm.binds_local_p) (function))
26761 output_asm_insn ("jmp\t%P0", xops);
26762 /* All thunks should be in the same object as their target,
26763 and thus binds_local_p should be true. */
26764 else if (TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
26765 gcc_unreachable ();
26768 tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xops[0]), UNSPEC_GOTPCREL);
26769 tmp = gen_rtx_CONST (Pmode, tmp);
26770 tmp = gen_rtx_MEM (QImode, tmp);
26772 output_asm_insn ("jmp\t%A0", xops);
26777 if (!flag_pic || (*targetm.binds_local_p) (function))
26778 output_asm_insn ("jmp\t%P0", xops);
26783 rtx sym_ref = XEXP (DECL_RTL (function), 0);
26784 tmp = (gen_rtx_SYMBOL_REF
26786 machopic_indirection_name (sym_ref, /*stub_p=*/true)));
26787 tmp = gen_rtx_MEM (QImode, tmp);
26789 output_asm_insn ("jmp\t%0", xops);
26792 #endif /* TARGET_MACHO */
26794 tmp = gen_rtx_REG (SImode, CX_REG);
26795 output_set_got (tmp, NULL_RTX);
26798 output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops);
26799 output_asm_insn ("jmp\t{*}%1", xops);
26805 x86_file_start (void)
26807 default_file_start ();
26809 darwin_file_start ();
26811 if (X86_FILE_START_VERSION_DIRECTIVE)
26812 fputs ("\t.version\t\"01.01\"\n", asm_out_file);
26813 if (X86_FILE_START_FLTUSED)
26814 fputs ("\t.global\t__fltused\n", asm_out_file);
26815 if (ix86_asm_dialect == ASM_INTEL)
26816 fputs ("\t.intel_syntax noprefix\n", asm_out_file);
26820 x86_field_alignment (tree field, int computed)
26822 enum machine_mode mode;
26823 tree type = TREE_TYPE (field);
26825 if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
26827 mode = TYPE_MODE (strip_array_types (type));
26828 if (mode == DFmode || mode == DCmode
26829 || GET_MODE_CLASS (mode) == MODE_INT
26830 || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
26831 return MIN (32, computed);
26835 /* Output assembler code to FILE to increment profiler label # LABELNO
26836 for profiling a function entry. */
26838 x86_function_profiler (FILE *file, int labelno ATTRIBUTE_UNUSED)
26842 #ifndef NO_PROFILE_COUNTERS
26843 fprintf (file, "\tleaq\t%sP%d(%%rip),%%r11\n", LPREFIX, labelno);
26846 if (DEFAULT_ABI == SYSV_ABI && flag_pic)
26847 fprintf (file, "\tcall\t*%s@GOTPCREL(%%rip)\n", MCOUNT_NAME);
26849 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26853 #ifndef NO_PROFILE_COUNTERS
26854 fprintf (file, "\tleal\t%sP%d@GOTOFF(%%ebx),%%%s\n",
26855 LPREFIX, labelno, PROFILE_COUNT_REGISTER);
26857 fprintf (file, "\tcall\t*%s@GOT(%%ebx)\n", MCOUNT_NAME);
26861 #ifndef NO_PROFILE_COUNTERS
26862 fprintf (file, "\tmovl\t$%sP%d,%%%s\n", LPREFIX, labelno,
26863 PROFILE_COUNT_REGISTER);
26865 fprintf (file, "\tcall\t%s\n", MCOUNT_NAME);
26869 /* We don't have exact information about the insn sizes, but we may assume
26870 quite safely that we are informed about all 1 byte insns and memory
26871 address sizes. This is enough to eliminate unnecessary padding in
26875 min_insn_size (rtx insn)
26879 if (!INSN_P (insn) || !active_insn_p (insn))
26882 /* Discard alignments we've emit and jump instructions. */
26883 if (GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
26884 && XINT (PATTERN (insn), 1) == UNSPECV_ALIGN)
26887 && (GET_CODE (PATTERN (insn)) == ADDR_VEC
26888 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC))
26891 /* Important case - calls are always 5 bytes.
26892 It is common to have many calls in the row. */
26894 && symbolic_reference_mentioned_p (PATTERN (insn))
26895 && !SIBLING_CALL_P (insn))
26897 if (get_attr_length (insn) <= 1)
26900 /* For normal instructions we may rely on the sizes of addresses
26901 and the presence of symbol to require 4 bytes of encoding.
26902 This is not the case for jumps where references are PC relative. */
26903 if (!JUMP_P (insn))
26905 l = get_attr_length_address (insn);
26906 if (l < 4 && symbolic_reference_mentioned_p (PATTERN (insn)))
26915 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
26919 ix86_avoid_jump_misspredicts (void)
26921 rtx insn, start = get_insns ();
26922 int nbytes = 0, njumps = 0;
26925 /* Look for all minimal intervals of instructions containing 4 jumps.
26926 The intervals are bounded by START and INSN. NBYTES is the total
26927 size of instructions in the interval including INSN and not including
26928 START. When the NBYTES is smaller than 16 bytes, it is possible
26929 that the end of START and INSN ends up in the same 16byte page.
26931 The smallest offset in the page INSN can start is the case where START
26932 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
26933 We add p2align to 16byte window with maxskip 17 - NBYTES + sizeof (INSN).
26935 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
26938 nbytes += min_insn_size (insn);
26940 fprintf(dump_file, "Insn %i estimated to %i bytes\n",
26941 INSN_UID (insn), min_insn_size (insn));
26943 && GET_CODE (PATTERN (insn)) != ADDR_VEC
26944 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
26952 start = NEXT_INSN (start);
26953 if ((JUMP_P (start)
26954 && GET_CODE (PATTERN (start)) != ADDR_VEC
26955 && GET_CODE (PATTERN (start)) != ADDR_DIFF_VEC)
26957 njumps--, isjump = 1;
26960 nbytes -= min_insn_size (start);
26962 gcc_assert (njumps >= 0);
26964 fprintf (dump_file, "Interval %i to %i has %i bytes\n",
26965 INSN_UID (start), INSN_UID (insn), nbytes);
26967 if (njumps == 3 && isjump && nbytes < 16)
26969 int padsize = 15 - nbytes + min_insn_size (insn);
26972 fprintf (dump_file, "Padding insn %i by %i bytes!\n",
26973 INSN_UID (insn), padsize);
26974 emit_insn_before (gen_align (GEN_INT (padsize)), insn);
26979 /* AMD Athlon works faster
26980 when RET is not destination of conditional jump or directly preceded
26981 by other jump instruction. We avoid the penalty by inserting NOP just
26982 before the RET instructions in such cases. */
26984 ix86_pad_returns (void)
26989 FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds)
26991 basic_block bb = e->src;
26992 rtx ret = BB_END (bb);
26994 bool replace = false;
26996 if (!JUMP_P (ret) || GET_CODE (PATTERN (ret)) != RETURN
26997 || optimize_bb_for_size_p (bb))
26999 for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev))
27000 if (active_insn_p (prev) || LABEL_P (prev))
27002 if (prev && LABEL_P (prev))
27007 FOR_EACH_EDGE (e, ei, bb->preds)
27008 if (EDGE_FREQUENCY (e) && e->src->index >= 0
27009 && !(e->flags & EDGE_FALLTHRU))
27014 prev = prev_active_insn (ret);
27016 && ((JUMP_P (prev) && any_condjump_p (prev))
27019 /* Empty functions get branch mispredict even when the jump destination
27020 is not visible to us. */
27021 if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED)
27026 emit_insn_before (gen_return_internal_long (), ret);
27032 /* Implement machine specific optimizations. We implement padding of returns
27033 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
27037 if (TARGET_PAD_RETURNS && optimize
27038 && optimize_function_for_speed_p (cfun))
27039 ix86_pad_returns ();
27040 if (TARGET_FOUR_JUMP_LIMIT && optimize
27041 && optimize_function_for_speed_p (cfun))
27042 ix86_avoid_jump_misspredicts ();
27045 /* Return nonzero when QImode register that must be represented via REX prefix
27048 x86_extended_QIreg_mentioned_p (rtx insn)
27051 extract_insn_cached (insn);
27052 for (i = 0; i < recog_data.n_operands; i++)
27053 if (REG_P (recog_data.operand[i])
27054 && REGNO (recog_data.operand[i]) > BX_REG)
27059 /* Return nonzero when P points to register encoded via REX prefix.
27060 Called via for_each_rtx. */
27062 extended_reg_mentioned_1 (rtx *p, void *data ATTRIBUTE_UNUSED)
27064 unsigned int regno;
27067 regno = REGNO (*p);
27068 return REX_INT_REGNO_P (regno) || REX_SSE_REGNO_P (regno);
27071 /* Return true when INSN mentions register that must be encoded using REX
27074 x86_extended_reg_mentioned_p (rtx insn)
27076 return for_each_rtx (INSN_P (insn) ? &PATTERN (insn) : &insn,
27077 extended_reg_mentioned_1, NULL);
27080 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
27081 optabs would emit if we didn't have TFmode patterns. */
27084 x86_emit_floatuns (rtx operands[2])
27086 rtx neglab, donelab, i0, i1, f0, in, out;
27087 enum machine_mode mode, inmode;
27089 inmode = GET_MODE (operands[1]);
27090 gcc_assert (inmode == SImode || inmode == DImode);
27093 in = force_reg (inmode, operands[1]);
27094 mode = GET_MODE (out);
27095 neglab = gen_label_rtx ();
27096 donelab = gen_label_rtx ();
27097 f0 = gen_reg_rtx (mode);
27099 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, inmode, 0, neglab);
27101 expand_float (out, in, 0);
27103 emit_jump_insn (gen_jump (donelab));
27106 emit_label (neglab);
27108 i0 = expand_simple_binop (inmode, LSHIFTRT, in, const1_rtx, NULL,
27110 i1 = expand_simple_binop (inmode, AND, in, const1_rtx, NULL,
27112 i0 = expand_simple_binop (inmode, IOR, i0, i1, i0, 1, OPTAB_DIRECT);
27114 expand_float (f0, i0, 0);
27116 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
27118 emit_label (donelab);
27121 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27122 with all elements equal to VAR. Return true if successful. */
27125 ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode,
27126 rtx target, rtx val)
27128 enum machine_mode hmode, smode, wsmode, wvmode;
27143 val = force_reg (GET_MODE_INNER (mode), val);
27144 x = gen_rtx_VEC_DUPLICATE (mode, val);
27145 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27151 if (TARGET_SSE || TARGET_3DNOW_A)
27153 val = gen_lowpart (SImode, val);
27154 x = gen_rtx_TRUNCATE (HImode, val);
27155 x = gen_rtx_VEC_DUPLICATE (mode, x);
27156 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27178 /* Extend HImode to SImode using a paradoxical SUBREG. */
27179 tmp1 = gen_reg_rtx (SImode);
27180 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27181 /* Insert the SImode value as low element of V4SImode vector. */
27182 tmp2 = gen_reg_rtx (V4SImode);
27183 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27184 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27185 CONST0_RTX (V4SImode),
27187 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27188 /* Cast the V4SImode vector back to a V8HImode vector. */
27189 tmp1 = gen_reg_rtx (V8HImode);
27190 emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2));
27191 /* Duplicate the low short through the whole low SImode word. */
27192 emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1));
27193 /* Cast the V8HImode vector back to a V4SImode vector. */
27194 tmp2 = gen_reg_rtx (V4SImode);
27195 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27196 /* Replicate the low element of the V4SImode vector. */
27197 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27198 /* Cast the V2SImode back to V8HImode, and store in target. */
27199 emit_move_insn (target, gen_lowpart (V8HImode, tmp2));
27210 /* Extend QImode to SImode using a paradoxical SUBREG. */
27211 tmp1 = gen_reg_rtx (SImode);
27212 emit_move_insn (tmp1, gen_lowpart (SImode, val));
27213 /* Insert the SImode value as low element of V4SImode vector. */
27214 tmp2 = gen_reg_rtx (V4SImode);
27215 tmp1 = gen_rtx_VEC_MERGE (V4SImode,
27216 gen_rtx_VEC_DUPLICATE (V4SImode, tmp1),
27217 CONST0_RTX (V4SImode),
27219 emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1));
27220 /* Cast the V4SImode vector back to a V16QImode vector. */
27221 tmp1 = gen_reg_rtx (V16QImode);
27222 emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2));
27223 /* Duplicate the low byte through the whole low SImode word. */
27224 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27225 emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1));
27226 /* Cast the V16QImode vector back to a V4SImode vector. */
27227 tmp2 = gen_reg_rtx (V4SImode);
27228 emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1));
27229 /* Replicate the low element of the V4SImode vector. */
27230 emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx));
27231 /* Cast the V2SImode back to V16QImode, and store in target. */
27232 emit_move_insn (target, gen_lowpart (V16QImode, tmp2));
27240 /* Replicate the value once into the next wider mode and recurse. */
27241 val = convert_modes (wsmode, smode, val, true);
27242 x = expand_simple_binop (wsmode, ASHIFT, val,
27243 GEN_INT (GET_MODE_BITSIZE (smode)),
27244 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27245 val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN);
27247 x = gen_reg_rtx (wvmode);
27248 if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val))
27249 gcc_unreachable ();
27250 emit_move_insn (target, gen_lowpart (mode, x));
27273 rtx tmp = gen_reg_rtx (hmode);
27274 ix86_expand_vector_init_duplicate (mmx_ok, hmode, tmp, val);
27275 emit_insn (gen_rtx_SET (VOIDmode, target,
27276 gen_rtx_VEC_CONCAT (mode, tmp, tmp)));
27285 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27286 whose ONE_VAR element is VAR, and other elements are zero. Return true
27290 ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode,
27291 rtx target, rtx var, int one_var)
27293 enum machine_mode vsimode;
27296 bool use_vector_set = false;
27301 /* For SSE4.1, we normally use vector set. But if the second
27302 element is zero and inter-unit moves are OK, we use movq
27304 use_vector_set = (TARGET_64BIT
27306 && !(TARGET_INTER_UNIT_MOVES
27312 use_vector_set = TARGET_SSE4_1;
27315 use_vector_set = TARGET_SSE2;
27318 use_vector_set = TARGET_SSE || TARGET_3DNOW_A;
27325 use_vector_set = TARGET_AVX;
27328 /* Use ix86_expand_vector_set in 64bit mode only. */
27329 use_vector_set = TARGET_AVX && TARGET_64BIT;
27335 if (use_vector_set)
27337 emit_insn (gen_rtx_SET (VOIDmode, target, CONST0_RTX (mode)));
27338 var = force_reg (GET_MODE_INNER (mode), var);
27339 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27355 var = force_reg (GET_MODE_INNER (mode), var);
27356 x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode)));
27357 emit_insn (gen_rtx_SET (VOIDmode, target, x));
27362 if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER)
27363 new_target = gen_reg_rtx (mode);
27365 new_target = target;
27366 var = force_reg (GET_MODE_INNER (mode), var);
27367 x = gen_rtx_VEC_DUPLICATE (mode, var);
27368 x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx);
27369 emit_insn (gen_rtx_SET (VOIDmode, new_target, x));
27372 /* We need to shuffle the value to the correct position, so
27373 create a new pseudo to store the intermediate result. */
27375 /* With SSE2, we can use the integer shuffle insns. */
27376 if (mode != V4SFmode && TARGET_SSE2)
27378 emit_insn (gen_sse2_pshufd_1 (new_target, new_target,
27380 GEN_INT (one_var == 1 ? 0 : 1),
27381 GEN_INT (one_var == 2 ? 0 : 1),
27382 GEN_INT (one_var == 3 ? 0 : 1)));
27383 if (target != new_target)
27384 emit_move_insn (target, new_target);
27388 /* Otherwise convert the intermediate result to V4SFmode and
27389 use the SSE1 shuffle instructions. */
27390 if (mode != V4SFmode)
27392 tmp = gen_reg_rtx (V4SFmode);
27393 emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target));
27398 emit_insn (gen_sse_shufps_v4sf (tmp, tmp, tmp,
27400 GEN_INT (one_var == 1 ? 0 : 1),
27401 GEN_INT (one_var == 2 ? 0+4 : 1+4),
27402 GEN_INT (one_var == 3 ? 0+4 : 1+4)));
27404 if (mode != V4SFmode)
27405 emit_move_insn (target, gen_lowpart (V4SImode, tmp));
27406 else if (tmp != target)
27407 emit_move_insn (target, tmp);
27409 else if (target != new_target)
27410 emit_move_insn (target, new_target);
27415 vsimode = V4SImode;
27421 vsimode = V2SImode;
27427 /* Zero extend the variable element to SImode and recurse. */
27428 var = convert_modes (SImode, GET_MODE_INNER (mode), var, true);
27430 x = gen_reg_rtx (vsimode);
27431 if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x,
27433 gcc_unreachable ();
27435 emit_move_insn (target, gen_lowpart (mode, x));
27443 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
27444 consisting of the values in VALS. It is known that all elements
27445 except ONE_VAR are constants. Return true if successful. */
27448 ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
27449 rtx target, rtx vals, int one_var)
27451 rtx var = XVECEXP (vals, 0, one_var);
27452 enum machine_mode wmode;
27455 const_vec = copy_rtx (vals);
27456 XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode));
27457 const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0));
27465 /* For the two element vectors, it's just as easy to use
27466 the general case. */
27470 /* Use ix86_expand_vector_set in 64bit mode only. */
27493 /* There's no way to set one QImode entry easily. Combine
27494 the variable value with its adjacent constant value, and
27495 promote to an HImode set. */
27496 x = XVECEXP (vals, 0, one_var ^ 1);
27499 var = convert_modes (HImode, QImode, var, true);
27500 var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8),
27501 NULL_RTX, 1, OPTAB_LIB_WIDEN);
27502 x = GEN_INT (INTVAL (x) & 0xff);
27506 var = convert_modes (HImode, QImode, var, true);
27507 x = gen_int_mode (INTVAL (x) << 8, HImode);
27509 if (x != const0_rtx)
27510 var = expand_simple_binop (HImode, IOR, var, x, var,
27511 1, OPTAB_LIB_WIDEN);
27513 x = gen_reg_rtx (wmode);
27514 emit_move_insn (x, gen_lowpart (wmode, const_vec));
27515 ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1);
27517 emit_move_insn (target, gen_lowpart (mode, x));
27524 emit_move_insn (target, const_vec);
27525 ix86_expand_vector_set (mmx_ok, target, var, one_var);
27529 /* A subroutine of ix86_expand_vector_init_general. Use vector
27530 concatenate to handle the most general case: all values variable,
27531 and none identical. */
27534 ix86_expand_vector_init_concat (enum machine_mode mode,
27535 rtx target, rtx *ops, int n)
27537 enum machine_mode cmode, hmode = VOIDmode;
27538 rtx first[8], second[4];
27578 gcc_unreachable ();
27581 if (!register_operand (ops[1], cmode))
27582 ops[1] = force_reg (cmode, ops[1]);
27583 if (!register_operand (ops[0], cmode))
27584 ops[0] = force_reg (cmode, ops[0]);
27585 emit_insn (gen_rtx_SET (VOIDmode, target,
27586 gen_rtx_VEC_CONCAT (mode, ops[0],
27606 gcc_unreachable ();
27622 gcc_unreachable ();
27627 /* FIXME: We process inputs backward to help RA. PR 36222. */
27630 for (; i > 0; i -= 2, j--)
27632 first[j] = gen_reg_rtx (cmode);
27633 v = gen_rtvec (2, ops[i - 1], ops[i]);
27634 ix86_expand_vector_init (false, first[j],
27635 gen_rtx_PARALLEL (cmode, v));
27641 gcc_assert (hmode != VOIDmode);
27642 for (i = j = 0; i < n; i += 2, j++)
27644 second[j] = gen_reg_rtx (hmode);
27645 ix86_expand_vector_init_concat (hmode, second [j],
27649 ix86_expand_vector_init_concat (mode, target, second, n);
27652 ix86_expand_vector_init_concat (mode, target, first, n);
27656 gcc_unreachable ();
27660 /* A subroutine of ix86_expand_vector_init_general. Use vector
27661 interleave to handle the most general case: all values variable,
27662 and none identical. */
27665 ix86_expand_vector_init_interleave (enum machine_mode mode,
27666 rtx target, rtx *ops, int n)
27668 enum machine_mode first_imode, second_imode, third_imode, inner_mode;
27671 rtx (*gen_load_even) (rtx, rtx, rtx);
27672 rtx (*gen_interleave_first_low) (rtx, rtx, rtx);
27673 rtx (*gen_interleave_second_low) (rtx, rtx, rtx);
27678 gen_load_even = gen_vec_setv8hi;
27679 gen_interleave_first_low = gen_vec_interleave_lowv4si;
27680 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27681 inner_mode = HImode;
27682 first_imode = V4SImode;
27683 second_imode = V2DImode;
27684 third_imode = VOIDmode;
27687 gen_load_even = gen_vec_setv16qi;
27688 gen_interleave_first_low = gen_vec_interleave_lowv8hi;
27689 gen_interleave_second_low = gen_vec_interleave_lowv4si;
27690 inner_mode = QImode;
27691 first_imode = V8HImode;
27692 second_imode = V4SImode;
27693 third_imode = V2DImode;
27696 gcc_unreachable ();
27699 for (i = 0; i < n; i++)
27701 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
27702 op0 = gen_reg_rtx (SImode);
27703 emit_move_insn (op0, gen_lowpart (SImode, ops [i + i]));
27705 /* Insert the SImode value as low element of V4SImode vector. */
27706 op1 = gen_reg_rtx (V4SImode);
27707 op0 = gen_rtx_VEC_MERGE (V4SImode,
27708 gen_rtx_VEC_DUPLICATE (V4SImode,
27710 CONST0_RTX (V4SImode),
27712 emit_insn (gen_rtx_SET (VOIDmode, op1, op0));
27714 /* Cast the V4SImode vector back to a vector in orignal mode. */
27715 op0 = gen_reg_rtx (mode);
27716 emit_move_insn (op0, gen_lowpart (mode, op1));
27718 /* Load even elements into the second positon. */
27719 emit_insn ((*gen_load_even) (op0,
27720 force_reg (inner_mode,
27724 /* Cast vector to FIRST_IMODE vector. */
27725 ops[i] = gen_reg_rtx (first_imode);
27726 emit_move_insn (ops[i], gen_lowpart (first_imode, op0));
27729 /* Interleave low FIRST_IMODE vectors. */
27730 for (i = j = 0; i < n; i += 2, j++)
27732 op0 = gen_reg_rtx (first_imode);
27733 emit_insn ((*gen_interleave_first_low) (op0, ops[i], ops[i + 1]));
27735 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
27736 ops[j] = gen_reg_rtx (second_imode);
27737 emit_move_insn (ops[j], gen_lowpart (second_imode, op0));
27740 /* Interleave low SECOND_IMODE vectors. */
27741 switch (second_imode)
27744 for (i = j = 0; i < n / 2; i += 2, j++)
27746 op0 = gen_reg_rtx (second_imode);
27747 emit_insn ((*gen_interleave_second_low) (op0, ops[i],
27750 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
27752 ops[j] = gen_reg_rtx (third_imode);
27753 emit_move_insn (ops[j], gen_lowpart (third_imode, op0));
27755 second_imode = V2DImode;
27756 gen_interleave_second_low = gen_vec_interleave_lowv2di;
27760 op0 = gen_reg_rtx (second_imode);
27761 emit_insn ((*gen_interleave_second_low) (op0, ops[0],
27764 /* Cast the SECOND_IMODE vector back to a vector on original
27766 emit_insn (gen_rtx_SET (VOIDmode, target,
27767 gen_lowpart (mode, op0)));
27771 gcc_unreachable ();
27775 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
27776 all values variable, and none identical. */
27779 ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
27780 rtx target, rtx vals)
27782 rtx ops[32], op0, op1;
27783 enum machine_mode half_mode = VOIDmode;
27790 if (!mmx_ok && !TARGET_SSE)
27802 n = GET_MODE_NUNITS (mode);
27803 for (i = 0; i < n; i++)
27804 ops[i] = XVECEXP (vals, 0, i);
27805 ix86_expand_vector_init_concat (mode, target, ops, n);
27809 half_mode = V16QImode;
27813 half_mode = V8HImode;
27817 n = GET_MODE_NUNITS (mode);
27818 for (i = 0; i < n; i++)
27819 ops[i] = XVECEXP (vals, 0, i);
27820 op0 = gen_reg_rtx (half_mode);
27821 op1 = gen_reg_rtx (half_mode);
27822 ix86_expand_vector_init_interleave (half_mode, op0, ops,
27824 ix86_expand_vector_init_interleave (half_mode, op1,
27825 &ops [n >> 1], n >> 2);
27826 emit_insn (gen_rtx_SET (VOIDmode, target,
27827 gen_rtx_VEC_CONCAT (mode, op0, op1)));
27831 if (!TARGET_SSE4_1)
27839 /* Don't use ix86_expand_vector_init_interleave if we can't
27840 move from GPR to SSE register directly. */
27841 if (!TARGET_INTER_UNIT_MOVES)
27844 n = GET_MODE_NUNITS (mode);
27845 for (i = 0; i < n; i++)
27846 ops[i] = XVECEXP (vals, 0, i);
27847 ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
27855 gcc_unreachable ();
27859 int i, j, n_elts, n_words, n_elt_per_word;
27860 enum machine_mode inner_mode;
27861 rtx words[4], shift;
27863 inner_mode = GET_MODE_INNER (mode);
27864 n_elts = GET_MODE_NUNITS (mode);
27865 n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD;
27866 n_elt_per_word = n_elts / n_words;
27867 shift = GEN_INT (GET_MODE_BITSIZE (inner_mode));
27869 for (i = 0; i < n_words; ++i)
27871 rtx word = NULL_RTX;
27873 for (j = 0; j < n_elt_per_word; ++j)
27875 rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1);
27876 elt = convert_modes (word_mode, inner_mode, elt, true);
27882 word = expand_simple_binop (word_mode, ASHIFT, word, shift,
27883 word, 1, OPTAB_LIB_WIDEN);
27884 word = expand_simple_binop (word_mode, IOR, word, elt,
27885 word, 1, OPTAB_LIB_WIDEN);
27893 emit_move_insn (target, gen_lowpart (mode, words[0]));
27894 else if (n_words == 2)
27896 rtx tmp = gen_reg_rtx (mode);
27897 emit_clobber (tmp);
27898 emit_move_insn (gen_lowpart (word_mode, tmp), words[0]);
27899 emit_move_insn (gen_highpart (word_mode, tmp), words[1]);
27900 emit_move_insn (target, tmp);
27902 else if (n_words == 4)
27904 rtx tmp = gen_reg_rtx (V4SImode);
27905 gcc_assert (word_mode == SImode);
27906 vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words));
27907 ix86_expand_vector_init_general (false, V4SImode, tmp, vals);
27908 emit_move_insn (target, gen_lowpart (mode, tmp));
27911 gcc_unreachable ();
27915 /* Initialize vector TARGET via VALS. Suppress the use of MMX
27916 instructions unless MMX_OK is true. */
27919 ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
27921 enum machine_mode mode = GET_MODE (target);
27922 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27923 int n_elts = GET_MODE_NUNITS (mode);
27924 int n_var = 0, one_var = -1;
27925 bool all_same = true, all_const_zero = true;
27929 for (i = 0; i < n_elts; ++i)
27931 x = XVECEXP (vals, 0, i);
27932 if (!(CONST_INT_P (x)
27933 || GET_CODE (x) == CONST_DOUBLE
27934 || GET_CODE (x) == CONST_FIXED))
27935 n_var++, one_var = i;
27936 else if (x != CONST0_RTX (inner_mode))
27937 all_const_zero = false;
27938 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
27942 /* Constants are best loaded from the constant pool. */
27945 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
27949 /* If all values are identical, broadcast the value. */
27951 && ix86_expand_vector_init_duplicate (mmx_ok, mode, target,
27952 XVECEXP (vals, 0, 0)))
27955 /* Values where only one field is non-constant are best loaded from
27956 the pool and overwritten via move later. */
27960 && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target,
27961 XVECEXP (vals, 0, one_var),
27965 if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var))
27969 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
27973 ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt)
27975 enum machine_mode mode = GET_MODE (target);
27976 enum machine_mode inner_mode = GET_MODE_INNER (mode);
27977 enum machine_mode half_mode;
27978 bool use_vec_merge = false;
27980 static rtx (*gen_extract[6][2]) (rtx, rtx)
27982 { gen_vec_extract_lo_v32qi, gen_vec_extract_hi_v32qi },
27983 { gen_vec_extract_lo_v16hi, gen_vec_extract_hi_v16hi },
27984 { gen_vec_extract_lo_v8si, gen_vec_extract_hi_v8si },
27985 { gen_vec_extract_lo_v4di, gen_vec_extract_hi_v4di },
27986 { gen_vec_extract_lo_v8sf, gen_vec_extract_hi_v8sf },
27987 { gen_vec_extract_lo_v4df, gen_vec_extract_hi_v4df }
27989 static rtx (*gen_insert[6][2]) (rtx, rtx, rtx)
27991 { gen_vec_set_lo_v32qi, gen_vec_set_hi_v32qi },
27992 { gen_vec_set_lo_v16hi, gen_vec_set_hi_v16hi },
27993 { gen_vec_set_lo_v8si, gen_vec_set_hi_v8si },
27994 { gen_vec_set_lo_v4di, gen_vec_set_hi_v4di },
27995 { gen_vec_set_lo_v8sf, gen_vec_set_hi_v8sf },
27996 { gen_vec_set_lo_v4df, gen_vec_set_hi_v4df }
28006 tmp = gen_reg_rtx (GET_MODE_INNER (mode));
28007 ix86_expand_vector_extract (true, tmp, target, 1 - elt);
28009 tmp = gen_rtx_VEC_CONCAT (mode, tmp, val);
28011 tmp = gen_rtx_VEC_CONCAT (mode, val, tmp);
28012 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28018 use_vec_merge = TARGET_SSE4_1;
28026 /* For the two element vectors, we implement a VEC_CONCAT with
28027 the extraction of the other element. */
28029 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt)));
28030 tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp);
28033 op0 = val, op1 = tmp;
28035 op0 = tmp, op1 = val;
28037 tmp = gen_rtx_VEC_CONCAT (mode, op0, op1);
28038 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28043 use_vec_merge = TARGET_SSE4_1;
28050 use_vec_merge = true;
28054 /* tmp = target = A B C D */
28055 tmp = copy_to_reg (target);
28056 /* target = A A B B */
28057 emit_insn (gen_sse_unpcklps (target, target, target));
28058 /* target = X A B B */
28059 ix86_expand_vector_set (false, target, val, 0);
28060 /* target = A X C D */
28061 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28062 GEN_INT (1), GEN_INT (0),
28063 GEN_INT (2+4), GEN_INT (3+4)));
28067 /* tmp = target = A B C D */
28068 tmp = copy_to_reg (target);
28069 /* tmp = X B C D */
28070 ix86_expand_vector_set (false, tmp, val, 0);
28071 /* target = A B X D */
28072 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28073 GEN_INT (0), GEN_INT (1),
28074 GEN_INT (0+4), GEN_INT (3+4)));
28078 /* tmp = target = A B C D */
28079 tmp = copy_to_reg (target);
28080 /* tmp = X B C D */
28081 ix86_expand_vector_set (false, tmp, val, 0);
28082 /* target = A B X D */
28083 emit_insn (gen_sse_shufps_v4sf (target, target, tmp,
28084 GEN_INT (0), GEN_INT (1),
28085 GEN_INT (2+4), GEN_INT (0+4)));
28089 gcc_unreachable ();
28094 use_vec_merge = TARGET_SSE4_1;
28098 /* Element 0 handled by vec_merge below. */
28101 use_vec_merge = true;
28107 /* With SSE2, use integer shuffles to swap element 0 and ELT,
28108 store into element 0, then shuffle them back. */
28112 order[0] = GEN_INT (elt);
28113 order[1] = const1_rtx;
28114 order[2] = const2_rtx;
28115 order[3] = GEN_INT (3);
28116 order[elt] = const0_rtx;
28118 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28119 order[1], order[2], order[3]));
28121 ix86_expand_vector_set (false, target, val, 0);
28123 emit_insn (gen_sse2_pshufd_1 (target, target, order[0],
28124 order[1], order[2], order[3]));
28128 /* For SSE1, we have to reuse the V4SF code. */
28129 ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target),
28130 gen_lowpart (SFmode, val), elt);
28135 use_vec_merge = TARGET_SSE2;
28138 use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28142 use_vec_merge = TARGET_SSE4_1;
28149 half_mode = V16QImode;
28155 half_mode = V8HImode;
28161 half_mode = V4SImode;
28167 half_mode = V2DImode;
28173 half_mode = V4SFmode;
28179 half_mode = V2DFmode;
28185 /* Compute offset. */
28189 gcc_assert (i <= 1);
28191 /* Extract the half. */
28192 tmp = gen_reg_rtx (half_mode);
28193 emit_insn ((*gen_extract[j][i]) (tmp, target));
28195 /* Put val in tmp at elt. */
28196 ix86_expand_vector_set (false, tmp, val, elt);
28199 emit_insn ((*gen_insert[j][i]) (target, target, tmp));
28208 tmp = gen_rtx_VEC_DUPLICATE (mode, val);
28209 tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt));
28210 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28214 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28216 emit_move_insn (mem, target);
28218 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28219 emit_move_insn (tmp, val);
28221 emit_move_insn (target, mem);
28226 ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt)
28228 enum machine_mode mode = GET_MODE (vec);
28229 enum machine_mode inner_mode = GET_MODE_INNER (mode);
28230 bool use_vec_extr = false;
28243 use_vec_extr = true;
28247 use_vec_extr = TARGET_SSE4_1;
28259 tmp = gen_reg_rtx (mode);
28260 emit_insn (gen_sse_shufps_v4sf (tmp, vec, vec,
28261 GEN_INT (elt), GEN_INT (elt),
28262 GEN_INT (elt+4), GEN_INT (elt+4)));
28266 tmp = gen_reg_rtx (mode);
28267 emit_insn (gen_sse_unpckhps (tmp, vec, vec));
28271 gcc_unreachable ();
28274 use_vec_extr = true;
28279 use_vec_extr = TARGET_SSE4_1;
28293 tmp = gen_reg_rtx (mode);
28294 emit_insn (gen_sse2_pshufd_1 (tmp, vec,
28295 GEN_INT (elt), GEN_INT (elt),
28296 GEN_INT (elt), GEN_INT (elt)));
28300 tmp = gen_reg_rtx (mode);
28301 emit_insn (gen_sse2_punpckhdq (tmp, vec, vec));
28305 gcc_unreachable ();
28308 use_vec_extr = true;
28313 /* For SSE1, we have to reuse the V4SF code. */
28314 ix86_expand_vector_extract (false, gen_lowpart (SFmode, target),
28315 gen_lowpart (V4SFmode, vec), elt);
28321 use_vec_extr = TARGET_SSE2;
28324 use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A);
28328 use_vec_extr = TARGET_SSE4_1;
28332 /* ??? Could extract the appropriate HImode element and shift. */
28339 tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt)));
28340 tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp);
28342 /* Let the rtl optimizers know about the zero extension performed. */
28343 if (inner_mode == QImode || inner_mode == HImode)
28345 tmp = gen_rtx_ZERO_EXTEND (SImode, tmp);
28346 target = gen_lowpart (SImode, target);
28349 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
28353 rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false);
28355 emit_move_insn (mem, vec);
28357 tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode));
28358 emit_move_insn (target, tmp);
28362 /* Expand a vector reduction on V4SFmode for SSE1. FN is the binary
28363 pattern to reduce; DEST is the destination; IN is the input vector. */
28366 ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in)
28368 rtx tmp1, tmp2, tmp3;
28370 tmp1 = gen_reg_rtx (V4SFmode);
28371 tmp2 = gen_reg_rtx (V4SFmode);
28372 tmp3 = gen_reg_rtx (V4SFmode);
28374 emit_insn (gen_sse_movhlps (tmp1, in, in));
28375 emit_insn (fn (tmp2, tmp1, in));
28377 emit_insn (gen_sse_shufps_v4sf (tmp3, tmp2, tmp2,
28378 GEN_INT (1), GEN_INT (1),
28379 GEN_INT (1+4), GEN_INT (1+4)));
28380 emit_insn (fn (dest, tmp2, tmp3));
28383 /* Target hook for scalar_mode_supported_p. */
28385 ix86_scalar_mode_supported_p (enum machine_mode mode)
28387 if (DECIMAL_FLOAT_MODE_P (mode))
28389 else if (mode == TFmode)
28392 return default_scalar_mode_supported_p (mode);
28395 /* Implements target hook vector_mode_supported_p. */
28397 ix86_vector_mode_supported_p (enum machine_mode mode)
28399 if (TARGET_SSE && VALID_SSE_REG_MODE (mode))
28401 if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode))
28403 if (TARGET_AVX && VALID_AVX256_REG_MODE (mode))
28405 if (TARGET_MMX && VALID_MMX_REG_MODE (mode))
28407 if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode))
28412 /* Target hook for c_mode_for_suffix. */
28413 static enum machine_mode
28414 ix86_c_mode_for_suffix (char suffix)
28424 /* Worker function for TARGET_MD_ASM_CLOBBERS.
28426 We do this in the new i386 backend to maintain source compatibility
28427 with the old cc0-based compiler. */
28430 ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
28431 tree inputs ATTRIBUTE_UNUSED,
28434 clobbers = tree_cons (NULL_TREE, build_string (5, "flags"),
28436 clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"),
28441 /* Implements target vector targetm.asm.encode_section_info. This
28442 is not used by netware. */
28444 static void ATTRIBUTE_UNUSED
28445 ix86_encode_section_info (tree decl, rtx rtl, int first)
28447 default_encode_section_info (decl, rtl, first);
28449 if (TREE_CODE (decl) == VAR_DECL
28450 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))
28451 && ix86_in_large_data_p (decl))
28452 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR;
28455 /* Worker function for REVERSE_CONDITION. */
28458 ix86_reverse_condition (enum rtx_code code, enum machine_mode mode)
28460 return (mode != CCFPmode && mode != CCFPUmode
28461 ? reverse_condition (code)
28462 : reverse_condition_maybe_unordered (code));
28465 /* Output code to perform an x87 FP register move, from OPERANDS[1]
28469 output_387_reg_move (rtx insn, rtx *operands)
28471 if (REG_P (operands[0]))
28473 if (REG_P (operands[1])
28474 && find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28476 if (REGNO (operands[0]) == FIRST_STACK_REG)
28477 return output_387_ffreep (operands, 0);
28478 return "fstp\t%y0";
28480 if (STACK_TOP_P (operands[0]))
28481 return "fld%z1\t%y1";
28484 else if (MEM_P (operands[0]))
28486 gcc_assert (REG_P (operands[1]));
28487 if (find_regno_note (insn, REG_DEAD, REGNO (operands[1])))
28488 return "fstp%z0\t%y0";
28491 /* There is no non-popping store to memory for XFmode.
28492 So if we need one, follow the store with a load. */
28493 if (GET_MODE (operands[0]) == XFmode)
28494 return "fstp%z0\t%y0\n\tfld%z0\t%y0";
28496 return "fst%z0\t%y0";
28503 /* Output code to perform a conditional jump to LABEL, if C2 flag in
28504 FP status register is set. */
28507 ix86_emit_fp_unordered_jump (rtx label)
28509 rtx reg = gen_reg_rtx (HImode);
28512 emit_insn (gen_x86_fnstsw_1 (reg));
28514 if (TARGET_SAHF && (TARGET_USE_SAHF || optimize_insn_for_size_p ()))
28516 emit_insn (gen_x86_sahf_1 (reg));
28518 temp = gen_rtx_REG (CCmode, FLAGS_REG);
28519 temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx);
28523 emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04)));
28525 temp = gen_rtx_REG (CCNOmode, FLAGS_REG);
28526 temp = gen_rtx_NE (VOIDmode, temp, const0_rtx);
28529 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
28530 gen_rtx_LABEL_REF (VOIDmode, label),
28532 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
28534 emit_jump_insn (temp);
28535 predict_jump (REG_BR_PROB_BASE * 10 / 100);
28538 /* Output code to perform a log1p XFmode calculation. */
28540 void ix86_emit_i387_log1p (rtx op0, rtx op1)
28542 rtx label1 = gen_label_rtx ();
28543 rtx label2 = gen_label_rtx ();
28545 rtx tmp = gen_reg_rtx (XFmode);
28546 rtx tmp2 = gen_reg_rtx (XFmode);
28548 emit_insn (gen_absxf2 (tmp, op1));
28549 emit_insn (gen_cmpxf (tmp,
28550 CONST_DOUBLE_FROM_REAL_VALUE (
28551 REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode),
28553 emit_jump_insn (gen_bge (label1));
28555 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28556 emit_insn (gen_fyl2xp1xf3_i387 (op0, op1, tmp2));
28557 emit_jump (label2);
28559 emit_label (label1);
28560 emit_move_insn (tmp, CONST1_RTX (XFmode));
28561 emit_insn (gen_addxf3 (tmp, op1, tmp));
28562 emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */
28563 emit_insn (gen_fyl2xxf3_i387 (op0, tmp, tmp2));
28565 emit_label (label2);
28568 /* Output code to perform a Newton-Rhapson approximation of a single precision
28569 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
28571 void ix86_emit_swdivsf (rtx res, rtx a, rtx b, enum machine_mode mode)
28573 rtx x0, x1, e0, e1, two;
28575 x0 = gen_reg_rtx (mode);
28576 e0 = gen_reg_rtx (mode);
28577 e1 = gen_reg_rtx (mode);
28578 x1 = gen_reg_rtx (mode);
28580 two = CONST_DOUBLE_FROM_REAL_VALUE (dconst2, SFmode);
28582 if (VECTOR_MODE_P (mode))
28583 two = ix86_build_const_vector (SFmode, true, two);
28585 two = force_reg (mode, two);
28587 /* a / b = a * rcp(b) * (2.0 - b * rcp(b)) */
28589 /* x0 = rcp(b) estimate */
28590 emit_insn (gen_rtx_SET (VOIDmode, x0,
28591 gen_rtx_UNSPEC (mode, gen_rtvec (1, b),
28594 emit_insn (gen_rtx_SET (VOIDmode, e0,
28595 gen_rtx_MULT (mode, x0, b)));
28597 emit_insn (gen_rtx_SET (VOIDmode, e1,
28598 gen_rtx_MINUS (mode, two, e0)));
28600 emit_insn (gen_rtx_SET (VOIDmode, x1,
28601 gen_rtx_MULT (mode, x0, e1)));
28603 emit_insn (gen_rtx_SET (VOIDmode, res,
28604 gen_rtx_MULT (mode, a, x1)));
28607 /* Output code to perform a Newton-Rhapson approximation of a
28608 single precision floating point [reciprocal] square root. */
28610 void ix86_emit_swsqrtsf (rtx res, rtx a, enum machine_mode mode,
28613 rtx x0, e0, e1, e2, e3, mthree, mhalf;
28616 x0 = gen_reg_rtx (mode);
28617 e0 = gen_reg_rtx (mode);
28618 e1 = gen_reg_rtx (mode);
28619 e2 = gen_reg_rtx (mode);
28620 e3 = gen_reg_rtx (mode);
28622 real_from_integer (&r, VOIDmode, -3, -1, 0);
28623 mthree = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28625 real_arithmetic (&r, NEGATE_EXPR, &dconsthalf, NULL);
28626 mhalf = CONST_DOUBLE_FROM_REAL_VALUE (r, SFmode);
28628 if (VECTOR_MODE_P (mode))
28630 mthree = ix86_build_const_vector (SFmode, true, mthree);
28631 mhalf = ix86_build_const_vector (SFmode, true, mhalf);
28634 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
28635 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
28637 /* x0 = rsqrt(a) estimate */
28638 emit_insn (gen_rtx_SET (VOIDmode, x0,
28639 gen_rtx_UNSPEC (mode, gen_rtvec (1, a),
28642 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
28647 zero = gen_reg_rtx (mode);
28648 mask = gen_reg_rtx (mode);
28650 zero = force_reg (mode, CONST0_RTX(mode));
28651 emit_insn (gen_rtx_SET (VOIDmode, mask,
28652 gen_rtx_NE (mode, zero, a)));
28654 emit_insn (gen_rtx_SET (VOIDmode, x0,
28655 gen_rtx_AND (mode, x0, mask)));
28659 emit_insn (gen_rtx_SET (VOIDmode, e0,
28660 gen_rtx_MULT (mode, x0, a)));
28662 emit_insn (gen_rtx_SET (VOIDmode, e1,
28663 gen_rtx_MULT (mode, e0, x0)));
28666 mthree = force_reg (mode, mthree);
28667 emit_insn (gen_rtx_SET (VOIDmode, e2,
28668 gen_rtx_PLUS (mode, e1, mthree)));
28670 mhalf = force_reg (mode, mhalf);
28672 /* e3 = -.5 * x0 */
28673 emit_insn (gen_rtx_SET (VOIDmode, e3,
28674 gen_rtx_MULT (mode, x0, mhalf)));
28676 /* e3 = -.5 * e0 */
28677 emit_insn (gen_rtx_SET (VOIDmode, e3,
28678 gen_rtx_MULT (mode, e0, mhalf)));
28679 /* ret = e2 * e3 */
28680 emit_insn (gen_rtx_SET (VOIDmode, res,
28681 gen_rtx_MULT (mode, e2, e3)));
28684 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
28686 static void ATTRIBUTE_UNUSED
28687 i386_solaris_elf_named_section (const char *name, unsigned int flags,
28690 /* With Binutils 2.15, the "@unwind" marker must be specified on
28691 every occurrence of the ".eh_frame" section, not just the first
28694 && strcmp (name, ".eh_frame") == 0)
28696 fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name,
28697 flags & SECTION_WRITE ? "aw" : "a");
28700 default_elf_asm_named_section (name, flags, decl);
28703 /* Return the mangling of TYPE if it is an extended fundamental type. */
28705 static const char *
28706 ix86_mangle_type (const_tree type)
28708 type = TYPE_MAIN_VARIANT (type);
28710 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28711 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28714 switch (TYPE_MODE (type))
28717 /* __float128 is "g". */
28720 /* "long double" or __float80 is "e". */
28727 /* For 32-bit code we can save PIC register setup by using
28728 __stack_chk_fail_local hidden function instead of calling
28729 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
28730 register, so it is better to call __stack_chk_fail directly. */
28733 ix86_stack_protect_fail (void)
28735 #if 0 /* XXX swildner */
28736 return TARGET_64BIT
28737 ? default_external_stack_protect_fail ()
28738 : default_hidden_stack_protect_fail ();
28740 return default_external_stack_protect_fail ();
28744 /* Select a format to encode pointers in exception handling data. CODE
28745 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
28746 true if the symbol may be affected by dynamic relocations.
28748 ??? All x86 object file formats are capable of representing this.
28749 After all, the relocation needed is the same as for the call insn.
28750 Whether or not a particular assembler allows us to enter such, I
28751 guess we'll have to see. */
28753 asm_preferred_eh_data_format (int code, int global)
28757 int type = DW_EH_PE_sdata8;
28759 || ix86_cmodel == CM_SMALL_PIC
28760 || (ix86_cmodel == CM_MEDIUM_PIC && (global || code)))
28761 type = DW_EH_PE_sdata4;
28762 return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type;
28764 if (ix86_cmodel == CM_SMALL
28765 || (ix86_cmodel == CM_MEDIUM && code))
28766 return DW_EH_PE_udata4;
28767 return DW_EH_PE_absptr;
28770 /* Expand copysign from SIGN to the positive value ABS_VALUE
28771 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
28774 ix86_sse_copysign_to_positive (rtx result, rtx abs_value, rtx sign, rtx mask)
28776 enum machine_mode mode = GET_MODE (sign);
28777 rtx sgn = gen_reg_rtx (mode);
28778 if (mask == NULL_RTX)
28780 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), false);
28781 if (!VECTOR_MODE_P (mode))
28783 /* We need to generate a scalar mode mask in this case. */
28784 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28785 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28786 mask = gen_reg_rtx (mode);
28787 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28791 mask = gen_rtx_NOT (mode, mask);
28792 emit_insn (gen_rtx_SET (VOIDmode, sgn,
28793 gen_rtx_AND (mode, mask, sign)));
28794 emit_insn (gen_rtx_SET (VOIDmode, result,
28795 gen_rtx_IOR (mode, abs_value, sgn)));
28798 /* Expand fabs (OP0) and return a new rtx that holds the result. The
28799 mask for masking out the sign-bit is stored in *SMASK, if that is
28802 ix86_expand_sse_fabs (rtx op0, rtx *smask)
28804 enum machine_mode mode = GET_MODE (op0);
28807 xa = gen_reg_rtx (mode);
28808 mask = ix86_build_signbit_mask (mode, VECTOR_MODE_P (mode), true);
28809 if (!VECTOR_MODE_P (mode))
28811 /* We need to generate a scalar mode mask in this case. */
28812 rtx tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, const0_rtx));
28813 tmp = gen_rtx_VEC_SELECT (mode, mask, tmp);
28814 mask = gen_reg_rtx (mode);
28815 emit_insn (gen_rtx_SET (VOIDmode, mask, tmp));
28817 emit_insn (gen_rtx_SET (VOIDmode, xa,
28818 gen_rtx_AND (mode, op0, mask)));
28826 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
28827 swapping the operands if SWAP_OPERANDS is true. The expanded
28828 code is a forward jump to a newly created label in case the
28829 comparison is true. The generated label rtx is returned. */
28831 ix86_expand_sse_compare_and_jump (enum rtx_code code, rtx op0, rtx op1,
28832 bool swap_operands)
28843 label = gen_label_rtx ();
28844 tmp = gen_rtx_REG (CCFPUmode, FLAGS_REG);
28845 emit_insn (gen_rtx_SET (VOIDmode, tmp,
28846 gen_rtx_COMPARE (CCFPUmode, op0, op1)));
28847 tmp = gen_rtx_fmt_ee (code, VOIDmode, tmp, const0_rtx);
28848 tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
28849 gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx);
28850 tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
28851 JUMP_LABEL (tmp) = label;
28856 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
28857 using comparison code CODE. Operands are swapped for the comparison if
28858 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
28860 ix86_expand_sse_compare_mask (enum rtx_code code, rtx op0, rtx op1,
28861 bool swap_operands)
28863 enum machine_mode mode = GET_MODE (op0);
28864 rtx mask = gen_reg_rtx (mode);
28873 if (mode == DFmode)
28874 emit_insn (gen_sse2_maskcmpdf3 (mask, op0, op1,
28875 gen_rtx_fmt_ee (code, mode, op0, op1)));
28877 emit_insn (gen_sse_maskcmpsf3 (mask, op0, op1,
28878 gen_rtx_fmt_ee (code, mode, op0, op1)));
28883 /* Generate and return a rtx of mode MODE for 2**n where n is the number
28884 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
28886 ix86_gen_TWO52 (enum machine_mode mode)
28888 REAL_VALUE_TYPE TWO52r;
28891 real_ldexp (&TWO52r, &dconst1, mode == DFmode ? 52 : 23);
28892 TWO52 = const_double_from_real_value (TWO52r, mode);
28893 TWO52 = force_reg (mode, TWO52);
28898 /* Expand SSE sequence for computing lround from OP1 storing
28901 ix86_expand_lround (rtx op0, rtx op1)
28903 /* C code for the stuff we're doing below:
28904 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
28907 enum machine_mode mode = GET_MODE (op1);
28908 const struct real_format *fmt;
28909 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
28912 /* load nextafter (0.5, 0.0) */
28913 fmt = REAL_MODE_FORMAT (mode);
28914 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
28915 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
28917 /* adj = copysign (0.5, op1) */
28918 adj = force_reg (mode, const_double_from_real_value (pred_half, mode));
28919 ix86_sse_copysign_to_positive (adj, adj, force_reg (mode, op1), NULL_RTX);
28921 /* adj = op1 + adj */
28922 adj = expand_simple_binop (mode, PLUS, adj, op1, NULL_RTX, 0, OPTAB_DIRECT);
28924 /* op0 = (imode)adj */
28925 expand_fix (op0, adj, 0);
28928 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
28931 ix86_expand_lfloorceil (rtx op0, rtx op1, bool do_floor)
28933 /* C code for the stuff we're doing below (for do_floor):
28935 xi -= (double)xi > op1 ? 1 : 0;
28938 enum machine_mode fmode = GET_MODE (op1);
28939 enum machine_mode imode = GET_MODE (op0);
28940 rtx ireg, freg, label, tmp;
28942 /* reg = (long)op1 */
28943 ireg = gen_reg_rtx (imode);
28944 expand_fix (ireg, op1, 0);
28946 /* freg = (double)reg */
28947 freg = gen_reg_rtx (fmode);
28948 expand_float (freg, ireg, 0);
28950 /* ireg = (freg > op1) ? ireg - 1 : ireg */
28951 label = ix86_expand_sse_compare_and_jump (UNLE,
28952 freg, op1, !do_floor);
28953 tmp = expand_simple_binop (imode, do_floor ? MINUS : PLUS,
28954 ireg, const1_rtx, NULL_RTX, 0, OPTAB_DIRECT);
28955 emit_move_insn (ireg, tmp);
28957 emit_label (label);
28958 LABEL_NUSES (label) = 1;
28960 emit_move_insn (op0, ireg);
28963 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
28964 result in OPERAND0. */
28966 ix86_expand_rint (rtx operand0, rtx operand1)
28968 /* C code for the stuff we're doing below:
28969 xa = fabs (operand1);
28970 if (!isless (xa, 2**52))
28972 xa = xa + 2**52 - 2**52;
28973 return copysign (xa, operand1);
28975 enum machine_mode mode = GET_MODE (operand0);
28976 rtx res, xa, label, TWO52, mask;
28978 res = gen_reg_rtx (mode);
28979 emit_move_insn (res, operand1);
28981 /* xa = abs (operand1) */
28982 xa = ix86_expand_sse_fabs (res, &mask);
28984 /* if (!isless (xa, TWO52)) goto label; */
28985 TWO52 = ix86_gen_TWO52 (mode);
28986 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
28988 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
28989 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
28991 ix86_sse_copysign_to_positive (res, xa, res, mask);
28993 emit_label (label);
28994 LABEL_NUSES (label) = 1;
28996 emit_move_insn (operand0, res);
28999 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29002 ix86_expand_floorceildf_32 (rtx operand0, rtx operand1, bool do_floor)
29004 /* C code for the stuff we expand below.
29005 double xa = fabs (x), x2;
29006 if (!isless (xa, TWO52))
29008 xa = xa + TWO52 - TWO52;
29009 x2 = copysign (xa, x);
29018 enum machine_mode mode = GET_MODE (operand0);
29019 rtx xa, TWO52, tmp, label, one, res, mask;
29021 TWO52 = ix86_gen_TWO52 (mode);
29023 /* Temporary for holding the result, initialized to the input
29024 operand to ease control flow. */
29025 res = gen_reg_rtx (mode);
29026 emit_move_insn (res, operand1);
29028 /* xa = abs (operand1) */
29029 xa = ix86_expand_sse_fabs (res, &mask);
29031 /* if (!isless (xa, TWO52)) goto label; */
29032 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29034 /* xa = xa + TWO52 - TWO52; */
29035 xa = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29036 xa = expand_simple_binop (mode, MINUS, xa, TWO52, xa, 0, OPTAB_DIRECT);
29038 /* xa = copysign (xa, operand1) */
29039 ix86_sse_copysign_to_positive (xa, xa, res, mask);
29041 /* generate 1.0 or -1.0 */
29042 one = force_reg (mode,
29043 const_double_from_real_value (do_floor
29044 ? dconst1 : dconstm1, mode));
29046 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29047 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29048 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29049 gen_rtx_AND (mode, one, tmp)));
29050 /* We always need to subtract here to preserve signed zero. */
29051 tmp = expand_simple_binop (mode, MINUS,
29052 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29053 emit_move_insn (res, tmp);
29055 emit_label (label);
29056 LABEL_NUSES (label) = 1;
29058 emit_move_insn (operand0, res);
29061 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
29064 ix86_expand_floorceil (rtx operand0, rtx operand1, bool do_floor)
29066 /* C code for the stuff we expand below.
29067 double xa = fabs (x), x2;
29068 if (!isless (xa, TWO52))
29070 x2 = (double)(long)x;
29077 if (HONOR_SIGNED_ZEROS (mode))
29078 return copysign (x2, x);
29081 enum machine_mode mode = GET_MODE (operand0);
29082 rtx xa, xi, TWO52, tmp, label, one, res, mask;
29084 TWO52 = ix86_gen_TWO52 (mode);
29086 /* Temporary for holding the result, initialized to the input
29087 operand to ease control flow. */
29088 res = gen_reg_rtx (mode);
29089 emit_move_insn (res, operand1);
29091 /* xa = abs (operand1) */
29092 xa = ix86_expand_sse_fabs (res, &mask);
29094 /* if (!isless (xa, TWO52)) goto label; */
29095 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29097 /* xa = (double)(long)x */
29098 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29099 expand_fix (xi, res, 0);
29100 expand_float (xa, xi, 0);
29103 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29105 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
29106 tmp = ix86_expand_sse_compare_mask (UNGT, xa, res, !do_floor);
29107 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29108 gen_rtx_AND (mode, one, tmp)));
29109 tmp = expand_simple_binop (mode, do_floor ? MINUS : PLUS,
29110 xa, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29111 emit_move_insn (res, tmp);
29113 if (HONOR_SIGNED_ZEROS (mode))
29114 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29116 emit_label (label);
29117 LABEL_NUSES (label) = 1;
29119 emit_move_insn (operand0, res);
29122 /* Expand SSE sequence for computing round from OPERAND1 storing
29123 into OPERAND0. Sequence that works without relying on DImode truncation
29124 via cvttsd2siq that is only available on 64bit targets. */
29126 ix86_expand_rounddf_32 (rtx operand0, rtx operand1)
29128 /* C code for the stuff we expand below.
29129 double xa = fabs (x), xa2, x2;
29130 if (!isless (xa, TWO52))
29132 Using the absolute value and copying back sign makes
29133 -0.0 -> -0.0 correct.
29134 xa2 = xa + TWO52 - TWO52;
29139 else if (dxa > 0.5)
29141 x2 = copysign (xa2, x);
29144 enum machine_mode mode = GET_MODE (operand0);
29145 rtx xa, xa2, dxa, TWO52, tmp, label, half, mhalf, one, res, mask;
29147 TWO52 = ix86_gen_TWO52 (mode);
29149 /* Temporary for holding the result, initialized to the input
29150 operand to ease control flow. */
29151 res = gen_reg_rtx (mode);
29152 emit_move_insn (res, operand1);
29154 /* xa = abs (operand1) */
29155 xa = ix86_expand_sse_fabs (res, &mask);
29157 /* if (!isless (xa, TWO52)) goto label; */
29158 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29160 /* xa2 = xa + TWO52 - TWO52; */
29161 xa2 = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29162 xa2 = expand_simple_binop (mode, MINUS, xa2, TWO52, xa2, 0, OPTAB_DIRECT);
29164 /* dxa = xa2 - xa; */
29165 dxa = expand_simple_binop (mode, MINUS, xa2, xa, NULL_RTX, 0, OPTAB_DIRECT);
29167 /* generate 0.5, 1.0 and -0.5 */
29168 half = force_reg (mode, const_double_from_real_value (dconsthalf, mode));
29169 one = expand_simple_binop (mode, PLUS, half, half, NULL_RTX, 0, OPTAB_DIRECT);
29170 mhalf = expand_simple_binop (mode, MINUS, half, one, NULL_RTX,
29174 tmp = gen_reg_rtx (mode);
29175 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
29176 tmp = ix86_expand_sse_compare_mask (UNGT, dxa, half, false);
29177 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29178 gen_rtx_AND (mode, one, tmp)));
29179 xa2 = expand_simple_binop (mode, MINUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29180 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
29181 tmp = ix86_expand_sse_compare_mask (UNGE, mhalf, dxa, false);
29182 emit_insn (gen_rtx_SET (VOIDmode, tmp,
29183 gen_rtx_AND (mode, one, tmp)));
29184 xa2 = expand_simple_binop (mode, PLUS, xa2, tmp, NULL_RTX, 0, OPTAB_DIRECT);
29186 /* res = copysign (xa2, operand1) */
29187 ix86_sse_copysign_to_positive (res, xa2, force_reg (mode, operand1), mask);
29189 emit_label (label);
29190 LABEL_NUSES (label) = 1;
29192 emit_move_insn (operand0, res);
29195 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29198 ix86_expand_trunc (rtx operand0, rtx operand1)
29200 /* C code for SSE variant we expand below.
29201 double xa = fabs (x), x2;
29202 if (!isless (xa, TWO52))
29204 x2 = (double)(long)x;
29205 if (HONOR_SIGNED_ZEROS (mode))
29206 return copysign (x2, x);
29209 enum machine_mode mode = GET_MODE (operand0);
29210 rtx xa, xi, TWO52, label, res, mask;
29212 TWO52 = ix86_gen_TWO52 (mode);
29214 /* Temporary for holding the result, initialized to the input
29215 operand to ease control flow. */
29216 res = gen_reg_rtx (mode);
29217 emit_move_insn (res, operand1);
29219 /* xa = abs (operand1) */
29220 xa = ix86_expand_sse_fabs (res, &mask);
29222 /* if (!isless (xa, TWO52)) goto label; */
29223 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29225 /* x = (double)(long)x */
29226 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29227 expand_fix (xi, res, 0);
29228 expand_float (res, xi, 0);
29230 if (HONOR_SIGNED_ZEROS (mode))
29231 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), mask);
29233 emit_label (label);
29234 LABEL_NUSES (label) = 1;
29236 emit_move_insn (operand0, res);
29239 /* Expand SSE sequence for computing trunc from OPERAND1 storing
29242 ix86_expand_truncdf_32 (rtx operand0, rtx operand1)
29244 enum machine_mode mode = GET_MODE (operand0);
29245 rtx xa, mask, TWO52, label, one, res, smask, tmp;
29247 /* C code for SSE variant we expand below.
29248 double xa = fabs (x), x2;
29249 if (!isless (xa, TWO52))
29251 xa2 = xa + TWO52 - TWO52;
29255 x2 = copysign (xa2, x);
29259 TWO52 = ix86_gen_TWO52 (mode);
29261 /* Temporary for holding the result, initialized to the input
29262 operand to ease control flow. */
29263 res = gen_reg_rtx (mode);
29264 emit_move_insn (res, operand1);
29266 /* xa = abs (operand1) */
29267 xa = ix86_expand_sse_fabs (res, &smask);
29269 /* if (!isless (xa, TWO52)) goto label; */
29270 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29272 /* res = xa + TWO52 - TWO52; */
29273 tmp = expand_simple_binop (mode, PLUS, xa, TWO52, NULL_RTX, 0, OPTAB_DIRECT);
29274 tmp = expand_simple_binop (mode, MINUS, tmp, TWO52, tmp, 0, OPTAB_DIRECT);
29275 emit_move_insn (res, tmp);
29278 one = force_reg (mode, const_double_from_real_value (dconst1, mode));
29280 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
29281 mask = ix86_expand_sse_compare_mask (UNGT, res, xa, false);
29282 emit_insn (gen_rtx_SET (VOIDmode, mask,
29283 gen_rtx_AND (mode, mask, one)));
29284 tmp = expand_simple_binop (mode, MINUS,
29285 res, mask, NULL_RTX, 0, OPTAB_DIRECT);
29286 emit_move_insn (res, tmp);
29288 /* res = copysign (res, operand1) */
29289 ix86_sse_copysign_to_positive (res, res, force_reg (mode, operand1), smask);
29291 emit_label (label);
29292 LABEL_NUSES (label) = 1;
29294 emit_move_insn (operand0, res);
29297 /* Expand SSE sequence for computing round from OPERAND1 storing
29300 ix86_expand_round (rtx operand0, rtx operand1)
29302 /* C code for the stuff we're doing below:
29303 double xa = fabs (x);
29304 if (!isless (xa, TWO52))
29306 xa = (double)(long)(xa + nextafter (0.5, 0.0));
29307 return copysign (xa, x);
29309 enum machine_mode mode = GET_MODE (operand0);
29310 rtx res, TWO52, xa, label, xi, half, mask;
29311 const struct real_format *fmt;
29312 REAL_VALUE_TYPE pred_half, half_minus_pred_half;
29314 /* Temporary for holding the result, initialized to the input
29315 operand to ease control flow. */
29316 res = gen_reg_rtx (mode);
29317 emit_move_insn (res, operand1);
29319 TWO52 = ix86_gen_TWO52 (mode);
29320 xa = ix86_expand_sse_fabs (res, &mask);
29321 label = ix86_expand_sse_compare_and_jump (UNLE, TWO52, xa, false);
29323 /* load nextafter (0.5, 0.0) */
29324 fmt = REAL_MODE_FORMAT (mode);
29325 real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
29326 REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
29328 /* xa = xa + 0.5 */
29329 half = force_reg (mode, const_double_from_real_value (pred_half, mode));
29330 xa = expand_simple_binop (mode, PLUS, xa, half, NULL_RTX, 0, OPTAB_DIRECT);
29332 /* xa = (double)(int64_t)xa */
29333 xi = gen_reg_rtx (mode == DFmode ? DImode : SImode);
29334 expand_fix (xi, xa, 0);
29335 expand_float (xa, xi, 0);
29337 /* res = copysign (xa, operand1) */
29338 ix86_sse_copysign_to_positive (res, xa, force_reg (mode, operand1), mask);
29340 emit_label (label);
29341 LABEL_NUSES (label) = 1;
29343 emit_move_insn (operand0, res);
29347 /* Validate whether a SSE5 instruction is valid or not.
29348 OPERANDS is the array of operands.
29349 NUM is the number of operands.
29350 USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
29351 NUM_MEMORY is the maximum number of memory operands to accept.
29352 when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
29355 ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
29356 bool uses_oc0, int num_memory, bool commutative)
29362 /* Count the number of memory arguments */
29365 for (i = 0; i < num; i++)
29367 enum machine_mode mode = GET_MODE (operands[i]);
29368 if (register_operand (operands[i], mode))
29371 else if (memory_operand (operands[i], mode))
29373 mem_mask |= (1 << i);
29379 rtx pattern = PATTERN (insn);
29381 /* allow 0 for pcmov */
29382 if (GET_CODE (pattern) != SET
29383 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
29385 || operands[i] != CONST0_RTX (mode))
29390 /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
29391 a memory operation. */
29392 if (num_memory < 0)
29394 num_memory = -num_memory;
29395 if ((mem_mask & (1 << (num-1))) != 0)
29397 mem_mask &= ~(1 << (num-1));
29402 /* If there were no memory operations, allow the insn */
29406 /* Do not allow the destination register to be a memory operand. */
29407 else if (mem_mask & (1 << 0))
29410 /* If there are too many memory operations, disallow the instruction. While
29411 the hardware only allows 1 memory reference, before register allocation
29412 for some insns, we allow two memory operations sometimes in order to allow
29413 code like the following to be optimized:
29415 float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
29417 or similar cases that are vectorized into using the fmaddss
29419 else if (mem_count > num_memory)
29422 /* Don't allow more than one memory operation if not optimizing. */
29423 else if (mem_count > 1 && !optimize)
29426 else if (num == 4 && mem_count == 1)
29428 /* formats (destination is the first argument), example fmaddss:
29429 xmm1, xmm1, xmm2, xmm3/mem
29430 xmm1, xmm1, xmm2/mem, xmm3
29431 xmm1, xmm2, xmm3/mem, xmm1
29432 xmm1, xmm2/mem, xmm3, xmm1 */
29434 return ((mem_mask == (1 << 1))
29435 || (mem_mask == (1 << 2))
29436 || (mem_mask == (1 << 3)));
29438 /* format, example pmacsdd:
29439 xmm1, xmm2, xmm3/mem, xmm1 */
29441 return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
29443 return (mem_mask == (1 << 2));
29446 else if (num == 4 && num_memory == 2)
29448 /* If there are two memory operations, we can load one of the memory ops
29449 into the destination register. This is for optimizing the
29450 multiply/add ops, which the combiner has optimized both the multiply
29451 and the add insns to have a memory operation. We have to be careful
29452 that the destination doesn't overlap with the inputs. */
29453 rtx op0 = operands[0];
29455 if (reg_mentioned_p (op0, operands[1])
29456 || reg_mentioned_p (op0, operands[2])
29457 || reg_mentioned_p (op0, operands[3]))
29460 /* formats (destination is the first argument), example fmaddss:
29461 xmm1, xmm1, xmm2, xmm3/mem
29462 xmm1, xmm1, xmm2/mem, xmm3
29463 xmm1, xmm2, xmm3/mem, xmm1
29464 xmm1, xmm2/mem, xmm3, xmm1
29466 For the oc0 case, we will load either operands[1] or operands[3] into
29467 operands[0], so any combination of 2 memory operands is ok. */
29471 /* format, example pmacsdd:
29472 xmm1, xmm2, xmm3/mem, xmm1
29474 For the integer multiply/add instructions be more restrictive and
29475 require operands[2] and operands[3] to be the memory operands. */
29477 return (mem_mask == ((1 << 1) | (1 << 3)) ||
29478 mem_mask == ((1 << 2) | (1 << 3)));
29480 return (mem_mask == ((1 << 2) | (1 << 3)));
29483 else if (num == 3 && num_memory == 1)
29485 /* formats, example protb:
29486 xmm1, xmm2, xmm3/mem
29487 xmm1, xmm2/mem, xmm3 */
29489 return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
29491 /* format, example comeq:
29492 xmm1, xmm2, xmm3/mem */
29494 return (mem_mask == (1 << 2));
29498 gcc_unreachable ();
29504 /* Fixup an SSE5 instruction that has 2 memory input references into a form the
29505 hardware will allow by using the destination register to load one of the
29506 memory operations. Presently this is used by the multiply/add routines to
29507 allow 2 memory references. */
29510 ix86_expand_sse5_multiple_memory (rtx operands[],
29512 enum machine_mode mode)
29514 rtx op0 = operands[0];
29516 || memory_operand (op0, mode)
29517 || reg_mentioned_p (op0, operands[1])
29518 || reg_mentioned_p (op0, operands[2])
29519 || reg_mentioned_p (op0, operands[3]))
29520 gcc_unreachable ();
29522 /* For 2 memory operands, pick either operands[1] or operands[3] to move into
29523 the destination register. */
29524 if (memory_operand (operands[1], mode))
29526 emit_move_insn (op0, operands[1]);
29529 else if (memory_operand (operands[3], mode))
29531 emit_move_insn (op0, operands[3]);
29535 gcc_unreachable ();
29541 /* Table of valid machine attributes. */
29542 static const struct attribute_spec ix86_attribute_table[] =
29544 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
29545 /* Stdcall attribute says callee is responsible for popping arguments
29546 if they are not variable. */
29547 { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29548 /* Fastcall attribute says callee is responsible for popping arguments
29549 if they are not variable. */
29550 { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29551 /* Cdecl attribute says the callee is a normal C declaration */
29552 { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29553 /* Regparm attribute specifies how many integer arguments are to be
29554 passed in registers. */
29555 { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute },
29556 /* Sseregparm attribute says we are using x86_64 calling conventions
29557 for FP arguments. */
29558 { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute },
29559 /* force_align_arg_pointer says this function realigns the stack at entry. */
29560 { (const char *)&ix86_force_align_arg_pointer_string, 0, 0,
29561 false, true, true, ix86_handle_cconv_attribute },
29562 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29563 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
29564 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
29565 { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute },
29567 { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29568 { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute },
29569 #ifdef SUBTARGET_ATTRIBUTE_TABLE
29570 SUBTARGET_ATTRIBUTE_TABLE,
29572 /* ms_abi and sysv_abi calling convention function attributes. */
29573 { "ms_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29574 { "sysv_abi", 0, 0, false, true, true, ix86_handle_abi_attribute },
29576 { NULL, 0, 0, false, false, false, NULL }
29579 /* Implement targetm.vectorize.builtin_vectorization_cost. */
29581 x86_builtin_vectorization_cost (bool runtime_test)
29583 /* If the branch of the runtime test is taken - i.e. - the vectorized
29584 version is skipped - this incurs a misprediction cost (because the
29585 vectorized version is expected to be the fall-through). So we subtract
29586 the latency of a mispredicted branch from the costs that are incured
29587 when the vectorized version is executed.
29589 TODO: The values in individual target tables have to be tuned or new
29590 fields may be needed. For eg. on K8, the default branch path is the
29591 not-taken path. If the taken path is predicted correctly, the minimum
29592 penalty of going down the taken-path is 1 cycle. If the taken-path is
29593 not predicted correctly, then the minimum penalty is 10 cycles. */
29597 return (-(ix86_cost->cond_taken_branch_cost));
29603 /* This function returns the calling abi specific va_list type node.
29604 It returns the FNDECL specific va_list type. */
29607 ix86_fn_abi_va_list (tree fndecl)
29612 return va_list_type_node;
29613 gcc_assert (fndecl != NULL_TREE);
29614 abi = ix86_function_abi ((const_tree) fndecl);
29617 return ms_va_list_type_node;
29619 return sysv_va_list_type_node;
29622 /* Returns the canonical va_list type specified by TYPE. If there
29623 is no valid TYPE provided, it return NULL_TREE. */
29626 ix86_canonical_va_list_type (tree type)
29630 /* Resolve references and pointers to va_list type. */
29631 if (INDIRECT_REF_P (type))
29632 type = TREE_TYPE (type);
29633 else if (POINTER_TYPE_P (type) && POINTER_TYPE_P (TREE_TYPE(type)))
29634 type = TREE_TYPE (type);
29638 wtype = va_list_type_node;
29639 gcc_assert (wtype != NULL_TREE);
29641 if (TREE_CODE (wtype) == ARRAY_TYPE)
29643 /* If va_list is an array type, the argument may have decayed
29644 to a pointer type, e.g. by being passed to another function.
29645 In that case, unwrap both types so that we can compare the
29646 underlying records. */
29647 if (TREE_CODE (htype) == ARRAY_TYPE
29648 || POINTER_TYPE_P (htype))
29650 wtype = TREE_TYPE (wtype);
29651 htype = TREE_TYPE (htype);
29654 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29655 return va_list_type_node;
29656 wtype = sysv_va_list_type_node;
29657 gcc_assert (wtype != NULL_TREE);
29659 if (TREE_CODE (wtype) == ARRAY_TYPE)
29661 /* If va_list is an array type, the argument may have decayed
29662 to a pointer type, e.g. by being passed to another function.
29663 In that case, unwrap both types so that we can compare the
29664 underlying records. */
29665 if (TREE_CODE (htype) == ARRAY_TYPE
29666 || POINTER_TYPE_P (htype))
29668 wtype = TREE_TYPE (wtype);
29669 htype = TREE_TYPE (htype);
29672 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29673 return sysv_va_list_type_node;
29674 wtype = ms_va_list_type_node;
29675 gcc_assert (wtype != NULL_TREE);
29677 if (TREE_CODE (wtype) == ARRAY_TYPE)
29679 /* If va_list is an array type, the argument may have decayed
29680 to a pointer type, e.g. by being passed to another function.
29681 In that case, unwrap both types so that we can compare the
29682 underlying records. */
29683 if (TREE_CODE (htype) == ARRAY_TYPE
29684 || POINTER_TYPE_P (htype))
29686 wtype = TREE_TYPE (wtype);
29687 htype = TREE_TYPE (htype);
29690 if (TYPE_MAIN_VARIANT (wtype) == TYPE_MAIN_VARIANT (htype))
29691 return ms_va_list_type_node;
29694 return std_canonical_va_list_type (type);
29697 /* Iterate through the target-specific builtin types for va_list.
29698 IDX denotes the iterator, *PTREE is set to the result type of
29699 the va_list builtin, and *PNAME to its internal type.
29700 Returns zero if there is no element for this index, otherwise
29701 IDX should be increased upon the next call.
29702 Note, do not iterate a base builtin's name like __builtin_va_list.
29703 Used from c_common_nodes_and_builtins. */
29706 ix86_enum_va_list (int idx, const char **pname, tree *ptree)
29712 *ptree = ms_va_list_type_node;
29713 *pname = "__builtin_ms_va_list";
29716 *ptree = sysv_va_list_type_node;
29717 *pname = "__builtin_sysv_va_list";
29725 /* Initialize the GCC target structure. */
29726 #undef TARGET_RETURN_IN_MEMORY
29727 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
29729 #undef TARGET_ATTRIBUTE_TABLE
29730 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
29731 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29732 # undef TARGET_MERGE_DECL_ATTRIBUTES
29733 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
29736 #undef TARGET_COMP_TYPE_ATTRIBUTES
29737 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
29739 #undef TARGET_INIT_BUILTINS
29740 #define TARGET_INIT_BUILTINS ix86_init_builtins
29741 #undef TARGET_EXPAND_BUILTIN
29742 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
29744 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
29745 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
29746 ix86_builtin_vectorized_function
29748 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
29749 #define TARGET_VECTORIZE_BUILTIN_CONVERSION ix86_vectorize_builtin_conversion
29751 #undef TARGET_BUILTIN_RECIPROCAL
29752 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
29754 #undef TARGET_ASM_FUNCTION_EPILOGUE
29755 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
29757 #undef TARGET_ENCODE_SECTION_INFO
29758 #ifndef SUBTARGET_ENCODE_SECTION_INFO
29759 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
29761 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
29764 #undef TARGET_ASM_OPEN_PAREN
29765 #define TARGET_ASM_OPEN_PAREN ""
29766 #undef TARGET_ASM_CLOSE_PAREN
29767 #define TARGET_ASM_CLOSE_PAREN ""
29769 #undef TARGET_ASM_ALIGNED_HI_OP
29770 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
29771 #undef TARGET_ASM_ALIGNED_SI_OP
29772 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
29774 #undef TARGET_ASM_ALIGNED_DI_OP
29775 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
29778 #undef TARGET_ASM_UNALIGNED_HI_OP
29779 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
29780 #undef TARGET_ASM_UNALIGNED_SI_OP
29781 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
29782 #undef TARGET_ASM_UNALIGNED_DI_OP
29783 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
29785 #undef TARGET_SCHED_ADJUST_COST
29786 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
29787 #undef TARGET_SCHED_ISSUE_RATE
29788 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
29789 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
29790 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
29791 ia32_multipass_dfa_lookahead
29793 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
29794 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
29797 #undef TARGET_HAVE_TLS
29798 #define TARGET_HAVE_TLS true
29800 #undef TARGET_CANNOT_FORCE_CONST_MEM
29801 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
29802 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
29803 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
29805 #undef TARGET_DELEGITIMIZE_ADDRESS
29806 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
29808 #undef TARGET_MS_BITFIELD_LAYOUT_P
29809 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
29812 #undef TARGET_BINDS_LOCAL_P
29813 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
29815 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
29816 #undef TARGET_BINDS_LOCAL_P
29817 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
29820 #undef TARGET_ASM_OUTPUT_MI_THUNK
29821 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
29822 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
29823 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
29825 #undef TARGET_ASM_FILE_START
29826 #define TARGET_ASM_FILE_START x86_file_start
29828 #undef TARGET_DEFAULT_TARGET_FLAGS
29829 #define TARGET_DEFAULT_TARGET_FLAGS \
29831 | TARGET_SUBTARGET_DEFAULT \
29832 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
29834 #undef TARGET_HANDLE_OPTION
29835 #define TARGET_HANDLE_OPTION ix86_handle_option
29837 #undef TARGET_RTX_COSTS
29838 #define TARGET_RTX_COSTS ix86_rtx_costs
29839 #undef TARGET_ADDRESS_COST
29840 #define TARGET_ADDRESS_COST ix86_address_cost
29842 #undef TARGET_FIXED_CONDITION_CODE_REGS
29843 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
29844 #undef TARGET_CC_MODES_COMPATIBLE
29845 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
29847 #undef TARGET_MACHINE_DEPENDENT_REORG
29848 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
29850 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
29851 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
29853 #undef TARGET_BUILD_BUILTIN_VA_LIST
29854 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
29856 #undef TARGET_FN_ABI_VA_LIST
29857 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
29859 #undef TARGET_CANONICAL_VA_LIST_TYPE
29860 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
29862 #undef TARGET_EXPAND_BUILTIN_VA_START
29863 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
29865 #undef TARGET_MD_ASM_CLOBBERS
29866 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
29868 #undef TARGET_PROMOTE_PROTOTYPES
29869 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
29870 #undef TARGET_STRUCT_VALUE_RTX
29871 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
29872 #undef TARGET_SETUP_INCOMING_VARARGS
29873 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
29874 #undef TARGET_MUST_PASS_IN_STACK
29875 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
29876 #undef TARGET_PASS_BY_REFERENCE
29877 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
29878 #undef TARGET_INTERNAL_ARG_POINTER
29879 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
29880 #undef TARGET_UPDATE_STACK_BOUNDARY
29881 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
29882 #undef TARGET_GET_DRAP_RTX
29883 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
29884 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
29885 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec
29886 #undef TARGET_STRICT_ARGUMENT_NAMING
29887 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
29889 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
29890 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
29892 #undef TARGET_SCALAR_MODE_SUPPORTED_P
29893 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
29895 #undef TARGET_VECTOR_MODE_SUPPORTED_P
29896 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
29898 #undef TARGET_C_MODE_FOR_SUFFIX
29899 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
29902 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
29903 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
29906 #ifdef SUBTARGET_INSERT_ATTRIBUTES
29907 #undef TARGET_INSERT_ATTRIBUTES
29908 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
29911 #undef TARGET_MANGLE_TYPE
29912 #define TARGET_MANGLE_TYPE ix86_mangle_type
29914 #undef TARGET_STACK_PROTECT_FAIL
29915 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
29917 #undef TARGET_FUNCTION_VALUE
29918 #define TARGET_FUNCTION_VALUE ix86_function_value
29920 #undef TARGET_SECONDARY_RELOAD
29921 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
29923 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
29924 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST x86_builtin_vectorization_cost
29926 #undef TARGET_SET_CURRENT_FUNCTION
29927 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
29929 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
29930 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
29932 #undef TARGET_OPTION_SAVE
29933 #define TARGET_OPTION_SAVE ix86_function_specific_save
29935 #undef TARGET_OPTION_RESTORE
29936 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
29938 #undef TARGET_OPTION_PRINT
29939 #define TARGET_OPTION_PRINT ix86_function_specific_print
29941 #undef TARGET_OPTION_CAN_INLINE_P
29942 #define TARGET_OPTION_CAN_INLINE_P ix86_can_inline_p
29944 #undef TARGET_EXPAND_TO_RTL_HOOK
29945 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
29947 struct gcc_target targetm = TARGET_INITIALIZER;
29949 #include "gt-i386.h"
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