sys/net/i4b/layer1/iwic/i4b_iwic_bchan.c

   1 /*
   2  * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
   3  *
   4  * Copyright (c) 2000, 2001 Hellmuth Michaelis. All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *---------------------------------------------------------------------------
  28  *
  29  *      i4b_iwic - isdn4bsd Winbond W6692 driver
  30  *      ----------------------------------------
  31  *
  32  * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_iwic_bchan.c,v 1.7.2.1 2001/08/10 14:08:40 obrien Exp $
  33  * $DragonFly: src/sys/net/i4b/layer1/iwic/i4b_iwic_bchan.c,v 1.6 2005/06/14 21:19:19 joerg Exp $
  34  *
  35  *      last edit-date: [Tue Jan 16 13:21:24 2001]
  36  *
  37  *---------------------------------------------------------------------------*/
  38
  39 #include "use_iwic.h"
  40 #include "use_pci.h"
  41 #include "opt_i4b.h"
  42
  43 #if (NIWIC > 0) && (NPCI > 0)
  44
  45 #include <sys/param.h>
  46 #include <sys/systm.h>
  47 #include <sys/mbuf.h>
  48 #include <sys/socket.h>
  49 #include <sys/thread2.h>
  50
  51 #include <net/if.h>
  52
  53 #include <net/i4b/include/machine/i4b_debug.h>
  54 #include <net/i4b/include/machine/i4b_ioctl.h>
  55 #include <net/i4b/include/machine/i4b_trace.h>
  56
  57 #include "../i4b_l1.h"
  58
  59 #include "i4b_iwic.h"
  60 #include "i4b_w6692.h"
  61
  62 #include "../../include/i4b_global.h"
  63 #include "../../include/i4b_mbuf.h"
  64
  65 static void iwic_bchan_init(struct iwic_softc *sc, int chan_no, int activate);
  66
  67 /*---------------------------------------------------------------------------*
  68  *      B-channel interrupt handler
  69  *---------------------------------------------------------------------------*/
  70 void
  71 iwic_bchan_xirq(struct iwic_softc *sc, int chan_no)
  72 {
  73         int irq_stat;
  74         struct iwic_bchan *chan;
  75         int cmd = 0;
  76         int activity = 0;
  77
  78         chan = &sc->sc_bchan[chan_no];
  79
  80         irq_stat = IWIC_READ(sc, chan->offset + B_EXIR);
  81
  82         NDBGL1(L1_H_IRQ, "irq_stat = 0x%x", irq_stat);
  83
  84         if((irq_stat & (B_EXIR_RMR | B_EXIR_RME | B_EXIR_RDOV | B_EXIR_XFR | B_EXIR_XDUN)) == 0)
  85         {
  86                 NDBGL1(L1_H_XFRERR, "spurious IRQ!");
  87                 return;
  88         }
  89
  90         if (irq_stat & B_EXIR_RDOV)
  91         {
  92                 NDBGL1(L1_H_XFRERR, "iwic%d: EXIR B-channel Receive Data Overflow", sc->sc_unit);
  93         }
  94
  95         if (irq_stat & B_EXIR_XDUN)
  96         {
  97                 NDBGL1(L1_H_XFRERR, "iwic%d: EXIR B-channel Transmit Data Underrun", sc->sc_unit);
  98                 cmd |= (B_CMDR_XRST);   /*XXX must retransmit frame ! */
  99         }
 100
 101 /* RX message end interrupt */
 102
 103         if(irq_stat & B_EXIR_RME)
 104         {
 105                 int error;
 106
 107                 NDBGL1(L1_H_IRQ, "B_EXIR_RME");
 108
 109                 error = (IWIC_READ(sc,chan->offset+B_STAR) &
 110                          (B_STAR_RDOV | B_STAR_CRCE | B_STAR_RMB));
 111
 112                 if(error)
 113                 {
 114                         if(error & B_STAR_RDOV)
 115                                 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel Receive Data Overflow", sc->sc_unit);
 116                         if(error & B_STAR_CRCE)
 117                                 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel CRC Error", sc->sc_unit);
 118                         if(error & B_STAR_RMB)
 119                                 NDBGL1(L1_H_XFRERR, "iwic%d: B-channel Receive Message Aborted", sc->sc_unit);
 120                 }
 121
 122                 /* all error conditions checked, now decide and take action */
 123
 124                 if(error == 0)
 125                 {
 126                         int fifo_data_len;
 127                         fifo_data_len = ((IWIC_READ(sc,chan->offset+B_RBCL)) &
 128                                         ((IWIC_BCHAN_FIFO_LEN)-1));
 129
 130                         if(fifo_data_len == 0)
 131                                 fifo_data_len = IWIC_BCHAN_FIFO_LEN;
 132
 133
 134                         if(chan->in_mbuf == NULL)
 135                         {
 136                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 137                                         panic("L1 iwic_bchan_irq: RME, cannot allocate mbuf!\n");
 138                                 chan->in_cbptr = chan->in_mbuf->m_data;
 139                                 chan->in_len = 0;
 140                         }
 141
 142                         if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
 143                         {
 144                                 /* read data from fifo */
 145
 146                                 NDBGL1(L1_H_IRQ, "B_EXIR_RME, rd fifo, len = %d", fifo_data_len);
 147
 148                                 IWIC_RDBFIFO(sc, chan, chan->in_cbptr, fifo_data_len);
 149
 150                                 cmd |= (B_CMDR_RACK | B_CMDR_RACT);
 151                                 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
 152                                 cmd = 0;
 153
 154                                 chan->in_len += fifo_data_len;
 155                                 chan->rxcount += fifo_data_len;
 156
 157                                 /* setup mbuf data length */
 158
 159                                 chan->in_mbuf->m_len = chan->in_len;
 160                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 161
 162                                 if(sc->sc_trace & TRACE_B_RX)
 163                                 {
 164                                         i4b_trace_hdr_t hdr;
 165                                         hdr.unit = L0IWICUNIT(sc->sc_unit);
 166                                         hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 167                                         hdr.dir = FROM_NT;
 168                                         hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 169                                         MICROTIME(hdr.time);
 170                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 171                                 }
 172
 173                                 (*chan->iwic_drvr_linktab->bch_rx_data_ready)(chan->iwic_drvr_linktab->unit);
 174
 175                                 activity = ACT_RX;
 176
 177                                 /* mark buffer ptr as unused */
 178
 179                                 chan->in_mbuf = NULL;
 180                                 chan->in_cbptr = NULL;
 181                                 chan->in_len = 0;
 182                         }
 183                         else
 184                         {
 185                                 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RME, in_len=%d, fifolen=%d", chan->in_len, fifo_data_len);
 186                                 chan->in_cbptr = chan->in_mbuf->m_data;
 187                                 chan->in_len = 0;
 188                                 cmd |= (B_CMDR_RRST | B_CMDR_RACK);
 189                         }
 190                 }
 191                 else
 192                 {
 193                         if (chan->in_mbuf != NULL)
 194                         {
 195                                 i4b_Bfreembuf(chan->in_mbuf);
 196                                 chan->in_mbuf = NULL;
 197                                 chan->in_cbptr = NULL;
 198                                 chan->in_len = 0;
 199                         }
 200                         cmd |= (B_CMDR_RRST | B_CMDR_RACK);
 201                 }
 202         }
 203
 204 /* RX fifo full interrupt */
 205
 206         if(irq_stat & B_EXIR_RMR)
 207         {
 208                 NDBGL1(L1_H_IRQ, "B_EXIR_RMR");
 209
 210                 if(chan->in_mbuf == NULL)
 211                 {
 212                         if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 213                                 panic("L1 iwic_bchan_irq: RMR, cannot allocate mbuf!\n");
 214                         chan->in_cbptr = chan->in_mbuf->m_data;
 215                         chan->in_len = 0;
 216                 }
 217
 218                 chan->rxcount += IWIC_BCHAN_FIFO_LEN;
 219
 220                 if((chan->in_len + IWIC_BCHAN_FIFO_LEN) <= BCH_MAX_DATALEN)
 221                 {
 222                         /* read data from fifo */
 223
 224                         NDBGL1(L1_H_IRQ, "B_EXIR_RMR, rd fifo, len = max (64)");
 225
 226                         IWIC_RDBFIFO(sc, chan, chan->in_cbptr, IWIC_BCHAN_FIFO_LEN);
 227
 228                         chan->in_cbptr += IWIC_BCHAN_FIFO_LEN;
 229                         chan->in_len += IWIC_BCHAN_FIFO_LEN;
 230                 }
 231                 else
 232                 {
 233                         if(chan->bprot == BPROT_NONE)
 234                         {
 235                                 /* setup mbuf data length */
 236
 237                                 chan->in_mbuf->m_len = chan->in_len;
 238                                 chan->in_mbuf->m_pkthdr.len = chan->in_len;
 239
 240                                 if(sc->sc_trace & TRACE_B_RX)
 241                                 {
 242                                         i4b_trace_hdr_t hdr;
 243                                         hdr.unit = L0IWICUNIT(sc->sc_unit);
 244                                         hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 245                                         hdr.dir = FROM_NT;
 246                                         hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 247                                         MICROTIME(hdr.time);
 248                                         i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
 249                                 }
 250
 251                                 /* silence detection */
 252
 253                                 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
 254                                         activity = ACT_RX;
 255
 256                                 if(!(IF_QFULL(&chan->rx_queue)))
 257                                 {
 258                                         IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
 259                                 }
 260                                 else
 261                                 {
 262                                         i4b_Bfreembuf(chan->in_mbuf);
 263                                 }
 264                                 /* signal upper driver that data is available */
 265
 266                                 (*chan->iwic_drvr_linktab->bch_rx_data_ready)(chan->iwic_drvr_linktab->unit);
 267
 268                                 /* alloc new buffer */
 269
 270                                 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
 271                                         panic("L1 iwic_bchan_irq: RMR, cannot allocate new mbuf!\n");
 272
 273                                 /* setup new data ptr */
 274
 275                                 chan->in_cbptr = chan->in_mbuf->m_data;
 276
 277                                 /* read data from fifo */
 278
 279                                 NDBGL1(L1_H_IRQ, "B_EXIR_RMR, rd fifo1, len = max (64)");
 280
 281                                 IWIC_RDBFIFO(sc, chan, chan->in_cbptr, IWIC_BCHAN_FIFO_LEN);
 282
 283                                 chan->in_cbptr += IWIC_BCHAN_FIFO_LEN;
 284                                 chan->in_len = IWIC_BCHAN_FIFO_LEN;
 285
 286                                 chan->rxcount += IWIC_BCHAN_FIFO_LEN;
 287                         }
 288                         else
 289                         {
 290                                 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
 291                                 chan->in_cbptr = chan->in_mbuf->m_data;
 292                                 chan->in_len = 0;
 293                                 cmd |= (B_CMDR_RRST | B_CMDR_RACK);
 294                         }
 295                 }
 296
 297                 /* command to release fifo space */
 298
 299                 cmd |= B_CMDR_RACK;
 300         }
 301
 302 /* TX interrupt */
 303
 304         if (irq_stat & B_EXIR_XFR)
 305         {
 306                 /* transmit fifo empty, new data can be written to fifo */
 307
 308                 int activity = -1;
 309                 int len;
 310                 int nextlen;
 311
 312                 NDBGL1(L1_H_IRQ, "B_EXIR_XFR");
 313
 314                 if(chan->out_mbuf_cur == NULL)  /* last frame is transmitted */
 315                 {
 316                         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 317
 318                         if(chan->out_mbuf_head == NULL)
 319                         {
 320                                 chan->state &= ~ST_TX_ACTIVE;
 321                                 (*chan->iwic_drvr_linktab->bch_tx_queue_empty)(chan->iwic_drvr_linktab->unit);
 322                         }
 323                         else
 324                         {
 325                                 chan->state |= ST_TX_ACTIVE;
 326                                 chan->out_mbuf_cur = chan->out_mbuf_head;
 327                                 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 328                                 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 329
 330                                 if(sc->sc_trace & TRACE_B_TX)
 331                                 {
 332                                         i4b_trace_hdr_t hdr;
 333                                         hdr.unit = L0IWICUNIT(sc->sc_unit);
 334                                         hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 335                                         hdr.dir = FROM_TE;
 336                                         hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 337                                         MICROTIME(hdr.time);
 338                                         i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 339                                 }
 340
 341                                 if(chan->bprot == BPROT_NONE)
 342                                 {
 343                                         if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 344                                                 activity = ACT_TX;
 345                                 }
 346                                 else
 347                                 {
 348                                         activity = ACT_TX;
 349                                 }
 350                         }
 351                 }
 352
 353                 len = 0;
 354
 355                 while(chan->out_mbuf_cur && len != IWIC_BCHAN_FIFO_LEN)
 356                 {
 357                         nextlen = min(chan->out_mbuf_cur_len, IWIC_BCHAN_FIFO_LEN - len);
 358
 359                         NDBGL1(L1_H_IRQ, "B_EXIR_XFR, wr fifo, len = %d", nextlen);
 360
 361                         IWIC_WRBFIFO(sc, chan, chan->out_mbuf_cur_ptr, nextlen);
 362
 363                         cmd |= B_CMDR_XMS;
 364
 365                         len += nextlen;
 366                         chan->txcount += nextlen;
 367
 368                         chan->out_mbuf_cur_ptr += nextlen;
 369                         chan->out_mbuf_cur_len -= nextlen;
 370
 371                         if(chan->out_mbuf_cur_len == 0)
 372                         {
 373                                 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
 374                                 {
 375                                         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 376                                         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 377
 378                                         if(sc->sc_trace & TRACE_B_TX)
 379                                         {
 380                                                 i4b_trace_hdr_t hdr;
 381                                                 hdr.unit = L0IWICUNIT(sc->sc_unit);
 382                                                 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 383                                                 hdr.dir = FROM_TE;
 384                                                 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 385                                                 MICROTIME(hdr.time);
 386                                                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 387                                         }
 388                                 }
 389                                 else
 390                                 {
 391                                         if (chan->bprot != BPROT_NONE)
 392                                                 cmd |= B_CMDR_XME;
 393                                         i4b_Bfreembuf(chan->out_mbuf_head);
 394                                         chan->out_mbuf_head = NULL;
 395                                 }
 396                         }
 397                 }
 398         }
 399         if(cmd)
 400         {
 401                 cmd |= B_CMDR_RACT;
 402                 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
 403         }
 404 }
 405
 406 /*---------------------------------------------------------------------------*
 407  *      initialize one B channels rx/tx data structures
 408  *---------------------------------------------------------------------------*/
 409 void
 410 iwic_bchannel_setup(int unit, int chan_no, int bprot, int activate)
 411 {
 412         struct iwic_softc *sc = &iwic_sc[unit];
 413         struct iwic_bchan *chan = &sc->sc_bchan[chan_no];
 414
 415         crit_enter();
 416
 417         NDBGL1(L1_BCHAN, "unit %d, chan %d, bprot %d, activate %d", unit, chan_no, bprot, activate);
 418
 419         /* general part */
 420
 421         chan->bprot = bprot;            /* B channel protocol */
 422         chan->state = ST_IDLE;          /* B channel state */
 423
 424         if(activate == 0)
 425         {
 426                 /* deactivation */
 427                 iwic_bchan_init(sc, chan_no, activate);
 428         }
 429
 430         /* receiver part */
 431
 432         chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
 433
 434         i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
 435
 436         chan->rxcount = 0;              /* reset rx counter */
 437
 438         i4b_Bfreembuf(chan->in_mbuf);   /* clean rx mbuf */
 439
 440         chan->in_mbuf = NULL;           /* reset mbuf ptr */
 441         chan->in_cbptr = NULL;          /* reset mbuf curr ptr */
 442         chan->in_len = 0;               /* reset mbuf data len */
 443
 444         /* transmitter part */
 445
 446         chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
 447
 448         i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
 449
 450         chan->txcount = 0;              /* reset tx counter */
 451
 452         i4b_Bfreembuf(chan->out_mbuf_head);     /* clean tx mbuf */
 453
 454         chan->out_mbuf_head = NULL;     /* reset head mbuf ptr */
 455         chan->out_mbuf_cur = NULL;      /* reset current mbuf ptr */
 456         chan->out_mbuf_cur_ptr = NULL;  /* reset current mbuf data ptr */
 457         chan->out_mbuf_cur_len = 0;     /* reset current mbuf data cnt */
 458
 459         if(activate != 0)
 460         {
 461                 /* activation */
 462                 iwic_bchan_init(sc, chan_no, activate);
 463         }
 464
 465         crit_exit();
 466 }
 467
 468 /*---------------------------------------------------------------------------*
 469  *      initalize / deinitialize B-channel hardware
 470  *---------------------------------------------------------------------------*/
 471 static void
 472 iwic_bchan_init(struct iwic_softc *sc, int chan_no, int activate)
 473 {
 474         struct iwic_bchan *bchan = &sc->sc_bchan[chan_no];
 475
 476         NDBGL1(L1_BCHAN, "chan %d, activate %d", chan_no, activate);
 477
 478         if(activate)
 479         {
 480                 if(bchan->bprot == BPROT_NONE)
 481                 {
 482                         /* Extended transparent mode */
 483                         IWIC_WRITE(sc, bchan->offset + B_MODE, B_MODE_MMS);
 484                 }
 485                 else
 486                 {
 487                         /* Transparent mode */
 488                         IWIC_WRITE(sc, bchan->offset + B_MODE, 0);
 489                         /* disable address comparation */
 490                         IWIC_WRITE (sc, bchan->offset+B_ADM1, 0xff);
 491                         IWIC_WRITE (sc, bchan->offset+B_ADM2, 0xff);
 492                 }
 493
 494                 /* reset & start receiver */
 495                 IWIC_WRITE(sc, bchan->offset + B_CMDR, B_CMDR_RRST|B_CMDR_RACT);
 496
 497                 /* clear irq mask */
 498                 IWIC_WRITE(sc, bchan->offset + B_EXIM, 0);
 499         }
 500         else
 501         {
 502                 /* mask all irqs */
 503                 IWIC_WRITE(sc, bchan->offset + B_EXIM, 0xff);
 504
 505                 /* reset mode */
 506                 IWIC_WRITE(sc, bchan->offset + B_MODE, 0);
 507
 508                 /* Bring interface down */
 509                 IWIC_WRITE(sc, bchan->offset + B_CMDR, B_CMDR_RRST | B_CMDR_XRST);
 510
 511                 /* Flush pending interrupts */
 512                 IWIC_READ(sc, bchan->offset + B_EXIR);
 513         }
 514 }
 515
 516 /*---------------------------------------------------------------------------*
 517  *      start transmission on a b channel
 518  *---------------------------------------------------------------------------*/
 519 static void
 520 iwic_bchannel_start(int unit, int chan_no)
 521 {
 522         struct iwic_softc *sc = &iwic_sc[unit];
 523         struct iwic_bchan *chan = &sc->sc_bchan[chan_no];
 524         int next_len;
 525         int len;
 526         int activity = -1;
 527         int cmd = 0;
 528
 529         crit_enter();
 530
 531         NDBGL1(L1_BCHAN, "unit %d, channel %d", unit, chan_no);
 532
 533         if(chan->state & ST_TX_ACTIVE)          /* already running ? */
 534         {
 535                 crit_exit();
 536                 return;                         /* yes, leave */
 537         }
 538
 539         /* get next mbuf from queue */
 540
 541         IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
 542
 543         if(chan->out_mbuf_head == NULL)         /* queue empty ? */
 544         {
 545                 crit_exit();
 546                 return;                         /* yes, exit */
 547         }
 548
 549         /* init current mbuf values */
 550
 551         chan->out_mbuf_cur = chan->out_mbuf_head;
 552         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 553         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 554
 555         /* activity indicator for timeout handling */
 556
 557         if(chan->bprot == BPROT_NONE)
 558         {
 559                 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
 560                         activity = ACT_TX;
 561         }
 562         else
 563         {
 564                 activity = ACT_TX;
 565         }
 566
 567         chan->state |= ST_TX_ACTIVE;            /* we start transmitting */
 568
 569         if(sc->sc_trace & TRACE_B_TX)   /* if trace, send mbuf to trace dev */
 570         {
 571                 i4b_trace_hdr_t hdr;
 572                 hdr.unit = L0IWICUNIT(unit);
 573                 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 574                 hdr.dir = FROM_TE;
 575                 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 576                 MICROTIME(hdr.time);
 577                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 578         }
 579
 580         len = 0;        /* # of chars put into tx fifo this time */
 581
 582         /*
 583          * fill the tx fifo with data from the current mbuf. if
 584          * current mbuf holds less data than fifo length, try to
 585          * get the next mbuf from (a possible) mbuf chain. if there is
 586          * not enough data in a single mbuf or in a chain, then this
 587          * is the last mbuf and we tell the chip that it has to send
 588          * CRC and closing flag
 589          */
 590
 591         while((len < IWIC_BCHAN_FIFO_LEN) && chan->out_mbuf_cur)
 592         {
 593                 /*
 594                  * put as much data into the fifo as is
 595                  * available from the current mbuf
 596                  */
 597
 598                 if((len + chan->out_mbuf_cur_len) >= IWIC_BCHAN_FIFO_LEN)
 599                         next_len = IWIC_BCHAN_FIFO_LEN - len;
 600                 else
 601                         next_len = chan->out_mbuf_cur_len;
 602
 603                 /* write what we have from current mbuf to fifo */
 604
 605                 IWIC_WRBFIFO(sc, chan, chan->out_mbuf_cur_ptr, next_len);
 606
 607                 len += next_len;                /* update # of bytes written */
 608                 chan->txcount += next_len;      /* statistics */
 609                 chan->out_mbuf_cur_ptr += next_len;     /* data ptr */
 610                 chan->out_mbuf_cur_len -= next_len;     /* data len */
 611
 612                 /*
 613                  * in case the current mbuf (of a possible chain) data
 614                  * has been put into the fifo, check if there is a next
 615                  * mbuf in the chain. If there is one, get ptr to it
 616                  * and update the data ptr and the length
 617                  */
 618
 619                 if((chan->out_mbuf_cur_len <= 0)        &&
 620                   ((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL))
 621                 {
 622                         chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
 623                         chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
 624
 625                         if(sc->sc_trace & TRACE_B_TX)
 626                         {
 627                                 i4b_trace_hdr_t hdr;
 628                                 hdr.unit = L0IWICUNIT(unit);
 629                                 hdr.type = (chan_no == IWIC_BCH_A ? TRC_CH_B1 : TRC_CH_B2);
 630                                 hdr.dir = FROM_TE;
 631                                 hdr.count = ++sc->sc_bchan[chan_no].sc_trace_bcount;
 632                                 MICROTIME(hdr.time);
 633                                 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
 634                         }
 635                 }
 636         }
 637
 638         /*
 639          * if there is either still data in the current mbuf and/or
 640          * there is a successor on the chain available issue just
 641          * a XTF (transmit) command to the chip. if there is no more
 642          * data available from the current mbuf (-chain), issue
 643          * an XTF and an XME (message end) command which will then
 644          * send the CRC and the closing HDLC flag sequence
 645          */
 646
 647         if(chan->out_mbuf_cur && (chan->out_mbuf_cur_len > 0))
 648         {
 649                 /*
 650                  * more data available, send current fifo out.
 651                  * next xfer to tx fifo is done in the
 652                  * interrupt routine.
 653                  */
 654
 655                 cmd |= B_CMDR_XMS;
 656         }
 657         else
 658         {
 659                 /* end of mbuf chain */
 660
 661                 if(chan->bprot == BPROT_NONE)
 662                         cmd |= B_CMDR_XMS;
 663                 else
 664                         cmd |= (B_CMDR_XMS | B_CMDR_XME);
 665
 666                 i4b_Bfreembuf(chan->out_mbuf_head);     /* free mbuf chain */
 667
 668                 chan->out_mbuf_head = NULL;
 669                 chan->out_mbuf_cur = NULL;
 670                 chan->out_mbuf_cur_ptr = NULL;
 671                 chan->out_mbuf_cur_len = 0;
 672         }
 673
 674         /* call timeout handling routine */
 675
 676         if(activity == ACT_RX || activity == ACT_TX)
 677                 (*chan->iwic_drvr_linktab->bch_activity)(chan->iwic_drvr_linktab->unit, activity);
 678
 679         if(cmd)
 680         {
 681                 cmd |= B_CMDR_RACT;
 682                 IWIC_WRITE(sc, chan->offset + B_CMDR, cmd);
 683         }
 684
 685         crit_exit();
 686 }
 687
 688 /*---------------------------------------------------------------------------*
 689  *      return B-channel statistics
 690  *---------------------------------------------------------------------------*/
 691 static void
 692 iwic_bchannel_stat(int unit, int chan_no, bchan_statistics_t *bsp)
 693 {
 694         struct iwic_softc *sc = iwic_find_sc(unit);
 695         struct iwic_bchan *bchan = &sc->sc_bchan[chan_no];
 696
 697         crit_enter();
 698
 699         bsp->outbytes = bchan->txcount;
 700         bsp->inbytes = bchan->rxcount;
 701
 702         bchan->txcount = 0;
 703         bchan->rxcount = 0;
 704
 705         crit_exit();
 706 }
 707
 708 /*---------------------------------------------------------------------------*
 709  *      initialize our local linktab
 710  *---------------------------------------------------------------------------*/
 711 void
 712 iwic_init_linktab(struct iwic_softc *sc)
 713 {
 714         struct iwic_bchan *chan;
 715         isdn_link_t *lt;
 716
 717         /* make sure the hardware driver is known to layer 4 */
 718         ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
 719         ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
 720
 721         /* channel A */
 722
 723         chan = &sc->sc_bchan[IWIC_BCH_A];
 724         lt = &chan->iwic_isdn_linktab;
 725
 726         lt->unit = sc->sc_unit;
 727         lt->channel = IWIC_BCH_A;
 728         lt->bch_config = iwic_bchannel_setup;
 729         lt->bch_tx_start = iwic_bchannel_start;
 730         lt->bch_stat = iwic_bchannel_stat;
 731         lt->tx_queue = &chan->tx_queue;
 732
 733         /* used by non-HDLC data transfers, i.e. telephony drivers */
 734         lt->rx_queue = &chan->rx_queue;
 735
 736         /* used by HDLC data transfers, i.e. ipr and isp drivers */
 737         lt->rx_mbuf = &chan->in_mbuf;
 738
 739         /* channel B */
 740
 741         chan = &sc->sc_bchan[IWIC_BCH_B];
 742         lt = &chan->iwic_isdn_linktab;
 743
 744         lt->unit = sc->sc_unit;
 745         lt->channel = IWIC_BCH_B;
 746         lt->bch_config = iwic_bchannel_setup;
 747         lt->bch_tx_start = iwic_bchannel_start;
 748         lt->bch_stat = iwic_bchannel_stat;
 749         lt->tx_queue = &chan->tx_queue;
 750
 751         /* used by non-HDLC data transfers, i.e. telephony drivers */
 752         lt->rx_queue = &chan->rx_queue;
 753
 754         /* used by HDLC data transfers, i.e. ipr and isp drivers */
 755         lt->rx_mbuf = &chan->in_mbuf;
 756 }
 757
 758 #endif /* NIWIC > 0 */