2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/mpapic.h>
58 #include <machine/psl.h>
59 #include <machine/segments.h>
60 #include <machine/tss.h>
61 #include <machine/specialreg.h>
62 #include <machine/globaldata.h>
63 #include <machine/pmap_inval.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/apic/ioapic_abi.h>
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 #define MPTABLE_POS_USE_DEFAULT(mpt) \
172 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
176 int mb_type; /* MPTABLE_BUS_ */
177 TAILQ_ENTRY(mptable_bus) mb_link;
180 #define MPTABLE_BUS_ISA 0
181 #define MPTABLE_BUS_PCI 1
183 struct mptable_bus_info {
184 TAILQ_HEAD(, mptable_bus) mbi_list;
187 struct mptable_pci_int {
194 TAILQ_ENTRY(mptable_pci_int) mpci_link;
197 struct mptable_ioapic {
203 TAILQ_ENTRY(mptable_ioapic) mio_link;
206 typedef int (*mptable_iter_func)(void *, const void *, int);
209 * this code MUST be enabled here and in mpboot.s.
210 * it follows the very early stages of AP boot by placing values in CMOS ram.
211 * it NORMALLY will never be needed and thus the primitive method for enabling.
214 #if defined(CHECK_POINTS)
215 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
216 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
218 #define CHECK_INIT(D); \
219 CHECK_WRITE(0x34, (D)); \
220 CHECK_WRITE(0x35, (D)); \
221 CHECK_WRITE(0x36, (D)); \
222 CHECK_WRITE(0x37, (D)); \
223 CHECK_WRITE(0x38, (D)); \
224 CHECK_WRITE(0x39, (D));
226 #define CHECK_PRINT(S); \
227 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
236 #else /* CHECK_POINTS */
238 #define CHECK_INIT(D)
239 #define CHECK_PRINT(S)
241 #endif /* CHECK_POINTS */
244 * Values to send to the POST hardware.
246 #define MP_BOOTADDRESS_POST 0x10
247 #define MP_PROBE_POST 0x11
248 #define MPTABLE_PASS1_POST 0x12
250 #define MP_START_POST 0x13
251 #define MP_ENABLE_POST 0x14
252 #define MPTABLE_PASS2_POST 0x15
254 #define START_ALL_APS_POST 0x16
255 #define INSTALL_AP_TRAMP_POST 0x17
256 #define START_AP_POST 0x18
258 #define MP_ANNOUNCE_POST 0x19
260 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
261 int current_postcode;
263 /** XXX FIXME: what system files declare these??? */
264 extern struct region_descriptor r_gdt, r_idt;
266 int mp_naps; /* # of Applications processors */
267 #ifdef SMP /* APIC-IO */
268 static int mp_nbusses; /* # of busses */
269 int mp_napics; /* # of IO APICs */
270 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
271 u_int32_t *io_apic_versions;
275 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
277 extern int64_t tsc_offsets[];
279 extern u_long ebda_addr;
281 #ifdef SMP /* APIC-IO */
282 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
286 * APIC ID logical/physical mapping structures.
287 * We oversize these to simplify boot-time config.
289 int cpu_num_to_apic_id[NAPICID];
290 #ifdef SMP /* APIC-IO */
291 int io_num_to_apic_id[NAPICID];
293 int apic_id_to_logical[NAPICID];
295 /* AP uses this during bootstrap. Do not staticize. */
299 struct pcb stoppcbs[MAXCPU];
301 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
303 static basetable_entry basetable_entry_types[] =
305 {0, 20, "Processor"},
313 * Local data and functions.
316 static u_int boot_address;
317 static u_int base_memory;
318 static int mp_finish;
319 static int mp_finish_lapic;
321 static void mp_enable(u_int boot_addr);
323 static int mptable_iterate_entries(const mpcth_t,
324 mptable_iter_func, void *);
325 static int mptable_search(void);
326 static long mptable_search_sig(u_int32_t target, int count);
327 static int mptable_hyperthread_fixup(cpumask_t, int);
328 #ifdef SMP /* APIC-IO */
329 static void mptable_pass1(struct mptable_pos *);
330 static void mptable_pass2(struct mptable_pos *);
331 static void mptable_default(int type);
332 static void mptable_fix(void);
334 static int mptable_map(struct mptable_pos *);
335 static void mptable_unmap(struct mptable_pos *);
336 static void mptable_bus_info_alloc(const mpcth_t,
337 struct mptable_bus_info *);
338 static void mptable_bus_info_free(struct mptable_bus_info *);
340 static int mptable_lapic_probe(struct lapic_enumerator *);
341 static void mptable_lapic_enumerate(struct lapic_enumerator *);
342 static void mptable_lapic_default(void);
344 static int mptable_ioapic_probe(struct ioapic_enumerator *);
345 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
347 #ifdef SMP /* APIC-IO */
348 static void setup_apic_irq_mapping(void);
349 static int apic_int_is_bus_type(int intr, int bus_type);
351 static int start_all_aps(u_int boot_addr);
353 static void install_ap_tramp(u_int boot_addr);
355 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
356 static int smitest(void);
358 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
359 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
360 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
361 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
362 static u_int bootMP_size;
366 static vm_paddr_t mptable_fps_phyaddr;
367 static int mptable_use_default;
368 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
369 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
370 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
371 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
374 * Calculate usable address in base memory for AP trampoline code.
377 mp_bootaddress(u_int basemem)
379 POSTCODE(MP_BOOTADDRESS_POST);
381 base_memory = basemem;
383 bootMP_size = mptramp_end - mptramp_start;
384 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
385 if (((basemem * 1024) - boot_address) < bootMP_size)
386 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
387 /* 3 levels of page table pages */
388 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
390 return mptramp_pagetables;
397 struct mptable_pos mpt;
400 KKASSERT(mptable_fps_phyaddr == 0);
402 mptable_fps_phyaddr = mptable_search();
403 if (mptable_fps_phyaddr == 0)
406 error = mptable_map(&mpt);
408 mptable_fps_phyaddr = 0;
412 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
413 kprintf("MPTABLE: use default configuration\n");
414 mptable_use_default = 1;
416 if (mpt.mp_fps->mpfb2 & 0x80)
421 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
424 * Look for an Intel MP spec table (ie, SMP capable hardware).
432 POSTCODE(MP_PROBE_POST);
434 /* see if EBDA exists */
435 if (ebda_addr != 0) {
436 /* search first 1K of EBDA */
437 target = (u_int32_t)ebda_addr;
438 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
441 /* last 1K of base memory, effective 'top of base' passed in */
442 target = (u_int32_t)(base_memory - 0x400);
443 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
447 /* search the BIOS */
448 target = (u_int32_t)BIOS_BASE;
449 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
452 /* search the extended BIOS */
453 target = (u_int32_t)BIOS_BASE2;
454 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
462 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
464 int count, total_size;
465 const void *position;
467 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
468 total_size = cth->base_table_length - sizeof(struct MPCTH);
469 position = (const uint8_t *)cth + sizeof(struct MPCTH);
470 count = cth->entry_count;
475 KKASSERT(total_size >= 0);
476 if (total_size == 0) {
477 kprintf("invalid base MP table, "
478 "entry count and length mismatch\n");
482 type = *(const uint8_t *)position;
484 case 0: /* processor_entry */
485 case 1: /* bus_entry */
486 case 2: /* io_apic_entry */
487 case 3: /* int_entry */
488 case 4: /* int_entry */
491 kprintf("unknown base MP table entry type %d\n", type);
495 if (total_size < basetable_entry_types[type].length) {
496 kprintf("invalid base MP table length, "
497 "does not contain all entries\n");
500 total_size -= basetable_entry_types[type].length;
502 error = func(arg, position, type);
506 position = (const uint8_t *)position +
507 basetable_entry_types[type].length;
514 * Startup the SMP processors.
519 POSTCODE(MP_START_POST);
520 mp_enable(boot_address);
525 * Print various information about the SMP system hardware and setup.
532 POSTCODE(MP_ANNOUNCE_POST);
534 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
535 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
536 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
537 for (x = 1; x <= mp_naps; ++x) {
538 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
539 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
542 if (apic_io_enable) {
543 if (ioapic_use_old) {
544 for (x = 0; x < mp_napics; ++x) {
545 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
546 kprintf(", version: 0x%08x", io_apic_versions[x]);
547 kprintf(", at 0x%08lx\n", io_apic_address[x]);
551 kprintf(" Warning: APIC I/O disabled\n");
556 * AP cpu's call this to sync up protected mode.
558 * WARNING! %gs is not set up on entry. This routine sets up %gs.
564 int x, myid = bootAP;
566 struct mdglobaldata *md;
567 struct privatespace *ps;
569 ps = &CPU_prvspace[myid];
571 gdt_segs[GPROC0_SEL].ssd_base =
572 (long) &ps->mdglobaldata.gd_common_tss;
573 ps->mdglobaldata.mi.gd_prvspace = ps;
575 /* We fill the 32-bit segment descriptors */
576 for (x = 0; x < NGDT; x++) {
577 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
578 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
580 /* And now a 64-bit one */
581 ssdtosyssd(&gdt_segs[GPROC0_SEL],
582 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
584 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
585 r_gdt.rd_base = (long) &gdt[myid * NGDT];
586 lgdt(&r_gdt); /* does magic intra-segment return */
588 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
589 wrmsr(MSR_FSBASE, 0); /* User value */
590 wrmsr(MSR_GSBASE, (u_int64_t)ps);
591 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
597 mdcpu->gd_currentldt = _default_ldt;
600 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
601 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
603 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
605 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
607 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
609 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
610 md->gd_common_tssd = *md->gd_tss_gdt;
612 /* double fault stack */
613 md->gd_common_tss.tss_ist1 =
614 (long)&md->mi.gd_prvspace->idlestack[
615 sizeof(md->mi.gd_prvspace->idlestack)];
620 * Set to a known state:
621 * Set by mpboot.s: CR0_PG, CR0_PE
622 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
625 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
628 /* Set up the fast syscall stuff */
629 msr = rdmsr(MSR_EFER) | EFER_SCE;
630 wrmsr(MSR_EFER, msr);
631 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
632 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
633 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
634 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
635 wrmsr(MSR_STAR, msr);
636 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
638 pmap_set_opt(); /* PSE/4MB pages, etc */
640 /* Initialize the PAT MSR. */
644 /* set up CPU registers and state */
647 /* set up SSE/NX registers */
650 /* set up FPU state on the AP */
651 npxinit(__INITIAL_NPXCW__);
653 /* disable the APIC, just to be SURE */
654 lapic->svr &= ~APIC_SVR_ENABLE;
656 /* data returned to BSP */
657 cpu_apic_versions[0] = lapic->version;
660 /*******************************************************************
661 * local functions and data
665 * start the SMP system
668 mp_enable(u_int boot_addr)
672 struct mptable_pos mpt;
674 POSTCODE(MP_ENABLE_POST);
678 /* Initialize BSP's local APIC */
681 /* start each Application Processor */
682 start_all_aps(boot_addr);
687 if (apic_io_enable && ioapic_use_old) {
690 if (!mptable_fps_phyaddr)
691 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
699 * Switch to I/O APIC MachIntrABI and reconfigure
700 * the default IDT entries.
702 MachIntrABI = MachIntrABI_IOAPIC;
703 MachIntrABI.setdefault();
708 * Examine the MP table for needed info
715 /* Post scan cleanup */
718 setup_apic_irq_mapping();
720 /* fill the LOGICAL io_apic_versions table */
721 for (apic = 0; apic < mp_napics; ++apic) {
722 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
723 io_apic_versions[apic] = ux;
724 io_apic_set_id(apic, IO_TO_ID(apic));
727 /* program each IO APIC in the system */
728 for (apic = 0; apic < mp_napics; ++apic)
729 if (io_apic_setup(apic) < 0)
730 panic("IO APIC setup failure");
734 MachIntrABI.cleanup();
740 MachIntrABI.finalize();
745 * look for the MP spec signature
748 /* string defined by the Intel MP Spec as identifying the MP table */
749 #define MP_SIG 0x5f504d5f /* _MP_ */
750 #define NEXT(X) ((X) += 4)
752 mptable_search_sig(u_int32_t target, int count)
758 KKASSERT(target != 0);
760 map_size = count * sizeof(u_int32_t);
761 addr = pmap_mapdev((vm_paddr_t)target, map_size);
764 for (x = 0; x < count; NEXT(x)) {
765 if (addr[x] == MP_SIG) {
766 /* make array index a byte index */
767 ret = target + (x * sizeof(u_int32_t));
772 pmap_unmapdev((vm_offset_t)addr, map_size);
777 typedef struct BUSDATA {
779 enum busTypes bus_type;
782 typedef struct INTDATA {
792 typedef struct BUSTYPENAME {
797 static bus_type_name bus_type_table[] =
803 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
810 {UNKNOWN_BUSTYPE, "---"},
812 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
815 {UNKNOWN_BUSTYPE, "---"},
817 {UNKNOWN_BUSTYPE, "---"}
820 /* from MP spec v1.4, table 5-1 */
821 static int default_data[7][5] =
823 /* nbus, id0, type0, id1, type1 */
824 {1, 0, ISA, 255, 255},
825 {1, 0, EISA, 255, 255},
826 {1, 0, EISA, 255, 255},
827 {1, 0, MCA, 255, 255},
829 {2, 0, EISA, 1, PCI},
834 static bus_datum *bus_data;
836 /* the IO INT data, one entry per possible APIC INTerrupt */
837 static io_int *io_apic_ints;
840 static int processor_entry (const struct PROCENTRY *entry, int cpu);
841 static int bus_entry (const struct BUSENTRY *entry, int bus);
842 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
843 static int int_entry (const struct INTENTRY *entry, int intr);
844 static int lookup_bus_type (char *name);
847 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
849 const struct IOAPICENTRY *ioapic_ent;
852 case 1: /* bus_entry */
856 case 2: /* io_apic_entry */
858 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
859 io_apic_address[mp_napics++] =
860 (vm_offset_t)ioapic_ent->apic_address;
864 case 3: /* int_entry */
872 * 1st pass on motherboard's Intel MP specification table.
881 mptable_pass1(struct mptable_pos *mpt)
886 POSTCODE(MPTABLE_PASS1_POST);
889 KKASSERT(fps != NULL);
891 /* clear various tables */
892 for (x = 0; x < NAPICID; ++x)
893 io_apic_address[x] = ~0; /* IO APIC address table */
899 /* check for use of 'default' configuration */
900 if (fps->mpfb1 != 0) {
901 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
902 mp_nbusses = default_data[fps->mpfb1 - 1][0];
908 error = mptable_iterate_entries(mpt->mp_cth,
909 mptable_ioapic_pass1_callback, NULL);
911 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
915 struct mptable_ioapic2_cbarg {
922 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
924 struct mptable_ioapic2_cbarg *arg = xarg;
928 if (bus_entry(pos, arg->bus))
933 if (io_apic_entry(pos, arg->apic))
938 if (int_entry(pos, arg->intr))
946 * 2nd pass on motherboard's Intel MP specification table.
949 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
950 * IO_TO_ID(N), logical IO to APIC ID table
955 mptable_pass2(struct mptable_pos *mpt)
957 struct mptable_ioapic2_cbarg arg;
961 POSTCODE(MPTABLE_PASS2_POST);
964 KKASSERT(fps != NULL);
966 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
968 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
969 M_DEVBUF, M_WAITOK | M_ZERO);
970 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
972 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
975 for (x = 0; x < mp_napics; x++)
976 ioapic[x] = ioapic_map(io_apic_address[x]);
978 /* clear various tables */
979 for (x = 0; x < NAPICID; ++x) {
980 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
981 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
984 /* clear bus data table */
985 for (x = 0; x < mp_nbusses; ++x)
986 bus_data[x].bus_id = 0xff;
988 /* clear IO APIC INT table */
989 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
990 io_apic_ints[x].int_type = 0xff;
991 io_apic_ints[x].int_vector = 0xff;
994 /* check for use of 'default' configuration */
995 if (fps->mpfb1 != 0) {
996 mptable_default(fps->mpfb1);
1000 bzero(&arg, sizeof(arg));
1001 error = mptable_iterate_entries(mpt->mp_cth,
1002 mptable_ioapic_pass2_callback, &arg);
1004 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1020 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1022 int i, id, lcpus_max, logical_cpus;
1024 if ((cpu_feature & CPUID_HTT) == 0)
1027 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1031 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1033 * INSTRUCTION SET REFERENCE, A-M (#253666)
1034 * Page 3-181, Table 3-20
1035 * "The nearest power-of-2 integer that is not smaller
1036 * than EBX[23:16] is the number of unique initial APIC
1037 * IDs reserved for addressing different logical
1038 * processors in a physical package."
1040 for (i = 0; ; ++i) {
1041 if ((1 << i) >= lcpus_max) {
1048 KKASSERT(cpu_count != 0);
1049 if (cpu_count == lcpus_max) {
1050 /* We have nothing to fix */
1052 } else if (cpu_count == 1) {
1053 /* XXX this may be incorrect */
1054 logical_cpus = lcpus_max;
1056 int cur, prev, dist;
1059 * Calculate the distances between two nearest
1060 * APIC IDs. If all such distances are same,
1061 * then it is the number of missing cpus that
1062 * we are going to fill later.
1064 dist = cur = prev = -1;
1065 for (id = 0; id < MAXCPU; ++id) {
1066 if ((id_mask & CPUMASK(id)) == 0)
1071 int new_dist = cur - prev;
1077 * Make sure that all distances
1078 * between two nearest APIC IDs
1081 if (dist != new_dist)
1089 /* Must be power of 2 */
1090 if (dist & (dist - 1))
1093 /* Can't exceed CPU package capacity */
1094 if (dist > lcpus_max)
1095 logical_cpus = lcpus_max;
1097 logical_cpus = dist;
1101 * For each APIC ID of a CPU that is set in the mask,
1102 * scan the other candidate APIC ID's for this
1103 * physical processor. If any of those ID's are
1104 * already in the table, then kill the fixup.
1106 for (id = 0; id < MAXCPU; id++) {
1107 if ((id_mask & CPUMASK(id)) == 0)
1109 /* First, make sure we are on a logical_cpus boundary. */
1110 if (id % logical_cpus != 0)
1112 for (i = id + 1; i < id + logical_cpus; i++)
1113 if ((id_mask & CPUMASK(i)) != 0)
1116 return logical_cpus;
1120 mptable_map(struct mptable_pos *mpt)
1124 vm_size_t cth_mapsz = 0;
1126 KKASSERT(mptable_fps_phyaddr != 0);
1128 bzero(mpt, sizeof(*mpt));
1130 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1131 if (fps->pap != 0) {
1133 * Map configuration table header to get
1134 * the base table size
1136 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1137 cth_mapsz = cth->base_table_length;
1138 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1140 if (cth_mapsz < sizeof(*cth)) {
1141 kprintf("invalid base MP table length %d\n",
1143 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1148 * Map the base table
1150 cth = pmap_mapdev(fps->pap, cth_mapsz);
1155 mpt->mp_cth_mapsz = cth_mapsz;
1161 mptable_unmap(struct mptable_pos *mpt)
1163 if (mpt->mp_cth != NULL) {
1164 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1166 mpt->mp_cth_mapsz = 0;
1168 if (mpt->mp_fps != NULL) {
1169 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1175 assign_apic_irq(int apic, int intpin, int irq)
1179 if (int_to_apicintpin[irq].ioapic != -1)
1180 panic("assign_apic_irq: inconsistent table");
1182 int_to_apicintpin[irq].ioapic = apic;
1183 int_to_apicintpin[irq].int_pin = intpin;
1184 int_to_apicintpin[irq].apic_address = ioapic[apic];
1185 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1187 for (x = 0; x < nintrs; x++) {
1188 if ((io_apic_ints[x].int_type == 0 ||
1189 io_apic_ints[x].int_type == 3) &&
1190 io_apic_ints[x].int_vector == 0xff &&
1191 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1192 io_apic_ints[x].dst_apic_int == intpin)
1193 io_apic_ints[x].int_vector = irq;
1198 revoke_apic_irq(int irq)
1204 if (int_to_apicintpin[irq].ioapic == -1)
1205 panic("revoke_apic_irq: inconsistent table");
1207 oldapic = int_to_apicintpin[irq].ioapic;
1208 oldintpin = int_to_apicintpin[irq].int_pin;
1210 int_to_apicintpin[irq].ioapic = -1;
1211 int_to_apicintpin[irq].int_pin = 0;
1212 int_to_apicintpin[irq].apic_address = NULL;
1213 int_to_apicintpin[irq].redirindex = 0;
1215 for (x = 0; x < nintrs; x++) {
1216 if ((io_apic_ints[x].int_type == 0 ||
1217 io_apic_ints[x].int_type == 3) &&
1218 io_apic_ints[x].int_vector != 0xff &&
1219 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1220 io_apic_ints[x].dst_apic_int == oldintpin)
1221 io_apic_ints[x].int_vector = 0xff;
1229 allocate_apic_irq(int intr)
1235 if (io_apic_ints[intr].int_vector != 0xff)
1236 return; /* Interrupt handler already assigned */
1238 if (io_apic_ints[intr].int_type != 0 &&
1239 (io_apic_ints[intr].int_type != 3 ||
1240 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1241 io_apic_ints[intr].dst_apic_int == 0)))
1242 return; /* Not INT or ExtInt on != (0, 0) */
1245 while (irq < APIC_INTMAPSIZE &&
1246 int_to_apicintpin[irq].ioapic != -1)
1249 if (irq >= APIC_INTMAPSIZE)
1250 return; /* No free interrupt handlers */
1252 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1253 intpin = io_apic_ints[intr].dst_apic_int;
1255 assign_apic_irq(apic, intpin, irq);
1260 swap_apic_id(int apic, int oldid, int newid)
1267 return; /* Nothing to do */
1269 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1270 apic, oldid, newid);
1272 /* Swap physical APIC IDs in interrupt entries */
1273 for (x = 0; x < nintrs; x++) {
1274 if (io_apic_ints[x].dst_apic_id == oldid)
1275 io_apic_ints[x].dst_apic_id = newid;
1276 else if (io_apic_ints[x].dst_apic_id == newid)
1277 io_apic_ints[x].dst_apic_id = oldid;
1280 /* Swap physical APIC IDs in IO_TO_ID mappings */
1281 for (oapic = 0; oapic < mp_napics; oapic++)
1282 if (IO_TO_ID(oapic) == newid)
1285 if (oapic < mp_napics) {
1286 kprintf("Changing APIC ID for IO APIC #%d from "
1287 "%d to %d in MP table\n",
1288 oapic, newid, oldid);
1289 IO_TO_ID(oapic) = oldid;
1291 IO_TO_ID(apic) = newid;
1296 fix_id_to_io_mapping(void)
1300 for (x = 0; x < NAPICID; x++)
1303 for (x = 0; x <= mp_naps; x++) {
1304 if ((u_int)CPU_TO_ID(x) < NAPICID)
1305 ID_TO_IO(CPU_TO_ID(x)) = x;
1308 for (x = 0; x < mp_napics; x++) {
1309 if ((u_int)IO_TO_ID(x) < NAPICID)
1310 ID_TO_IO(IO_TO_ID(x)) = x;
1316 first_free_apic_id(void)
1320 for (freeid = 0; freeid < NAPICID; freeid++) {
1321 for (x = 0; x <= mp_naps; x++)
1322 if (CPU_TO_ID(x) == freeid)
1326 for (x = 0; x < mp_napics; x++)
1327 if (IO_TO_ID(x) == freeid)
1338 io_apic_id_acceptable(int apic, int id)
1340 int cpu; /* Logical CPU number */
1341 int oapic; /* Logical IO APIC number for other IO APIC */
1343 if ((u_int)id >= NAPICID)
1344 return 0; /* Out of range */
1346 for (cpu = 0; cpu <= mp_naps; cpu++) {
1347 if (CPU_TO_ID(cpu) == id)
1348 return 0; /* Conflict with CPU */
1351 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1352 if (IO_TO_ID(oapic) == id)
1353 return 0; /* Conflict with other APIC */
1356 return 1; /* ID is acceptable for IO APIC */
1361 io_apic_find_int_entry(int apic, int pin)
1365 /* search each of the possible INTerrupt sources */
1366 for (x = 0; x < nintrs; ++x) {
1367 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1368 (pin == io_apic_ints[x].dst_apic_int))
1369 return (&io_apic_ints[x]);
1375 * parse an Intel MP specification table
1382 int apic; /* IO APIC unit number */
1383 int freeid; /* Free physical APIC ID */
1384 int physid; /* Current physical IO APIC ID */
1386 int bus_0 = 0; /* Stop GCC warning */
1387 int bus_pci = 0; /* Stop GCC warning */
1391 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1392 * did it wrong. The MP spec says that when more than 1 PCI bus
1393 * exists the BIOS must begin with bus entries for the PCI bus and use
1394 * actual PCI bus numbering. This implies that when only 1 PCI bus
1395 * exists the BIOS can choose to ignore this ordering, and indeed many
1396 * MP motherboards do ignore it. This causes a problem when the PCI
1397 * sub-system makes requests of the MP sub-system based on PCI bus
1398 * numbers. So here we look for the situation and renumber the
1399 * busses and associated INTs in an effort to "make it right".
1402 /* find bus 0, PCI bus, count the number of PCI busses */
1403 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1404 if (bus_data[x].bus_id == 0) {
1407 if (bus_data[x].bus_type == PCI) {
1413 * bus_0 == slot of bus with ID of 0
1414 * bus_pci == slot of last PCI bus encountered
1417 /* check the 1 PCI bus case for sanity */
1418 /* if it is number 0 all is well */
1419 if (num_pci_bus == 1 &&
1420 bus_data[bus_pci].bus_id != 0) {
1422 /* mis-numbered, swap with whichever bus uses slot 0 */
1424 /* swap the bus entry types */
1425 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1426 bus_data[bus_0].bus_type = PCI;
1428 /* swap each relevant INTerrupt entry */
1429 id = bus_data[bus_pci].bus_id;
1430 for (x = 0; x < nintrs; ++x) {
1431 if (io_apic_ints[x].src_bus_id == id) {
1432 io_apic_ints[x].src_bus_id = 0;
1434 else if (io_apic_ints[x].src_bus_id == 0) {
1435 io_apic_ints[x].src_bus_id = id;
1440 /* Assign IO APIC IDs.
1442 * First try the existing ID. If a conflict is detected, try
1443 * the ID in the MP table. If a conflict is still detected, find
1446 * We cannot use the ID_TO_IO table before all conflicts has been
1447 * resolved and the table has been corrected.
1449 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1451 /* First try to use the value set by the BIOS */
1452 physid = io_apic_get_id(apic);
1453 if (io_apic_id_acceptable(apic, physid)) {
1454 if (IO_TO_ID(apic) != physid)
1455 swap_apic_id(apic, IO_TO_ID(apic), physid);
1459 /* Then check if the value in the MP table is acceptable */
1460 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1463 /* Last resort, find a free APIC ID and use it */
1464 freeid = first_free_apic_id();
1465 if (freeid >= NAPICID)
1466 panic("No free physical APIC IDs found");
1468 if (io_apic_id_acceptable(apic, freeid)) {
1469 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1472 panic("Free physical APIC ID not usable");
1474 fix_id_to_io_mapping();
1476 /* detect and fix broken Compaq MP table */
1477 if (apic_int_type(0, 0) == -1) {
1478 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1479 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1480 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1481 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1482 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1483 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1485 } else if (apic_int_type(0, 0) == 0) {
1486 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1487 for (x = 0; x < nintrs; ++x)
1488 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1489 (io_apic_ints[x].dst_apic_int) == 0) {
1490 io_apic_ints[x].int_type = 3;
1491 io_apic_ints[x].int_vector = 0xff;
1497 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1498 * controllers universally come in pairs. If IRQ 14 is specified
1499 * as an ISA interrupt, then IRQ 15 had better be too.
1501 * [ Shuttle XPC / AMD Athlon X2 ]
1502 * The MPTable is missing an entry for IRQ 15. Note that the
1503 * ACPI table has an entry for both 14 and 15.
1505 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1506 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1507 io14 = io_apic_find_int_entry(0, 14);
1508 io_apic_ints[nintrs] = *io14;
1509 io_apic_ints[nintrs].src_bus_irq = 15;
1510 io_apic_ints[nintrs].dst_apic_int = 15;
1515 /* Assign low level interrupt handlers */
1517 setup_apic_irq_mapping(void)
1523 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1524 int_to_apicintpin[x].ioapic = -1;
1525 int_to_apicintpin[x].int_pin = 0;
1526 int_to_apicintpin[x].apic_address = NULL;
1527 int_to_apicintpin[x].redirindex = 0;
1529 /* Default to masked */
1530 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1533 /* First assign ISA/EISA interrupts */
1534 for (x = 0; x < nintrs; x++) {
1535 int_vector = io_apic_ints[x].src_bus_irq;
1536 if (int_vector < APIC_INTMAPSIZE &&
1537 io_apic_ints[x].int_vector == 0xff &&
1538 int_to_apicintpin[int_vector].ioapic == -1 &&
1539 (apic_int_is_bus_type(x, ISA) ||
1540 apic_int_is_bus_type(x, EISA)) &&
1541 io_apic_ints[x].int_type == 0) {
1542 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1543 io_apic_ints[x].dst_apic_int,
1548 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1549 for (x = 0; x < nintrs; x++) {
1550 if (io_apic_ints[x].dst_apic_int == 0 &&
1551 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1552 io_apic_ints[x].int_vector == 0xff &&
1553 int_to_apicintpin[0].ioapic == -1 &&
1554 io_apic_ints[x].int_type == 3) {
1555 assign_apic_irq(0, 0, 0);
1560 /* Assign PCI interrupts */
1561 for (x = 0; x < nintrs; ++x) {
1562 if (io_apic_ints[x].int_type == 0 &&
1563 io_apic_ints[x].int_vector == 0xff &&
1564 apic_int_is_bus_type(x, PCI))
1565 allocate_apic_irq(x);
1570 mp_set_cpuids(int cpu_id, int apic_id)
1572 CPU_TO_ID(cpu_id) = apic_id;
1573 ID_TO_CPU(apic_id) = cpu_id;
1575 if (apic_id > lapic_id_max)
1576 lapic_id_max = apic_id;
1580 processor_entry(const struct PROCENTRY *entry, int cpu)
1584 /* check for usability */
1585 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1588 /* check for BSP flag */
1589 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1590 mp_set_cpuids(0, entry->apic_id);
1591 return 0; /* its already been counted */
1594 /* add another AP to list, if less than max number of CPUs */
1595 else if (cpu < MAXCPU) {
1596 mp_set_cpuids(cpu, entry->apic_id);
1604 bus_entry(const struct BUSENTRY *entry, int bus)
1609 /* encode the name into an index */
1610 for (x = 0; x < 6; ++x) {
1611 if ((c = entry->bus_type[x]) == ' ')
1617 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1618 panic("unknown bus type: '%s'", name);
1620 bus_data[bus].bus_id = entry->bus_id;
1621 bus_data[bus].bus_type = x;
1627 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1629 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1632 IO_TO_ID(apic) = entry->apic_id;
1633 ID_TO_IO(entry->apic_id) = apic;
1639 lookup_bus_type(char *name)
1643 for (x = 0; x < MAX_BUSTYPE; ++x)
1644 if (strcmp(bus_type_table[x].name, name) == 0)
1645 return bus_type_table[x].type;
1647 return UNKNOWN_BUSTYPE;
1651 int_entry(const struct INTENTRY *entry, int intr)
1655 io_apic_ints[intr].int_type = entry->int_type;
1656 io_apic_ints[intr].int_flags = entry->int_flags;
1657 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1658 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1659 if (entry->dst_apic_id == 255) {
1660 /* This signal goes to all IO APICS. Select an IO APIC
1661 with sufficient number of interrupt pins */
1662 for (apic = 0; apic < mp_napics; apic++)
1663 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1664 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1665 entry->dst_apic_int)
1667 if (apic < mp_napics)
1668 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1670 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1672 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1673 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1679 apic_int_is_bus_type(int intr, int bus_type)
1683 for (bus = 0; bus < mp_nbusses; ++bus)
1684 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1685 && ((int) bus_data[bus].bus_type == bus_type))
1692 * Given a traditional ISA INT mask, return an APIC mask.
1695 isa_apic_mask(u_int isa_mask)
1700 #if defined(SKIP_IRQ15_REDIRECT)
1701 if (isa_mask == (1 << 15)) {
1702 kprintf("skipping ISA IRQ15 redirect\n");
1705 #endif /* SKIP_IRQ15_REDIRECT */
1707 isa_irq = ffs(isa_mask); /* find its bit position */
1708 if (isa_irq == 0) /* doesn't exist */
1710 --isa_irq; /* make it zero based */
1712 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1716 return (1 << apic_pin); /* convert pin# to a mask */
1720 * Determine which APIC pin an ISA/EISA INT is attached to.
1722 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1723 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1724 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1725 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1727 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1729 isa_apic_irq(int isa_irq)
1733 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1734 if (INTTYPE(intr) == 0) { /* standard INT */
1735 if (SRCBUSIRQ(intr) == isa_irq) {
1736 if (apic_int_is_bus_type(intr, ISA) ||
1737 apic_int_is_bus_type(intr, EISA)) {
1738 if (INTIRQ(intr) == 0xff)
1739 return -1; /* unassigned */
1740 return INTIRQ(intr); /* found */
1745 return -1; /* NOT found */
1750 * Determine which APIC pin a PCI INT is attached to.
1752 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1753 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1754 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1756 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1760 --pciInt; /* zero based */
1762 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1763 if ((INTTYPE(intr) == 0) /* standard INT */
1764 && (SRCBUSID(intr) == pciBus)
1765 && (SRCBUSDEVICE(intr) == pciDevice)
1766 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1767 if (apic_int_is_bus_type(intr, PCI)) {
1768 if (INTIRQ(intr) == 0xff) {
1769 kprintf("IOAPIC: pci_apic_irq() "
1771 return -1; /* unassigned */
1773 return INTIRQ(intr); /* exact match */
1778 return -1; /* NOT found */
1782 next_apic_irq(int irq)
1789 for (intr = 0; intr < nintrs; intr++) {
1790 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1792 bus = SRCBUSID(intr);
1793 bustype = apic_bus_type(bus);
1794 if (bustype != ISA &&
1800 if (intr >= nintrs) {
1803 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1804 if (INTTYPE(ointr) != 0)
1806 if (bus != SRCBUSID(ointr))
1808 if (bustype == PCI) {
1809 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1811 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1814 if (bustype == ISA || bustype == EISA) {
1815 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1818 if (INTPIN(intr) == INTPIN(ointr))
1822 if (ointr >= nintrs) {
1825 return INTIRQ(ointr);
1838 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1841 * Exactly what this means is unclear at this point. It is a solution
1842 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1843 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1844 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1848 undirect_isa_irq(int rirq)
1852 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1853 /** FIXME: tickle the MB redirector chip */
1857 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1864 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1867 undirect_pci_irq(int rirq)
1871 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1873 /** FIXME: tickle the MB redirector chip */
1877 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1885 * given a bus ID, return:
1886 * the bus type if found
1890 apic_bus_type(int id)
1894 for (x = 0; x < mp_nbusses; ++x)
1895 if (bus_data[x].bus_id == id)
1896 return bus_data[x].bus_type;
1902 * given a LOGICAL APIC# and pin#, return:
1903 * the associated src bus ID if found
1907 apic_src_bus_id(int apic, int pin)
1911 /* search each of the possible INTerrupt sources */
1912 for (x = 0; x < nintrs; ++x)
1913 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1914 (pin == io_apic_ints[x].dst_apic_int))
1915 return (io_apic_ints[x].src_bus_id);
1917 return -1; /* NOT found */
1921 * given a LOGICAL APIC# and pin#, return:
1922 * the associated src bus IRQ if found
1926 apic_src_bus_irq(int apic, int pin)
1930 for (x = 0; x < nintrs; x++)
1931 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1932 (pin == io_apic_ints[x].dst_apic_int))
1933 return (io_apic_ints[x].src_bus_irq);
1935 return -1; /* NOT found */
1940 * given a LOGICAL APIC# and pin#, return:
1941 * the associated INTerrupt type if found
1945 apic_int_type(int apic, int pin)
1949 /* search each of the possible INTerrupt sources */
1950 for (x = 0; x < nintrs; ++x) {
1951 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1952 (pin == io_apic_ints[x].dst_apic_int))
1953 return (io_apic_ints[x].int_type);
1955 return -1; /* NOT found */
1959 * Return the IRQ associated with an APIC pin
1962 apic_irq(int apic, int pin)
1967 for (x = 0; x < nintrs; ++x) {
1968 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1969 (pin == io_apic_ints[x].dst_apic_int)) {
1970 res = io_apic_ints[x].int_vector;
1973 if (apic != int_to_apicintpin[res].ioapic)
1974 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1975 if (pin != int_to_apicintpin[res].int_pin)
1976 panic("apic_irq inconsistent table (2)");
1985 * given a LOGICAL APIC# and pin#, return:
1986 * the associated trigger mode if found
1990 apic_trigger(int apic, int pin)
1994 /* search each of the possible INTerrupt sources */
1995 for (x = 0; x < nintrs; ++x)
1996 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1997 (pin == io_apic_ints[x].dst_apic_int))
1998 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2000 return -1; /* NOT found */
2005 * given a LOGICAL APIC# and pin#, return:
2006 * the associated 'active' level if found
2010 apic_polarity(int apic, int pin)
2014 /* search each of the possible INTerrupt sources */
2015 for (x = 0; x < nintrs; ++x)
2016 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2017 (pin == io_apic_ints[x].dst_apic_int))
2018 return (io_apic_ints[x].int_flags & 0x03);
2020 return -1; /* NOT found */
2024 * set data according to MP defaults
2025 * FIXME: probably not complete yet...
2028 mptable_default(int type)
2034 kprintf(" MP default config type: %d\n", type);
2037 kprintf(" bus: ISA, APIC: 82489DX\n");
2040 kprintf(" bus: EISA, APIC: 82489DX\n");
2043 kprintf(" bus: EISA, APIC: 82489DX\n");
2046 kprintf(" bus: MCA, APIC: 82489DX\n");
2049 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2052 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2055 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2058 kprintf(" future type\n");
2064 /* one and only IO APIC */
2065 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2068 * sanity check, refer to MP spec section 3.6.6, last paragraph
2069 * necessary as some hardware isn't properly setting up the IO APIC
2071 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2072 if (io_apic_id != 2) {
2074 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2075 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2076 io_apic_set_id(0, 2);
2079 IO_TO_ID(0) = io_apic_id;
2080 ID_TO_IO(io_apic_id) = 0;
2082 /* fill out bus entries */
2091 bus_data[0].bus_id = default_data[type - 1][1];
2092 bus_data[0].bus_type = default_data[type - 1][2];
2093 bus_data[1].bus_id = default_data[type - 1][3];
2094 bus_data[1].bus_type = default_data[type - 1][4];
2097 /* case 4: case 7: MCA NOT supported */
2098 default: /* illegal/reserved */
2099 panic("BAD default MP config: %d", type);
2103 /* general cases from MP v1.4, table 5-2 */
2104 for (pin = 0; pin < 16; ++pin) {
2105 io_apic_ints[pin].int_type = 0;
2106 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2107 io_apic_ints[pin].src_bus_id = 0;
2108 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2109 io_apic_ints[pin].dst_apic_id = io_apic_id;
2110 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2113 /* special cases from MP v1.4, table 5-2 */
2115 io_apic_ints[2].int_type = 0xff; /* N/C */
2116 io_apic_ints[13].int_type = 0xff; /* N/C */
2117 #if !defined(APIC_MIXED_MODE)
2119 panic("sorry, can't support type 2 default yet");
2120 #endif /* APIC_MIXED_MODE */
2123 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2126 io_apic_ints[0].int_type = 0xff; /* N/C */
2128 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2132 * Map a physical memory address representing I/O into KVA. The I/O
2133 * block is assumed not to cross a page boundary.
2136 ioapic_map(vm_paddr_t pa)
2138 KKASSERT(pa < 0x100000000LL);
2140 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2144 * start each AP in our list
2147 start_all_aps(u_int boot_addr)
2149 vm_offset_t va = boot_address + KERNBASE;
2150 u_int64_t *pt4, *pt3, *pt2;
2156 u_char mpbiosreason;
2157 u_long mpbioswarmvec;
2158 struct mdglobaldata *gd;
2159 struct privatespace *ps;
2161 POSTCODE(START_ALL_APS_POST);
2163 /* install the AP 1st level boot code */
2164 pmap_kenter(va, boot_address);
2165 cpu_invlpg((void *)va); /* JG XXX */
2166 bcopy(mptramp_start, (void *)va, bootMP_size);
2168 /* Locate the page tables, they'll be below the trampoline */
2169 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2170 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2171 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2173 /* Create the initial 1GB replicated page tables */
2174 for (i = 0; i < 512; i++) {
2175 /* Each slot of the level 4 pages points to the same level 3 page */
2176 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2177 pt4[i] |= PG_V | PG_RW | PG_U;
2179 /* Each slot of the level 3 pages points to the same level 2 page */
2180 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2181 pt3[i] |= PG_V | PG_RW | PG_U;
2183 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2184 pt2[i] = i * (2 * 1024 * 1024);
2185 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2188 /* save the current value of the warm-start vector */
2189 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2190 outb(CMOS_REG, BIOS_RESET);
2191 mpbiosreason = inb(CMOS_DATA);
2193 /* setup a vector to our boot code */
2194 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2195 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2196 outb(CMOS_REG, BIOS_RESET);
2197 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2200 * If we have a TSC we can figure out the SMI interrupt rate.
2201 * The SMI does not necessarily use a constant rate. Spend
2202 * up to 250ms trying to figure it out.
2205 if (cpu_feature & CPUID_TSC) {
2206 set_apic_timer(275000);
2207 smilast = read_apic_timer();
2208 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2209 smicount = smitest();
2210 if (smibest == 0 || smilast - smicount < smibest)
2211 smibest = smilast - smicount;
2214 if (smibest > 250000)
2217 smibest = smibest * (int64_t)1000000 /
2218 get_apic_timer_frequency();
2222 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2223 1000000 / smibest, smibest);
2226 for (x = 1; x <= mp_naps; ++x) {
2228 /* This is a bit verbose, it will go away soon. */
2230 /* first page of AP's private space */
2231 pg = x * x86_64_btop(sizeof(struct privatespace));
2233 /* allocate new private data page(s) */
2234 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2235 MDGLOBALDATA_BASEALLOC_SIZE);
2237 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2238 bzero(gd, sizeof(*gd));
2239 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2241 /* prime data page for it to use */
2242 mi_gdinit(&gd->mi, x);
2244 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2245 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2247 /* setup a vector to our boot code */
2248 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2249 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2250 outb(CMOS_REG, BIOS_RESET);
2251 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2254 * Setup the AP boot stack
2256 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2259 /* attempt to start the Application Processor */
2260 CHECK_INIT(99); /* setup checkpoints */
2261 if (!start_ap(gd, boot_addr, smibest)) {
2262 kprintf("\nAP #%d (PHY# %d) failed!\n",
2264 CHECK_PRINT("trace"); /* show checkpoints */
2265 /* better panic as the AP may be running loose */
2266 kprintf("panic y/n? [y] ");
2267 if (cngetc() != 'n')
2270 CHECK_PRINT("trace"); /* show checkpoints */
2272 /* record its version info */
2273 cpu_apic_versions[x] = cpu_apic_versions[0];
2276 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2279 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2280 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2283 ncpus2_shift = shift;
2284 ncpus2 = 1 << shift;
2285 ncpus2_mask = ncpus2 - 1;
2287 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2288 if ((1 << shift) < ncpus)
2290 ncpus_fit = 1 << shift;
2291 ncpus_fit_mask = ncpus_fit - 1;
2293 /* build our map of 'other' CPUs */
2294 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2295 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2296 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2298 /* fill in our (BSP) APIC version */
2299 cpu_apic_versions[0] = lapic->version;
2301 /* restore the warmstart vector */
2302 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2303 outb(CMOS_REG, BIOS_RESET);
2304 outb(CMOS_DATA, mpbiosreason);
2307 * NOTE! The idlestack for the BSP was setup by locore. Finish
2308 * up, clean out the P==V mapping we did earlier.
2313 * Wait all APs to finish initializing LAPIC
2315 mp_finish_lapic = 1;
2317 kprintf("SMP: Waiting APs LAPIC initialization\n");
2318 if (cpu_feature & CPUID_TSC)
2319 tsc0_offset = rdtsc();
2322 while (smp_lapic_mask != smp_startup_mask) {
2324 if (cpu_feature & CPUID_TSC)
2325 tsc0_offset = rdtsc();
2327 while (try_mplock() == 0)
2330 /* number of APs actually started */
2336 * load the 1st level AP boot code into base memory.
2339 /* targets for relocation */
2340 extern void bigJump(void);
2341 extern void bootCodeSeg(void);
2342 extern void bootDataSeg(void);
2343 extern void MPentry(void);
2344 extern u_int MP_GDT;
2345 extern u_int mp_gdtbase;
2350 install_ap_tramp(u_int boot_addr)
2353 int size = *(int *) ((u_long) & bootMP_size);
2354 u_char *src = (u_char *) ((u_long) bootMP);
2355 u_char *dst = (u_char *) boot_addr + KERNBASE;
2356 u_int boot_base = (u_int) bootMP;
2361 POSTCODE(INSTALL_AP_TRAMP_POST);
2363 for (x = 0; x < size; ++x)
2367 * modify addresses in code we just moved to basemem. unfortunately we
2368 * need fairly detailed info about mpboot.s for this to work. changes
2369 * to mpboot.s might require changes here.
2372 /* boot code is located in KERNEL space */
2373 dst = (u_char *) boot_addr + KERNBASE;
2375 /* modify the lgdt arg */
2376 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2377 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2379 /* modify the ljmp target for MPentry() */
2380 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2381 *dst32 = ((u_int) MPentry - KERNBASE);
2383 /* modify the target for boot code segment */
2384 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2385 dst8 = (u_int8_t *) (dst16 + 1);
2386 *dst16 = (u_int) boot_addr & 0xffff;
2387 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2389 /* modify the target for boot data segment */
2390 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2391 dst8 = (u_int8_t *) (dst16 + 1);
2392 *dst16 = (u_int) boot_addr & 0xffff;
2393 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2399 * This function starts the AP (application processor) identified
2400 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2401 * to accomplish this. This is necessary because of the nuances
2402 * of the different hardware we might encounter. It ain't pretty,
2403 * but it seems to work.
2405 * NOTE: eventually an AP gets to ap_init(), which is called just
2406 * before the AP goes into the LWKT scheduler's idle loop.
2409 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2413 u_long icr_lo, icr_hi;
2415 POSTCODE(START_AP_POST);
2417 /* get the PHYSICAL APIC ID# */
2418 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2420 /* calculate the vector */
2421 vector = (boot_addr >> 12) & 0xff;
2423 /* We don't want anything interfering */
2426 /* Make sure the target cpu sees everything */
2430 * Try to detect when a SMI has occurred, wait up to 200ms.
2432 * If a SMI occurs during an AP reset but before we issue
2433 * the STARTUP command, the AP may brick. To work around
2434 * this problem we hold off doing the AP startup until
2435 * after we have detected the SMI. Hopefully another SMI
2436 * will not occur before we finish the AP startup.
2438 * Retries don't seem to help. SMIs have a window of opportunity
2439 * and if USB->legacy keyboard emulation is enabled in the BIOS
2440 * the interrupt rate can be quite high.
2442 * NOTE: Don't worry about the L1 cache load, it might bloat
2443 * ldelta a little but ndelta will be so huge when the SMI
2444 * occurs the detection logic will still work fine.
2447 set_apic_timer(200000);
2452 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2453 * and running the target CPU. OR this INIT IPI might be latched (P5
2454 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2457 * see apic/apicreg.h for icr bit definitions.
2459 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2463 * Setup the address for the target AP. We can setup
2464 * icr_hi once and then just trigger operations with
2467 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2468 icr_hi |= (physical_cpu << 24);
2469 icr_lo = lapic->icr_lo & 0xfff00000;
2470 lapic->icr_hi = icr_hi;
2473 * Do an INIT IPI: assert RESET
2475 * Use edge triggered mode to assert INIT
2477 lapic->icr_lo = icr_lo | 0x00004500;
2478 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2482 * The spec calls for a 10ms delay but we may have to use a
2483 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2484 * interrupt. We have other loops here too and dividing by 2
2485 * doesn't seem to be enough even after subtracting 350us,
2486 * so we divide by 4.
2488 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2489 * interrupt was detected we use the full 10ms.
2493 else if (smibest < 150 * 4 + 350)
2495 else if ((smibest - 350) / 4 < 10000)
2496 u_sleep((smibest - 350) / 4);
2501 * Do an INIT IPI: deassert RESET
2503 * Use level triggered mode to deassert. It is unclear
2504 * why we need to do this.
2506 lapic->icr_lo = icr_lo | 0x00008500;
2507 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2509 u_sleep(150); /* wait 150us */
2512 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2513 * latched, (P5 bug) this 1st STARTUP would then terminate
2514 * immediately, and the previously started INIT IPI would continue. OR
2515 * the previous INIT IPI has already run. and this STARTUP IPI will
2516 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2519 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2520 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2522 u_sleep(200); /* wait ~200uS */
2525 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2526 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2527 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2528 * recognized after hardware RESET or INIT IPI.
2530 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2531 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2534 /* Resume normal operation */
2537 /* wait for it to start, see ap_init() */
2538 set_apic_timer(5000000);/* == 5 seconds */
2539 while (read_apic_timer()) {
2540 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2541 return 1; /* return SUCCESS */
2544 return 0; /* return FAILURE */
2559 while (read_apic_timer()) {
2561 for (count = 0; count < 100; ++count)
2562 ntsc = rdtsc(); /* force loop to occur */
2564 ndelta = ntsc - ltsc;
2565 if (ldelta > ndelta)
2567 if (ndelta > ldelta * 2)
2570 ldelta = ntsc - ltsc;
2573 return(read_apic_timer());
2577 * Synchronously flush the TLB on all other CPU's. The current cpu's
2578 * TLB is not flushed. If the caller wishes to flush the current cpu's
2579 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2581 * NOTE: If for some reason we were unable to start all cpus we cannot
2582 * safely use broadcast IPIs.
2585 static cpumask_t smp_invltlb_req;
2587 #define SMP_INVLTLB_DEBUG
2593 struct mdglobaldata *md = mdcpu;
2594 #ifdef SMP_INVLTLB_DEBUG
2599 crit_enter_gd(&md->mi);
2600 md->gd_invltlb_ret = 0;
2601 ++md->mi.gd_cnt.v_smpinvltlb;
2602 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2603 #ifdef SMP_INVLTLB_DEBUG
2606 if (smp_startup_mask == smp_active_mask) {
2607 all_but_self_ipi(XINVLTLB_OFFSET);
2609 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2610 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2613 #ifdef SMP_INVLTLB_DEBUG
2615 kprintf("smp_invltlb: ipi sent\n");
2617 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2618 (smp_active_mask & ~md->mi.gd_cpumask)) {
2621 #ifdef SMP_INVLTLB_DEBUG
2623 if (++count == 400000000) {
2624 print_backtrace(-1);
2625 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2626 "rflags %016jx retry",
2627 (long)md->gd_invltlb_ret,
2628 (long)smp_invltlb_req,
2629 (intmax_t)read_rflags());
2630 __asm __volatile ("sti");
2633 lwkt_process_ipiq();
2635 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2636 ~md->mi.gd_cpumask &
2640 kprintf("bcpu %d\n", bcpu);
2641 xgd = globaldata_find(bcpu);
2642 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2645 Debugger("giving up");
2651 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2652 crit_exit_gd(&md->mi);
2659 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2660 * bother to bump the critical section count or nested interrupt count
2661 * so only do very low level operations here.
2664 smp_invltlb_intr(void)
2666 struct mdglobaldata *md = mdcpu;
2667 struct mdglobaldata *omd;
2672 mask = smp_invltlb_req;
2675 cpu = BSFCPUMASK(mask);
2676 mask &= ~CPUMASK(cpu);
2677 omd = (struct mdglobaldata *)globaldata_find(cpu);
2678 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2685 * When called the executing CPU will send an IPI to all other CPUs
2686 * requesting that they halt execution.
2688 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2690 * - Signals all CPUs in map to stop.
2691 * - Waits for each to stop.
2698 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2699 * from executing at same time.
2702 stop_cpus(cpumask_t map)
2704 map &= smp_active_mask;
2706 /* send the Xcpustop IPI to all CPUs in map */
2707 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2709 while ((stopped_cpus & map) != map)
2717 * Called by a CPU to restart stopped CPUs.
2719 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2721 * - Signals all CPUs in map to restart.
2722 * - Waits for each to restart.
2730 restart_cpus(cpumask_t map)
2732 /* signal other cpus to restart */
2733 started_cpus = map & smp_active_mask;
2735 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2742 * This is called once the mpboot code has gotten us properly relocated
2743 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2744 * and when it returns the scheduler will call the real cpu_idle() main
2745 * loop for the idlethread. Interrupts are disabled on entry and should
2746 * remain disabled at return.
2754 * Adjust smp_startup_mask to signal the BSP that we have started
2755 * up successfully. Note that we do not yet hold the BGL. The BSP
2756 * is waiting for our signal.
2758 * We can't set our bit in smp_active_mask yet because we are holding
2759 * interrupts physically disabled and remote cpus could deadlock
2760 * trying to send us an IPI.
2762 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2766 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
2767 * non-zero, then get the MP lock.
2769 * Note: We are in a critical section.
2771 * Note: we are the idle thread, we can only spin.
2773 * Note: The load fence is memory volatile and prevents the compiler
2774 * from improperly caching mp_finish_lapic, and the cpu from improperly
2777 while (mp_finish_lapic == 0)
2779 while (try_mplock() == 0)
2782 if (cpu_feature & CPUID_TSC) {
2784 * The BSP is constantly updating tsc0_offset, figure out
2785 * the relative difference to synchronize ktrdump.
2787 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2790 /* BSP may have changed PTD while we're waiting for the lock */
2793 /* Build our map of 'other' CPUs. */
2794 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2796 /* A quick check from sanity claus */
2797 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2798 if (mycpu->gd_cpuid != apic_id) {
2799 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2800 kprintf("SMP: apic_id = %d lapicid %d\n",
2801 apic_id, (lapic->id & 0xff000000) >> 24);
2803 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2805 panic("cpuid mismatch! boom!!");
2808 /* Initialize AP's local APIC for irq's */
2811 /* LAPIC initialization is done */
2812 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
2815 /* Let BSP move onto the next initialization stage */
2819 * Interlock for finalization. Wait until mp_finish is non-zero,
2820 * then get the MP lock.
2822 * Note: We are in a critical section.
2824 * Note: we are the idle thread, we can only spin.
2826 * Note: The load fence is memory volatile and prevents the compiler
2827 * from improperly caching mp_finish, and the cpu from improperly
2830 while (mp_finish == 0)
2832 while (try_mplock() == 0)
2835 /* BSP may have changed PTD while we're waiting for the lock */
2838 /* Set memory range attributes for this CPU to match the BSP */
2839 mem_range_AP_init();
2842 * Once we go active we must process any IPIQ messages that may
2843 * have been queued, because no actual IPI will occur until we
2844 * set our bit in the smp_active_mask. If we don't the IPI
2845 * message interlock could be left set which would also prevent
2848 * The idle loop doesn't expect the BGL to be held and while
2849 * lwkt_switch() normally cleans things up this is a special case
2850 * because we returning almost directly into the idle loop.
2852 * The idle thread is never placed on the runq, make sure
2853 * nothing we've done put it there.
2855 KKASSERT(get_mplock_count(curthread) == 1);
2856 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2859 * Enable interrupts here. idle_restore will also do it, but
2860 * doing it here lets us clean up any strays that got posted to
2861 * the CPU during the AP boot while we are still in a critical
2864 __asm __volatile("sti; pause; pause"::);
2865 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2867 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2868 lwkt_process_ipiq();
2871 * Releasing the mp lock lets the BSP finish up the SMP init
2874 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2878 * Get SMP fully working before we start initializing devices.
2886 kprintf("Finish MP startup\n");
2888 while (smp_active_mask != smp_startup_mask)
2890 while (try_mplock() == 0)
2893 kprintf("Active CPU Mask: %016jx\n",
2894 (uintmax_t)smp_active_mask);
2898 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2901 cpu_send_ipiq(int dcpu)
2903 if (CPUMASK(dcpu) & smp_active_mask)
2904 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2907 #if 0 /* single_apic_ipi_passive() not working yet */
2909 * Returns 0 on failure, 1 on success
2912 cpu_send_ipiq_passive(int dcpu)
2915 if (CPUMASK(dcpu) & smp_active_mask) {
2916 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2917 APIC_DELMODE_FIXED);
2924 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2926 struct mptable_bus_info *bus_info = xarg;
2927 const struct BUSENTRY *ent;
2928 struct mptable_bus *bus;
2934 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2935 if (bus->mb_id == ent->bus_id) {
2936 kprintf("mptable_bus_info_alloc: duplicated bus id "
2937 "(%d)\n", bus->mb_id);
2943 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2944 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2945 bus->mb_type = MPTABLE_BUS_PCI;
2946 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2947 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2948 bus->mb_type = MPTABLE_BUS_ISA;
2952 bus->mb_id = ent->bus_id;
2953 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2959 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2963 bzero(bus_info, sizeof(*bus_info));
2964 TAILQ_INIT(&bus_info->mbi_list);
2966 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2968 mptable_bus_info_free(bus_info);
2972 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2974 struct mptable_bus *bus;
2976 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2977 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2982 struct mptable_lapic_cbarg1 {
2985 u_int ht_apicid_mask;
2989 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2991 const struct PROCENTRY *ent;
2992 struct mptable_lapic_cbarg1 *arg = xarg;
2998 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3002 if (ent->apic_id < 32) {
3003 arg->ht_apicid_mask |= 1 << ent->apic_id;
3004 } else if (arg->ht_fixup) {
3005 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
3011 struct mptable_lapic_cbarg2 {
3018 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
3020 const struct PROCENTRY *ent;
3021 struct mptable_lapic_cbarg2 *arg = xarg;
3027 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3028 KKASSERT(!arg->found_bsp);
3032 if (processor_entry(ent, arg->cpu))
3035 if (arg->logical_cpus) {
3036 struct PROCENTRY proc;
3040 * Create fake mptable processor entries
3041 * and feed them to processor_entry() to
3042 * enumerate the logical CPUs.
3044 bzero(&proc, sizeof(proc));
3046 proc.cpu_flags = PROCENTRY_FLAG_EN;
3047 proc.apic_id = ent->apic_id;
3049 for (i = 1; i < arg->logical_cpus; i++) {
3051 processor_entry(&proc, arg->cpu);
3059 mptable_lapic_default(void)
3061 int ap_apicid, bsp_apicid;
3063 mp_naps = 1; /* exclude BSP */
3065 /* Map local apic before the id field is accessed */
3066 lapic_map(DEFAULT_APIC_BASE);
3068 bsp_apicid = APIC_ID(lapic->id);
3069 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3072 mp_set_cpuids(0, bsp_apicid);
3073 /* one and only AP */
3074 mp_set_cpuids(1, ap_apicid);
3080 * ID_TO_CPU(N), APIC ID to logical CPU table
3081 * CPU_TO_ID(N), logical CPU to APIC ID table
3084 mptable_lapic_enumerate(struct lapic_enumerator *e)
3086 struct mptable_pos mpt;
3087 struct mptable_lapic_cbarg1 arg1;
3088 struct mptable_lapic_cbarg2 arg2;
3090 int error, logical_cpus = 0;
3091 vm_offset_t lapic_addr;
3093 if (mptable_use_default) {
3094 mptable_lapic_default();
3098 error = mptable_map(&mpt);
3100 panic("mptable_lapic_enumerate mptable_map failed\n");
3101 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3105 /* Save local apic address */
3106 lapic_addr = (vm_offset_t)cth->apic_address;
3107 KKASSERT(lapic_addr != 0);
3110 * Find out how many CPUs do we have
3112 bzero(&arg1, sizeof(arg1));
3113 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3115 error = mptable_iterate_entries(cth,
3116 mptable_lapic_pass1_callback, &arg1);
3118 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3119 KKASSERT(arg1.cpu_count != 0);
3121 /* See if we need to fixup HT logical CPUs. */
3122 if (arg1.ht_fixup) {
3123 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3125 if (logical_cpus != 0)
3126 arg1.cpu_count *= logical_cpus;
3128 mp_naps = arg1.cpu_count;
3130 /* Qualify the numbers again, after possible HT fixup */
3131 if (mp_naps > MAXCPU) {
3132 kprintf("Warning: only using %d of %d available CPUs!\n",
3138 --mp_naps; /* subtract the BSP */
3141 * Link logical CPU id to local apic id
3143 bzero(&arg2, sizeof(arg2));
3145 arg2.logical_cpus = logical_cpus;
3147 error = mptable_iterate_entries(cth,
3148 mptable_lapic_pass2_callback, &arg2);
3150 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3151 KKASSERT(arg2.found_bsp);
3153 /* Map local apic */
3154 lapic_map(lapic_addr);
3156 mptable_unmap(&mpt);
3159 struct mptable_lapic_probe_cbarg {
3165 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3167 const struct PROCENTRY *ent;
3168 struct mptable_lapic_probe_cbarg *arg = xarg;
3174 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3178 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3179 if (arg->found_bsp) {
3180 kprintf("more than one BSP in base MP table\n");
3189 mptable_lapic_probe(struct lapic_enumerator *e)
3191 struct mptable_pos mpt;
3192 struct mptable_lapic_probe_cbarg arg;
3196 if (mptable_fps_phyaddr == 0)
3199 if (mptable_use_default)
3202 error = mptable_map(&mpt);
3205 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3210 if (cth->apic_address == 0)
3213 bzero(&arg, sizeof(arg));
3214 error = mptable_iterate_entries(cth,
3215 mptable_lapic_probe_callback, &arg);
3217 if (arg.cpu_count == 0) {
3218 kprintf("MP table contains no processor entries\n");
3220 } else if (!arg.found_bsp) {
3221 kprintf("MP table does not contains BSP entry\n");
3226 mptable_unmap(&mpt);
3230 static struct lapic_enumerator mptable_lapic_enumerator = {
3231 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3232 .lapic_probe = mptable_lapic_probe,
3233 .lapic_enumerate = mptable_lapic_enumerate
3237 mptable_lapic_enum_register(void)
3239 lapic_enumerator_register(&mptable_lapic_enumerator);
3241 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3242 mptable_lapic_enum_register, 0);
3245 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3247 const struct IOAPICENTRY *ent;
3248 struct mptable_ioapic *nioapic, *ioapic;
3254 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3257 if (ent->apic_address == 0) {
3258 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3262 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3263 if (ioapic->mio_apic_id == ent->apic_id) {
3264 kprintf("mptable_ioapic_create_list: duplicated "
3265 "apic id %d\n", ioapic->mio_apic_id);
3268 if (ioapic->mio_addr == ent->apic_address) {
3269 kprintf("mptable_ioapic_create_list: overlapped "
3270 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3275 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3276 nioapic->mio_apic_id = ent->apic_id;
3277 nioapic->mio_addr = ent->apic_address;
3280 * Create IOAPIC list in ascending order of APIC ID
3282 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3283 mptable_ioapic_list, mio_link) {
3284 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3285 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3286 ioapic, nioapic, mio_link);
3291 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3297 mptable_ioapic_create_list(void)
3299 struct mptable_ioapic *ioapic;
3300 struct mptable_pos mpt;
3303 if (mptable_fps_phyaddr == 0)
3306 if (mptable_use_default) {
3307 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3308 ioapic->mio_idx = 0;
3309 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3310 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3312 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3316 error = mptable_map(&mpt);
3318 panic("mptable_ioapic_create_list: mptable_map failed\n");
3319 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3321 error = mptable_iterate_entries(mpt.mp_cth,
3322 mptable_ioapic_list_callback, NULL);
3324 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3325 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3326 kfree(ioapic, M_DEVBUF);
3332 * Assign index number for each IOAPIC
3335 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3336 ioapic->mio_idx = idx;
3340 mptable_unmap(&mpt);
3342 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3343 mptable_ioapic_create_list, 0);
3346 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3348 const struct mptable_bus_info *bus_info = xarg;
3349 const struct mptable_ioapic *ioapic;
3350 const struct mptable_bus *bus;
3351 struct mptable_pci_int *pci_int;
3352 const struct INTENTRY *ent;
3353 int pci_pin, pci_dev;
3359 if (ent->int_type != 0)
3362 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3363 if (bus->mb_type == MPTABLE_BUS_PCI &&
3364 bus->mb_id == ent->src_bus_id)
3370 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3371 if (ioapic->mio_apic_id == ent->dst_apic_id)
3374 if (ioapic == NULL) {
3375 kprintf("MPTABLE: warning PCI int dst apic id %d "
3376 "does not exist\n", ent->dst_apic_id);
3380 pci_pin = ent->src_bus_irq & 0x3;
3381 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3383 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3384 if (pci_int->mpci_bus == ent->src_bus_id &&
3385 pci_int->mpci_dev == pci_dev &&
3386 pci_int->mpci_pin == pci_pin) {
3387 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3388 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3389 kprintf("MPTABLE: warning duplicated "
3390 "PCI int entry for "
3391 "bus %d, dev %d, pin %d\n",
3397 kprintf("mptable_pci_int_register: "
3398 "conflict PCI int entry for "
3399 "bus %d, dev %d, pin %d, "
3400 "IOAPIC %d.%d -> %d.%d\n",
3404 pci_int->mpci_ioapic_idx,
3405 pci_int->mpci_ioapic_pin,
3413 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3415 pci_int->mpci_bus = ent->src_bus_id;
3416 pci_int->mpci_dev = pci_dev;
3417 pci_int->mpci_pin = pci_pin;
3418 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3419 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3421 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3427 mptable_pci_int_register(void)
3429 struct mptable_bus_info bus_info;
3430 const struct mptable_bus *bus;
3431 struct mptable_pci_int *pci_int;
3432 struct mptable_pos mpt;
3433 int error, force_pci0, npcibus;
3436 if (mptable_fps_phyaddr == 0)
3439 if (mptable_use_default)
3442 if (TAILQ_EMPTY(&mptable_ioapic_list))
3445 error = mptable_map(&mpt);
3447 panic("mptable_pci_int_register: mptable_map failed\n");
3448 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3452 mptable_bus_info_alloc(cth, &bus_info);
3453 if (TAILQ_EMPTY(&bus_info.mbi_list))
3458 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3459 if (bus->mb_type == MPTABLE_BUS_PCI)
3463 mptable_bus_info_free(&bus_info);
3465 } else if (npcibus == 1) {
3469 error = mptable_iterate_entries(cth,
3470 mptable_pci_int_callback, &bus_info);
3472 mptable_bus_info_free(&bus_info);
3475 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3476 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3477 kfree(pci_int, M_DEVBUF);
3483 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3484 pci_int->mpci_bus = 0;
3487 mptable_unmap(&mpt);
3489 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3490 mptable_pci_int_register, 0);
3492 struct mptable_ioapic_probe_cbarg {
3493 const struct mptable_bus_info *bus_info;
3497 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3499 struct mptable_ioapic_probe_cbarg *arg = xarg;
3500 const struct mptable_ioapic *ioapic;
3501 const struct mptable_bus *bus;
3502 const struct INTENTRY *ent;
3508 if (ent->int_type != 0)
3511 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3512 if (bus->mb_type == MPTABLE_BUS_ISA &&
3513 bus->mb_id == ent->src_bus_id)
3519 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3520 if (ioapic->mio_apic_id == ent->dst_apic_id)
3523 if (ioapic == NULL) {
3524 kprintf("MPTABLE: warning ISA int dst apic id %d "
3525 "does not exist\n", ent->dst_apic_id);
3529 /* XXX magic number */
3530 if (ent->src_bus_irq >= 16) {
3531 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3539 mptable_ioapic_probe(struct ioapic_enumerator *e)
3541 struct mptable_ioapic_probe_cbarg arg;
3542 struct mptable_bus_info bus_info;
3543 struct mptable_pos mpt;
3547 if (mptable_fps_phyaddr == 0)
3550 if (mptable_use_default)
3553 if (TAILQ_EMPTY(&mptable_ioapic_list))
3556 error = mptable_map(&mpt);
3558 panic("mptable_ioapic_probe: mptable_map failed\n");
3559 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3563 mptable_bus_info_alloc(cth, &bus_info);
3565 bzero(&arg, sizeof(arg));
3566 arg.bus_info = &bus_info;
3568 error = mptable_iterate_entries(cth,
3569 mptable_ioapic_probe_callback, &arg);
3571 mptable_bus_info_free(&bus_info);
3572 mptable_unmap(&mpt);
3577 struct mptable_ioapic_int_cbarg {
3578 const struct mptable_bus_info *bus_info;
3583 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3585 struct mptable_ioapic_int_cbarg *arg = xarg;
3586 const struct mptable_ioapic *ioapic;
3587 const struct mptable_bus *bus;
3588 const struct INTENTRY *ent;
3596 if (ent->int_type != 0)
3599 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3600 if (bus->mb_type == MPTABLE_BUS_ISA &&
3601 bus->mb_id == ent->src_bus_id)
3607 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3608 if (ioapic->mio_apic_id == ent->dst_apic_id)
3611 if (ioapic == NULL) {
3612 kprintf("MPTABLE: warning ISA int dst apic id %d "
3613 "does not exist\n", ent->dst_apic_id);
3617 if (!ioapic_use_old) {
3620 if (ent->dst_apic_int >= ioapic->mio_npin) {
3621 panic("mptable_ioapic_enumerate: invalid I/O APIC "
3622 "pin %d, should be < %d",
3623 ent->dst_apic_int, ioapic->mio_npin);
3625 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
3627 if (ent->src_bus_irq != gsi) {
3629 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3630 ent->src_bus_irq, gsi);
3632 ioapic_intsrc(ent->src_bus_irq, gsi,
3633 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
3636 /* XXX rough estimation */
3637 if (ent->src_bus_irq != ent->dst_apic_int) {
3639 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3640 ent->src_bus_irq, ent->dst_apic_int);
3648 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3650 struct mptable_bus_info bus_info;
3651 struct mptable_ioapic *ioapic;
3652 struct mptable_pos mpt;
3656 KKASSERT(mptable_fps_phyaddr != 0);
3657 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3659 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3660 if (!ioapic_use_old) {
3661 const struct mptable_ioapic *prev_ioapic;
3665 addr = ioapic_map(ioapic->mio_addr);
3667 ver = ioapic_read(addr, IOAPIC_VER);
3668 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3669 >> MAXREDIRSHIFT) + 1;
3671 prev_ioapic = TAILQ_PREV(ioapic,
3672 mptable_ioapic_list, mio_link);
3673 if (prev_ioapic == NULL) {
3674 ioapic->mio_gsi_base = 0;
3676 ioapic->mio_gsi_base =
3677 prev_ioapic->mio_gsi_base +
3678 prev_ioapic->mio_npin;
3680 ioapic_add(addr, ioapic->mio_gsi_base,
3684 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3685 "apic id %d, idx %d, gsi base %d, npin %d\n",
3687 ioapic->mio_apic_id,
3689 ioapic->mio_gsi_base,
3694 if (mptable_use_default) {
3696 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3697 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
3701 error = mptable_map(&mpt);
3703 panic("mptable_ioapic_probe: mptable_map failed\n");
3704 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3708 mptable_bus_info_alloc(cth, &bus_info);
3710 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3712 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3713 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
3715 struct mptable_ioapic_int_cbarg arg;
3717 bzero(&arg, sizeof(arg));
3718 arg.bus_info = &bus_info;
3720 error = mptable_iterate_entries(cth,
3721 mptable_ioapic_int_callback, &arg);
3723 panic("mptable_ioapic_int failed\n");
3725 if (arg.ioapic_nint == 0) {
3727 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3730 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
3731 INTR_POLARITY_HIGH);
3735 mptable_bus_info_free(&bus_info);
3737 mptable_unmap(&mpt);
3740 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3741 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3742 .ioapic_probe = mptable_ioapic_probe,
3743 .ioapic_enumerate = mptable_ioapic_enumerate
3747 mptable_ioapic_enum_register(void)
3749 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3751 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3752 mptable_ioapic_enum_register, 0);
3755 mptable_pci_int_dump(void)
3757 const struct mptable_pci_int *pci_int;
3759 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3760 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
3763 pci_int->mpci_pin + 'A',
3764 pci_int->mpci_ioapic_idx,
3765 pci_int->mpci_ioapic_pin);
3770 mptable_pci_int_route(int bus, int dev, int pin, int intline)
3772 const struct mptable_pci_int *pci_int;
3776 --pin; /* zero based */
3778 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3779 if (pci_int->mpci_bus == bus &&
3780 pci_int->mpci_dev == dev &&
3781 pci_int->mpci_pin == pin)
3784 if (pci_int != NULL) {
3787 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
3788 pci_int->mpci_ioapic_pin);
3790 irq = ioapic_abi_find_gsi(gsi,
3791 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
3797 kprintf("MPTABLE: fixed interrupt routing "
3798 "for %d:%d INT%c\n", bus, dev, pin + 'A');
3801 irq = ioapic_abi_find_irq(intline,
3802 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
3805 if (irq >= 0 && bootverbose) {
3806 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
3807 bus, dev, pin + 'A', irq);