2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4 * Copyright (c) 1997 KATO Takenori.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39 * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/sysctl.h>
49 #include <machine/asmacros.h>
50 #include <machine/clock.h>
51 #include <machine/cputypes.h>
52 #include <machine/segments.h>
53 #include <machine/specialreg.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
56 #include <machine/npx.h>
58 #define IDENTBLUE_CYRIX486 0
59 #define IDENTBLUE_IBMCPU 1
60 #define IDENTBLUE_CYRIXM2 2
62 /* XXX - should be in header file: */
63 void printcpuinfo(void);
64 void finishidentcpu(void);
65 void earlysetcpuclass(void);
66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
67 void enable_K5_wt_alloc(void);
68 void enable_K6_wt_alloc(void);
69 void enable_K6_2_wt_alloc(void);
71 void panicifcpuunsupported(void);
73 static void init_exthigh(void);
74 static u_int find_cpu_vendor_id(void);
75 static void print_AMD_info(void);
76 static void print_INTEL_info(void);
77 static void print_INTEL_TLB(u_int data);
78 static void print_AMD_assoc(int i);
79 static void print_transmeta_info(void);
80 static void print_via_padlock_info(void);
83 u_int cpu_exthigh; /* Highest arg to extended CPUID */
84 char machine[] = MACHINE;
85 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
86 machine, 0, "Machine class");
88 static char cpu_model[128];
89 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
90 cpu_model, 0, "Machine model");
92 static int hw_clockrate;
93 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
94 &hw_clockrate, 0, "CPU instruction clock rate");
96 static char cpu_brand[48];
98 #define MAX_ADDITIONAL_INFO 16
100 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
101 static u_int additional_cpu_info_count;
103 #define MAX_BRAND_INDEX 8
105 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
109 "Intel Pentium III Xeon",
121 { "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
122 { "i386SX", CPUCLASS_386 }, /* CPU_386SX */
123 { "i386DX", CPUCLASS_386 }, /* CPU_386 */
124 { "i486SX", CPUCLASS_486 }, /* CPU_486SX */
125 { "i486DX", CPUCLASS_486 }, /* CPU_486 */
126 { "Pentium", CPUCLASS_586 }, /* CPU_586 */
127 { "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
128 { "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
129 { "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
130 { "Pentium II", CPUCLASS_686 }, /* CPU_PII */
131 { "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
132 { "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
139 { INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
140 { AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
141 { CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
142 { NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
143 { TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
144 { SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
145 { UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
146 { NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
147 { RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
149 /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
150 { "TransmetaCPU", CPU_VENDOR_TRANSMETA },
155 static int cpu_cores;
156 static int cpu_logical;
159 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
160 int has_f00f_bug = 0; /* Initialized so that it can be patched. */
171 (cpu_vendor_id == CPU_VENDOR_INTEL ||
172 cpu_vendor_id == CPU_VENDOR_AMD ||
173 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
174 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
175 cpu_vendor_id == CPU_VENDOR_NSC)) {
176 do_cpuid(0x80000000, regs);
177 if (regs[0] >= 0x80000000)
178 cpu_exthigh = regs[0];
191 cpu_class = i386_cpus[cpu].cpu_class;
193 strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
195 /* Check for extended CPUID information and a processor name. */
197 if (cpu_exthigh >= 0x80000004) {
199 for (i = 0x80000002; i < 0x80000005; i++) {
201 memcpy(brand, regs, sizeof(regs));
202 brand += sizeof(regs);
206 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
207 if ((cpu_id & 0xf00) > 0x300) {
212 switch (cpu_id & 0x3000) {
214 strcpy(cpu_model, "Overdrive ");
217 strcpy(cpu_model, "Dual ");
221 switch (cpu_id & 0xf00) {
223 strcat(cpu_model, "i486 ");
224 /* Check the particular flavor of 486 */
225 switch (cpu_id & 0xf0) {
228 strcat(cpu_model, "DX");
231 strcat(cpu_model, "SX");
234 strcat(cpu_model, "DX2");
237 strcat(cpu_model, "SL");
240 strcat(cpu_model, "SX2");
244 "DX2 Write-Back Enhanced");
247 strcat(cpu_model, "DX4");
252 /* Check the particular flavor of 586 */
253 strcat(cpu_model, "Pentium");
254 switch (cpu_id & 0xf0) {
256 strcat(cpu_model, " A-step");
259 strcat(cpu_model, "/P5");
262 strcat(cpu_model, "/P54C");
265 strcat(cpu_model, "/P24T");
268 strcat(cpu_model, "/P55C");
271 strcat(cpu_model, "/P54C");
274 strcat(cpu_model, "/P55C (quarter-micron)");
280 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
282 * XXX - If/when Intel fixes the bug, this
283 * should also check the version of the
284 * CPU, not just that it's a Pentium.
290 /* Check the particular flavor of 686 */
291 switch (cpu_id & 0xf0) {
293 strcat(cpu_model, "Pentium Pro A-step");
296 strcat(cpu_model, "Pentium Pro");
302 "Pentium II/Pentium II Xeon/Celeron");
310 "Pentium III/Pentium III Xeon/Celeron");
314 strcat(cpu_model, "Unknown 80686");
319 strcat(cpu_model, "Pentium 4");
323 strcat(cpu_model, "unknown");
328 * If we didn't get a brand name from the extended
329 * CPUID, try to look it up in the brand table.
331 if (cpu_high > 0 && *cpu_brand == '\0') {
332 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
333 if (brand_index <= MAX_BRAND_INDEX &&
334 cpu_brandtable[brand_index] != NULL)
336 cpu_brandtable[brand_index]);
339 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
341 * Values taken from AMD Processor Recognition
342 * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
343 * (also describes ``Features'' encodings.
345 strcpy(cpu_model, "AMD ");
346 switch (cpu_id & 0xFF0) {
348 strcat(cpu_model, "Standard Am486DX");
351 strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
354 strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
357 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
360 strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
363 strcat(cpu_model, "Am5x86 Write-Through");
366 strcat(cpu_model, "Am5x86 Write-Back");
369 strcat(cpu_model, "K5 model 0");
373 strcat(cpu_model, "K5 model 1");
376 strcat(cpu_model, "K5 PR166 (model 2)");
379 strcat(cpu_model, "K5 PR200 (model 3)");
382 strcat(cpu_model, "K6");
385 strcat(cpu_model, "K6 266 (model 1)");
388 strcat(cpu_model, "K6-2");
391 strcat(cpu_model, "K6-III");
394 strcat(cpu_model, "Geode LX");
396 * Make sure the TSC runs through suspension,
397 * otherwise we can't use it as timecounter
399 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
402 strcat(cpu_model, "Unknown");
405 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
406 if ((cpu_id & 0xf00) == 0x500) {
407 if (((cpu_id & 0x0f0) > 0)
408 && ((cpu_id & 0x0f0) < 0x60)
409 && ((cpu_id & 0x00f) > 3))
410 enable_K5_wt_alloc();
411 else if (((cpu_id & 0x0f0) > 0x80)
412 || (((cpu_id & 0x0f0) == 0x80)
413 && (cpu_id & 0x00f) > 0x07))
414 enable_K6_2_wt_alloc();
415 else if ((cpu_id & 0x0f0) > 0x50)
416 enable_K6_wt_alloc();
419 } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
420 strcpy(cpu_model, "Rise ");
421 switch (cpu_id & 0xff0) {
423 strcat(cpu_model, "mP6");
426 strcat(cpu_model, "Unknown");
428 } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
429 switch (cpu_id & 0xff0) {
431 strcpy(cpu_model, "IDT WinChip C6");
435 strcpy(cpu_model, "IDT WinChip 2");
438 strcpy(cpu_model, "VIA C3 Samuel");
442 strcpy(cpu_model, "VIA C3 Ezra");
444 strcpy(cpu_model, "VIA C3 Samuel 2");
447 strcpy(cpu_model, "VIA C3 Ezra-T");
450 strcpy(cpu_model, "VIA C3 Nehemiah");
454 strcpy(cpu_model, "VIA C7 Esther");
457 strcpy(cpu_model, "VIA Nano");
460 strcpy(cpu_model, "VIA/IDT Unknown");
462 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
463 strcpy(cpu_model, "Blue Lightning CPU");
464 } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
465 switch (cpu_id & 0xfff) {
467 strcpy(cpu_model, "Geode SC1100");
472 strcpy(cpu_model, "Geode/NSC unknown");
478 * Replace cpu_model with cpu_brand minus leading spaces if
482 while (*brand == ' ')
485 strcpy(cpu_model, brand);
487 kprintf("%s (", cpu_model);
495 #if defined(I486_CPU)
500 #if defined(I586_CPU)
502 hw_clockrate = (tsc_frequency + 5000) / 1000000;
503 kprintf("%jd.%02d-MHz ",
504 (intmax_t)(tsc_frequency + 4999) / 1000000,
505 (u_int)((tsc_frequency + 4999) / 10000) % 100);
509 #if defined(I686_CPU)
511 hw_clockrate = (tsc_frequency + 5000) / 1000000;
512 kprintf("%jd.%02d-MHz ",
513 (intmax_t)(tsc_frequency + 4999) / 1000000,
514 (u_int)((tsc_frequency + 4999) / 10000) % 100);
519 kprintf("Unknown"); /* will panic below... */
521 kprintf("-class CPU)\n");
523 kprintf(" Origin = \"%s\"",cpu_vendor);
525 kprintf(" Id = 0x%x", cpu_id);
527 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
528 cpu_vendor_id == CPU_VENDOR_AMD ||
529 cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
530 cpu_vendor_id == CPU_VENDOR_RISE ||
531 cpu_vendor_id == CPU_VENDOR_CENTAUR ||
532 cpu_vendor_id == CPU_VENDOR_NSC) {
533 kprintf(" Stepping = %u", cpu_id & 0xf);
536 u_int cmp = 1, htt = 1;
539 * Here we should probably set up flags indicating
540 * whether or not various features are available.
541 * The interesting ones are probably VME, PSE, PAE,
542 * and PGE. The code already assumes without bothering
543 * to check that all CPUs >= Pentium have a TSC and
546 kprintf("\n Features=0x%b", cpu_feature,
548 "\001FPU" /* Integral FPU */
549 "\002VME" /* Extended VM86 mode support */
550 "\003DE" /* Debugging Extensions (CR4.DE) */
551 "\004PSE" /* 4MByte page tables */
552 "\005TSC" /* Timestamp counter */
553 "\006MSR" /* Machine specific registers */
554 "\007PAE" /* Physical address extension */
555 "\010MCE" /* Machine Check support */
556 "\011CX8" /* CMPEXCH8 instruction */
557 "\012APIC" /* SMP local APIC */
558 "\013oldMTRR" /* Previous implementation of MTRR */
559 "\014SEP" /* Fast System Call */
560 "\015MTRR" /* Memory Type Range Registers */
561 "\016PGE" /* PG_G (global bit) support */
562 "\017MCA" /* Machine Check Architecture */
563 "\020CMOV" /* CMOV instruction */
564 "\021PAT" /* Page attributes table */
565 "\022PSE36" /* 36 bit address space support */
566 "\023PN" /* Processor Serial number */
567 "\024CLFLUSH" /* Has the CLFLUSH instruction */
569 "\026DTS" /* Debug Trace Store */
570 "\027ACPI" /* ACPI support */
571 "\030MMX" /* MMX instructions */
572 "\031FXSR" /* FXSAVE/FXRSTOR */
573 "\032SSE" /* Streaming SIMD Extensions */
574 "\033SSE2" /* Streaming SIMD Extensions #2 */
575 "\034SS" /* Self snoop */
576 "\035HTT" /* Hyperthreading (see EBX bit 16-23) */
577 "\036TM" /* Thermal Monitor clock slowdown */
578 "\037IA64" /* CPU can execute IA64 instructions */
579 "\040PBE" /* Pending Break Enable */
582 if (cpu_feature2 != 0) {
583 kprintf("\n Features2=0x%b", cpu_feature2,
585 "\001SSE3" /* SSE3 */
586 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
587 "\003DTES64" /* 64-bit Debug Trace */
588 "\004MON" /* MONITOR/MWAIT Instructions */
589 "\005DS_CPL" /* CPL Qualified Debug Store */
590 "\006VMX" /* Virtual Machine Extensions */
591 "\007SMX" /* Safer Mode Extensions */
592 "\010EST" /* Enhanced SpeedStep */
593 "\011TM2" /* Thermal Monitor 2 */
594 "\012SSSE3" /* SSSE3 */
595 "\013CNXT-ID" /* L1 context ID available */
597 "\015FMA" /* Fused Multiply Add */
598 "\016CX16" /* CMPXCHG16B Instruction */
599 "\017xTPR" /* Send Task Priority Messages */
600 "\020PDCM" /* Perf/Debug Capability MSR */
602 "\022PCID" /* Process-context Identifiers */
603 "\023DCA" /* Direct Cache Access */
604 "\024SSE4.1" /* SSE 4.1 */
605 "\025SSE4.2" /* SSE 4.2 */
606 "\026x2APIC" /* xAPIC Extensions */
607 "\027MOVBE" /* MOVBE Instruction */
608 "\030POPCNT" /* POPCNT Instruction */
609 "\031TSCDLT" /* TSC-Deadline Timer */
610 "\032AESNI" /* AES Crypto */
611 "\033XSAVE" /* XSAVE/XRSTOR States */
612 "\034OSXSAVE" /* OS-Enabled State Management */
613 "\035AVX" /* Advanced Vector Extensions */
614 "\036F16C" /* Half-precision conversions */
615 "\037RDRND" /* RDRAND RNG function */
616 "\040VMM" /* Running on a hypervisor */
621 * AMD64 Architecture Programmer's Manual Volume 3:
622 * General-Purpose and System Instructions
623 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
625 * IA-32 Intel Architecture Software Developer's Manual,
626 * Volume 2A: Instruction Set Reference, A-M
627 * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
629 if (amd_feature != 0) {
630 kprintf("\n AMD Features=0x%b", amd_feature,
632 "\001<s0>" /* Same */
633 "\002<s1>" /* Same */
634 "\003<s2>" /* Same */
635 "\004<s3>" /* Same */
636 "\005<s4>" /* Same */
637 "\006<s5>" /* Same */
638 "\007<s6>" /* Same */
639 "\010<s7>" /* Same */
640 "\011<s8>" /* Same */
641 "\012<s9>" /* Same */
642 "\013<b10>" /* Undefined */
643 "\014SYSCALL" /* Have SYSCALL/SYSRET */
644 "\015<s12>" /* Same */
645 "\016<s13>" /* Same */
646 "\017<s14>" /* Same */
647 "\020<s15>" /* Same */
648 "\021<s16>" /* Same */
649 "\022<s17>" /* Same */
650 "\023<b18>" /* Reserved, unknown */
651 "\024MP" /* Multiprocessor Capable */
652 "\025NX" /* Has EFER.NXE, NX */
653 "\026<b21>" /* Undefined */
654 "\027MMX+" /* AMD MMX Extensions */
655 "\030<s23>" /* Same */
656 "\031<s24>" /* Same */
657 "\032FFXSR" /* Fast FXSAVE/FXRSTOR */
658 "\033Page1GB" /* 1-GB large page support */
659 "\034RDTSCP" /* RDTSCP */
660 "\035<b28>" /* Undefined */
661 "\036LM" /* 64 bit long mode */
662 "\0373DNow!+" /* AMD 3DNow! Extensions */
663 "\0403DNow!" /* AMD 3DNow! */
667 if (amd_feature2 != 0) {
668 kprintf("\n AMD Features2=0x%b", amd_feature2,
670 "\001LAHF" /* LAHF/SAHF in long mode */
671 "\002CMP" /* CMP legacy */
672 "\003SVM" /* Secure Virtual Mode */
673 "\004ExtAPIC" /* Extended APIC register */
674 "\005CR8" /* CR8 in legacy mode */
675 "\006ABM" /* LZCNT instruction */
676 "\007SSE4A" /* SSE4A */
677 "\010MAS" /* Misaligned SSE mode */
678 "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
679 "\012OSVW" /* OS visible workaround */
680 "\013IBS" /* Instruction based sampling */
681 "\014XOP" /* XOP extended instructions */
682 "\015SKINIT" /* SKINIT/STGI */
683 "\016WDT" /* Watchdog timer */
685 "\020LWP" /* Lightweight Profiling */
686 "\021FMA4" /* 4-operand FMA instructions */
687 "\022TCE" /* Translation Cache Extension */
689 "\024NodeId" /* NodeId MSR support */
691 "\026TBM" /* Trailing Bit Manipulation */
692 "\027Topology" /* Topology Extensions */
693 "\030PCX_CORE" /* Core Performance Counter */
694 "\031PCX_NB" /* NB Performance Counter */
695 "\032SPM" /* Streaming Perf Monitor */
696 "\033DBE" /* Data Breakpoint Extension */
697 "\034PTSC" /* Performance TSC */
698 "\035PCX_L2I" /* L2I Performance Counter */
705 if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
706 print_via_padlock_info();
709 * INVALID CPU TOPOLOGY INFORMATION PRINT
710 * DEPRECATED - CPU_TOPOLOGY_DETECTION moved to
711 * - sys/platform/pc64/x86_64/mp_machdep.c
712 * - sys/kern/subr_cpu_topology
716 if ((cpu_feature & CPUID_HTT) &&
717 cpu_vendor_id == CPU_VENDOR_AMD)
718 cpu_feature &= ~CPUID_HTT;
722 * If this CPU supports HTT or CMP then mention the
723 * number of physical/logical cores it contains.
726 if (cpu_feature & CPUID_HTT)
727 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
728 if (cpu_vendor_id == CPU_VENDOR_AMD &&
729 (amd_feature2 & AMDID2_CMP))
730 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
731 else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
733 cpuid_count(4, 0, regs);
734 if ((regs[0] & 0x1f) != 0)
735 cmp = ((regs[0] >> 26) & 0x3f) + 1;
740 * XXX For Intel CPUs, this is max number of cores per
741 * package, not the actual cores per package.
745 cpu_logical = htt / cmp;
748 kprintf("\n Cores per package: %d", cpu_cores);
749 if (cpu_logical > 1) {
750 kprintf("\n Logical CPUs per core: %d",
758 * If this CPU supports P-state invariant TSC then
759 * mention the capability.
761 switch (cpu_vendor_id) {
763 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
764 CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
766 tsc_is_invariant = 1;
768 case CPU_VENDOR_INTEL:
769 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
770 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
771 CPUID_TO_MODEL(cpu_id) >= 0xe) ||
772 (CPUID_TO_FAMILY(cpu_id) == 0xf &&
773 CPUID_TO_MODEL(cpu_id) >= 0x3))
774 tsc_is_invariant = 1;
776 case CPU_VENDOR_CENTAUR:
777 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
778 CPUID_TO_MODEL(cpu_id) >= 0xf &&
779 (rdmsr(0x1203) & 0x100000000ULL) == 0)
780 tsc_is_invariant = 1;
783 if (tsc_is_invariant)
784 kprintf("\n TSC: P-state invariant");
790 /* Avoid ugly blank lines: only print newline when we have to. */
791 if (*cpu_vendor || cpu_id)
794 for (i = 0; i < additional_cpu_info_count; ++i) {
795 kprintf(" %s\n", additional_cpu_info_ary[i]);
801 if (cpu_vendor_id == CPU_VENDOR_AMD)
803 else if (cpu_vendor_id == CPU_VENDOR_INTEL)
805 else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
806 print_transmeta_info();
809 kprintf("Use SSE2 (lfence, mfence)\n");
811 kprintf("npx mask: 0x%8.8x\n", npx_mxcsr_mask);
815 panicifcpuunsupported(void)
819 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
820 #error This kernel is not configured for one of the supported CPUs
825 * Now that we have told the user what they have,
826 * let them know if that machine type isn't configured.
829 case CPUCLASS_286: /* a 286 should not make it this far, anyway */
831 #if !defined(I486_CPU)
834 #if !defined(I586_CPU)
837 #if !defined(I686_CPU)
840 panic("CPU class not configured");
847 static volatile u_int trap_by_rdmsr;
850 * Special exception 6 handler.
851 * The rdmsr instruction generates invalid opcodes fault on 486-class
852 * Cyrix CPU. Stacked eip register points the rdmsr instruction in the
853 * function identblue() when this handler is called. Stacked eip should
862 .type " __XSTRING(CNAME(bluetrap6)) ",@function \n\
863 " __XSTRING(CNAME(bluetrap6)) ": \n\
865 movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
866 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
871 * Special exception 13 handler.
872 * Accessing non-existent MSR generates general protection fault.
874 inthand_t bluetrap13;
880 .type " __XSTRING(CNAME(bluetrap13)) ",@function \n\
881 " __XSTRING(CNAME(bluetrap13)) ": \n\
883 movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) " \n\
884 popl %eax /* discard error code */ \n\
885 addl $2, (%esp) /* rdmsr is a 2-byte instruction */ \n\
890 * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
891 * support cpuid instruction. This function should be called after
892 * loading interrupt descriptor table register.
894 * I don't like this method that handles fault, but I couldn't get
895 * information for any other methods. Does blue giant know?
904 * Cyrix 486-class CPU does not support rdmsr instruction.
905 * The rdmsr instruction generates invalid opcode fault, and exception
906 * will be trapped by bluetrap6() on Cyrix 486-class CPU. The
907 * bluetrap6() set the magic number to trap_by_rdmsr.
909 setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
910 GSEL(GCODE_SEL, SEL_KPL));
913 * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
914 * In this case, rdmsr generates general protection fault, and
915 * exception will be trapped by bluetrap13().
917 setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
918 GSEL(GCODE_SEL, SEL_KPL));
920 rdmsr(0x1002); /* Cyrix CPU generates fault. */
922 if (trap_by_rdmsr == 0xa8c1d)
923 return IDENTBLUE_CYRIX486;
924 else if (trap_by_rdmsr == 0xa89c4)
925 return IDENTBLUE_CYRIXM2;
926 return IDENTBLUE_IBMCPU;
930 /* Update TSC freq with the value indicated by the caller. */
932 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
935 * If there was an error during the transition or
936 * TSC is P-state invariant, don't do anything.
938 if (status != 0 || tsc_is_invariant)
941 /* Total setting for this level gives the new frequency in MHz. */
942 hw_clockrate = level->total_set.freq;
947 * Final stage of CPU identification. -- Should I check TI?
955 cpu_vendor_id = find_cpu_vendor_id();
958 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
959 * function number again if it is set from BIOS. It is necessary
960 * for probing correct CPU topology later.
961 * XXX This is only done on the BSP package.
963 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
964 ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
965 (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
967 msr = rdmsr(MSR_IA32_MISC_ENABLE);
968 if ((msr & 0x400000ULL) != 0) {
969 wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
975 /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
976 if (cpu_vendor_id == CPU_VENDOR_INTEL ||
977 cpu_vendor_id == CPU_VENDOR_AMD) {
979 if (cpu_exthigh >= 0x80000001) {
980 do_cpuid(0x80000001, regs);
981 amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
982 amd_feature2 = regs[2];
985 if (cpu_exthigh >= 0x80000007) {
986 do_cpuid(0x80000007, regs);
987 amd_pminfo = regs[3];
990 if (cpu_exthigh >= 0x80000008) {
991 do_cpuid(0x80000008, regs);
992 cpu_procinfo2 = regs[2];
994 } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
996 * There are BlueLightning CPUs that do not change
997 * undefined flags by dividing 5 by 2. In this case,
998 * the CPU identification routine in locore.s leaves
999 * cpu_vendor null string and puts CPU_486 into the
1002 isblue = identblue();
1003 if (isblue == IDENTBLUE_IBMCPU) {
1004 strcpy(cpu_vendor, "IBM");
1005 cpu_vendor_id = CPU_VENDOR_IBM;
1011 * Set MI flags for MI procedures implemented using machine-specific
1014 if (cpu_feature & CPUID_SSE2)
1015 cpu_mi_feature |= CPU_MI_BZERONT;
1017 if (cpu_feature2 & CPUID2_MON)
1018 cpu_mi_feature |= CPU_MI_MONITOR;
1021 if ((cpu_feature & CPUID_SSE2) == 0)
1022 panic("CPU does not has SSE2, remove options CPU_HAS_SSE2");
1027 find_cpu_vendor_id(void)
1031 for (i = 0; i < NELEM(cpu_vendors); i++)
1032 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1033 return (cpu_vendors[i].vendor_id);
1038 print_AMD_assoc(int i)
1041 kprintf(", fully associative\n");
1043 kprintf(", %d-way associative\n", i);
1047 * #31116 Rev 3.06 section 3.9
1048 * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1051 print_AMD_L2L3_assoc(int i)
1053 static const char *assoc_str[] = {
1055 [0x1] = "direct mapped",
1056 [0x2] = "2-way associative",
1057 [0x4] = "4-way associative",
1058 [0x6] = "8-way associative",
1059 [0x8] = "16-way associative",
1060 [0xa] = "32-way associative",
1061 [0xb] = "48-way associative",
1062 [0xc] = "64-way associative",
1063 [0xd] = "96-way associative",
1064 [0xe] = "128-way associative",
1065 [0xf] = "fully associative"
1069 if (assoc_str[i] == NULL)
1070 kprintf(", unknown associative\n");
1072 kprintf(", %s\n", assoc_str[i]);
1076 print_AMD_info(void)
1080 if (cpu_exthigh >= 0x80000005) {
1083 do_cpuid(0x80000005, regs);
1084 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1085 print_AMD_assoc(regs[1] >> 24);
1086 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1087 print_AMD_assoc((regs[1] >> 8) & 0xff);
1088 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1089 kprintf(", %d bytes/line", regs[2] & 0xff);
1090 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1091 print_AMD_assoc((regs[2] >> 16) & 0xff);
1092 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1093 kprintf(", %d bytes/line", regs[3] & 0xff);
1094 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1095 print_AMD_assoc((regs[3] >> 16) & 0xff);
1096 if (cpu_exthigh >= 0x80000006) { /* K6-III or later */
1097 do_cpuid(0x80000006, regs);
1099 * Report right L2 cache size on Duron rev. A0.
1101 if ((cpu_id & 0xFF0) == 0x630)
1102 kprintf("L2 internal cache: 64 kbytes");
1104 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1106 kprintf(", %d bytes/line", regs[2] & 0xff);
1107 kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1108 print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1111 * #31116 Rev 3.06 section 2.16.2:
1112 * ... If EDX[31:16] is not zero then the processor
1113 * includes an L3. ...
1115 if ((regs[3] & 0xffff0000) != 0) {
1116 kprintf("L3 shared cache: %d kbytes",
1117 (regs[3] >> 18) * 512);
1118 kprintf(", %d bytes/line", regs[3] & 0xff);
1119 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1120 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1124 if (((cpu_id & 0xf00) == 0x500)
1125 && (((cpu_id & 0x0f0) > 0x80)
1126 || (((cpu_id & 0x0f0) == 0x80)
1127 && (cpu_id & 0x00f) > 0x07))) {
1128 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1129 amd_whcr = rdmsr(0xc0000082);
1130 if (!(amd_whcr & (0x3ff << 22))) {
1131 kprintf("Write Allocate Disable\n");
1133 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1134 (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1135 kprintf("Write Allocate 15-16M bytes: %s\n",
1136 (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1138 } else if (((cpu_id & 0xf00) == 0x500)
1139 && ((cpu_id & 0x0f0) > 0x50)) {
1140 /* K6, K6-2(old core) */
1141 amd_whcr = rdmsr(0xc0000082);
1142 if (!(amd_whcr & (0x7f << 1))) {
1143 kprintf("Write Allocate Disable\n");
1145 kprintf("Write Allocate Enable Limit: %dM bytes\n",
1146 (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1147 kprintf("Write Allocate 15-16M bytes: %s\n",
1148 (amd_whcr & 0x0001) ? "Enable" : "Disable");
1149 kprintf("Hardware Write Allocate Control: %s\n",
1150 (amd_whcr & 0x0100) ? "Enable" : "Disable");
1155 * Opteron Rev E shows a bug as in very rare occasions a read memory
1156 * barrier is not performed as expected if it is followed by a
1157 * non-atomic read-modify-write instruction.
1158 * As long as that bug pops up very rarely (intensive machine usage
1159 * on other operating systems generally generates one unexplainable
1160 * crash any 2 months) and as long as a model specific fix would be
1161 * impratical at this stage, print out a warning string if the broken
1162 * model and family are identified.
1164 if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1165 CPUID_TO_MODEL(cpu_id) <= 0x3f)
1166 kprintf("WARNING: This architecture revision has known SMP "
1167 "hardware bugs which may cause random instability\n");
1171 print_INTEL_info(void)
1174 u_int rounds, regnum;
1175 u_int nwaycode, nway;
1177 if (cpu_high >= 2) {
1180 do_cpuid(0x2, regs);
1181 if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1182 break; /* we have a buggy CPU */
1184 for (regnum = 0; regnum <= 3; ++regnum) {
1185 if (regs[regnum] & (1<<31))
1188 print_INTEL_TLB(regs[regnum] & 0xff);
1189 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1190 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1191 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1193 } while (--rounds > 0);
1196 if (cpu_exthigh >= 0x80000006) {
1197 do_cpuid(0x80000006, regs);
1198 nwaycode = (regs[2] >> 12) & 0x0f;
1199 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1200 nway = 1 << (nwaycode / 2);
1203 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1204 (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1211 print_INTEL_TLB(u_int data)
1219 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1222 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1225 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1228 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1231 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1234 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1237 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1240 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1243 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1246 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1249 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1252 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1255 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1258 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1261 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1264 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1267 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1270 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1273 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1276 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1279 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1282 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1285 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1288 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1291 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1294 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1297 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1300 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1303 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1306 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1309 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1312 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1315 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1318 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1321 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1324 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1327 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1330 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1333 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1336 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1339 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1342 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1345 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1348 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1351 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1354 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1357 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1360 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1363 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1366 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1369 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1372 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1378 print_transmeta_info(void)
1380 u_int regs[4], nreg = 0;
1382 do_cpuid(0x80860000, regs);
1384 if (nreg >= 0x80860001) {
1385 do_cpuid(0x80860001, regs);
1386 kprintf(" Processor revision %u.%u.%u.%u\n",
1387 (regs[1] >> 24) & 0xff,
1388 (regs[1] >> 16) & 0xff,
1389 (regs[1] >> 8) & 0xff,
1392 if (nreg >= 0x80860002) {
1393 do_cpuid(0x80860002, regs);
1394 kprintf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
1395 (regs[1] >> 24) & 0xff,
1396 (regs[1] >> 16) & 0xff,
1397 (regs[1] >> 8) & 0xff,
1401 if (nreg >= 0x80860006) {
1403 do_cpuid(0x80860003, (u_int*) &info[0]);
1404 do_cpuid(0x80860004, (u_int*) &info[16]);
1405 do_cpuid(0x80860005, (u_int*) &info[32]);
1406 do_cpuid(0x80860006, (u_int*) &info[48]);
1408 kprintf(" %s\n", info);
1413 print_via_padlock_info(void)
1417 /* Check for supported models. */
1418 switch (cpu_id & 0xff0) {
1420 if ((cpu_id & 0xf) < 3)
1430 do_cpuid(0xc0000000, regs);
1431 if (regs[0] >= 0xc0000001)
1432 do_cpuid(0xc0000001, regs);
1436 kprintf("\n VIA Padlock Features=0x%b", regs[3],
1440 "\011AES-CTR" /* ACE2 */
1441 "\013SHA1,SHA256" /* PHE */
1447 additional_cpu_info(const char *line)
1451 if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1452 additional_cpu_info_ary[i] = line;
1453 ++additional_cpu_info_count;