2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine/pmap.h>
36 #include <machine_base/apic/mpapic.h>
37 #include <machine/segments.h>
38 #include <sys/thread2.h>
40 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
44 /* EISA Edge/Level trigger control registers */
45 #define ELCR0 0x4d0 /* eisa irq 0-7 */
46 #define ELCR1 0x4d1 /* eisa irq 8-15 */
48 volatile lapic_t *lapic;
50 static void lapic_timer_calibrate(void);
51 static void lapic_timer_set_divisor(int);
52 static void lapic_timer_fixup_handler(void *);
53 static void lapic_timer_restart_handler(void *);
55 void lapic_timer_process(void);
56 void lapic_timer_process_frame(struct intrframe *);
58 static int lapic_timer_enable = 1;
59 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
61 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
62 static void lapic_timer_intr_enable(struct cputimer_intr *);
63 static void lapic_timer_intr_restart(struct cputimer_intr *);
64 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
66 static struct cputimer_intr lapic_cputimer_intr = {
68 .reload = lapic_timer_intr_reload,
69 .enable = lapic_timer_intr_enable,
70 .config = cputimer_intr_default_config,
71 .restart = lapic_timer_intr_restart,
72 .pmfixup = lapic_timer_intr_pmfixup,
73 .initclock = cputimer_intr_default_initclock,
74 .next = SLIST_ENTRY_INITIALIZER,
76 .type = CPUTIMER_INTR_LAPIC,
77 .prio = CPUTIMER_INTR_PRIO_LAPIC,
78 .caps = CPUTIMER_INTR_CAP_NONE
82 * pointers to pmapped apic hardware.
85 volatile ioapic_t **ioapic;
87 static int lapic_timer_divisor_idx = -1;
88 static const uint32_t lapic_timer_divisors[] = {
89 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
90 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
92 #define APIC_TIMER_NDIVISORS \
93 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
104 * Enable APIC, configure interrupts.
107 apic_initialize(boolean_t bsp)
113 * setup LVT1 as ExtINT on the BSP. This is theoretically an
114 * aggregate interrupt input from the 8259. The INTA cycle
115 * will be routed to the external controller (the 8259) which
116 * is expected to supply the vector.
118 * Must be setup edge triggered, active high.
120 * Disable LVT1 on the APs. It doesn't matter what delivery
121 * mode we use because we leave it masked.
123 temp = lapic->lvt_lint0;
124 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
125 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
126 if (mycpu->gd_cpuid == 0)
127 temp |= APIC_LVT_DM_EXTINT;
129 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
130 lapic->lvt_lint0 = temp;
133 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
135 temp = lapic->lvt_lint1;
136 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
137 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
138 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
139 lapic->lvt_lint1 = temp;
142 * Mask the apic error interrupt, apic performance counter
145 lapic->lvt_error = lapic->lvt_error | APIC_LVT_MASKED;
146 lapic->lvt_pcint = lapic->lvt_pcint | APIC_LVT_MASKED;
148 /* Set apic timer vector and mask the apic timer interrupt. */
149 timer = lapic->lvt_timer;
150 timer &= ~APIC_LVTT_VECTOR;
151 timer |= XTIMER_OFFSET;
152 timer |= APIC_LVTT_MASKED;
153 lapic->lvt_timer = timer;
156 * Set the Task Priority Register as needed. At the moment allow
157 * interrupts on all cpus (the APs will remain CLId until they are
158 * ready to deal). We could disable all but IPIs by setting
159 * temp |= TPR_IPI_ONLY for cpu != 0.
162 temp &= ~APIC_TPR_PRIO; /* clear priority field */
165 * If we are NOT running the IO APICs, the LAPIC will only be used
166 * for IPIs. Set the TPR to prevent any unintentional interrupts.
168 temp |= TPR_IPI_ONLY;
174 * enable the local APIC
177 temp |= APIC_SVR_ENABLE; /* enable the APIC */
178 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
181 * Set the spurious interrupt vector. The low 4 bits of the vector
184 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
185 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
186 temp &= ~APIC_SVR_VECTOR;
187 temp |= XSPURIOUSINT_OFFSET;
192 * Pump out a few EOIs to clean out interrupts that got through
193 * before we were able to set the TPR.
200 lapic_timer_calibrate();
201 if (lapic_timer_enable) {
202 cputimer_intr_register(&lapic_cputimer_intr);
203 cputimer_intr_select(&lapic_cputimer_intr, 0);
206 lapic_timer_set_divisor(lapic_timer_divisor_idx);
210 apic_dump("apic_initialize()");
215 lapic_timer_set_divisor(int divisor_idx)
217 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
218 lapic->dcr_timer = lapic_timer_divisors[divisor_idx];
222 lapic_timer_oneshot(u_int count)
226 value = lapic->lvt_timer;
227 value &= ~APIC_LVTT_PERIODIC;
228 lapic->lvt_timer = value;
229 lapic->icr_timer = count;
233 lapic_timer_oneshot_quick(u_int count)
235 lapic->icr_timer = count;
239 lapic_timer_calibrate(void)
243 /* Try to calibrate the local APIC timer. */
244 for (lapic_timer_divisor_idx = 0;
245 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
246 lapic_timer_divisor_idx++) {
247 lapic_timer_set_divisor(lapic_timer_divisor_idx);
248 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
250 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer;
251 if (value != APIC_TIMER_MAX_COUNT)
254 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
255 panic("lapic: no proper timer divisor?!\n");
256 lapic_cputimer_intr.freq = value / 2;
258 kprintf("lapic: divisor index %d, frequency %u Hz\n",
259 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
263 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
267 gd->gd_timer_running = 0;
269 count = sys_cputimer->count();
270 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
271 systimer_intr(&count, 0, frame);
275 lapic_timer_process(void)
277 lapic_timer_process_oncpu(mycpu, NULL);
281 lapic_timer_process_frame(struct intrframe *frame)
283 lapic_timer_process_oncpu(mycpu, frame);
287 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
289 struct globaldata *gd = mycpu;
291 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
295 if (gd->gd_timer_running) {
296 if (reload < lapic->ccr_timer)
297 lapic_timer_oneshot_quick(reload);
299 gd->gd_timer_running = 1;
300 lapic_timer_oneshot_quick(reload);
305 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
309 timer = lapic->lvt_timer;
310 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
311 lapic->lvt_timer = timer;
313 lapic_timer_fixup_handler(NULL);
317 lapic_timer_fixup_handler(void *arg)
324 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
326 * Detect the presence of C1E capability mostly on latest
327 * dual-cores (or future) k8 family. This feature renders
328 * the local APIC timer dead, so we disable it by reading
329 * the Interrupt Pending Message register and clearing both
330 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
333 * "BIOS and Kernel Developer's Guide for AMD NPT
334 * Family 0Fh Processors"
335 * #32559 revision 3.00
337 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
338 (cpu_id & 0x0fff0000) >= 0x00040000) {
341 msr = rdmsr(0xc0010055);
342 if (msr & 0x18000000) {
343 struct globaldata *gd = mycpu;
345 kprintf("cpu%d: AMD C1E detected\n",
347 wrmsr(0xc0010055, msr & ~0x18000000ULL);
350 * We are kinda stalled;
353 gd->gd_timer_running = 1;
354 lapic_timer_oneshot_quick(2);
364 lapic_timer_restart_handler(void *dummy __unused)
368 lapic_timer_fixup_handler(&started);
370 struct globaldata *gd = mycpu;
372 gd->gd_timer_running = 1;
373 lapic_timer_oneshot_quick(2);
378 * This function is called only by ACPI-CA code currently:
379 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
380 * module controls PM. So once ACPI-CA is attached, we try
381 * to apply the fixup to prevent LAPIC timer from hanging.
384 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
386 lwkt_send_ipiq_mask(smp_active_mask,
387 lapic_timer_fixup_handler, NULL);
391 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
393 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
398 * dump contents of local APIC registers
403 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
404 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
405 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr);
415 #define IOAPIC_ISA_INTS 16
416 #define REDIRCNT_IOAPIC(A) \
417 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
419 static int trigger (int apic, int pin, u_int32_t * flags);
420 static void polarity (int apic, int pin, u_int32_t * flags, int level);
422 #define DEFAULT_FLAGS \
428 #define DEFAULT_ISA_FLAGS \
437 io_apic_set_id(int apic, int id)
441 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
442 if (((ux & APIC_ID_MASK) >> 24) != id) {
443 kprintf("Changing APIC ID for IO APIC #%d"
444 " from %d to %d on chip\n",
445 apic, ((ux & APIC_ID_MASK) >> 24), id);
446 ux &= ~APIC_ID_MASK; /* clear the ID field */
448 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
449 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
450 if (((ux & APIC_ID_MASK) >> 24) != id)
451 panic("can't control IO APIC #%d ID, reg: 0x%08x",
458 io_apic_get_id(int apic)
460 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
469 io_apic_setup_intpin(int apic, int pin)
471 int bus, bustype, irq;
472 u_char select; /* the select register is 8 bits */
473 u_int32_t flags; /* the window register is 32 bits */
474 u_int32_t target; /* the window register is 32 bits */
475 u_int32_t vector; /* the window register is 32 bits */
480 select = pin * 2 + IOAPIC_REDTBL0; /* register */
483 * Always clear an IO APIC pin before [re]programming it. This is
484 * particularly important if the pin is set up for a level interrupt
485 * as the IOART_REM_IRR bit might be set. When we reprogram the
486 * vector any EOI from pending ints on this pin could be lost and
487 * IRR might never get reset.
489 * To fix this problem, clear the vector and make sure it is
490 * programmed as an edge interrupt. This should theoretically
491 * clear IRR so we can later, safely program it as a level
496 flags = io_apic_read(apic, select) & IOART_RESV;
497 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
498 flags |= IOART_DESTPHY | IOART_DELFIXED;
500 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
501 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
505 io_apic_write(apic, select, flags | vector);
506 io_apic_write(apic, select + 1, target);
511 * We only deal with vectored interrupts here. ? documentation is
512 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
515 * This test also catches unconfigured pins.
517 if (apic_int_type(apic, pin) != 0)
521 * Leave the pin unprogrammed if it does not correspond to
524 irq = apic_irq(apic, pin);
528 /* determine the bus type for this pin */
529 bus = apic_src_bus_id(apic, pin);
532 bustype = apic_bus_type(bus);
534 if ((bustype == ISA) &&
535 (pin < IOAPIC_ISA_INTS) &&
537 (apic_polarity(apic, pin) == 0x1) &&
538 (apic_trigger(apic, pin) == 0x3)) {
540 * A broken BIOS might describe some ISA
541 * interrupts as active-high level-triggered.
542 * Use default ISA flags for those interrupts.
544 flags = DEFAULT_ISA_FLAGS;
547 * Program polarity and trigger mode according to
550 flags = DEFAULT_FLAGS;
551 level = trigger(apic, pin, &flags);
553 int_to_apicintpin[irq].flags |= AIMI_FLAG_LEVEL;
554 polarity(apic, pin, &flags, level);
558 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
559 kgetenv_int(envpath, &cpuid);
561 /* ncpus may not be available yet */
566 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
567 apic, pin, irq, cpuid);
571 * Program the appropriate registers. This routing may be
572 * overridden when an interrupt handler for a device is
573 * actually added (see register_int(), which calls through
574 * the MACHINTR ABI to set up an interrupt handler/vector).
576 * The order in which we must program the two registers for
577 * safety is unclear! XXX
581 vector = IDT_OFFSET + irq; /* IDT vec */
582 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
583 /* Deliver all interrupts to CPU0 (BSP) */
584 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
586 flags |= io_apic_read(apic, select) & IOART_RESV;
587 io_apic_write(apic, select, flags | vector);
588 io_apic_write(apic, select + 1, target);
594 io_apic_setup(int apic)
599 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
600 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
602 for (pin = 0; pin < maxpin; ++pin) {
603 io_apic_setup_intpin(apic, pin);
606 if (apic_int_type(apic, pin) >= 0) {
607 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
608 " cannot program!\n", apic, pin);
613 /* return GOOD status */
616 #undef DEFAULT_ISA_FLAGS
620 #define DEFAULT_EXTINT_FLAGS \
629 * XXX this function is only used by 8254 setup
630 * Setup the source of External INTerrupts.
633 ext_int_setup(int apic, int intr)
635 u_char select; /* the select register is 8 bits */
636 u_int32_t flags; /* the window register is 32 bits */
637 u_int32_t target; /* the window register is 32 bits */
638 u_int32_t vector; /* the window register is 32 bits */
642 if (apic_int_type(apic, intr) != 3)
646 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
647 kgetenv_int(envpath, &cpuid);
649 /* ncpus may not be available yet */
653 /* Deliver interrupts to CPU0 (BSP) */
654 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
656 select = IOAPIC_REDTBL0 + (2 * intr);
657 vector = IDT_OFFSET + intr;
658 flags = DEFAULT_EXTINT_FLAGS;
660 io_apic_write(apic, select, flags | vector);
661 io_apic_write(apic, select + 1, target);
665 #undef DEFAULT_EXTINT_FLAGS
669 * Set the trigger level for an IO APIC pin.
672 trigger(int apic, int pin, u_int32_t * flags)
677 static int intcontrol = -1;
679 switch (apic_trigger(apic, pin)) {
685 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
689 *flags |= IOART_TRGRLVL;
697 if ((id = apic_src_bus_id(apic, pin)) == -1)
700 switch (apic_bus_type(id)) {
702 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
706 eirq = apic_src_bus_irq(apic, pin);
708 if (eirq < 0 || eirq > 15) {
709 kprintf("EISA IRQ %d?!?!\n", eirq);
713 if (intcontrol == -1) {
714 intcontrol = inb(ELCR1) << 8;
715 intcontrol |= inb(ELCR0);
716 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
719 /* Use ELCR settings to determine level or edge mode */
720 level = (intcontrol >> eirq) & 1;
723 * Note that on older Neptune chipset based systems, any
724 * pci interrupts often show up here and in the ELCR as well
725 * as level sensitive interrupts attributed to the EISA bus.
729 *flags |= IOART_TRGRLVL;
731 *flags &= ~IOART_TRGRLVL;
736 *flags |= IOART_TRGRLVL;
745 panic("bad APIC IO INT flags");
750 * Set the polarity value for an IO APIC pin.
753 polarity(int apic, int pin, u_int32_t * flags, int level)
757 switch (apic_polarity(apic, pin)) {
763 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
767 *flags |= IOART_INTALO;
775 if ((id = apic_src_bus_id(apic, pin)) == -1)
778 switch (apic_bus_type(id)) {
780 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
784 /* polarity converter always gives active high */
785 *flags &= ~IOART_INTALO;
789 *flags |= IOART_INTALO;
798 panic("bad APIC IO INT flags");
803 * Print contents of unmasked IRQs.
810 kprintf("SMP: enabled INTs: ");
811 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
812 if ((int_to_apicintpin[x].flags & AIMI_FLAG_MASKED) == 0)
820 * Inter Processor Interrupt functions.
826 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
828 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
829 * vector is any valid SYSTEM INT vector
830 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
832 * A backlog of requests can create a deadlock between cpus. To avoid this
833 * we have to be able to accept IPIs at the same time we are trying to send
834 * them. The critical section prevents us from attempting to send additional
835 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
836 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
837 * to occur but fortunately it does not happen too often.
840 apic_ipi(int dest_type, int vector, int delivery_mode)
845 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
846 unsigned long rflags = read_rflags();
848 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
851 write_rflags(rflags);
854 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
855 delivery_mode | vector;
856 lapic->icr_lo = icr_lo;
862 single_apic_ipi(int cpu, int vector, int delivery_mode)
868 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
869 unsigned long rflags = read_rflags();
871 while ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
874 write_rflags(rflags);
876 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
877 icr_hi |= (CPU_TO_ID(cpu) << 24);
878 lapic->icr_hi = icr_hi;
881 icr_lo = (lapic->icr_lo & APIC_ICRLO_RESV_MASK)
882 | APIC_DEST_DESTFLD | delivery_mode | vector;
885 lapic->icr_lo = icr_lo;
892 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
894 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
895 * to the target, and the scheduler does not 'poll' for IPI messages.
898 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
904 if ((lapic->icr_lo & APIC_DELSTAT_MASK) != 0) {
908 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
909 icr_hi |= (CPU_TO_ID(cpu) << 24);
910 lapic->icr_hi = icr_hi;
913 icr_lo = (lapic->icr_lo & APIC_RESV2_MASK)
914 | APIC_DEST_DESTFLD | delivery_mode | vector;
917 lapic->icr_lo = icr_lo;
925 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
927 * target is a bitmask of destination cpus. Vector is any
928 * valid system INT vector. Delivery mode may be either
929 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
932 selected_apic_ipi(u_int target, int vector, int delivery_mode)
936 int n = bsfl(target);
938 single_apic_ipi(n, vector, delivery_mode);
944 * Timer code, in development...
945 * - suggested by rgrimes@gndrsh.aac.dev.com
948 get_apic_timer_frequency(void)
950 return(lapic_cputimer_intr.freq);
954 * Load a 'downcount time' in uSeconds.
957 set_apic_timer(int us)
962 * When we reach here, lapic timer's frequency
963 * must have been calculated as well as the
964 * divisor (lapic->dcr_timer is setup during the
965 * divisor calculation).
967 KKASSERT(lapic_cputimer_intr.freq != 0 &&
968 lapic_timer_divisor_idx >= 0);
970 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
971 lapic_timer_oneshot(count);
976 * Read remaining time in timer.
979 read_apic_timer(void)
982 /** XXX FIXME: we need to return the actual remaining time,
983 * for now we just return the remaining count.
986 return lapic->ccr_timer;
992 * Spin-style delay, set delay time in uS, spin till it drains.
997 set_apic_timer(count);
998 while (read_apic_timer())
1003 lapic_init(vm_offset_t lapic_addr)
1006 * lapic not mapped yet (pmap_init is called too late)
1008 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
1011 /* Local apic is mapped on last page */
1012 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1013 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1016 kprintf("lapic: at 0x%08lx\n", lapic_addr);
1019 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1020 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1025 struct lapic_enumerator *e;
1028 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1029 error = e->lapic_probe(e);
1034 panic("can't config lapic\n");
1036 e->lapic_enumerate(e);
1040 lapic_enumerator_register(struct lapic_enumerator *ne)
1042 struct lapic_enumerator *e;
1044 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1045 if (e->lapic_prio < ne->lapic_prio) {
1046 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1050 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);