2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bgereg.h,v 1.25 2008/10/22 14:24:24 sephe Exp $
38 * BCM570x memory map. The internal memory layout varies somewhat
39 * depending on whether or not we have external SSRAM attached.
40 * The BCM5700 can have up to 16MB of external memory. The BCM5701
41 * is apparently not designed to use external SSRAM. The mappings
42 * up to the first 4 send rings are the same for both internal and
43 * external memory configurations. Note that mini RX ring space is
44 * only available with external SSRAM configurations, which means
45 * the mini RX ring is not supported on the BCM5701.
47 * The NIC's memory can be accessed by the host in one of 3 ways:
49 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
50 * registers in PCI config space can be used to read any 32-bit
51 * address within the NIC's memory.
53 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
54 * space can be used in conjunction with the memory window in the
55 * device register space at offset 0x8000 to read any 32K chunk
58 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
59 * set, the device I/O mapping consumes 32MB of host address space,
60 * allowing all of the registers and internal NIC memory to be
61 * accessed directly. NIC memory addresses are offset by 0x01000000.
62 * Flat mode consumes so much host address space that it is not
65 #define BGE_PAGE_ZERO 0x00000000
66 #define BGE_PAGE_ZERO_END 0x000000FF
67 #define BGE_SEND_RING_RCB 0x00000100
68 #define BGE_SEND_RING_RCB_END 0x000001FF
69 #define BGE_RX_RETURN_RING_RCB 0x00000200
70 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
71 #define BGE_STATS_BLOCK 0x00000300
72 #define BGE_STATS_BLOCK_END 0x00000AFF
73 #define BGE_STATUS_BLOCK 0x00000B00
74 #define BGE_STATUS_BLOCK_END 0x00000B4F
75 #define BGE_SOFTWARE_GENCOMM 0x00000B50
76 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
77 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
78 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
79 #define BGE_UNMAPPED 0x00001000
80 #define BGE_UNMAPPED_END 0x00001FFF
81 #define BGE_DMA_DESCRIPTORS 0x00002000
82 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
83 #define BGE_SEND_RING_1_TO_4 0x00004000
84 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
86 /* Mappings for internal memory configuration */
87 #define BGE_STD_RX_RINGS 0x00006000
88 #define BGE_STD_RX_RINGS_END 0x00006FFF
89 #define BGE_JUMBO_RX_RINGS 0x00007000
90 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
91 #define BGE_BUFFPOOL_1 0x00008000
92 #define BGE_BUFFPOOL_1_END 0x0000FFFF
93 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
94 #define BGE_BUFFPOOL_2_END 0x00017FFF
95 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
96 #define BGE_BUFFPOOL_3_END 0x0001FFFF
98 /* Mappings for external SSRAM configurations */
99 #define BGE_SEND_RING_5_TO_6 0x00006000
100 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
101 #define BGE_SEND_RING_7_TO_8 0x00007000
102 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
103 #define BGE_SEND_RING_9_TO_16 0x00008000
104 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
105 #define BGE_EXT_STD_RX_RINGS 0x0000C000
106 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
107 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
108 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
109 #define BGE_MINI_RX_RINGS 0x0000E000
110 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
111 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
112 #define BGE_AVAIL_REGION1_END 0x00017FFF
113 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
114 #define BGE_AVAIL_REGION2_END 0x0001FFFF
115 #define BGE_EXT_SSRAM 0x00020000
116 #define BGE_EXT_SSRAM_END 0x000FFFFF
120 * BCM570x register offsets. These are memory mapped registers
121 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
122 * Each register must be accessed using 32 bit operations.
124 * All registers are accessed through a 32K shared memory block.
125 * The first group of registers are actually copies of the PCI
126 * configuration space registers.
130 * PCI registers defined in the PCI 2.2 spec.
132 #define BGE_PCI_VID 0x00
133 #define BGE_PCI_DID 0x02
134 #define BGE_PCI_CMD 0x04
135 #define BGE_PCI_STS 0x06
136 #define BGE_PCI_REV 0x08
137 #define BGE_PCI_CLASS 0x09
138 #define BGE_PCI_CACHESZ 0x0C
139 #define BGE_PCI_LATTIMER 0x0D
140 #define BGE_PCI_HDRTYPE 0x0E
141 #define BGE_PCI_BIST 0x0F
142 #define BGE_PCI_BAR0 0x10
143 #define BGE_PCI_BAR1 0x14
144 #define BGE_PCI_SUBSYS 0x2C
145 #define BGE_PCI_SUBVID 0x2E
146 #define BGE_PCI_ROMBASE 0x30
147 #define BGE_PCI_CAPPTR 0x34
148 #define BGE_PCI_INTLINE 0x3C
149 #define BGE_PCI_INTPIN 0x3D
150 #define BGE_PCI_MINGNT 0x3E
151 #define BGE_PCI_MAXLAT 0x3F
152 #define BGE_PCI_PCIXCAP 0x40
153 #define BGE_PCI_NEXTPTR_PM 0x41
154 #define BGE_PCI_PCIX_CMD 0x42
155 #define BGE_PCI_PCIX_STS 0x44
156 #define BGE_PCI_PWRMGMT_CAPID 0x48
157 #define BGE_PCI_NEXTPTR_VPD 0x49
158 #define BGE_PCI_PWRMGMT_CAPS 0x4A
159 #define BGE_PCI_PWRMGMT_CMD 0x4C
160 #define BGE_PCI_PWRMGMT_STS 0x4D
161 #define BGE_PCI_PWRMGMT_DATA 0x4F
162 #define BGE_PCI_VPD_CAPID 0x50
163 #define BGE_PCI_NEXTPTR_MSI 0x51
164 #define BGE_PCI_VPD_ADDR 0x52
165 #define BGE_PCI_VPD_DATA 0x54
166 #define BGE_PCI_MSI_CAPID 0x58
167 #define BGE_PCI_NEXTPTR_NONE 0x59
168 #define BGE_PCI_MSI_CTL 0x5A
169 #define BGE_PCI_MSI_ADDR_HI 0x5C
170 #define BGE_PCI_MSI_ADDR_LO 0x60
171 #define BGE_PCI_MSI_DATA 0x64
174 #define BGE_PCIE_CAPID_REG 0xD0
175 #define BGE_PCIE_CAPID 0x10
178 * PCI registers specific to the BCM570x family.
180 #define BGE_PCI_MISC_CTL 0x68
181 #define BGE_PCI_DMA_RW_CTL 0x6C
182 #define BGE_PCI_PCISTATE 0x70
183 #define BGE_PCI_CLKCTL 0x74
184 #define BGE_PCI_REG_BASEADDR 0x78
185 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
186 #define BGE_PCI_REG_DATA 0x80
187 #define BGE_PCI_MEMWIN_DATA 0x84
188 #define BGE_PCI_MODECTL 0x88
189 #define BGE_PCI_MISC_CFG 0x8C
190 #define BGE_PCI_MISC_LOCALCTL 0x90
191 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
192 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
193 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
194 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
195 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
196 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
197 #define BGE_PCI_ISR_MBX_HI 0xB0
198 #define BGE_PCI_ISR_MBX_LO 0xB4
199 #define BGE_PCI_PRODID_ASICREV 0xBC
201 /* PCI Misc. Host control register */
202 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
203 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
204 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
205 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
206 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
207 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
208 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
209 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
210 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200
211 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
212 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16
214 #if BYTE_ORDER == LITTLE_ENDIAN
215 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
216 BGE_MODECTL_BYTESWAP_DATA | \
217 BGE_MODECTL_WORDSWAP_DATA)
219 #define BGE_DMA_SWAP_OPTIONS (BGE_MODECTL_WORDSWAP_NONFRAME |\
220 BGE_MODECTL_BYTESWAP_NONFRAME |\
221 BGE_MODECTL_BYTESWAP_DATA |
222 BGE_MODECTL_WORDSWAP_DATA)
225 #define BGE_HIF_SWAP_OPTIONS BGE_PCIMISCCTL_ENDIAN_WORDSWAP
226 #define BGE_INIT (BGE_HIF_SWAP_OPTIONS | \
227 BGE_PCIMISCCTL_CLEAR_INTA | \
228 BGE_PCIMISCCTL_MASK_PCI_INTR | \
229 BGE_PCIMISCCTL_INDIRECT_ACCESS)
231 #define BGE_PCISTAT_INTR_NOTACT 0x2
233 #define BGE_CHIPID_TIGON_I 0x4000
234 #define BGE_CHIPID_TIGON_II 0x6000
235 #define BGE_CHIPID_BCM5700_A0 0x7000
236 #define BGE_CHIPID_BCM5700_A1 0x7001
237 #define BGE_CHIPID_BCM5700_B0 0x7100
238 #define BGE_CHIPID_BCM5700_B1 0x7101
239 #define BGE_CHIPID_BCM5700_B2 0x7102
240 #define BGE_CHIPID_BCM5700_B3 0x7103
241 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104
242 #define BGE_CHIPID_BCM5700_C0 0x7200
243 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
244 #define BGE_CHIPID_BCM5701_B0 0x0100
245 #define BGE_CHIPID_BCM5701_B2 0x0102
246 #define BGE_CHIPID_BCM5701_B5 0x0105
247 #define BGE_CHIPID_BCM5703_A0 0x1000
248 #define BGE_CHIPID_BCM5703_A1 0x1001
249 #define BGE_CHIPID_BCM5703_A2 0x1002
250 #define BGE_CHIPID_BCM5703_A3 0x1003
251 #define BGE_CHIPID_BCM5703_B0 0x1100
252 #define BGE_CHIPID_BCM5704_A0 0x2000
253 #define BGE_CHIPID_BCM5704_A1 0x2001
254 #define BGE_CHIPID_BCM5704_A2 0x2002
255 #define BGE_CHIPID_BCM5704_A3 0x2003
256 #define BGE_CHIPID_BCM5704_B0 0x2100
257 #define BGE_CHIPID_BCM5705_A0 0x3000
258 #define BGE_CHIPID_BCM5705_A1 0x3001
259 #define BGE_CHIPID_BCM5705_A2 0x3002
260 #define BGE_CHIPID_BCM5705_A3 0x3003
261 #define BGE_CHIPID_BCM5750_A0 0x4000
262 #define BGE_CHIPID_BCM5750_A1 0x4001
263 #define BGE_CHIPID_BCM5750_A3 0x4003
264 #define BGE_CHIPID_BCM5750_B0 0x4100
265 #define BGE_CHIPID_BCM5750_B1 0x4101
266 #define BGE_CHIPID_BCM5750_C0 0x4200
267 #define BGE_CHIPID_BCM5750_C1 0x4201
268 #define BGE_CHIPID_BCM5750_C2 0x4202
269 #define BGE_CHIPID_BCM5714_A0 0x5000
270 #define BGE_CHIPID_BCM5752_A0 0x6000
271 #define BGE_CHIPID_BCM5752_A1 0x6001
272 #define BGE_CHIPID_BCM5752_A2 0x6002
273 #define BGE_CHIPID_BCM5714_B0 0x8000
274 #define BGE_CHIPID_BCM5714_B3 0x8003
275 #define BGE_CHIPID_BCM5715_A0 0x9000
276 #define BGE_CHIPID_BCM5715_A1 0x9001
277 #define BGE_CHIPID_BCM5715_A3 0x9003
278 #define BGE_CHIPID_BCM5722_A0 0xa200
279 #define BGE_CHIPID_BCM5755_A0 0xa000
280 #define BGE_CHIPID_BCM5755_A1 0xa001
281 #define BGE_CHIPID_BCM5755_A2 0xa002
282 #define BGE_CHIPID_BCM5754_A0 0xb000
283 #define BGE_CHIPID_BCM5754_A1 0xb001
284 #define BGE_CHIPID_BCM5754_A2 0xb002
285 #define BGE_CHIPID_BCM5761_A0 0x5761000
286 #define BGE_CHIPID_BCM5761_A1 0x5761100
287 #define BGE_CHIPID_BCM5784_A0 0x5784000
288 #define BGE_CHIPID_BCM5784_A1 0x5784100
289 #define BGE_CHIPID_BCM5787_A0 0xb000
290 #define BGE_CHIPID_BCM5787_A1 0xb001
291 #define BGE_CHIPID_BCM5787_A2 0xb002
292 #define BGE_CHIPID_BCM5906_A0 0xc000
293 #define BGE_CHIPID_BCM5906_A1 0xc001
294 #define BGE_CHIPID_BCM5906_A2 0xc002
295 #define BGE_CHIPID_BCM57780_A0 0x57780000
296 #define BGE_CHIPID_BCM57780_A1 0x57780001
299 #define BGE_ASICREV(x) ((x) >> 12)
300 #define BGE_ASICREV_BCM5701 0x00
301 #define BGE_ASICREV_BCM5703 0x01
302 #define BGE_ASICREV_BCM5704 0x02
303 #define BGE_ASICREV_BCM5705 0x03
304 #define BGE_ASICREV_BCM5750 0x04
305 #define BGE_ASICREV_BCM5714_A0 0x05
306 #define BGE_ASICREV_BCM5752 0x06
307 #define BGE_ASICREV_BCM5700 0x07
308 #define BGE_ASICREV_BCM5780 0x08
309 #define BGE_ASICREV_BCM5714 0x09
310 #define BGE_ASICREV_BCM5755 0x0a
311 #define BGE_ASICREV_BCM5754 0x0b
312 #define BGE_ASICREV_BCM5787 0x0b
313 #define BGE_ASICREV_BCM5906 0x0c
315 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
316 #define BGE_ASICREV_USE_PRODID_REG 0x0f
317 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
318 #define BGE_ASICREV_BCM5761 0x5761
319 #define BGE_ASICREV_BCM5784 0x5784
320 #define BGE_ASICREV_BCM5785 0x5785
321 #define BGE_ASICREV_BCM57780 0x57780
324 #define BGE_CHIPREV(x) ((x) >> 8)
325 #define BGE_CHIPREV_5700_AX 0x70
326 #define BGE_CHIPREV_5700_BX 0x71
327 #define BGE_CHIPREV_5700_CX 0x72
328 #define BGE_CHIPREV_5701_AX 0x00
329 #define BGE_CHIPREV_5703_AX 0x10
330 #define BGE_CHIPREV_5704_AX 0x20
331 #define BGE_CHIPREV_5704_BX 0x21
332 #define BGE_CHIPREV_5750_AX 0x40
333 #define BGE_CHIPREV_5750_BX 0x41
334 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
335 #define BGE_CHIPREV_5761_AX 0x57611
336 #define BGE_CHIPREV_5784_AX 0x57841
338 /* PCI DMA Read/Write Control register */
339 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
340 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
341 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
342 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
343 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
344 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
345 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
346 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
347 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
348 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
349 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
350 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
351 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
352 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
354 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
355 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
356 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
357 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
358 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
359 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
360 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
361 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
363 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
364 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
365 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
366 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
367 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
368 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
369 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
370 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
373 * PCI state register -- note, this register is read only
374 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
377 #define BGE_PCISTATE_FORCE_RESET 0x00000001
378 #define BGE_PCISTATE_INTR_STATE 0x00000002
379 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
380 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
381 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
382 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
383 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
384 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
385 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
388 * PCI Clock Control register -- note, this register is read only
389 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
392 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
393 #define BGE_PCICLOCKCTL_M66EN 0x00000080
394 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
395 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
396 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
397 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
398 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
399 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
400 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
401 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
404 #ifndef PCIM_CMD_MWIEN
405 #define PCIM_CMD_MWIEN 0x0010
409 * High priority mailbox registers
410 * Each mailbox is 64-bits wide, though we only use the
411 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
412 * first. The NIC will load the mailbox after the lower 32 bit word
415 #define BGE_MBX_IRQ0_HI 0x0200
416 #define BGE_MBX_IRQ0_LO 0x0204
417 #define BGE_MBX_IRQ1_HI 0x0208
418 #define BGE_MBX_IRQ1_LO 0x020C
419 #define BGE_MBX_IRQ2_HI 0x0210
420 #define BGE_MBX_IRQ2_LO 0x0214
421 #define BGE_MBX_IRQ3_HI 0x0218
422 #define BGE_MBX_IRQ3_LO 0x021C
423 #define BGE_MBX_GEN0_HI 0x0220
424 #define BGE_MBX_GEN0_LO 0x0224
425 #define BGE_MBX_GEN1_HI 0x0228
426 #define BGE_MBX_GEN1_LO 0x022C
427 #define BGE_MBX_GEN2_HI 0x0230
428 #define BGE_MBX_GEN2_LO 0x0234
429 #define BGE_MBX_GEN3_HI 0x0228
430 #define BGE_MBX_GEN3_LO 0x022C
431 #define BGE_MBX_GEN4_HI 0x0240
432 #define BGE_MBX_GEN4_LO 0x0244
433 #define BGE_MBX_GEN5_HI 0x0248
434 #define BGE_MBX_GEN5_LO 0x024C
435 #define BGE_MBX_GEN6_HI 0x0250
436 #define BGE_MBX_GEN6_LO 0x0254
437 #define BGE_MBX_GEN7_HI 0x0258
438 #define BGE_MBX_GEN7_LO 0x025C
439 #define BGE_MBX_RELOAD_STATS_HI 0x0260
440 #define BGE_MBX_RELOAD_STATS_LO 0x0264
441 #define BGE_MBX_RX_STD_PROD_HI 0x0268
442 #define BGE_MBX_RX_STD_PROD_LO 0x026C
443 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
444 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
445 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
446 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
447 #define BGE_MBX_RX_CONS0_HI 0x0280
448 #define BGE_MBX_RX_CONS0_LO 0x0284
449 #define BGE_MBX_RX_CONS1_HI 0x0288
450 #define BGE_MBX_RX_CONS1_LO 0x028C
451 #define BGE_MBX_RX_CONS2_HI 0x0290
452 #define BGE_MBX_RX_CONS2_LO 0x0294
453 #define BGE_MBX_RX_CONS3_HI 0x0298
454 #define BGE_MBX_RX_CONS3_LO 0x029C
455 #define BGE_MBX_RX_CONS4_HI 0x02A0
456 #define BGE_MBX_RX_CONS4_LO 0x02A4
457 #define BGE_MBX_RX_CONS5_HI 0x02A8
458 #define BGE_MBX_RX_CONS5_LO 0x02AC
459 #define BGE_MBX_RX_CONS6_HI 0x02B0
460 #define BGE_MBX_RX_CONS6_LO 0x02B4
461 #define BGE_MBX_RX_CONS7_HI 0x02B8
462 #define BGE_MBX_RX_CONS7_LO 0x02BC
463 #define BGE_MBX_RX_CONS8_HI 0x02C0
464 #define BGE_MBX_RX_CONS8_LO 0x02C4
465 #define BGE_MBX_RX_CONS9_HI 0x02C8
466 #define BGE_MBX_RX_CONS9_LO 0x02CC
467 #define BGE_MBX_RX_CONS10_HI 0x02D0
468 #define BGE_MBX_RX_CONS10_LO 0x02D4
469 #define BGE_MBX_RX_CONS11_HI 0x02D8
470 #define BGE_MBX_RX_CONS11_LO 0x02DC
471 #define BGE_MBX_RX_CONS12_HI 0x02E0
472 #define BGE_MBX_RX_CONS12_LO 0x02E4
473 #define BGE_MBX_RX_CONS13_HI 0x02E8
474 #define BGE_MBX_RX_CONS13_LO 0x02EC
475 #define BGE_MBX_RX_CONS14_HI 0x02F0
476 #define BGE_MBX_RX_CONS14_LO 0x02F4
477 #define BGE_MBX_RX_CONS15_HI 0x02F8
478 #define BGE_MBX_RX_CONS15_LO 0x02FC
479 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
480 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
481 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
482 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
483 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
484 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
485 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
486 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
487 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
488 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
489 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
490 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
491 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
492 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
493 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
494 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
495 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
496 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
497 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
498 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
499 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
500 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
501 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
502 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
503 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
504 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
505 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
506 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
507 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
508 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
509 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
510 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
511 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
512 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
513 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
514 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
515 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
516 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
517 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
518 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
519 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
520 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
521 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
522 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
523 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
524 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
525 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
526 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
527 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
528 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
529 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
530 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
531 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
532 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
533 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
534 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
535 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
536 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
537 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
538 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
539 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
540 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
541 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
542 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
544 #define BGE_TX_RINGS_MAX 4
545 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
546 #define BGE_RX_RINGS_MAX 16
548 /* Ethernet MAC control registers */
549 #define BGE_MAC_MODE 0x0400
550 #define BGE_MAC_STS 0x0404
551 #define BGE_MAC_EVT_ENB 0x0408
552 #define BGE_MAC_LED_CTL 0x040C
553 #define BGE_MAC_ADDR1_LO 0x0410
554 #define BGE_MAC_ADDR1_HI 0x0414
555 #define BGE_MAC_ADDR2_LO 0x0418
556 #define BGE_MAC_ADDR2_HI 0x041C
557 #define BGE_MAC_ADDR3_LO 0x0420
558 #define BGE_MAC_ADDR3_HI 0x0424
559 #define BGE_MAC_ADDR4_LO 0x0428
560 #define BGE_MAC_ADDR4_HI 0x042C
561 #define BGE_WOL_PATPTR 0x0430
562 #define BGE_WOL_PATCFG 0x0434
563 #define BGE_TX_RANDOM_BACKOFF 0x0438
564 #define BGE_RX_MTU 0x043C
565 #define BGE_GBIT_PCS_TEST 0x0440
566 #define BGE_TX_TBI_AUTONEG 0x0444
567 #define BGE_RX_TBI_AUTONEG 0x0448
568 #define BGE_MI_COMM 0x044C
569 #define BGE_MI_STS 0x0450
570 #define BGE_MI_MODE 0x0454
571 #define BGE_AUTOPOLL_STS 0x0458
572 #define BGE_TX_MODE 0x045C
573 #define BGE_TX_STS 0x0460
574 #define BGE_TX_LENGTHS 0x0464
575 #define BGE_RX_MODE 0x0468
576 #define BGE_RX_STS 0x046C
577 #define BGE_MAR0 0x0470
578 #define BGE_MAR1 0x0474
579 #define BGE_MAR2 0x0478
580 #define BGE_MAR3 0x047C
581 #define BGE_RX_BD_RULES_CTL0 0x0480
582 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
583 #define BGE_RX_BD_RULES_CTL1 0x0488
584 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
585 #define BGE_RX_BD_RULES_CTL2 0x0490
586 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
587 #define BGE_RX_BD_RULES_CTL3 0x0498
588 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
589 #define BGE_RX_BD_RULES_CTL4 0x04A0
590 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
591 #define BGE_RX_BD_RULES_CTL5 0x04A8
592 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
593 #define BGE_RX_BD_RULES_CTL6 0x04B0
594 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
595 #define BGE_RX_BD_RULES_CTL7 0x04B8
596 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
597 #define BGE_RX_BD_RULES_CTL8 0x04C0
598 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
599 #define BGE_RX_BD_RULES_CTL9 0x04C8
600 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
601 #define BGE_RX_BD_RULES_CTL10 0x04D0
602 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
603 #define BGE_RX_BD_RULES_CTL11 0x04D8
604 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
605 #define BGE_RX_BD_RULES_CTL12 0x04E0
606 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
607 #define BGE_RX_BD_RULES_CTL13 0x04E8
608 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
609 #define BGE_RX_BD_RULES_CTL14 0x04F0
610 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
611 #define BGE_RX_BD_RULES_CTL15 0x04F8
612 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
613 #define BGE_RX_RULES_CFG 0x0500
614 #define BGE_MAX_RX_FRAME_LOWAT 0x0504
615 #define BGE_SERDES_CFG 0x0590
616 #define BGE_SERDES_STS 0x0594
617 #define BGE_SGDIG_CFG 0x05B0
618 #define BGE_SGDIG_STS 0x05B4
619 #define BGE_RX_STATS 0x0800
620 #define BGE_TX_STATS 0x0880
622 /* Ethernet MAC Mode register */
623 #define BGE_MACMODE_RESET 0x00000001
624 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
625 #define BGE_MACMODE_PORTMODE 0x0000000C
626 #define BGE_MACMODE_LOOPBACK 0x00000010
627 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
628 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
629 #define BGE_MACMODE_MAX_DEFER 0x00000200
630 #define BGE_MACMODE_LINK_POLARITY 0x00000400
631 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
632 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
633 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
634 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
635 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
636 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
637 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
638 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
639 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
640 #define BGE_MACMODE_MIP_ENB 0x00100000
641 #define BGE_MACMODE_TXDMA_ENB 0x00200000
642 #define BGE_MACMODE_RXDMA_ENB 0x00400000
643 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
645 #define BGE_PORTMODE_NONE 0x00000000
646 #define BGE_PORTMODE_MII 0x00000004
647 #define BGE_PORTMODE_GMII 0x00000008
648 #define BGE_PORTMODE_TBI 0x0000000C
650 /* MAC Status register */
651 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
652 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
653 #define BGE_MACSTAT_RX_CFG 0x00000004
654 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
655 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
656 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
657 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
658 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
659 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
660 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
661 #define BGE_MACSTAT_ODI_ERROR 0x02000000
662 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
663 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
665 /* MAC Event Enable Register */
666 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
667 #define BGE_EVTENB_LINK_CHANGED 0x00001000
668 #define BGE_EVTENB_MI_COMPLETE 0x00400000
669 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
670 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
671 #define BGE_EVTENB_ODI_ERROR 0x02000000
672 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
673 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
675 /* LED Control Register */
676 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
677 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
678 #define BGE_LEDCTL_100MBPS_LED 0x00000004
679 #define BGE_LEDCTL_10MBPS_LED 0x00000008
680 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
681 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
682 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
683 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
684 #define BGE_LEDCTL_100MBPS_STS 0x00000100
685 #define BGE_LEDCTL_10MBPS_STS 0x00000200
686 #define BGE_LEDCTL_TRADLED_STS 0x00000400
687 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
688 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
690 /* TX backoff seed register */
691 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
693 /* Autopoll status register */
694 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
696 /* Transmit MAC mode register */
697 #define BGE_TXMODE_RESET 0x00000001
698 #define BGE_TXMODE_ENABLE 0x00000002
699 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
700 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
701 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
702 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100
704 /* Transmit MAC status register */
705 #define BGE_TXSTAT_RX_XOFFED 0x00000001
706 #define BGE_TXSTAT_SENT_XOFF 0x00000002
707 #define BGE_TXSTAT_SENT_XON 0x00000004
708 #define BGE_TXSTAT_LINK_UP 0x00000008
709 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
710 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
712 /* Transmit MAC lengths register */
713 #define BGE_TXLEN_SLOTTIME 0x000000FF
714 #define BGE_TXLEN_IPG 0x00000F00
715 #define BGE_TXLEN_CRS 0x00003000
717 /* Receive MAC mode register */
718 #define BGE_RXMODE_RESET 0x00000001
719 #define BGE_RXMODE_ENABLE 0x00000002
720 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
721 #define BGE_RXMODE_RX_GIANTS 0x00000020
722 #define BGE_RXMODE_RX_RUNTS 0x00000040
723 #define BGE_RXMODE_8022_LENCHECK 0x00000080
724 #define BGE_RXMODE_RX_PROMISC 0x00000100
725 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
726 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
728 /* Receive MAC status register */
729 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
730 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
731 #define BGE_RXSTAT_RCVD_XON 0x00000004
733 /* Receive Rules Control register */
734 #define BGE_RXRULECTL_OFFSET 0x000000FF
735 #define BGE_RXRULECTL_CLASS 0x00001F00
736 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
737 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
738 #define BGE_RXRULECTL_MAP 0x01000000
739 #define BGE_RXRULECTL_DISCARD 0x02000000
740 #define BGE_RXRULECTL_MASK 0x04000000
741 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
742 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
743 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
744 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
746 /* Receive Rules Mask register */
747 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
748 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
750 /* SERDES configuration register */
751 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
752 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
753 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
754 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
755 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
756 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
757 #define BGE_SERDESCFG_TXMODE 0x00001000
758 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
759 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
760 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
761 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
762 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
763 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
764 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
765 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
766 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
768 /* SERDES status register */
769 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
770 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
772 /* SGDIG config (not documented) */
773 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
774 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
775 #define BGE_SGDIGCFG_SEND 0x40000000
776 #define BGE_SGDIGCFG_AUTO 0x80000000
778 /* SGDIG status (not documented) */
779 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
780 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
781 #define BGE_SGDIGSTS_DONE 0x00000002
783 /* MI communication register */
784 #define BGE_MICOMM_DATA 0x0000FFFF
785 #define BGE_MICOMM_REG 0x001F0000
786 #define BGE_MICOMM_PHY 0x03E00000
787 #define BGE_MICOMM_CMD 0x0C000000
788 #define BGE_MICOMM_READFAIL 0x10000000
789 #define BGE_MICOMM_BUSY 0x20000000
791 #define BGE_MIREG(x) ((x & 0x1F) << 16)
792 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
793 #define BGE_MICMD_WRITE 0x04000000
794 #define BGE_MICMD_READ 0x08000000
796 /* MI status register */
797 #define BGE_MISTS_LINK 0x00000001
798 #define BGE_MISTS_10MBPS 0x00000002
800 #define BGE_MIMODE_CLK_10MHZ 0x00000001
801 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
802 #define BGE_MIMODE_AUTOPOLL 0x00000010
803 #define BGE_MIMODE_CLKCNT 0x001F0000
804 #define BGE_MIMODE_500KHZ_CONST 0x00008000
805 #define BGE_MIMODE_BASE 0x000C0000
809 * Send data initiator control registers.
811 #define BGE_SDI_MODE 0x0C00
812 #define BGE_SDI_STATUS 0x0C04
813 #define BGE_SDI_STATS_CTL 0x0C08
814 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
815 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
816 #define BGE_ISO_PKT_TX 0x0C20
817 #define BGE_LOCSTATS_COS0 0x0C80
818 #define BGE_LOCSTATS_COS1 0x0C84
819 #define BGE_LOCSTATS_COS2 0x0C88
820 #define BGE_LOCSTATS_COS3 0x0C8C
821 #define BGE_LOCSTATS_COS4 0x0C90
822 #define BGE_LOCSTATS_COS5 0x0C84
823 #define BGE_LOCSTATS_COS6 0x0C98
824 #define BGE_LOCSTATS_COS7 0x0C9C
825 #define BGE_LOCSTATS_COS8 0x0CA0
826 #define BGE_LOCSTATS_COS9 0x0CA4
827 #define BGE_LOCSTATS_COS10 0x0CA8
828 #define BGE_LOCSTATS_COS11 0x0CAC
829 #define BGE_LOCSTATS_COS12 0x0CB0
830 #define BGE_LOCSTATS_COS13 0x0CB4
831 #define BGE_LOCSTATS_COS14 0x0CB8
832 #define BGE_LOCSTATS_COS15 0x0CBC
833 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
834 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
835 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
836 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
837 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
838 #define BGE_LOCSTATS_IRQS 0x0CD4
839 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
840 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
842 /* Send Data Initiator mode register */
843 #define BGE_SDIMODE_RESET 0x00000001
844 #define BGE_SDIMODE_ENABLE 0x00000002
845 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
847 /* Send Data Initiator stats register */
848 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
850 /* Send Data Initiator stats control register */
851 #define BGE_SDISTATSCTL_ENABLE 0x00000001
852 #define BGE_SDISTATSCTL_FASTER 0x00000002
853 #define BGE_SDISTATSCTL_CLEAR 0x00000004
854 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
855 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
858 * Send Data Completion Control registers
860 #define BGE_SDC_MODE 0x1000
861 #define BGE_SDC_STATUS 0x1004
863 /* Send Data completion mode register */
864 #define BGE_SDCMODE_RESET 0x00000001
865 #define BGE_SDCMODE_ENABLE 0x00000002
866 #define BGE_SDCMODE_ATTN 0x00000004
867 #define BGE_SDCMODE_CDELAY 0x00000010
869 /* Send Data completion status register */
870 #define BGE_SDCSTAT_ATTN 0x00000004
873 * Send BD Ring Selector Control registers
875 #define BGE_SRS_MODE 0x1400
876 #define BGE_SRS_STATUS 0x1404
877 #define BGE_SRS_HWDIAG 0x1408
878 #define BGE_SRS_LOC_NIC_CONS0 0x1440
879 #define BGE_SRS_LOC_NIC_CONS1 0x1444
880 #define BGE_SRS_LOC_NIC_CONS2 0x1448
881 #define BGE_SRS_LOC_NIC_CONS3 0x144C
882 #define BGE_SRS_LOC_NIC_CONS4 0x1450
883 #define BGE_SRS_LOC_NIC_CONS5 0x1454
884 #define BGE_SRS_LOC_NIC_CONS6 0x1458
885 #define BGE_SRS_LOC_NIC_CONS7 0x145C
886 #define BGE_SRS_LOC_NIC_CONS8 0x1460
887 #define BGE_SRS_LOC_NIC_CONS9 0x1464
888 #define BGE_SRS_LOC_NIC_CONS10 0x1468
889 #define BGE_SRS_LOC_NIC_CONS11 0x146C
890 #define BGE_SRS_LOC_NIC_CONS12 0x1470
891 #define BGE_SRS_LOC_NIC_CONS13 0x1474
892 #define BGE_SRS_LOC_NIC_CONS14 0x1478
893 #define BGE_SRS_LOC_NIC_CONS15 0x147C
895 /* Send BD Ring Selector Mode register */
896 #define BGE_SRSMODE_RESET 0x00000001
897 #define BGE_SRSMODE_ENABLE 0x00000002
898 #define BGE_SRSMODE_ATTN 0x00000004
900 /* Send BD Ring Selector Status register */
901 #define BGE_SRSSTAT_ERROR 0x00000004
903 /* Send BD Ring Selector HW Diagnostics register */
904 #define BGE_SRSHWDIAG_STATE 0x0000000F
905 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
906 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
907 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
910 * Send BD Initiator Selector Control registers
912 #define BGE_SBDI_MODE 0x1800
913 #define BGE_SBDI_STATUS 0x1804
914 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
915 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
916 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
917 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
918 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
919 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
920 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
921 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
922 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
923 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
924 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
925 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
926 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
927 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
928 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
929 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
931 /* Send BD Initiator Mode register */
932 #define BGE_SBDIMODE_RESET 0x00000001
933 #define BGE_SBDIMODE_ENABLE 0x00000002
934 #define BGE_SBDIMODE_ATTN 0x00000004
936 /* Send BD Initiator Status register */
937 #define BGE_SBDISTAT_ERROR 0x00000004
940 * Send BD Completion Control registers
942 #define BGE_SBDC_MODE 0x1C00
943 #define BGE_SBDC_STATUS 0x1C04
945 /* Send BD Completion Control Mode register */
946 #define BGE_SBDCMODE_RESET 0x00000001
947 #define BGE_SBDCMODE_ENABLE 0x00000002
948 #define BGE_SBDCMODE_ATTN 0x00000004
950 /* Send BD Completion Control Status register */
951 #define BGE_SBDCSTAT_ATTN 0x00000004
954 * Receive List Placement Control registers
956 #define BGE_RXLP_MODE 0x2000
957 #define BGE_RXLP_STATUS 0x2004
958 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
959 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
960 #define BGE_RXLP_CFG 0x2010
961 #define BGE_RXLP_STATS_CTL 0x2014
962 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
963 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
964 #define BGE_RXLP_HEAD0 0x2100
965 #define BGE_RXLP_TAIL0 0x2104
966 #define BGE_RXLP_COUNT0 0x2108
967 #define BGE_RXLP_HEAD1 0x2110
968 #define BGE_RXLP_TAIL1 0x2114
969 #define BGE_RXLP_COUNT1 0x2118
970 #define BGE_RXLP_HEAD2 0x2120
971 #define BGE_RXLP_TAIL2 0x2124
972 #define BGE_RXLP_COUNT2 0x2128
973 #define BGE_RXLP_HEAD3 0x2130
974 #define BGE_RXLP_TAIL3 0x2134
975 #define BGE_RXLP_COUNT3 0x2138
976 #define BGE_RXLP_HEAD4 0x2140
977 #define BGE_RXLP_TAIL4 0x2144
978 #define BGE_RXLP_COUNT4 0x2148
979 #define BGE_RXLP_HEAD5 0x2150
980 #define BGE_RXLP_TAIL5 0x2154
981 #define BGE_RXLP_COUNT5 0x2158
982 #define BGE_RXLP_HEAD6 0x2160
983 #define BGE_RXLP_TAIL6 0x2164
984 #define BGE_RXLP_COUNT6 0x2168
985 #define BGE_RXLP_HEAD7 0x2170
986 #define BGE_RXLP_TAIL7 0x2174
987 #define BGE_RXLP_COUNT7 0x2178
988 #define BGE_RXLP_HEAD8 0x2180
989 #define BGE_RXLP_TAIL8 0x2184
990 #define BGE_RXLP_COUNT8 0x2188
991 #define BGE_RXLP_HEAD9 0x2190
992 #define BGE_RXLP_TAIL9 0x2194
993 #define BGE_RXLP_COUNT9 0x2198
994 #define BGE_RXLP_HEAD10 0x21A0
995 #define BGE_RXLP_TAIL10 0x21A4
996 #define BGE_RXLP_COUNT10 0x21A8
997 #define BGE_RXLP_HEAD11 0x21B0
998 #define BGE_RXLP_TAIL11 0x21B4
999 #define BGE_RXLP_COUNT11 0x21B8
1000 #define BGE_RXLP_HEAD12 0x21C0
1001 #define BGE_RXLP_TAIL12 0x21C4
1002 #define BGE_RXLP_COUNT12 0x21C8
1003 #define BGE_RXLP_HEAD13 0x21D0
1004 #define BGE_RXLP_TAIL13 0x21D4
1005 #define BGE_RXLP_COUNT13 0x21D8
1006 #define BGE_RXLP_HEAD14 0x21E0
1007 #define BGE_RXLP_TAIL14 0x21E4
1008 #define BGE_RXLP_COUNT14 0x21E8
1009 #define BGE_RXLP_HEAD15 0x21F0
1010 #define BGE_RXLP_TAIL15 0x21F4
1011 #define BGE_RXLP_COUNT15 0x21F8
1012 #define BGE_RXLP_LOCSTAT_COS0 0x2200
1013 #define BGE_RXLP_LOCSTAT_COS1 0x2204
1014 #define BGE_RXLP_LOCSTAT_COS2 0x2208
1015 #define BGE_RXLP_LOCSTAT_COS3 0x220C
1016 #define BGE_RXLP_LOCSTAT_COS4 0x2210
1017 #define BGE_RXLP_LOCSTAT_COS5 0x2214
1018 #define BGE_RXLP_LOCSTAT_COS6 0x2218
1019 #define BGE_RXLP_LOCSTAT_COS7 0x221C
1020 #define BGE_RXLP_LOCSTAT_COS8 0x2220
1021 #define BGE_RXLP_LOCSTAT_COS9 0x2224
1022 #define BGE_RXLP_LOCSTAT_COS10 0x2228
1023 #define BGE_RXLP_LOCSTAT_COS11 0x222C
1024 #define BGE_RXLP_LOCSTAT_COS12 0x2230
1025 #define BGE_RXLP_LOCSTAT_COS13 0x2234
1026 #define BGE_RXLP_LOCSTAT_COS14 0x2238
1027 #define BGE_RXLP_LOCSTAT_COS15 0x223C
1028 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1029 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1030 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1031 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1032 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1033 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1034 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1037 /* Receive List Placement mode register */
1038 #define BGE_RXLPMODE_RESET 0x00000001
1039 #define BGE_RXLPMODE_ENABLE 0x00000002
1040 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1041 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1042 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1044 /* Receive List Placement Status register */
1045 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1046 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1047 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1050 * Receive Data and Receive BD Initiator Control Registers
1052 #define BGE_RDBDI_MODE 0x2400
1053 #define BGE_RDBDI_STATUS 0x2404
1054 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1055 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1056 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1057 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1058 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
1059 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
1060 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1061 #define BGE_RX_STD_RCB_NICADDR 0x245C
1062 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1063 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1064 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1065 #define BGE_RX_MINI_RCB_NICADDR 0x246C
1066 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1067 #define BGE_RDBDI_STD_RX_CONS 0x2474
1068 #define BGE_RDBDI_MINI_RX_CONS 0x2478
1069 #define BGE_RDBDI_RETURN_PROD0 0x2480
1070 #define BGE_RDBDI_RETURN_PROD1 0x2484
1071 #define BGE_RDBDI_RETURN_PROD2 0x2488
1072 #define BGE_RDBDI_RETURN_PROD3 0x248C
1073 #define BGE_RDBDI_RETURN_PROD4 0x2490
1074 #define BGE_RDBDI_RETURN_PROD5 0x2494
1075 #define BGE_RDBDI_RETURN_PROD6 0x2498
1076 #define BGE_RDBDI_RETURN_PROD7 0x249C
1077 #define BGE_RDBDI_RETURN_PROD8 0x24A0
1078 #define BGE_RDBDI_RETURN_PROD9 0x24A4
1079 #define BGE_RDBDI_RETURN_PROD10 0x24A8
1080 #define BGE_RDBDI_RETURN_PROD11 0x24AC
1081 #define BGE_RDBDI_RETURN_PROD12 0x24B0
1082 #define BGE_RDBDI_RETURN_PROD13 0x24B4
1083 #define BGE_RDBDI_RETURN_PROD14 0x24B8
1084 #define BGE_RDBDI_RETURN_PROD15 0x24BC
1085 #define BGE_RDBDI_HWDIAG 0x24C0
1088 /* Receive Data and Receive BD Initiator Mode register */
1089 #define BGE_RDBDIMODE_RESET 0x00000001
1090 #define BGE_RDBDIMODE_ENABLE 0x00000002
1091 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1092 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1093 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1095 /* Receive Data and Receive BD Initiator Status register */
1096 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1097 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1098 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1102 * Receive Data Completion Control registers
1104 #define BGE_RDC_MODE 0x2800
1106 /* Receive Data Completion Mode register */
1107 #define BGE_RDCMODE_RESET 0x00000001
1108 #define BGE_RDCMODE_ENABLE 0x00000002
1109 #define BGE_RDCMODE_ATTN 0x00000004
1112 * Receive BD Initiator Control registers
1114 #define BGE_RBDI_MODE 0x2C00
1115 #define BGE_RBDI_STATUS 0x2C04
1116 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1117 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1118 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1119 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1120 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
1121 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1123 /* Receive BD Initiator Mode register */
1124 #define BGE_RBDIMODE_RESET 0x00000001
1125 #define BGE_RBDIMODE_ENABLE 0x00000002
1126 #define BGE_RBDIMODE_ATTN 0x00000004
1128 /* Receive BD Initiator Status register */
1129 #define BGE_RBDISTAT_ATTN 0x00000004
1132 * Receive BD Completion Control registers
1134 #define BGE_RBDC_MODE 0x3000
1135 #define BGE_RBDC_STATUS 0x3004
1136 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1137 #define BGE_RBDC_STD_BD_PROD 0x300C
1138 #define BGE_RBDC_MINI_BD_PROD 0x3010
1140 /* Receive BD completion mode register */
1141 #define BGE_RBDCMODE_RESET 0x00000001
1142 #define BGE_RBDCMODE_ENABLE 0x00000002
1143 #define BGE_RBDCMODE_ATTN 0x00000004
1145 /* Receive BD completion status register */
1146 #define BGE_RBDCSTAT_ERROR 0x00000004
1149 * Receive List Selector Control registers
1151 #define BGE_RXLS_MODE 0x3400
1152 #define BGE_RXLS_STATUS 0x3404
1154 /* Receive List Selector Mode register */
1155 #define BGE_RXLSMODE_RESET 0x00000001
1156 #define BGE_RXLSMODE_ENABLE 0x00000002
1157 #define BGE_RXLSMODE_ATTN 0x00000004
1159 /* Receive List Selector Status register */
1160 #define BGE_RXLSSTAT_ERROR 0x00000004
1162 #define BGE_CPMU_CTRL 0x3600
1163 #define BGE_CPMU_LSPD_10MB_CLK 0x3604
1164 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C
1165 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
1166 #define BGE_CPMU_HST_ACC 0x361C
1167 #define BGE_CPMU_CLCK_STAT 0x3630
1168 #define BGE_CPMU_MUTEX_REQ 0x365C
1169 #define BGE_CPMU_MUTEX_GNT 0x3660
1170 #define BGE_CPMU_PHY_STRAP 0x3664
1172 /* Central Power Management Unit (CPMU) register */
1173 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1174 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1175 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1176 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1178 /* Link Speed 10MB/No Link Power Mode Clock Policy register */
1179 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
1180 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1182 /* Link Speed 1000MB Power Mode Clock Policy register */
1183 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1184 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1185 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
1187 /* Link Aware Power Mode Clock Policy register */
1188 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
1189 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1191 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
1192 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
1194 /* CPMU Clock Status register */
1195 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
1196 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1197 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1198 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1200 /* CPMU Mutex Request register */
1201 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
1202 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
1204 /* CPMU GPHY Strap register */
1205 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1208 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1210 #define BGE_MBCF_MODE 0x3800
1211 #define BGE_MBCF_STATUS 0x3804
1213 /* Mbuf Cluster Free mode register */
1214 #define BGE_MBCFMODE_RESET 0x00000001
1215 #define BGE_MBCFMODE_ENABLE 0x00000002
1216 #define BGE_MBCFMODE_ATTN 0x00000004
1218 /* Mbuf Cluster Free status register */
1219 #define BGE_MBCFSTAT_ERROR 0x00000004
1222 * Host Coalescing Control registers
1224 #define BGE_HCC_MODE 0x3C00
1225 #define BGE_HCC_STATUS 0x3C04
1226 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1227 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1228 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1229 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1230 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1231 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1232 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1233 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1234 #define BGE_HCC_STATS_TICKS 0x3C28
1235 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1236 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1237 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1238 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1239 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1240 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1241 #define BGE_FLOW_ATTN 0x3C48
1242 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1243 #define BGE_HCC_STD_BD_CONS 0x3C54
1244 #define BGE_HCC_MINI_BD_CONS 0x3C58
1245 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1246 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1247 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1248 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1249 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1250 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1251 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1252 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1253 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1254 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1255 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1256 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1257 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1258 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1259 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1260 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1261 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1262 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1263 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1264 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1265 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1266 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1267 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1268 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1269 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1270 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1271 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1272 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1273 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1274 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1275 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1276 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1279 /* Host coalescing mode register */
1280 #define BGE_HCCMODE_RESET 0x00000001
1281 #define BGE_HCCMODE_ENABLE 0x00000002
1282 #define BGE_HCCMODE_ATTN 0x00000004
1283 #define BGE_HCCMODE_COAL_NOW 0x00000008
1284 #define BGE_HCCMODE_MSI_BITS 0x0x000070
1285 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1287 #define BGE_STATBLKSZ_FULL 0x00000000
1288 #define BGE_STATBLKSZ_64BYTE 0x00000080
1289 #define BGE_STATBLKSZ_32BYTE 0x00000100
1291 /* Host coalescing status register */
1292 #define BGE_HCCSTAT_ERROR 0x00000004
1294 /* Flow attention register */
1295 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1296 #define BGE_FLOWATTN_MEMARB 0x00000080
1297 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1298 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1299 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1300 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1301 #define BGE_FLOWATTN_RDBDI 0x00080000
1302 #define BGE_FLOWATTN_RXLS 0x00100000
1303 #define BGE_FLOWATTN_RXLP 0x00200000
1304 #define BGE_FLOWATTN_RBDC 0x00400000
1305 #define BGE_FLOWATTN_RBDI 0x00800000
1306 #define BGE_FLOWATTN_SDC 0x08000000
1307 #define BGE_FLOWATTN_SDI 0x10000000
1308 #define BGE_FLOWATTN_SRS 0x20000000
1309 #define BGE_FLOWATTN_SBDC 0x40000000
1310 #define BGE_FLOWATTN_SBDI 0x80000000
1313 * Memory arbiter registers
1315 #define BGE_MARB_MODE 0x4000
1316 #define BGE_MARB_STATUS 0x4004
1317 #define BGE_MARB_TRAPADDR_HI 0x4008
1318 #define BGE_MARB_TRAPADDR_LO 0x400C
1320 /* Memory arbiter mode register */
1321 #define BGE_MARBMODE_RESET 0x00000001
1322 #define BGE_MARBMODE_ENABLE 0x00000002
1323 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1324 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1325 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1326 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1327 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1328 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1329 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1330 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1331 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1332 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1333 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1334 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1335 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1336 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1337 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1338 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1339 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1340 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1341 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1342 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1343 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1344 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1345 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1346 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1348 /* Memory arbiter status register */
1349 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1350 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1351 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1352 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1353 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1354 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1355 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1356 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1357 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1358 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1359 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1360 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1361 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1362 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1363 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1364 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1365 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1366 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1367 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1368 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1369 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1370 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1371 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1372 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1375 * Buffer manager control registers
1377 #define BGE_BMAN_MODE 0x4400
1378 #define BGE_BMAN_STATUS 0x4404
1379 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1380 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1381 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1382 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1383 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1384 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1385 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1386 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1387 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1388 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1389 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1390 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1391 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1392 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1393 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1394 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1395 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1396 #define BGE_BMAN_HWDIAG_1 0x444C
1397 #define BGE_BMAN_HWDIAG_2 0x4450
1398 #define BGE_BMAN_HWDIAG_3 0x4454
1400 /* Buffer manager mode register */
1401 #define BGE_BMANMODE_RESET 0x00000001
1402 #define BGE_BMANMODE_ENABLE 0x00000002
1403 #define BGE_BMANMODE_ATTN 0x00000004
1404 #define BGE_BMANMODE_TESTMODE 0x00000008
1405 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1407 /* Buffer manager status register */
1408 #define BGE_BMANSTAT_ERRO 0x00000004
1409 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1413 * Read DMA Control registers
1415 #define BGE_RDMA_MODE 0x4800
1416 #define BGE_RDMA_STATUS 0x4804
1417 #define BGE_RDMA_RSRVCTRL 0x4900
1419 /* Read DMA mode register */
1420 #define BGE_RDMAMODE_RESET 0x00000001
1421 #define BGE_RDMAMODE_ENABLE 0x00000002
1422 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1423 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1424 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1425 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1426 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1427 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1428 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1429 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1430 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1431 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1432 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1433 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1434 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1435 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1437 /* Read DMA status register */
1438 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1439 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1440 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1441 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1442 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1443 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1444 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1445 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1447 /* Read DMA Reserved Control register */
1448 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1451 * Write DMA control registers
1453 #define BGE_WDMA_MODE 0x4C00
1454 #define BGE_WDMA_STATUS 0x4C04
1456 /* Write DMA mode register */
1457 #define BGE_WDMAMODE_RESET 0x00000001
1458 #define BGE_WDMAMODE_ENABLE 0x00000002
1459 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1460 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1461 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1462 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1463 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1464 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1465 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1466 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1467 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1468 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1469 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000
1471 /* Write DMA status register */
1472 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1473 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1474 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1475 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1476 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1477 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1478 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1479 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1485 #define BGE_RXCPU_MODE 0x5000
1486 #define BGE_RXCPU_STATUS 0x5004
1487 #define BGE_RXCPU_PC 0x501C
1489 /* RX CPU mode register */
1490 #define BGE_RXCPUMODE_RESET 0x00000001
1491 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1492 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1493 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1494 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1495 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1496 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1497 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1498 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1499 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1500 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1501 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1502 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1503 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1505 /* RX CPU status register */
1506 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1507 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1508 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1509 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1510 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1511 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1512 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1513 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1514 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1515 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1516 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1517 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1518 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1519 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1520 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1521 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1522 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1527 #define BGE_VCPU_STATUS 0x5100
1528 #define BGE_VCPU_EXT_CTRL 0x6890
1530 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1531 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1533 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1534 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1540 #define BGE_TXCPU_MODE 0x5400
1541 #define BGE_TXCPU_STATUS 0x5404
1542 #define BGE_TXCPU_PC 0x541C
1544 /* TX CPU mode register */
1545 #define BGE_TXCPUMODE_RESET 0x00000001
1546 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1547 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1548 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1549 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1550 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1551 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1552 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1553 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1554 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1555 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1556 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1557 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1559 /* TX CPU status register */
1560 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1561 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1562 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1563 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1564 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1565 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1566 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1567 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1568 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1569 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1570 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1571 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1572 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1573 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1574 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1575 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1576 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1580 * Low priority mailbox registers
1582 #define BGE_LPMBX_IRQ0_HI 0x5800
1583 #define BGE_LPMBX_IRQ0_LO 0x5804
1584 #define BGE_LPMBX_IRQ1_HI 0x5808
1585 #define BGE_LPMBX_IRQ1_LO 0x580C
1586 #define BGE_LPMBX_IRQ2_HI 0x5810
1587 #define BGE_LPMBX_IRQ2_LO 0x5814
1588 #define BGE_LPMBX_IRQ3_HI 0x5818
1589 #define BGE_LPMBX_IRQ3_LO 0x581C
1590 #define BGE_LPMBX_GEN0_HI 0x5820
1591 #define BGE_LPMBX_GEN0_LO 0x5824
1592 #define BGE_LPMBX_GEN1_HI 0x5828
1593 #define BGE_LPMBX_GEN1_LO 0x582C
1594 #define BGE_LPMBX_GEN2_HI 0x5830
1595 #define BGE_LPMBX_GEN2_LO 0x5834
1596 #define BGE_LPMBX_GEN3_HI 0x5828
1597 #define BGE_LPMBX_GEN3_LO 0x582C
1598 #define BGE_LPMBX_GEN4_HI 0x5840
1599 #define BGE_LPMBX_GEN4_LO 0x5844
1600 #define BGE_LPMBX_GEN5_HI 0x5848
1601 #define BGE_LPMBX_GEN5_LO 0x584C
1602 #define BGE_LPMBX_GEN6_HI 0x5850
1603 #define BGE_LPMBX_GEN6_LO 0x5854
1604 #define BGE_LPMBX_GEN7_HI 0x5858
1605 #define BGE_LPMBX_GEN7_LO 0x585C
1606 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1607 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1608 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1609 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1610 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1611 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1612 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1613 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1614 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1615 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1616 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1617 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1618 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1619 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1620 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1621 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1622 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1623 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1624 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1625 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1626 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1627 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1628 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1629 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1630 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1631 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1632 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1633 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1634 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1635 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1636 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1637 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1638 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1639 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1640 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1641 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1642 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1643 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1644 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1645 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1646 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1647 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1648 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1649 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1650 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1651 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1652 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1653 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1654 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1655 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1656 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1657 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1658 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1659 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1660 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1661 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1662 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1663 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1664 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1665 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1666 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1667 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1668 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1669 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1670 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1671 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1672 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1673 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1674 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1675 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1676 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1677 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1678 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1679 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1680 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1681 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1682 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1683 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1684 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1685 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1686 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1687 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1688 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1689 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1690 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1691 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1692 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1693 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1694 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1695 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1696 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1697 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1698 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1699 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1700 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1701 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1702 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1703 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1704 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1705 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1706 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1707 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1708 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1709 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1712 * Flow throw Queue reset register
1714 #define BGE_FTQ_RESET 0x5C00
1716 #define BGE_FTQRESET_DMAREAD 0x00000002
1717 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1718 #define BGE_FTQRESET_DMADONE 0x00000010
1719 #define BGE_FTQRESET_SBDC 0x00000020
1720 #define BGE_FTQRESET_SDI 0x00000040
1721 #define BGE_FTQRESET_WDMA 0x00000080
1722 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1723 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1724 #define BGE_FTQRESET_SDC 0x00000400
1725 #define BGE_FTQRESET_HCC 0x00000800
1726 #define BGE_FTQRESET_TXFIFO 0x00001000
1727 #define BGE_FTQRESET_MBC 0x00002000
1728 #define BGE_FTQRESET_RBDC 0x00004000
1729 #define BGE_FTQRESET_RXLP 0x00008000
1730 #define BGE_FTQRESET_RDBDI 0x00010000
1731 #define BGE_FTQRESET_RDC 0x00020000
1732 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1735 * Message Signaled Interrupt registers
1737 #define BGE_MSI_MODE 0x6000
1738 #define BGE_MSI_STATUS 0x6004
1739 #define BGE_MSI_FIFOACCESS 0x6008
1741 /* MSI mode register */
1742 #define BGE_MSIMODE_RESET 0x00000001
1743 #define BGE_MSIMODE_ENABLE 0x00000002
1744 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1745 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1746 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1747 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1748 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1750 /* MSI status register */
1751 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1752 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1753 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1754 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1755 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1759 * DMA Completion registers
1761 #define BGE_DMAC_MODE 0x6400
1763 /* DMA Completion mode register */
1764 #define BGE_DMACMODE_RESET 0x00000001
1765 #define BGE_DMACMODE_ENABLE 0x00000002
1769 * General control registers.
1771 #define BGE_MODE_CTL 0x6800
1772 #define BGE_MISC_CFG 0x6804
1773 #define BGE_MISC_LOCAL_CTL 0x6808
1774 #define BGE_EE_ADDR 0x6838
1775 #define BGE_EE_DATA 0x683C
1776 #define BGE_EE_CTL 0x6840
1777 #define BGE_MDI_CTL 0x6844
1778 #define BGE_EE_DELAY 0x6848
1779 #define BGE_FASTBOOT_PC 0x6894
1782 * NVRAM Control registers
1784 #define BGE_NVRAM_CMD 0x7000
1785 #define BGE_NVRAM_STAT 0x7004
1786 #define BGE_NVRAM_WRDATA 0x7008
1787 #define BGE_NVRAM_ADDR 0x700c
1788 #define BGE_NVRAM_RDDATA 0x7010
1789 #define BGE_NVRAM_CFG1 0x7014
1790 #define BGE_NVRAM_CFG2 0x7018
1791 #define BGE_NVRAM_CFG3 0x701c
1792 #define BGE_NVRAM_SWARB 0x7020
1793 #define BGE_NVRAM_ACCESS 0x7024
1794 #define BGE_NVRAM_WRITE1 0x7028
1796 #define BGE_NVRAMCMD_RESET 0x00000001
1797 #define BGE_NVRAMCMD_DONE 0x00000008
1798 #define BGE_NVRAMCMD_START 0x00000010
1799 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1800 #define BGE_NVRAMCMD_ERASE 0x00000040
1801 #define BGE_NVRAMCMD_FIRST 0x00000080
1802 #define BGE_NVRAMCMD_LAST 0x00000100
1804 #define BGE_NVRAM_READCMD \
1805 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1806 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1807 #define BGE_NVRAM_WRITECMD \
1808 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1809 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1811 #define BGE_NVRAMSWARB_SET0 0x00000001
1812 #define BGE_NVRAMSWARB_SET1 0x00000002
1813 #define BGE_NVRAMSWARB_SET2 0x00000003
1814 #define BGE_NVRAMSWARB_SET3 0x00000004
1815 #define BGE_NVRAMSWARB_CLR0 0x00000010
1816 #define BGE_NVRAMSWARB_CLR1 0x00000020
1817 #define BGE_NVRAMSWARB_CLR2 0x00000040
1818 #define BGE_NVRAMSWARB_CLR3 0x00000080
1819 #define BGE_NVRAMSWARB_GNT0 0x00000100
1820 #define BGE_NVRAMSWARB_GNT1 0x00000200
1821 #define BGE_NVRAMSWARB_GNT2 0x00000400
1822 #define BGE_NVRAMSWARB_GNT3 0x00000800
1823 #define BGE_NVRAMSWARB_REQ0 0x00001000
1824 #define BGE_NVRAMSWARB_REQ1 0x00002000
1825 #define BGE_NVRAMSWARB_REQ2 0x00004000
1826 #define BGE_NVRAMSWARB_REQ3 0x00008000
1828 #define BGE_NVRAMACC_ENABLE 0x00000001
1829 #define BGE_NVRAMACC_WRENABLE 0x00000002
1831 /* Mode control register */
1832 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1833 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1834 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1835 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1836 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1837 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1838 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1839 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1840 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1841 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1842 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1843 #define BGE_MODECTL_STACKUP 0x00010000
1844 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1845 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1846 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1847 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1848 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1849 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1850 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1851 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1852 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1853 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1855 /* Misc. config register */
1856 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1857 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1858 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1859 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1860 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001e000
1861 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1862 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000
1864 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1866 /* Misc. Local Control */
1867 #define BGE_MLC_INTR_STATE 0x00000001
1868 #define BGE_MLC_INTR_CLR 0x00000002
1869 #define BGE_MLC_INTR_SET 0x00000004
1870 #define BGE_MLC_INTR_ONATTN 0x00000008
1871 #define BGE_MLC_MISCIO_IN0 0x00000100
1872 #define BGE_MLC_MISCIO_IN1 0x00000200
1873 #define BGE_MLC_MISCIO_IN2 0x00000400
1874 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1875 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1876 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1877 #define BGE_MLC_MISCIO_OUT0 0x00004000
1878 #define BGE_MLC_MISCIO_OUT1 0x00008000
1879 #define BGE_MLC_MISCIO_OUT2 0x00010000
1880 #define BGE_MLC_EXTRAM_ENB 0x00020000
1881 #define BGE_MLC_SRAM_SIZE 0x001C0000
1882 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1883 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1884 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1885 #define BGE_MLC_AUTO_EEPROM 0x01000000
1887 #define BGE_SSRAMSIZE_256KB 0x00000000
1888 #define BGE_SSRAMSIZE_512KB 0x00040000
1889 #define BGE_SSRAMSIZE_1MB 0x00080000
1890 #define BGE_SSRAMSIZE_2MB 0x000C0000
1891 #define BGE_SSRAMSIZE_4MB 0x00100000
1892 #define BGE_SSRAMSIZE_8MB 0x00140000
1893 #define BGE_SSRAMSIZE_16M 0x00180000
1895 /* EEPROM address register */
1896 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1897 #define BGE_EEADDR_HALFCLK 0x01FF0000
1898 #define BGE_EEADDR_START 0x02000000
1899 #define BGE_EEADDR_DEVID 0x1C000000
1900 #define BGE_EEADDR_RESET 0x20000000
1901 #define BGE_EEADDR_DONE 0x40000000
1902 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1904 #define BGE_EEDEVID(x) ((x & 7) << 26)
1905 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1906 #define BGE_HALFCLK_384SCL 0x60
1907 #define BGE_EE_READCMD \
1908 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1909 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1910 #define BGE_EE_WRCMD \
1911 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1912 BGE_EEADDR_START|BGE_EEADDR_DONE)
1914 /* EEPROM Control register */
1915 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1916 #define BGE_EECTL_CLKOUT 0x00000002
1917 #define BGE_EECTL_CLKIN 0x00000004
1918 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1919 #define BGE_EECTL_DATAOUT 0x00000010
1920 #define BGE_EECTL_DATAIN 0x00000020
1922 /* MDI (MII/GMII) access register */
1923 #define BGE_MDI_DATA 0x00000001
1924 #define BGE_MDI_DIR 0x00000002
1925 #define BGE_MDI_SEL 0x00000004
1926 #define BGE_MDI_CLK 0x00000008
1928 #define BGE_MEMWIN_START 0x00008000
1929 #define BGE_MEMWIN_END 0x0000FFFF
1932 #define BGE_MEMWIN_READ(sc, x, val) \
1934 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1935 (0xFFFF0000 & x), 4); \
1936 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1939 #define BGE_MEMWIN_WRITE(sc, x, val) \
1941 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1942 (0xFFFF0000 & x), 4); \
1943 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1947 * This magic number is written to the firmware mailbox at 0xb50
1948 * before a software reset is issued. After the internal firmware
1949 * has completed its initialization it will write the opposite of
1950 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1951 * driver to synchronize with the firmware.
1953 #define BGE_MAGIC_NUMBER 0x4B657654
1956 uint32_t bge_addr_hi;
1957 uint32_t bge_addr_lo;
1960 #define BGE_HOSTADDR(x, y) \
1962 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
1963 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
1966 #define BGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
1967 #define BGE_ADDR_HI(y) ((uint64_t) (y) >> 32)
1969 /* Ring control block structure */
1971 bge_hostaddr bge_hostaddr;
1972 uint32_t bge_maxlen_flags;
1973 uint32_t bge_nicaddr;
1975 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1976 #define RCB_WRITE_4(sc, rcb, offset, val) \
1977 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
1978 rcb + offsetof(struct bge_rcb, offset), val)
1980 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1981 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
1984 bge_hostaddr bge_addr;
1985 #if BYTE_ORDER == LITTLE_ENDIAN
1988 uint16_t bge_vlan_tag;
1994 uint16_t bge_vlan_tag;
1998 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1999 #define BGE_TXBDFLAG_IP_CSUM 0x0002
2000 #define BGE_TXBDFLAG_END 0x0004
2001 #define BGE_TXBDFLAG_IP_FRAG 0x0008
2002 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
2003 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
2004 #define BGE_TXBDFLAG_COAL_NOW 0x0080
2005 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
2006 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
2007 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
2008 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
2009 #define BGE_TXBDFLAG_NO_CRC 0x8000
2011 #define BGE_NIC_TXRING_ADDR(ringno, size) \
2012 BGE_SEND_RING_1_TO_4 + \
2013 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
2016 bge_hostaddr bge_addr;
2017 #if BYTE_ORDER == LITTLE_ENDIAN
2022 uint16_t bge_tcp_udp_csum;
2023 uint16_t bge_ip_csum;
2024 uint16_t bge_vlan_tag;
2025 uint16_t bge_error_flag;
2031 uint16_t bge_ip_csum;
2032 uint16_t bge_tcp_udp_csum;
2033 uint16_t bge_error_flag;
2034 uint16_t bge_vlan_tag;
2037 uint32_t bge_opaque;
2040 #define BGE_RXBDFLAG_END 0x0004
2041 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
2042 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
2043 #define BGE_RXBDFLAG_ERROR 0x0400
2044 #define BGE_RXBDFLAG_MINI_RING 0x0800
2045 #define BGE_RXBDFLAG_IP_CSUM 0x1000
2046 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2047 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2049 #define BGE_RXERRFLAG_BAD_CRC 0x0001
2050 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
2051 #define BGE_RXERRFLAG_LINK_LOST 0x0004
2052 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2053 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
2054 #define BGE_RXERRFLAG_RUNT 0x0020
2055 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2056 #define BGE_RXERRFLAG_GIANT 0x0080
2058 struct bge_sts_idx {
2059 #if BYTE_ORDER == LITTLE_ENDIAN
2060 uint16_t bge_rx_prod_idx;
2061 uint16_t bge_tx_cons_idx;
2063 uint16_t bge_tx_cons_idx;
2064 uint16_t bge_rx_prod_idx;
2068 struct bge_status_block {
2069 uint32_t bge_status;
2070 uint32_t bge_status_tag;
2071 #if BYTE_ORDER == LITTLE_ENDIAN
2072 uint16_t bge_rx_jumbo_cons_idx;
2073 uint16_t bge_rx_std_cons_idx;
2074 uint16_t bge_rx_mini_cons_idx;
2077 uint16_t bge_rx_std_cons_idx;
2078 uint16_t bge_rx_jumbo_cons_idx;
2080 uint16_t bge_rx_mini_cons_idx;
2082 struct bge_sts_idx bge_idx[16];
2085 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
2086 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
2088 #define BGE_STATFLAG_UPDATED 0x00000001
2089 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2090 #define BGE_STATFLAG_ERROR 0x00000004
2094 * Offset of MAC address inside EEPROM.
2096 #define BGE_EE_MAC_OFFSET 0x7C
2097 #define BGE_EE_MAC_OFFSET_5906 0x10
2098 #define BGE_EE_HWCFG_OFFSET 0xC8
2100 #define BGE_HWCFG_VOLTAGE 0x00000003
2101 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
2102 #define BGE_HWCFG_MEDIA 0x00000030
2104 #define BGE_VOLTAGE_1POINT3 0x00000000
2105 #define BGE_VOLTAGE_1POINT8 0x00000001
2107 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
2108 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2109 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
2111 #define BGE_MEDIA_UNSPEC 0x00000000
2112 #define BGE_MEDIA_COPPER 0x00000010
2113 #define BGE_MEDIA_FIBER 0x00000020
2115 #define BGE_PCI_READ_CMD 0x06000000
2116 #define BGE_PCI_WRITE_CMD 0x70000000
2118 #define BGE_TICKS_PER_SEC 1000000
2121 * Ring size constants.
2123 #define BGE_EVENT_RING_CNT 256
2124 #define BGE_CMD_RING_CNT 64
2125 #define BGE_STD_RX_RING_CNT 512
2126 #define BGE_JUMBO_RX_RING_CNT 256
2127 #define BGE_MINI_RX_RING_CNT 1024
2128 #define BGE_RETURN_RING_CNT 1024
2130 /* 5705 has smaller return ring size */
2132 #define BGE_RETURN_RING_CNT_5705 512
2135 * Possible TX ring sizes.
2137 #define BGE_TX_RING_CNT_128 128
2138 #define BGE_TX_RING_BASE_128 0x3800
2140 #define BGE_TX_RING_CNT_256 256
2141 #define BGE_TX_RING_BASE_256 0x3000
2143 #define BGE_TX_RING_CNT_512 512
2144 #define BGE_TX_RING_BASE_512 0x2000
2146 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2147 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2150 * Tigon III statistics counters.
2152 /* Statistics maintained MAC Receive block. */
2153 struct bge_rx_mac_stats {
2154 bge_hostaddr ifHCInOctets;
2155 bge_hostaddr Reserved1;
2156 bge_hostaddr etherStatsFragments;
2157 bge_hostaddr ifHCInUcastPkts;
2158 bge_hostaddr ifHCInMulticastPkts;
2159 bge_hostaddr ifHCInBroadcastPkts;
2160 bge_hostaddr dot3StatsFCSErrors;
2161 bge_hostaddr dot3StatsAlignmentErrors;
2162 bge_hostaddr xonPauseFramesReceived;
2163 bge_hostaddr xoffPauseFramesReceived;
2164 bge_hostaddr macControlFramesReceived;
2165 bge_hostaddr xoffStateEntered;
2166 bge_hostaddr dot3StatsFramesTooLong;
2167 bge_hostaddr etherStatsJabbers;
2168 bge_hostaddr etherStatsUndersizePkts;
2169 bge_hostaddr inRangeLengthError;
2170 bge_hostaddr outRangeLengthError;
2171 bge_hostaddr etherStatsPkts64Octets;
2172 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2173 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2174 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2175 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2176 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2177 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2178 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2179 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2180 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2184 /* Statistics maintained MAC Transmit block. */
2185 struct bge_tx_mac_stats {
2186 bge_hostaddr ifHCOutOctets;
2187 bge_hostaddr Reserved2;
2188 bge_hostaddr etherStatsCollisions;
2189 bge_hostaddr outXonSent;
2190 bge_hostaddr outXoffSent;
2191 bge_hostaddr flowControlDone;
2192 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2193 bge_hostaddr dot3StatsSingleCollisionFrames;
2194 bge_hostaddr dot3StatsMultipleCollisionFrames;
2195 bge_hostaddr dot3StatsDeferredTransmissions;
2196 bge_hostaddr Reserved3;
2197 bge_hostaddr dot3StatsExcessiveCollisions;
2198 bge_hostaddr dot3StatsLateCollisions;
2199 bge_hostaddr dot3Collided2Times;
2200 bge_hostaddr dot3Collided3Times;
2201 bge_hostaddr dot3Collided4Times;
2202 bge_hostaddr dot3Collided5Times;
2203 bge_hostaddr dot3Collided6Times;
2204 bge_hostaddr dot3Collided7Times;
2205 bge_hostaddr dot3Collided8Times;
2206 bge_hostaddr dot3Collided9Times;
2207 bge_hostaddr dot3Collided10Times;
2208 bge_hostaddr dot3Collided11Times;
2209 bge_hostaddr dot3Collided12Times;
2210 bge_hostaddr dot3Collided13Times;
2211 bge_hostaddr dot3Collided14Times;
2212 bge_hostaddr dot3Collided15Times;
2213 bge_hostaddr ifHCOutUcastPkts;
2214 bge_hostaddr ifHCOutMulticastPkts;
2215 bge_hostaddr ifHCOutBroadcastPkts;
2216 bge_hostaddr dot3StatsCarrierSenseErrors;
2217 bge_hostaddr ifOutDiscards;
2218 bge_hostaddr ifOutErrors;
2221 /* Stats counters access through registers */
2222 struct bge_mac_stats_regs {
2223 uint32_t ifHCOutOctets;
2225 uint32_t etherStatsCollisions;
2226 uint32_t outXonSent;
2227 uint32_t outXoffSent;
2229 uint32_t dot3StatsInternalMacTransmitErrors;
2230 uint32_t dot3StatsSingleCollisionFrames;
2231 uint32_t dot3StatsMultipleCollisionFrames;
2232 uint32_t dot3StatsDeferredTransmissions;
2234 uint32_t dot3StatsExcessiveCollisions;
2235 uint32_t dot3StatsLateCollisions;
2236 uint32_t Reserved3[14];
2237 uint32_t ifHCOutUcastPkts;
2238 uint32_t ifHCOutMulticastPkts;
2239 uint32_t ifHCOutBroadcastPkts;
2240 uint32_t Reserved4[2];
2241 uint32_t ifHCInOctets;
2243 uint32_t etherStatsFragments;
2244 uint32_t ifHCInUcastPkts;
2245 uint32_t ifHCInMulticastPkts;
2246 uint32_t ifHCInBroadcastPkts;
2247 uint32_t dot3StatsFCSErrors;
2248 uint32_t dot3StatsAlignmentErrors;
2249 uint32_t xonPauseFramesReceived;
2250 uint32_t xoffPauseFramesReceived;
2251 uint32_t macControlFramesReceived;
2252 uint32_t xoffStateEntered;
2253 uint32_t dot3StatsFramesTooLong;
2254 uint32_t etherStatsJabbers;
2255 uint32_t etherStatsUndersizePkts;
2259 uint8_t Reserved0[256];
2261 /* Statistics maintained by Receive MAC. */
2262 struct bge_rx_mac_stats rxstats;
2264 bge_hostaddr Unused1[37];
2266 /* Statistics maintained by Transmit MAC. */
2267 struct bge_tx_mac_stats txstats;
2269 bge_hostaddr Unused2[31];
2271 /* Statistics maintained by Receive List Placement. */
2272 bge_hostaddr COSIfHCInPkts[16];
2273 bge_hostaddr COSFramesDroppedDueToFilters;
2274 bge_hostaddr nicDmaWriteQueueFull;
2275 bge_hostaddr nicDmaWriteHighPriQueueFull;
2276 bge_hostaddr nicNoMoreRxBDs;
2277 bge_hostaddr ifInDiscards;
2278 bge_hostaddr ifInErrors;
2279 bge_hostaddr nicRecvThresholdHit;
2281 bge_hostaddr Unused3[9];
2283 /* Statistics maintained by Send Data Initiator. */
2284 bge_hostaddr COSIfHCOutPkts[16];
2285 bge_hostaddr nicDmaReadQueueFull;
2286 bge_hostaddr nicDmaReadHighPriQueueFull;
2287 bge_hostaddr nicSendDataCompQueueFull;
2289 /* Statistics maintained by Host Coalescing. */
2290 bge_hostaddr nicRingSetSendProdIndex;
2291 bge_hostaddr nicRingStatusUpdate;
2292 bge_hostaddr nicInterrupts;
2293 bge_hostaddr nicAvoidedInterrupts;
2294 bge_hostaddr nicSendThresholdHit;
2296 uint8_t Reserved4[320];
2300 * Tigon general information block. This resides in host memory
2301 * and contains the status counters, ring control blocks and
2302 * producer pointers.
2306 struct bge_stats bge_stats;
2307 struct bge_rcb bge_tx_rcb[16];
2308 struct bge_rcb bge_std_rx_rcb;
2309 struct bge_rcb bge_jumbo_rx_rcb;
2310 struct bge_rcb bge_mini_rx_rcb;
2311 struct bge_rcb bge_return_rcb;
2315 * NOTE! On the Alpha, we have an alignment constraint.
2316 * The first thing in the packet is a 14-byte Ethernet header.
2317 * This means that the packet is misaligned. To compensate,
2318 * we actually offset the data 2 bytes into the cluster. This
2319 * alignes the packet after the Ethernet header at a 32-bit
2323 #define ETHER_ALIGN 2
2325 #define BGE_FRAMELEN 1518
2326 #define BGE_MAX_FRAMELEN 1536
2327 #define BGE_JUMBO_FRAMELEN 9018
2328 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2329 #define BGE_PAGE_SIZE PAGE_SIZE
2330 #define BGE_MIN_FRAMELEN 60
2333 * Other utility macros.
2335 #define BGE_INC(x, y) (x) = (x + 1) % y
2338 * Vital product data and structures.
2340 #define BGE_VPD_FLAG 0x8000
2342 /* VPD structures */
2354 #define VPD_RES_ID 0x82 /* ID string */
2355 #define VPD_RES_READ 0x90 /* start of read only area */
2356 #define VPD_RES_WRITE 0x81 /* start of read/write area */
2357 #define VPD_RES_END 0x78 /* end tag */
2361 * Register access macros. The Tigon always uses memory mapped register
2362 * accesses and all registers must be accessed with 32 bit operations.
2365 #define CSR_WRITE_4(sc, reg, val) \
2366 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2368 #define CSR_READ_4(sc, reg) \
2369 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2371 #define BGE_SETBIT(sc, reg, x) \
2372 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
2373 #define BGE_CLRBIT(sc, reg, x) \
2374 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
2376 #define PCI_SETBIT(dev, reg, x, s) \
2377 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
2378 #define PCI_CLRBIT(dev, reg, x, s) \
2379 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
2382 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2383 * values are tuneable. They control the actual amount of buffers
2384 * allocated for the standard, mini and jumbo receive rings.
2387 #define BGE_SSLOTS 256
2388 #define BGE_MSLOTS 256
2389 #define BGE_JSLOTS 384
2391 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2392 #define BGE_JLEN (BGE_JRAWLEN + \
2393 (sizeof(uint64_t) - BGE_JRAWLEN % sizeof(uint64_t)))
2394 #define BGE_JPAGESZ PAGE_SIZE
2395 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2396 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2401 struct bge_softc *bge_sc;
2403 bus_addr_t bge_paddr;
2406 SLIST_ENTRY(bge_jslot) jslot_link;
2409 #if (BUS_SPACE_MAXADDR != BUS_SPACE_MAXADDR_32BIT)
2410 #define BGE_DMA_MAXADDR_40BIT 0xFFFFFFFFFF
2411 #define BGE_DMA_BOUNDARY_4G 0x100000000ULL
2413 #define BGE_DMA_MAXADDR_40BIT BUS_SPACE_MAXADDR
2414 #define BGE_DMA_BOUNDARY_4G 0
2418 * Ring structures. Most of these reside in host memory and we tell
2419 * the NIC where they are via the ring control blocks. The exceptions
2420 * are the tx and command rings, which live in NIC memory and which
2421 * we access via the shared memory window.
2423 struct bge_ring_data {
2424 struct bge_rx_bd *bge_rx_std_ring;
2425 bus_addr_t bge_rx_std_ring_paddr;
2426 struct bge_rx_bd *bge_rx_jumbo_ring;
2427 bus_addr_t bge_rx_jumbo_ring_paddr;
2428 struct bge_rx_bd *bge_rx_return_ring;
2429 bus_addr_t bge_rx_return_ring_paddr;
2430 struct bge_tx_bd *bge_tx_ring;
2431 bus_addr_t bge_tx_ring_paddr;
2432 struct bge_status_block *bge_status_block;
2433 bus_addr_t bge_status_block_paddr;
2434 struct bge_stats *bge_stats;
2435 bus_addr_t bge_stats_paddr;
2436 void *bge_jumbo_buf;
2437 struct bge_gib bge_info;
2440 #define BGE_STD_RX_RING_SZ \
2441 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2442 #define BGE_JUMBO_RX_RING_SZ \
2443 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT)
2444 #define BGE_TX_RING_SZ \
2445 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2446 #define BGE_RX_RTN_RING_SZ(x) \
2447 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2449 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2451 #define BGE_STATS_SZ sizeof (struct bge_stats)
2453 struct bge_rxchain {
2454 struct mbuf *bge_mbuf;
2455 bus_addr_t bge_paddr;
2459 * Mbuf pointers. We need these to keep track of the virtual addresses
2460 * of our mbuf chains since we can only convert from physical to virtual,
2461 * not the other way around.
2463 struct bge_chain_data {
2464 bus_dma_tag_t bge_parent_tag;
2465 bus_dma_tag_t bge_rx_std_ring_tag;
2466 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2467 bus_dma_tag_t bge_rx_return_ring_tag;
2468 bus_dma_tag_t bge_tx_ring_tag;
2469 bus_dma_tag_t bge_status_tag;
2470 bus_dma_tag_t bge_stats_tag;
2471 bus_dma_tag_t bge_jumbo_tag;
2472 bus_dma_tag_t bge_tx_mtag; /* TX mbuf DMA tag */
2473 bus_dma_tag_t bge_rx_mtag; /* RX mbuf DMA tag */
2474 bus_dmamap_t bge_rx_tmpmap;
2475 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2476 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2477 bus_dmamap_t bge_rx_std_ring_map;
2478 bus_dmamap_t bge_rx_jumbo_ring_map;
2479 bus_dmamap_t bge_tx_ring_map;
2480 bus_dmamap_t bge_rx_return_ring_map;
2481 bus_dmamap_t bge_status_map;
2482 bus_dmamap_t bge_stats_map;
2483 bus_dmamap_t bge_jumbo_map;
2484 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2485 struct bge_rxchain bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2486 struct bge_rxchain bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2487 /* Stick the jumbo mem management stuff here too. */
2488 struct bge_jslot bge_jslots[BGE_JSLOTS];
2497 #define BGE_HWREV_TIGON 0x01
2498 #define BGE_HWREV_TIGON_II 0x02
2499 #define BGE_TIMEOUT 5000
2500 #define BGE_FIRMWARE_TIMEOUT 20000
2501 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2503 struct bge_bcom_hack {
2509 struct arpcom arpcom; /* interface info */
2511 device_t bge_miibus;
2512 bus_space_handle_t bge_bhandle;
2513 bus_space_tag_t bge_btag;
2515 struct resource *bge_irq;
2516 struct resource *bge_res;
2517 struct ifmedia bge_ifmedia; /* TBI media info */
2520 uint32_t bge_pci_miscctl;
2521 uint32_t bge_status_tag;
2522 uint32_t bge_flags; /* BGE_FLAG_ */
2523 #define BGE_FLAG_TBI 0x00000001
2524 #define BGE_FLAG_JUMBO 0x00000002
2525 #define BGE_FLAG_MII_SERDES 0x00000010
2526 #define BGE_FLAG_CPMU 0x00000020
2527 #define BGE_FLAG_PCIX 0x00000200
2528 #define BGE_FLAG_PCIE 0x00000400
2529 #define BGE_FLAG_5700_FAMILY 0x00001000
2530 #define BGE_FLAG_5705_PLUS 0x00002000
2531 #define BGE_FLAG_5714_FAMILY 0x00004000
2532 #define BGE_FLAG_575X_PLUS 0x00008000
2533 #define BGE_FLAG_5755_PLUS 0x00010000
2534 #define BGE_FLAG_MAXADDR_40BIT 0x00020000
2535 #define BGE_FLAG_RX_ALIGNBUG 0x00100000
2536 #define BGE_FLAG_NO_EEPROM 0x10000000
2537 #define BGE_FLAG_5788 0x20000000
2538 #define BGE_FLAG_SHORTDMA 0x40000000
2539 #define BGE_FLAG_STATUS_TAG 0x80000000
2541 uint32_t bge_chipid;
2542 uint32_t bge_asicrev;
2543 uint32_t bge_chiprev;
2544 struct bge_ring_data bge_ldata; /* rings */
2545 struct bge_chain_data bge_cdata; /* mbufs */
2546 uint16_t bge_tx_saved_considx;
2547 uint16_t bge_rx_saved_considx;
2548 uint16_t bge_ev_saved_considx;
2549 uint16_t bge_return_ring_cnt;
2550 uint16_t bge_std; /* current std ring head */
2551 uint16_t bge_jumbo; /* current jumo ring head */
2552 SLIST_HEAD(__bge_jfreehead, bge_jslot) bge_jfree_listhead;
2553 struct lwkt_serialize bge_jslot_serializer;
2554 uint32_t bge_stat_ticks;
2555 uint32_t bge_rx_coal_ticks;
2556 uint32_t bge_tx_coal_ticks;
2557 uint32_t bge_rx_coal_bds;
2558 uint32_t bge_tx_coal_bds;
2559 uint32_t bge_rx_coal_ticks_int;
2560 uint32_t bge_tx_coal_ticks_int;
2561 uint32_t bge_rx_coal_bds_int;
2562 uint32_t bge_tx_coal_bds_int;
2563 uint32_t bge_tx_prodidx;
2564 uint32_t bge_tx_buf_ratio;
2565 uint32_t bge_mi_mode;
2566 int bge_force_defrag;
2567 int bge_mbox_reorder;
2572 struct callout bge_stat_timer;
2574 struct sysctl_ctx_list bge_sysctl_ctx;
2575 struct sysctl_oid *bge_sysctl_tree;
2577 uint32_t bge_phy_flags;
2578 #define BGE_PHY_NO_3LED 0x00200000
2579 #define BGE_PHY_ADC_BUG 0x00400000
2580 #define BGE_PHY_5704_A0_BUG 0x00800000
2581 #define BGE_PHY_JITTER_BUG 0x01000000
2582 #define BGE_PHY_BER_BUG 0x02000000
2583 #define BGE_PHY_ADJUST_TRIM 0x04000000
2584 #define BGE_PHY_CRC_BUG 0x08000000
2585 #define BGE_PHY_WIRESPEED 0x00000004
2588 uint32_t bge_coal_chg;
2589 #define BGE_RX_COAL_TICKS_CHG 0x01
2590 #define BGE_TX_COAL_TICKS_CHG 0x02
2591 #define BGE_RX_COAL_BDS_CHG 0x04
2592 #define BGE_TX_COAL_BDS_CHG 0x08
2593 #define BGE_RX_COAL_TICKS_INT_CHG 0x10
2594 #define BGE_TX_COAL_TICKS_INT_CHG 0x20
2595 #define BGE_RX_COAL_BDS_INT_CHG 0x40
2596 #define BGE_TX_COAL_BDS_INT_CHG 0x80
2598 void (*bge_link_upd)(struct bge_softc *, uint32_t);
2599 uint32_t bge_link_chg;
2602 #define BGE_NSEG_NEW 32
2603 #define BGE_NSEG_SPARE 5
2604 #define BGE_NSEG_RSVD 16
2606 /* RX coalesce ticks, unit: us */
2607 #define BGE_RX_COAL_TICKS_MIN 0
2608 #define BGE_RX_COAL_TICKS_DEF 100
2609 #define BGE_RX_COAL_TICKS_MAX 1023
2611 /* TX coalesce ticks, unit: us */
2612 #define BGE_TX_COAL_TICKS_MIN 0
2613 #define BGE_TX_COAL_TICKS_DEF 1023
2614 #define BGE_TX_COAL_TICKS_MAX 1023
2616 /* RX coalesce BDs */
2617 #define BGE_RX_COAL_BDS_MIN 1
2618 #define BGE_RX_COAL_BDS_DEF 80
2619 #define BGE_RX_COAL_BDS_MAX 255
2621 /* TX coalesce BDs */
2622 #define BGE_TX_COAL_BDS_MIN 1
2623 #define BGE_TX_COAL_BDS_DEF 128
2624 #define BGE_TX_COAL_BDS_MAX 255