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32 * $FreeBSD: src/sys/i386/isa/rpreg.h,v 1.2.6.1 2000/08/03 01:01:20 peter Exp $
36 * Begin OS-specific defines - rpreg.h - for RocketPort FreeBSD
39 typedef unsigned char Byte_t;
40 typedef unsigned int ByteIO_t;
42 typedef unsigned int Word_t;
43 typedef unsigned int WordIO_t;
45 typedef unsigned long DWord_t;
46 typedef unsigned int DWordIO_t;
48 #define sOutB(a, b) outb(a, b)
49 #define sOutW(a, b) outw(a, b)
50 #define sOutDW(a, b) outl(a, b)
51 #define sInB(a) (inb(a))
52 #define sInW(a) (inw(a))
53 #define sOutStrW(port, addr, count) outsw(port, addr, count)
54 #define sInStrW(port, addr, count) insw(port, addr, count)
57 * End of OS-specific defines
63 #define AIOP_CTL_SIZE 4
64 #define CHAN_AIOP_SIZE 8
65 #define MAX_PORTS_PER_AIOP 8
66 #define MAX_AIOPS_PER_BOARD 4
67 #define MAX_PORTS_PER_BOARD 32
74 /* Controller ID numbers */
75 #define CTLID_NULL -1 /* no controller exists */
76 #define CTLID_0001 0x0001 /* controller release 1 */
79 #define RP_VENDOR_ID 0x11FE
80 #define RP_DEVICE_ID_8OCTA 0x0001
81 #define RP_DEVICE_ID_8INTF 0x0002
82 #define RP_DEVICE_ID_16INTF 0x0003
83 #define RP_DEVICE_ID_32INTF 0x0004
85 /* AIOP ID numbers, identifies AIOP type implementing channel */
86 #define AIOPID_NULL -1 /* no AIOP or channel exists */
87 #define AIOPID_0001 0x0001 /* AIOP release 1 */
89 #define NULLDEV -1 /* identifies non-existant device */
90 #define NULLCTL -1 /* identifies non-existant controller */
91 #define NULLCTLPTR (CONTROLLER_T *)0 /* identifies non-existant controller */
92 #define NULLAIOP -1 /* identifies non-existant AIOP */
93 #define NULLCHAN -1 /* identifies non-existant channel */
95 /************************************************************************
96 Global Register Offsets - Direct Access - Fixed values
97 ************************************************************************/
99 #define _CMD_REG 0x38 /* Command Register 8 Write */
100 #define _INT_CHAN 0x39 /* Interrupt Channel Register 8 Read */
101 #define _INT_MASK 0x3A /* Interrupt Mask Register 8 Read / Write */
102 #define _UNUSED 0x3B /* Unused 8 */
103 #define _INDX_ADDR 0x3C /* Index Register Address 16 Write */
104 #define _INDX_DATA 0x3E /* Index Register Data 8/16 Read / Write */
106 /************************************************************************
107 Channel Register Offsets for 1st channel in AIOP - Direct Access
108 ************************************************************************/
109 #define _TD0 0x00 /* Transmit Data 16 Write */
110 #define _RD0 0x00 /* Receive Data 16 Read */
111 #define _CHN_STAT0 0x20 /* Channel Status 8/16 Read / Write */
112 #define _FIFO_CNT0 0x10 /* Transmit/Receive FIFO Count 16 Read */
113 #define _INT_ID0 0x30 /* Interrupt Identification 8 Read */
115 /************************************************************************
116 Tx Control Register Offsets - Indexed - External - Fixed
117 ************************************************************************/
118 #define _TX_ENBLS 0x980 /* Tx Processor Enables Register 8 Read / Write */
119 #define _TXCMP1 0x988 /* Transmit Compare Value #1 8 Read / Write */
120 #define _TXCMP2 0x989 /* Transmit Compare Value #2 8 Read / Write */
121 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
122 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
123 #define _TXREP2 0x98C /* Transmit Replace Value #2 8 Read / Write */
125 /************************************************************************
127 ************************************************************************/
128 #define RXFIFO_DATA 0x5f
129 #define RXFIFO_OUT 0x5c
130 #define RXFIFO_EN 0x08
131 #define RXFIFO_DIS 0xa7
133 /************************************************************************
134 Memory Controller Register Offsets - Indexed - External - Fixed
135 ************************************************************************/
136 #define _RX_FIFO 0x000 /* Rx FIFO */
137 #define _TX_FIFO 0x800 /* Tx FIFO */
138 #define _RXF_OUTP 0x990 /* Rx FIFO OUT pointer 16 Read / Write */
139 #define _RXF_INP 0x992 /* Rx FIFO IN pointer 16 Read / Write */
140 #define _TXF_OUTP 0x994 /* Tx FIFO OUT pointer 8 Read / Write */
141 #define _TXF_INP 0x995 /* Tx FIFO IN pointer 8 Read / Write */
142 #define _TXP_CNT 0x996 /* Tx Priority Count 8 Read / Write */
143 #define _TXP_PNTR 0x997 /* Tx Priority Pointer 8 Read / Write */
145 #define PRI_PEND 0x80 /* Priority data pending (bit7, Tx pri cnt) */
146 #define TXFIFO_SIZE 255 /* size of Tx FIFO */
147 #define RXFIFO_SIZE 1023 /* size of Rx FIFO */
149 /************************************************************************
150 Tx Priority Buffer - Indexed - External - Fixed
151 ************************************************************************/
152 #define _TXP_BUF 0x9C0 /* Tx Priority Buffer 32 Bytes Read / Write */
153 #define TXP_SIZE 0x20 /* 32 bytes */
155 /************************************************************************
156 Channel Register Offsets - Indexed - Internal - Fixed
157 ************************************************************************/
159 #define _TX_CTRL 0xFF0 /* Transmit Control 16 Write */
160 #define _RX_CTRL 0xFF2 /* Receive Control 8 Write */
161 #define _BAUD 0xFF4 /* Baud Rate 16 Write */
162 #define _CLK_PRE 0xFF6 /* Clock Prescaler 8 Write */
164 #define CLOCK_PRESC 0x19 /* mod 9 (divide by 10) prescale */
190 #define STMBREAK 0x08 /* BREAK */
191 #define STMFRAME 0x04 /* framing error */
192 #define STMRCVROVR 0x02 /* receiver over run error */
193 #define STMPARITY 0x01 /* parity error */
194 #define STMERROR (STMBREAK | STMFRAME | STMPARITY)
195 #define STMBREAKH 0x800 /* BREAK */
196 #define STMFRAMEH 0x400 /* framing error */
197 #define STMRCVROVRH 0x200 /* receiver over run error */
198 #define STMPARITYH 0x100 /* parity error */
199 #define STMERRORH (STMBREAKH | STMFRAMEH | STMPARITYH)
201 #define CTS_ACT 0x20 /* CTS input asserted */
202 #define DSR_ACT 0x10 /* DSR input asserted */
203 #define CD_ACT 0x08 /* CD input asserted */
204 #define TXFIFOMT 0x04 /* Tx FIFO is empty */
205 #define TXSHRMT 0x02 /* Tx shift register is empty */
206 #define RDA 0x01 /* Rx data available */
207 #define DRAINED (TXFIFOMT | TXSHRMT) /* indicates Tx is drained */
209 #define STATMODE 0x8000 /* status mode enable bit */
210 #define RXFOVERFL 0x2000 /* receive FIFO overflow */
211 #define RX2MATCH 0x1000 /* receive compare byte 2 match */
212 #define RX1MATCH 0x0800 /* receive compare byte 1 match */
213 #define RXBREAK 0x0400 /* received BREAK */
214 #define RXFRAME 0x0200 /* received framing error */
215 #define RXPARITY 0x0100 /* received parity error */
216 #define STATERROR (RXBREAK | RXFRAME | RXPARITY)
218 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
219 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
220 #define TXINT_EN 0x10 /* transmit interrupt enable */
221 #define STOP2 0x08 /* enable 2 stop bits (0 = 1 stop) */
222 #define PARITY_EN 0x04 /* enable parity (0 = no parity) */
223 #define EVEN_PAR 0x02 /* even parity (0 = odd parity) */
224 #define DATA8BIT 0x01 /* 8 bit data (0 = 7 bit data) */
226 #define SETBREAK 0x10 /* send break condition (must clear) */
227 #define LOCALLOOP 0x08 /* local loopback set for test */
228 #define SET_DTR 0x04 /* assert DTR */
229 #define SET_RTS 0x02 /* assert RTS */
230 #define TX_ENABLE 0x01 /* enable transmitter */
232 #define RTSFC_EN 0x40 /* RTS flow control enable */
233 #define RXPROC_EN 0x20 /* receive processor enable */
234 #define TRIG_NO 0x00 /* Rx FIFO trigger level 0 (no trigger) */
235 #define TRIG_1 0x08 /* trigger level 1 char */
236 #define TRIG_1_2 0x10 /* trigger level 1/2 */
237 #define TRIG_7_8 0x18 /* trigger level 7/8 */
238 #define TRIG_MASK 0x18 /* trigger level mask */
239 #define SRCINT_EN 0x04 /* special Rx condition interrupt enable */
240 #define RXINT_EN 0x02 /* Rx interrupt enable */
241 #define MCINT_EN 0x01 /* modem change interrupt enable */
243 #define RXF_TRIG 0x20 /* Rx FIFO trigger level interrupt */
244 #define TXFIFO_MT 0x10 /* Tx FIFO empty interrupt */
245 #define SRC_INT 0x08 /* special receive condition interrupt */
246 #define DELTA_CD 0x04 /* CD change interrupt */
247 #define DELTA_CTS 0x02 /* CTS change interrupt */
248 #define DELTA_DSR 0x01 /* DSR change interrupt */
250 #define REP1W2_EN 0x10 /* replace byte 1 with 2 bytes enable */
251 #define IGN2_EN 0x08 /* ignore byte 2 enable */
252 #define IGN1_EN 0x04 /* ignore byte 1 enable */
253 #define COMP2_EN 0x02 /* compare byte 2 enable */
254 #define COMP1_EN 0x01 /* compare byte 1 enable */
256 #define RESET_ALL 0x80 /* reset AIOP (all channels) */
257 #define TXOVERIDE 0x40 /* Transmit software off override */
258 #define RESETUART 0x20 /* reset channel's UART */
259 #define RESTXFCNT 0x10 /* reset channel's Tx FIFO count register */
260 #define RESRXFCNT 0x08 /* reset channel's Rx FIFO count register */
262 #define INTSTAT0 0x01 /* AIOP 0 interrupt status */
263 #define INTSTAT1 0x02 /* AIOP 1 interrupt status */
264 #define INTSTAT2 0x04 /* AIOP 2 interrupt status */
265 #define INTSTAT3 0x08 /* AIOP 3 interrupt status */
267 #define INTR_EN 0x08 /* allow interrupts to host */
268 #define INT_STROB 0x04 /* strobe and clear interrupt line (EOI) */
270 /**************************************************************************
271 MUDBAC remapped for PCI
272 **************************************************************************/
274 #define _CFG_INT_PCI 0x40
275 #define _PCI_INT_FUNC 0x3A
277 #define PCI_STROB 0x2000
278 #define INTR_EN_PCI 0x0010
280 #define CHAN3_EN 0x08 /* enable AIOP 3 */
281 #define CHAN2_EN 0x04 /* enable AIOP 2 */
282 #define CHAN1_EN 0x02 /* enable AIOP 1 */
283 #define CHAN0_EN 0x01 /* enable AIOP 0 */
284 #define FREQ_DIS 0x00
285 #define FREQ_274HZ 0x60
286 #define FREQ_137HZ 0x50
287 #define FREQ_69HZ 0x40
288 #define FREQ_34HZ 0x30
289 #define FREQ_17HZ 0x20
290 #define FREQ_9HZ 0x10
291 #define PERIODIC_ONLY 0x80 /* only PERIODIC interrupt */
293 #define CHANINT_EN 0x0100 /* flags to enable/disable channel ints */
296 #define RREGDATASIZE 52
298 /* Controller level information structure */
312 WordIO_t AiopIO[AIOP_CTL_SIZE];
313 ByteIO_t AiopIntChanIO[AIOP_CTL_SIZE];
314 int AiopID[AIOP_CTL_SIZE];
315 int AiopNumChan[AIOP_CTL_SIZE];
318 typedef CONTROLLER_T CONTROLLER_t;
320 /* Channel level information structure */
347 Byte_t R[RREGDATASIZE];
354 Byte_t TxReplace1[4];
355 Byte_t TxReplace2[4];
358 typedef CHANNEL_T CHANNEL_t;
359 typedef CHANNEL_T * CHANPTR_T;
361 /***************************************************************************
363 Purpose: Stop sending a transmit BREAK signal
365 CHANNEL_T *ChP; Ptr to channel structure
367 #define sClrBreak(ChP) \
369 (ChP)->TxControl[3] &= ~SETBREAK; \
370 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
373 /***************************************************************************
375 Purpose: Clr the DTR output
377 CHANNEL_T *ChP; Ptr to channel structure
379 #define sClrDTR(ChP) \
381 (ChP)->TxControl[3] &= ~SET_DTR; \
382 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
385 /***************************************************************************
387 Purpose: Clr the RTS output
389 CHANNEL_T *ChP; Ptr to channel structure
391 #define sClrRTS(ChP) \
393 (ChP)->TxControl[3] &= ~SET_RTS; \
394 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
397 /***************************************************************************
399 Purpose: Clear any existing transmit software flow control off condition
400 Call: sClrTxXOFF(ChP)
401 CHANNEL_T *ChP; Ptr to channel structure
403 #define sClrTxXOFF(ChP) \
405 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
406 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
409 /***************************************************************************
410 Function: sCtlNumToCtlPtr
411 Purpose: Convert a controller number to controller structure pointer
412 Call: sCtlNumToCtlPtr(CtlNum)
413 int CtlNum; Controller number
414 Return: CONTROLLER_T *: Ptr to controller structure
416 #define sCtlNumToCtlPtr(CTLNUM) &sController[CTLNUM]
418 /***************************************************************************
419 Function: sControllerEOI
420 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
421 Call: sControllerEOI(CtlP)
422 CONTROLLER_T *CtlP; Ptr to controller structure
424 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
427 /***************************************************************************
428 Function: sPCIControllerEOI
429 Purpose: Strobe the MUDBAC's End Of Interrupt bit.
430 Call: sPCIControllerEOI(CtlP)
431 CONTROLLER_T *CtlP; Ptr to controller structure
433 #define sPCIControllerEOI(CTLP) sOutW((CTLP)->PCIIO, PCI_STROB)
435 /***************************************************************************
437 Purpose: Disable I/O access to an AIOP
439 CONTROLLER_T *CtlP; Ptr to controller structure
440 int AiopNum; Number of AIOP on controller
442 #define sDisAiop(CTLP,AIOPNUM) \
444 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
445 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
448 /***************************************************************************
449 Function: sDisCTSFlowCtl
450 Purpose: Disable output flow control using CTS
451 Call: sDisCTSFlowCtl(ChP)
452 CHANNEL_T *ChP; Ptr to channel structure
454 #define sDisCTSFlowCtl(ChP) \
456 (ChP)->TxControl[2] &= ~CTSFC_EN; \
457 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
460 /***************************************************************************
462 Purpose: Disable parity
463 Call: sDisParity(ChP)
464 CHANNEL_T *ChP; Ptr to channel structure
465 Comments: Function sSetParity() can be used in place of functions sEnParity(),
466 sDisParity(), sSetOddParity(), and sSetEvenParity().
468 #define sDisParity(ChP) \
470 (ChP)->TxControl[2] &= ~PARITY_EN; \
471 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
474 /***************************************************************************
476 Purpose: Disable Rx FIFO
477 Call: sDisRxFIFO(ChP)
478 CHANNEL_T *ChP; Ptr to channel structure
480 #define sDisRxFIFO(ChP) \
482 (ChP)->R[0x32] = 0x0a; \
483 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
486 /***************************************************************************
487 Function: sDisRxStatusMode
488 Purpose: Disable the Rx status mode
489 Call: sDisRxStatusMode(ChP)
490 CHANNEL_T *ChP; Ptr to channel structure
491 Comments: This takes the channel out of the receive status mode. All
492 subsequent reads of receive data using sReadRxWord() will return
495 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
497 /***************************************************************************
498 Function: sDisTransmit
499 Purpose: Disable transmit
500 Call: sDisTransmit(ChP)
501 CHANNEL_T *ChP; Ptr to channel structure
502 This disables movement of Tx data from the Tx FIFO into the 1 byte
503 Tx buffer. Therefore there could be up to a 2 byte latency
504 between the time sDisTransmit() is called and the transmit buffer
505 and transmit shift register going completely empty.
507 #define sDisTransmit(ChP) \
509 (ChP)->TxControl[3] &= ~TX_ENABLE; \
510 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
513 /***************************************************************************
514 Function: sDisTxSoftFlowCtl
515 Purpose: Disable Tx Software Flow Control
516 Call: sDisTxSoftFlowCtl(ChP)
517 CHANNEL_T *ChP; Ptr to channel structure
519 #define sDisTxSoftFlowCtl(ChP) \
521 (ChP)->R[0x06] = 0x8a; \
522 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x04]); \
525 /***************************************************************************
527 Purpose: Enable I/O access to an AIOP
529 CONTROLLER_T *CtlP; Ptr to controller structure
530 int AiopNum; Number of AIOP on controller
532 #define sEnAiop(CTLP,AIOPNUM) \
534 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
535 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
538 /***************************************************************************
539 Function: sEnCTSFlowCtl
540 Purpose: Enable output flow control using CTS
541 Call: sEnCTSFlowCtl(ChP)
542 CHANNEL_T *ChP; Ptr to channel structure
544 #define sEnCTSFlowCtl(ChP) \
546 (ChP)->TxControl[2] |= CTSFC_EN; \
547 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
550 /***************************************************************************
552 Purpose: Enable parity
554 CHANNEL_T *ChP; Ptr to channel structure
555 Comments: Function sSetParity() can be used in place of functions sEnParity(),
556 sDisParity(), sSetOddParity(), and sSetEvenParity().
558 Warnings: Before enabling parity odd or even parity should be chosen using
559 functions sSetOddParity() or sSetEvenParity().
561 #define sEnParity(ChP) \
563 (ChP)->TxControl[2] |= PARITY_EN; \
564 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
567 /***************************************************************************
568 Function: sEnRTSFlowCtl
571 #define sEnRTSFlowCtl(ChP) \
573 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
574 (ChP)->TxControl[3] &= ~SET_RTS; \
575 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
576 (ChP)->RxControl[2] |= RTSFC_EN; \
577 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
580 /***************************************************************************
581 Function: sDisRTSFlowCtl
584 #define sDisRTSFlowCtl(ChP) \
586 (ChP)->RxControl[2] &= ~RTSFC_EN; \
587 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
590 /***************************************************************************
592 Purpose: Enable Rx FIFO
594 CHANNEL_T *ChP; Ptr to channel structure
596 #define sEnRxFIFO(ChP) \
598 (ChP)->R[0x32] = 0x08; \
599 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0x30]); \
602 /***************************************************************************
603 Function: sEnRxProcessor
604 Purpose: Enable the receive processor
605 Call: sEnRxProcessor(ChP)
606 CHANNEL_T *ChP; Ptr to channel structure
607 Comments: This function is used to start the receive processor. When
608 the channel is in the reset state the receive processor is not
609 running. This is done to prevent the receive processor from
610 executing invalid microcode instructions prior to the
611 downloading of the microcode.
613 Warnings: This function must be called after valid microcode has been
614 downloaded to the AIOP, and it must not be called before the
615 microcode has been downloaded.
617 #define sEnRxProcessor(ChP) \
619 (ChP)->RxControl[2] |= RXPROC_EN; \
620 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
623 /***************************************************************************
624 Function: sEnRxStatusMode
625 Purpose: Enable the Rx status mode
626 Call: sEnRxStatusMode(ChP)
627 CHANNEL_T *ChP; Ptr to channel structure
628 Comments: This places the channel in the receive status mode. All subsequent
629 reads of receive data using sReadRxWord() will return a data byte
630 in the low word and a status byte in the high word.
633 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
635 /***************************************************************************
636 Function: sEnTransmit
637 Purpose: Enable transmit
638 Call: sEnTransmit(ChP)
639 CHANNEL_T *ChP; Ptr to channel structure
641 #define sEnTransmit(ChP) \
643 (ChP)->TxControl[3] |= TX_ENABLE; \
644 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
647 /***************************************************************************
648 Function: sGetAiopIntStatus
649 Purpose: Get the AIOP interrupt status
650 Call: sGetAiopIntStatus(CtlP,AiopNum)
651 CONTROLLER_T *CtlP; Ptr to controller structure
652 int AiopNum; AIOP number
653 Return: Byte_t: The AIOP interrupt status. Bits 0 through 7
654 represent channels 0 through 7 respectively. If a
655 bit is set that channel is interrupting.
657 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
659 /***************************************************************************
660 Function: sGetAiopNumChan
661 Purpose: Get the number of channels supported by an AIOP
662 Call: sGetAiopNumChan(CtlP,AiopNum)
663 CONTROLLER_T *CtlP; Ptr to controller structure
664 int AiopNum; AIOP number
665 Return: int: The number of channels supported by the AIOP
667 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
669 /***************************************************************************
670 Function: sGetChanIntID
671 Purpose: Get a channel's interrupt identification byte
672 Call: sGetChanIntID(ChP)
673 CHANNEL_T *ChP; Ptr to channel structure
674 Return: Byte_t: The channel interrupt ID. Can be any
675 combination of the following flags:
676 RXF_TRIG: Rx FIFO trigger level interrupt
677 TXFIFO_MT: Tx FIFO empty interrupt
678 SRC_INT: Special receive condition interrupt
679 DELTA_CD: CD change interrupt
680 DELTA_CTS: CTS change interrupt
681 DELTA_DSR: DSR change interrupt
683 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR))
685 /***************************************************************************
686 Function: sGetChanNum
687 Purpose: Get the number of a channel within an AIOP
688 Call: sGetChanNum(ChP)
689 CHANNEL_T *ChP; Ptr to channel structure
690 Return: int: Channel number within AIOP, or NULLCHAN if channel does
693 #define sGetChanNum(ChP) (ChP)->ChanNum
695 /***************************************************************************
696 Function: sGetChanStatus
697 Purpose: Get the channel status
698 Call: sGetChanStatus(ChP)
699 CHANNEL_T *ChP; Ptr to channel structure
700 Return: Word_t: The channel status. Can be any combination of
703 CTS_ACT: CTS input asserted
704 DSR_ACT: DSR input asserted
705 CD_ACT: CD input asserted
706 TXFIFOMT: Tx FIFO is empty
707 TXSHRMT: Tx shift register is empty
708 RDA: Rx data available
711 STATMODE: status mode enable bit
712 RXFOVERFL: receive FIFO overflow
713 RX2MATCH: receive compare byte 2 match
714 RX1MATCH: receive compare byte 1 match
715 RXBREAK: received BREAK
716 RXFRAME: received framing error
717 RXPARITY: received parity error
718 Warnings: This function will clear the high byte flags in the Channel
721 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
723 /***************************************************************************
724 Function: sGetChanStatusLo
725 Purpose: Get the low byte only of the channel status
726 Call: sGetChanStatusLo(ChP)
727 CHANNEL_T *ChP; Ptr to channel structure
728 Return: Byte_t: The channel status low byte. Can be any combination
729 of the following flags:
730 CTS_ACT: CTS input asserted
731 DSR_ACT: DSR input asserted
732 CD_ACT: CD input asserted
733 TXFIFOMT: Tx FIFO is empty
734 TXSHRMT: Tx shift register is empty
735 RDA: Rx data available
737 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
739 /***************************************************************************
740 Function: sGetControllerIntStatus
741 Purpose: Get the controller interrupt status
742 Call: sGetControllerIntStatus(CtlP)
743 CONTROLLER_T *CtlP; Ptr to controller structure
744 Return: Byte_t: The controller interrupt status in the lower 4
745 bits. Bits 0 through 3 represent AIOP's 0
746 through 3 respectively. If a bit is set that
747 AIOP is interrupting. Bits 4 through 7 will
750 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
752 /***************************************************************************
753 Function: sPCIGetControllerIntStatus
754 Purpose: Get the controller interrupt status
755 Call: sPCIGetControllerIntStatus(CtlP)
756 CONTROLLER_T *CtlP; Ptr to controller structure
757 Return: Byte_t: The controller interrupt status in the lower 4
758 bits. Bits 0 through 3 represent AIOP's 0
759 through 3 respectively. If a bit is set that
760 AIOP is interrupting. Bits 4 through 7 will
763 #define sPCIGetControllerIntStatus(CTLP) ((sInW((CTLP)->PCIIO) >> 8) & 0x1f)
765 /***************************************************************************
767 Purpose: Get the number of data bytes in the Rx FIFO
769 CHANNEL_T *ChP; Ptr to channel structure
770 Return: int: The number of data bytes in the Rx FIFO.
771 Comments: Byte read of count register is required to obtain Rx count.
774 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
776 /***************************************************************************
778 Purpose: Get the number of data bytes in the Tx FIFO
780 CHANNEL_T *ChP; Ptr to channel structure
781 Return: Byte_t: The number of data bytes in the Tx FIFO.
782 Comments: Byte read of count register is required to obtain Tx count.
785 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
787 /*****************************************************************************
788 Function: sGetTxRxDataIO
789 Purpose: Get the I/O address of a channel's TxRx Data register
790 Call: sGetTxRxDataIO(ChP)
791 CHANNEL_T *ChP; Ptr to channel structure
792 Return: WordIO_t: I/O address of a channel's TxRx Data register
794 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
796 /***************************************************************************
797 Function: sInitChanDefaults
798 Purpose: Initialize a channel structure to its default state.
799 Call: sInitChanDefaults(ChP)
800 CHANNEL_T *ChP; Ptr to the channel structure
801 Comments: This function must be called once for every channel structure
802 that exists before any other SSCI calls can be made.
805 #define sInitChanDefaults(ChP) \
807 (ChP)->CtlP = NULLCTLPTR; \
808 (ChP)->AiopNum = NULLAIOP; \
809 (ChP)->ChanID = AIOPID_NULL; \
810 (ChP)->ChanNum = NULLCHAN; \
813 /***************************************************************************
814 Function: sResetAiopByNum
815 Purpose: Reset the AIOP by number
816 Call: sResetAiopByNum(CTLP,AIOPNUM)
817 CONTROLLER_T CTLP; Ptr to controller structure
820 #define sResetAiopByNum(CTLP,AIOPNUM) \
822 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
823 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
826 /***************************************************************************
828 Purpose: Send a transmit BREAK signal
829 Call: sSendBreak(ChP)
830 CHANNEL_T *ChP; Ptr to channel structure
832 #define sSendBreak(ChP) \
834 (ChP)->TxControl[3] |= SETBREAK; \
835 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
838 /***************************************************************************
840 Purpose: Set baud rate
841 Call: sSetBaud(ChP,Divisor)
842 CHANNEL_T *ChP; Ptr to channel structure
843 Word_t Divisor; 16 bit baud rate divisor for channel
845 #define sSetBaud(ChP,DIVISOR) \
847 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
848 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
849 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->BaudDiv[0]); \
852 /***************************************************************************
854 Purpose: Set data bits to 7
856 CHANNEL_T *ChP; Ptr to channel structure
858 #define sSetData7(ChP) \
860 (ChP)->TxControl[2] &= ~DATA8BIT; \
861 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
864 /***************************************************************************
866 Purpose: Set data bits to 8
868 CHANNEL_T *ChP; Ptr to channel structure
870 #define sSetData8(ChP) \
872 (ChP)->TxControl[2] |= DATA8BIT; \
873 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
876 /***************************************************************************
878 Purpose: Set the DTR output
880 CHANNEL_T *ChP; Ptr to channel structure
882 #define sSetDTR(ChP) \
884 (ChP)->TxControl[3] |= SET_DTR; \
885 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
888 /***************************************************************************
889 Function: sSetEvenParity
890 Purpose: Set even parity
891 Call: sSetEvenParity(ChP)
892 CHANNEL_T *ChP; Ptr to channel structure
893 Comments: Function sSetParity() can be used in place of functions sEnParity(),
894 sDisParity(), sSetOddParity(), and sSetEvenParity().
896 Warnings: This function has no effect unless parity is enabled with function
899 #define sSetEvenParity(ChP) \
901 (ChP)->TxControl[2] |= EVEN_PAR; \
902 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
905 /***************************************************************************
906 Function: sSetOddParity
907 Purpose: Set odd parity
908 Call: sSetOddParity(ChP)
909 CHANNEL_T *ChP; Ptr to channel structure
910 Comments: Function sSetParity() can be used in place of functions sEnParity(),
911 sDisParity(), sSetOddParity(), and sSetEvenParity().
913 Warnings: This function has no effect unless parity is enabled with function
916 #define sSetOddParity(ChP) \
918 (ChP)->TxControl[2] &= ~EVEN_PAR; \
919 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
922 /***************************************************************************
924 Purpose: Set the RTS output
926 CHANNEL_T *ChP; Ptr to channel structure
928 #define sSetRTS(ChP) \
930 (ChP)->TxControl[3] |= SET_RTS; \
931 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
934 /***************************************************************************
935 Function: sSetRxTrigger
936 Purpose: Set the Rx FIFO trigger level
937 Call: sSetRxProcessor(ChP,Level)
938 CHANNEL_T *ChP; Ptr to channel structure
939 Byte_t Level; Number of characters in Rx FIFO at which the
940 interrupt will be generated. Can be any of the following flags:
943 TRIG_1: 1 character in FIFO
944 TRIG_1_2: FIFO 1/2 full
945 TRIG_7_8: FIFO 7/8 full
946 Comments: An interrupt will be generated when the trigger level is reached
947 only if function sEnInterrupt() has been called with flag
948 RXINT_EN set. The RXF_TRIG flag in the Interrupt Idenfification
949 register will be set whenever the trigger level is reached
950 regardless of the setting of RXINT_EN.
953 #define sSetRxTrigger(ChP,LEVEL) \
955 (ChP)->RxControl[2] &= ~TRIG_MASK; \
956 (ChP)->RxControl[2] |= LEVEL; \
957 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->RxControl[0]); \
960 /***************************************************************************
962 Purpose: Set stop bits to 1
964 CHANNEL_T *ChP; Ptr to channel structure
966 #define sSetStop1(ChP) \
968 (ChP)->TxControl[2] &= ~STOP2; \
969 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
972 /***************************************************************************
974 Purpose: Set stop bits to 2
976 CHANNEL_T *ChP; Ptr to channel structure
978 #define sSetStop2(ChP) \
980 (ChP)->TxControl[2] |= STOP2; \
981 sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->TxControl[0]); \
984 /***************************************************************************
985 Function: sStartRxProcessor
986 Purpose: Start a channel's receive processor
987 Call: sStartRxProcessor(ChP)
988 CHANNEL_T *ChP; Ptr to channel structure
989 Comments: This function is used to start a Rx processor after it was
990 stopped with sStopRxProcessor() or sStopSWInFlowCtl(). It
991 will restart both the Rx processor and software input flow control.
994 #define sStartRxProcessor(ChP) sOutDW((ChP)->IndexAddr,*(DWord_t *)&(ChP)->R[0])
996 /***************************************************************************
997 Function: sWriteTxByte
998 Purpose: Write a transmit data byte to a channel.
999 ByteIO_t io: Channel transmit register I/O address. This can
1000 be obtained with sGetTxRxDataIO().
1001 Byte_t Data; The transmit data byte.
1002 Warnings: This function writes the data byte without checking to see if
1003 sMaxTxSize is exceeded in the Tx FIFO.
1005 #define sWriteTxByte(IO,DATA) sOutB(IO,DATA)
1007 int sInitController( CONTROLLER_T *CtlP,
1010 ByteIO_t *AiopIOList,
1016 int sPCIInitController( CONTROLLER_T *CtlP,
1018 ByteIO_t *AiopIOList,
1024 int sReadAiopID(ByteIO_t io);
1025 int sReadAiopNumChan(WordIO_t io);
1026 int sInitChan( CONTROLLER_T *CtlP,
1030 Byte_t sGetRxErrStatus(CHANNEL_T *ChP);
1031 void sStopRxProcessor(CHANNEL_T *ChP);
1032 void sStopSWInFlowCtl(CHANNEL_T *ChP);
1033 void sFlushRxFIFO(CHANNEL_T *ChP);
1034 void sFlushTxFIFO(CHANNEL_T *ChP);
1035 int sWriteTxPrioByte(CHANNEL_T *ChP, Byte_t Data);
1036 void sEnInterrupts(CHANNEL_T *ChP,Word_t Flags);
1037 void sDisInterrupts(CHANNEL_T *ChP,Word_t Flags);
1040 extern Byte_t R[RDATASIZE];
1041 extern CONTROLLER_T sController[CTL_SIZE];
1042 extern Byte_t sIRQMap[16];
1043 extern Byte_t sBitMapClrTbl[8];
1044 extern Byte_t sBitMapSetTbl[8];