sys/i386/isa/clock.c

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * This code is derived from software contributed to Berkeley by
   6  * William Jolitz and Don Ahn.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by the University of
  19  *      California, Berkeley and its contributors.
  20  * 4. Neither the name of the University nor the names of its contributors
  21  *    may be used to endorse or promote products derived from this software
  22  *    without specific prior written permission.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
  37  * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
  38  */
  39
  40 /*
  41  * Routines to handle clock hardware.
  42  */
  43
  44 /*
  45  * inittodr, settodr and support routines written
  46  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
  47  *
  48  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
  49  */
  50
  51 #include "opt_clock.h"
  52 #include "apm.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/systm.h>
  56 #include <sys/time.h>
  57 #include <sys/kernel.h>
  58 #ifndef SMP
  59 #include <sys/lock.h>
  60 #endif
  61 #include <sys/sysctl.h>
  62 #include <sys/cons.h>
  63
  64 #include <machine/clock.h>
  65 #ifdef CLK_CALIBRATION_LOOP
  66 #endif
  67 #include <machine/cputypes.h>
  68 #include <machine/frame.h>
  69 #include <machine/ipl.h>
  70 #include <machine/limits.h>
  71 #include <machine/md_var.h>
  72 #include <machine/psl.h>
  73 #ifdef APIC_IO
  74 #include <machine/segments.h>
  75 #endif
  76 #if defined(SMP) || defined(APIC_IO)
  77 #include <machine/smp.h>
  78 #endif /* SMP || APIC_IO */
  79 #include <machine/specialreg.h>
  80
  81 #include <i386/isa/icu.h>
  82 #include <i386/isa/isa.h>
  83 #include <isa/rtc.h>
  84 #include <i386/isa/timerreg.h>
  85
  86 #include <i386/isa/intr_machdep.h>
  87
  88 #include "mca.h"
  89 #if NMCA > 0
  90 #include <i386/isa/mca_machdep.h>
  91 #endif
  92
  93 #ifdef SMP
  94 #define disable_intr()  CLOCK_DISABLE_INTR()
  95 #define enable_intr()   CLOCK_ENABLE_INTR()
  96
  97 #ifdef APIC_IO
  98 #include <i386/isa/intr_machdep.h>
  99 /* The interrupt triggered by the 8254 (timer) chip */
 100 int apic_8254_intr;
 101 static u_long read_intr_count __P((int vec));
 102 static void setup_8254_mixed_mode __P((void));
 103 #endif
 104 #endif /* SMP */
 105
 106 /*
 107  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
 108  * can use a simple formula for leap years.
 109  */
 110 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
 111 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
 112
 113 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
 114
 115 /*
 116  * Time in timer cycles that it takes for microtime() to disable interrupts
 117  * and latch the count.  microtime() currently uses "cli; outb ..." so it
 118  * normally takes less than 2 timer cycles.  Add a few for cache misses.
 119  * Add a few more to allow for latency in bogus calls to microtime() with
 120  * interrupts already disabled.
 121  */
 122 #define TIMER0_LATCH_COUNT      20
 123
 124 /*
 125  * Maximum frequency that we are willing to allow for timer0.  Must be
 126  * low enough to guarantee that the timer interrupt handler returns
 127  * before the next timer interrupt.
 128  */
 129 #define TIMER0_MAX_FREQ         20000
 130
 131 int     adjkerntz;              /* local offset from GMT in seconds */
 132 int     clkintr_pending;
 133 int     disable_rtc_set;        /* disable resettodr() if != 0 */
 134 volatile u_int  idelayed;
 135 int     statclock_disable;
 136 u_int   stat_imask = SWI_CLOCK_MASK;
 137 #ifndef TIMER_FREQ
 138 #define TIMER_FREQ   1193182
 139 #endif
 140 u_int   timer_freq = TIMER_FREQ;
 141 int     timer0_max_count;
 142 u_int   tsc_freq;
 143 int     tsc_is_broken;
 144 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
 145
 146 static  int     beeping = 0;
 147 static  u_int   clk_imask = HWI_MASK | SWI_MASK;
 148 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
 149 static  u_int   hardclock_max_count;
 150 static  u_int32_t i8254_lastcount;
 151 static  u_int32_t i8254_offset;
 152 static  int     i8254_ticked;
 153 /*
 154  * XXX new_function and timer_func should not handle clockframes, but
 155  * timer_func currently needs to hold hardclock to handle the
 156  * timer0_state == 0 case.  We should use inthand_add()/inthand_remove()
 157  * to switch between clkintr() and a slightly different timerintr().
 158  */
 159 static  void    (*new_function) __P((struct clockframe *frame));
 160 static  u_int   new_rate;
 161 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
 162 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
 163 static  u_int   timer0_prescaler_count;
 164
 165 /* Values for timerX_state: */
 166 #define RELEASED        0
 167 #define RELEASE_PENDING 1
 168 #define ACQUIRED        2
 169 #define ACQUIRE_PENDING 3
 170
 171 static  u_char  timer0_state;
 172 static  u_char  timer2_state;
 173 static  void    (*timer_func) __P((struct clockframe *frame)) = hardclock;
 174 static  u_int   tsc_present;
 175
 176 static  unsigned i8254_get_timecount __P((struct timecounter *tc));
 177 static  unsigned tsc_get_timecount __P((struct timecounter *tc));
 178 static  void    set_timer_freq(u_int freq, int intr_freq);
 179
 180 static struct timecounter tsc_timecounter = {
 181         tsc_get_timecount,      /* get_timecount */
 182         0,                      /* no poll_pps */
 183         ~0u,                    /* counter_mask */
 184         0,                      /* frequency */
 185          "TSC"                  /* name */
 186 };
 187
 188 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
 189         &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
 190
 191 static struct timecounter i8254_timecounter = {
 192         i8254_get_timecount,    /* get_timecount */
 193         0,                      /* no poll_pps */
 194         ~0u,                    /* counter_mask */
 195         0,                      /* frequency */
 196         "i8254"                 /* name */
 197 };
 198
 199 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
 200         &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
 201
 202 static void
 203 clkintr(struct clockframe frame)
 204 {
 205         if (timecounter->tc_get_timecount == i8254_get_timecount) {
 206                 disable_intr();
 207                 if (i8254_ticked)
 208                         i8254_ticked = 0;
 209                 else {
 210                         i8254_offset += timer0_max_count;
 211                         i8254_lastcount = 0;
 212                 }
 213                 clkintr_pending = 0;
 214                 enable_intr();
 215         }
 216         timer_func(&frame);
 217         switch (timer0_state) {
 218
 219         case RELEASED:
 220                 setdelayed();
 221                 break;
 222
 223         case ACQUIRED:
 224                 if ((timer0_prescaler_count += timer0_max_count)
 225                     >= hardclock_max_count) {
 226                         timer0_prescaler_count -= hardclock_max_count;
 227                         hardclock(&frame);
 228                         setdelayed();
 229                 }
 230                 break;
 231
 232         case ACQUIRE_PENDING:
 233                 disable_intr();
 234                 i8254_offset = i8254_get_timecount(NULL);
 235                 i8254_lastcount = 0;
 236                 timer0_max_count = TIMER_DIV(new_rate);
 237                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 238                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
 239                 outb(TIMER_CNTR0, timer0_max_count >> 8);
 240                 enable_intr();
 241                 timer_func = new_function;
 242                 timer0_state = ACQUIRED;
 243                 setdelayed();
 244                 break;
 245
 246         case RELEASE_PENDING:
 247                 if ((timer0_prescaler_count += timer0_max_count)
 248                     >= hardclock_max_count) {
 249                         disable_intr();
 250                         i8254_offset = i8254_get_timecount(NULL);
 251                         i8254_lastcount = 0;
 252                         timer0_max_count = hardclock_max_count;
 253                         outb(TIMER_MODE,
 254                              TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 255                         outb(TIMER_CNTR0, timer0_max_count & 0xff);
 256                         outb(TIMER_CNTR0, timer0_max_count >> 8);
 257                         enable_intr();
 258                         timer0_prescaler_count = 0;
 259                         timer_func = hardclock;
 260                         timer0_state = RELEASED;
 261                         hardclock(&frame);
 262                         setdelayed();
 263                 }
 264                 break;
 265         }
 266 #if NMCA > 0
 267         /* Reset clock interrupt by asserting bit 7 of port 0x61 */
 268         if (MCA_system)
 269                 outb(0x61, inb(0x61) | 0x80);
 270 #endif
 271 }
 272
 273 /*
 274  * The acquire and release functions must be called at ipl >= splclock().
 275  */
 276 int
 277 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame)))
 278 {
 279         static int old_rate;
 280
 281         if (rate <= 0 || rate > TIMER0_MAX_FREQ)
 282                 return (-1);
 283         switch (timer0_state) {
 284
 285         case RELEASED:
 286                 timer0_state = ACQUIRE_PENDING;
 287                 break;
 288
 289         case RELEASE_PENDING:
 290                 if (rate != old_rate)
 291                         return (-1);
 292                 /*
 293                  * The timer has been released recently, but is being
 294                  * re-acquired before the release completed.  In this
 295                  * case, we simply reclaim it as if it had not been
 296                  * released at all.
 297                  */
 298                 timer0_state = ACQUIRED;
 299                 break;
 300
 301         default:
 302                 return (-1);    /* busy */
 303         }
 304         new_function = function;
 305         old_rate = new_rate = rate;
 306         return (0);
 307 }
 308
 309 int
 310 acquire_timer2(int mode)
 311 {
 312
 313         if (timer2_state != RELEASED)
 314                 return (-1);
 315         timer2_state = ACQUIRED;
 316
 317         /*
 318          * This access to the timer registers is as atomic as possible
 319          * because it is a single instruction.  We could do better if we
 320          * knew the rate.  Use of splclock() limits glitches to 10-100us,
 321          * and this is probably good enough for timer2, so we aren't as
 322          * careful with it as with timer0.
 323          */
 324         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
 325
 326         return (0);
 327 }
 328
 329 int
 330 release_timer0()
 331 {
 332         switch (timer0_state) {
 333
 334         case ACQUIRED:
 335                 timer0_state = RELEASE_PENDING;
 336                 break;
 337
 338         case ACQUIRE_PENDING:
 339                 /* Nothing happened yet, release quickly. */
 340                 timer0_state = RELEASED;
 341                 break;
 342
 343         default:
 344                 return (-1);
 345         }
 346         return (0);
 347 }
 348
 349 int
 350 release_timer2()
 351 {
 352
 353         if (timer2_state != ACQUIRED)
 354                 return (-1);
 355         timer2_state = RELEASED;
 356         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
 357         return (0);
 358 }
 359
 360 /*
 361  * This routine receives statistical clock interrupts from the RTC.
 362  * As explained above, these occur at 128 interrupts per second.
 363  * When profiling, we receive interrupts at a rate of 1024 Hz.
 364  *
 365  * This does not actually add as much overhead as it sounds, because
 366  * when the statistical clock is active, the hardclock driver no longer
 367  * needs to keep (inaccurate) statistics on its own.  This decouples
 368  * statistics gathering from scheduling interrupts.
 369  *
 370  * The RTC chip requires that we read status register C (RTC_INTR)
 371  * to acknowledge an interrupt, before it will generate the next one.
 372  * Under high interrupt load, rtcintr() can be indefinitely delayed and
 373  * the clock can tick immediately after the read from RTC_INTR.  In this
 374  * case, the mc146818A interrupt signal will not drop for long enough
 375  * to register with the 8259 PIC.  If an interrupt is missed, the stat
 376  * clock will halt, considerably degrading system performance.  This is
 377  * why we use 'while' rather than a more straightforward 'if' below.
 378  * Stat clock ticks can still be lost, causing minor loss of accuracy
 379  * in the statistics, but the stat clock will no longer stop.
 380  */
 381 static void
 382 rtcintr(struct clockframe frame)
 383 {
 384         while (rtcin(RTC_INTR) & RTCIR_PERIOD)
 385                 statclock(&frame);
 386 }
 387
 388 #include "opt_ddb.h"
 389 #ifdef DDB
 390 #include <ddb/ddb.h>
 391
 392 DB_SHOW_COMMAND(rtc, rtc)
 393 {
 394         printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
 395                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
 396                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
 397                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
 398 }
 399 #endif /* DDB */
 400
 401 static int
 402 getit(void)
 403 {
 404         u_long ef;
 405         int high, low;
 406
 407         ef = read_eflags();
 408         disable_intr();
 409
 410         /* Select timer0 and latch counter value. */
 411         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
 412
 413         low = inb(TIMER_CNTR0);
 414         high = inb(TIMER_CNTR0);
 415
 416         CLOCK_UNLOCK();
 417         write_eflags(ef);
 418         return ((high << 8) | low);
 419 }
 420
 421 /*
 422  * Wait "n" microseconds.
 423  * Relies on timer 1 counting down from (timer_freq / hz)
 424  * Note: timer had better have been programmed before this is first used!
 425  */
 426 void
 427 DELAY(int n)
 428 {
 429         int delta, prev_tick, tick, ticks_left;
 430
 431 #ifdef DELAYDEBUG
 432         int getit_calls = 1;
 433         int n1;
 434         static int state = 0;
 435
 436         if (state == 0) {
 437                 state = 1;
 438                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
 439                         DELAY(n1);
 440                 state = 2;
 441         }
 442         if (state == 1)
 443                 printf("DELAY(%d)...", n);
 444 #endif
 445         /*
 446          * Guard against the timer being uninitialized if we are called
 447          * early for console i/o.
 448          */
 449         if (timer0_max_count == 0)
 450                 set_timer_freq(timer_freq, hz);
 451
 452         /*
 453          * Read the counter first, so that the rest of the setup overhead is
 454          * counted.  Guess the initial overhead is 20 usec (on most systems it
 455          * takes about 1.5 usec for each of the i/o's in getit().  The loop
 456          * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
 457          * multiplications and divisions to scale the count take a while).
 458          */
 459         prev_tick = getit();
 460         n -= 0;                 /* XXX actually guess no initial overhead */
 461         /*
 462          * Calculate (n * (timer_freq / 1e6)) without using floating point
 463          * and without any avoidable overflows.
 464          */
 465         if (n <= 0)
 466                 ticks_left = 0;
 467         else if (n < 256)
 468                 /*
 469                  * Use fixed point to avoid a slow division by 1000000.
 470                  * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
 471                  * 2^15 is the first power of 2 that gives exact results
 472                  * for n between 0 and 256.
 473                  */
 474                 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
 475         else
 476                 /*
 477                  * Don't bother using fixed point, although gcc-2.7.2
 478                  * generates particularly poor code for the long long
 479                  * division, since even the slow way will complete long
 480                  * before the delay is up (unless we're interrupted).
 481                  */
 482                 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
 483                              / 1000000;
 484
 485         while (ticks_left > 0) {
 486                 tick = getit();
 487 #ifdef DELAYDEBUG
 488                 ++getit_calls;
 489 #endif
 490                 delta = prev_tick - tick;
 491                 prev_tick = tick;
 492                 if (delta < 0) {
 493                         delta += timer0_max_count;
 494                         /*
 495                          * Guard against timer0_max_count being wrong.
 496                          * This shouldn't happen in normal operation,
 497                          * but it may happen if set_timer_freq() is
 498                          * traced.
 499                          */
 500                         if (delta < 0)
 501                                 delta = 0;
 502                 }
 503                 ticks_left -= delta;
 504         }
 505 #ifdef DELAYDEBUG
 506         if (state == 1)
 507                 printf(" %d calls to getit() at %d usec each\n",
 508                        getit_calls, (n + 5) / getit_calls);
 509 #endif
 510 }
 511
 512 static void
 513 sysbeepstop(void *chan)
 514 {
 515         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
 516         release_timer2();
 517         beeping = 0;
 518 }
 519
 520 int
 521 sysbeep(int pitch, int period)
 522 {
 523         int x = splclock();
 524
 525         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
 526                 if (!beeping) {
 527                         /* Something else owns it. */
 528                         splx(x);
 529                         return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
 530                 }
 531         disable_intr();
 532         outb(TIMER_CNTR2, pitch);
 533         outb(TIMER_CNTR2, (pitch>>8));
 534         enable_intr();
 535         if (!beeping) {
 536                 /* enable counter2 output to speaker */
 537                 outb(IO_PPI, inb(IO_PPI) | 3);
 538                 beeping = period;
 539                 timeout(sysbeepstop, (void *)NULL, period);
 540         }
 541         splx(x);
 542         return (0);
 543 }
 544
 545 /*
 546  * RTC support routines
 547  */
 548
 549 int
 550 rtcin(reg)
 551         int reg;
 552 {
 553         int s;
 554         u_char val;
 555
 556         s = splhigh();
 557         outb(IO_RTC, reg);
 558         inb(0x84);
 559         val = inb(IO_RTC + 1);
 560         inb(0x84);
 561         splx(s);
 562         return (val);
 563 }
 564
 565 static __inline void
 566 writertc(u_char reg, u_char val)
 567 {
 568         int s;
 569
 570         s = splhigh();
 571         inb(0x84);
 572         outb(IO_RTC, reg);
 573         inb(0x84);
 574         outb(IO_RTC + 1, val);
 575         inb(0x84);              /* XXX work around wrong order in rtcin() */
 576         splx(s);
 577 }
 578
 579 static __inline int
 580 readrtc(int port)
 581 {
 582         return(bcd2bin(rtcin(port)));
 583 }
 584
 585 static u_int
 586 calibrate_clocks(void)
 587 {
 588         u_int64_t old_tsc;
 589         u_int count, prev_count, tot_count;
 590         int sec, start_sec, timeout;
 591
 592         if (bootverbose)
 593                 printf("Calibrating clock(s) ... ");
 594         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 595                 goto fail;
 596         timeout = 100000000;
 597
 598         /* Read the mc146818A seconds counter. */
 599         for (;;) {
 600                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 601                         sec = rtcin(RTC_SEC);
 602                         break;
 603                 }
 604                 if (--timeout == 0)
 605                         goto fail;
 606         }
 607
 608         /* Wait for the mC146818A seconds counter to change. */
 609         start_sec = sec;
 610         for (;;) {
 611                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 612                         sec = rtcin(RTC_SEC);
 613                         if (sec != start_sec)
 614                                 break;
 615                 }
 616                 if (--timeout == 0)
 617                         goto fail;
 618         }
 619
 620         /* Start keeping track of the i8254 counter. */
 621         prev_count = getit();
 622         if (prev_count == 0 || prev_count > timer0_max_count)
 623                 goto fail;
 624         tot_count = 0;
 625
 626         if (tsc_present)
 627                 old_tsc = rdtsc();
 628         else
 629                 old_tsc = 0;            /* shut up gcc */
 630
 631         /*
 632          * Wait for the mc146818A seconds counter to change.  Read the i8254
 633          * counter for each iteration since this is convenient and only
 634          * costs a few usec of inaccuracy. The timing of the final reads
 635          * of the counters almost matches the timing of the initial reads,
 636          * so the main cause of inaccuracy is the varying latency from
 637          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
 638          * rtcin(RTC_SEC) that returns a changed seconds count.  The
 639          * maximum inaccuracy from this cause is < 10 usec on 486's.
 640          */
 641         start_sec = sec;
 642         for (;;) {
 643                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
 644                         sec = rtcin(RTC_SEC);
 645                 count = getit();
 646                 if (count == 0 || count > timer0_max_count)
 647                         goto fail;
 648                 if (count > prev_count)
 649                         tot_count += prev_count - (count - timer0_max_count);
 650                 else
 651                         tot_count += prev_count - count;
 652                 prev_count = count;
 653                 if (sec != start_sec)
 654                         break;
 655                 if (--timeout == 0)
 656                         goto fail;
 657         }
 658
 659         /*
 660          * Read the cpu cycle counter.  The timing considerations are
 661          * similar to those for the i8254 clock.
 662          */
 663         if (tsc_present)
 664                 tsc_freq = rdtsc() - old_tsc;
 665
 666         if (bootverbose) {
 667                 if (tsc_present)
 668                         printf("TSC clock: %u Hz, ", tsc_freq);
 669                 printf("i8254 clock: %u Hz\n", tot_count);
 670         }
 671         return (tot_count);
 672
 673 fail:
 674         if (bootverbose)
 675                 printf("failed, using default i8254 clock of %u Hz\n",
 676                        timer_freq);
 677         return (timer_freq);
 678 }
 679
 680 static void
 681 set_timer_freq(u_int freq, int intr_freq)
 682 {
 683         u_long ef;
 684         int new_timer0_max_count;
 685
 686         ef = read_eflags();
 687         disable_intr();
 688         timer_freq = freq;
 689         new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
 690         if (new_timer0_max_count != timer0_max_count) {
 691                 timer0_max_count = new_timer0_max_count;
 692                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 693                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
 694                 outb(TIMER_CNTR0, timer0_max_count >> 8);
 695         }
 696         CLOCK_UNLOCK();
 697         write_eflags(ef);
 698 }
 699
 700 static void
 701 i8254_restore(void)
 702 {
 703         u_long ef;
 704
 705         ef = read_eflags();
 706         disable_intr();
 707         outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
 708         outb(TIMER_CNTR0, timer0_max_count & 0xff);
 709         outb(TIMER_CNTR0, timer0_max_count >> 8);
 710         CLOCK_UNLOCK();
 711         write_eflags(ef);
 712 }
 713
 714 static void
 715 rtc_restore(void)
 716 {
 717
 718         /* Restore all of the RTC's "status" (actually, control) registers. */
 719         writertc(RTC_STATUSB, RTCSB_24HR);
 720         writertc(RTC_STATUSA, rtc_statusa);
 721         writertc(RTC_STATUSB, rtc_statusb);
 722 }
 723
 724 /*
 725  * Restore all the timers non-atomically (XXX: should be atomically).
 726  *
 727  * This function is called from apm_default_resume() to restore all the timers.
 728  * This should not be necessary, but there are broken laptops that do not
 729  * restore all the timers on resume.
 730  */
 731 void
 732 timer_restore(void)
 733 {
 734
 735         i8254_restore();                /* restore timer_freq and hz */
 736         rtc_restore();                  /* reenable RTC interrupts */
 737 }
 738
 739 /*
 740  * Initialize 8254 timer 0 early so that it can be used in DELAY().
 741  * XXX initialization of other timers is unintentionally left blank.
 742  */
 743 void
 744 startrtclock()
 745 {
 746         u_int delta, freq;
 747
 748         if (cpu_feature & CPUID_TSC)
 749                 tsc_present = 1;
 750         else
 751                 tsc_present = 0;
 752
 753         writertc(RTC_STATUSA, rtc_statusa);
 754         writertc(RTC_STATUSB, RTCSB_24HR);
 755
 756         set_timer_freq(timer_freq, hz);
 757         freq = calibrate_clocks();
 758 #ifdef CLK_CALIBRATION_LOOP
 759         if (bootverbose) {
 760                 printf(
 761                 "Press a key on the console to abort clock calibration\n");
 762                 while (cncheckc() == -1)
 763                         calibrate_clocks();
 764         }
 765 #endif
 766
 767         /*
 768          * Use the calibrated i8254 frequency if it seems reasonable.
 769          * Otherwise use the default, and don't use the calibrated i586
 770          * frequency.
 771          */
 772         delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
 773         if (delta < timer_freq / 100) {
 774 #ifndef CLK_USE_I8254_CALIBRATION
 775                 if (bootverbose)
 776                         printf(
 777 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
 778                 freq = timer_freq;
 779 #endif
 780                 timer_freq = freq;
 781         } else {
 782                 if (bootverbose)
 783                         printf(
 784                     "%d Hz differs from default of %d Hz by more than 1%%\n",
 785                                freq, timer_freq);
 786                 tsc_freq = 0;
 787         }
 788
 789         set_timer_freq(timer_freq, hz);
 790         i8254_timecounter.tc_frequency = timer_freq;
 791         init_timecounter(&i8254_timecounter);
 792
 793 #ifndef CLK_USE_TSC_CALIBRATION
 794         if (tsc_freq != 0) {
 795                 if (bootverbose)
 796                         printf(
 797 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
 798                 tsc_freq = 0;
 799         }
 800 #endif
 801         if (tsc_present && tsc_freq == 0) {
 802                 /*
 803                  * Calibration of the i586 clock relative to the mc146818A
 804                  * clock failed.  Do a less accurate calibration relative
 805                  * to the i8254 clock.
 806                  */
 807                 u_int64_t old_tsc = rdtsc();
 808
 809                 DELAY(1000000);
 810                 tsc_freq = rdtsc() - old_tsc;
 811 #ifdef CLK_USE_TSC_CALIBRATION
 812                 if (bootverbose)
 813                         printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
 814 #endif
 815         }
 816
 817 #if !defined(SMP)
 818         /*
 819          * We can not use the TSC in SMP mode, until we figure out a
 820          * cheap (impossible), reliable and precise (yeah right!)  way
 821          * to synchronize the TSCs of all the CPUs.
 822          * Curse Intel for leaving the counter out of the I/O APIC.
 823          */
 824
 825 #if NAPM > 0
 826         /*
 827          * We can not use the TSC if we support APM. Precise timekeeping
 828          * on an APM'ed machine is at best a fools pursuit, since
 829          * any and all of the time spent in various SMM code can't
 830          * be reliably accounted for.  Reading the RTC is your only
 831          * source of reliable time info.  The i8254 looses too of course
 832          * but we need to have some kind of time...
 833          * We don't know at this point whether APM is going to be used
 834          * or not, nor when it might be activated.  Play it safe.
 835          */
 836         return;
 837 #endif /* NAPM > 0 */
 838
 839         if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
 840                 tsc_timecounter.tc_frequency = tsc_freq;
 841                 init_timecounter(&tsc_timecounter);
 842         }
 843
 844 #endif /* !defined(SMP) */
 845 }
 846
 847 /*
 848  * Initialize the time of day register, based on the time base which is, e.g.
 849  * from a filesystem.
 850  */
 851 void
 852 inittodr(time_t base)
 853 {
 854         unsigned long   sec, days;
 855         int             yd;
 856         int             year, month;
 857         int             y, m, s;
 858         struct timespec ts;
 859
 860         if (base) {
 861                 s = splclock();
 862                 ts.tv_sec = base;
 863                 ts.tv_nsec = 0;
 864                 set_timecounter(&ts);
 865                 splx(s);
 866         }
 867
 868         /* Look if we have a RTC present and the time is valid */
 869         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 870                 goto wrong_time;
 871
 872         /* wait for time update to complete */
 873         /* If RTCSA_TUP is zero, we have at least 244us before next update */
 874         s = splhigh();
 875         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
 876                 splx(s);
 877                 s = splhigh();
 878         }
 879
 880         days = 0;
 881 #ifdef USE_RTC_CENTURY
 882         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
 883 #else
 884         year = readrtc(RTC_YEAR) + 1900;
 885         if (year < 1970)
 886                 year += 100;
 887 #endif
 888         if (year < 1970) {
 889                 splx(s);
 890                 goto wrong_time;
 891         }
 892         month = readrtc(RTC_MONTH);
 893         for (m = 1; m < month; m++)
 894                 days += daysinmonth[m-1];
 895         if ((month > 2) && LEAPYEAR(year))
 896                 days ++;
 897         days += readrtc(RTC_DAY) - 1;
 898         yd = days;
 899         for (y = 1970; y < year; y++)
 900                 days += DAYSPERYEAR + LEAPYEAR(y);
 901         sec = ((( days * 24 +
 902                   readrtc(RTC_HRS)) * 60 +
 903                   readrtc(RTC_MIN)) * 60 +
 904                   readrtc(RTC_SEC));
 905         /* sec now contains the number of seconds, since Jan 1 1970,
 906            in the local time zone */
 907
 908         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 909
 910         y = time_second - sec;
 911         if (y <= -2 || y >= 2) {
 912                 /* badly off, adjust it */
 913                 ts.tv_sec = sec;
 914                 ts.tv_nsec = 0;
 915                 set_timecounter(&ts);
 916         }
 917         splx(s);
 918         return;
 919
 920 wrong_time:
 921         printf("Invalid time in real time clock.\n");
 922         printf("Check and reset the date immediately!\n");
 923 }
 924
 925 /*
 926  * Write system time back to RTC
 927  */
 928 void
 929 resettodr()
 930 {
 931         unsigned long   tm;
 932         int             y, m, s;
 933
 934         if (disable_rtc_set)
 935                 return;
 936
 937         s = splclock();
 938         tm = time_second;
 939         splx(s);
 940
 941         /* Disable RTC updates and interrupts. */
 942         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
 943
 944         /* Calculate local time to put in RTC */
 945
 946         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 947
 948         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
 949         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
 950         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
 951
 952         /* We have now the days since 01-01-1970 in tm */
 953         writertc(RTC_WDAY, (tm+4)%7);                   /* Write back Weekday */
 954         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
 955              tm >= m;
 956              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
 957              tm -= m;
 958
 959         /* Now we have the years in y and the day-of-the-year in tm */
 960         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
 961 #ifdef USE_RTC_CENTURY
 962         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
 963 #endif
 964         for (m = 0; ; m++) {
 965                 int ml;
 966
 967                 ml = daysinmonth[m];
 968                 if (m == 1 && LEAPYEAR(y))
 969                         ml++;
 970                 if (tm < ml)
 971                         break;
 972                 tm -= ml;
 973         }
 974
 975         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
 976         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
 977
 978         /* Reenable RTC updates and interrupts. */
 979         writertc(RTC_STATUSB, rtc_statusb);
 980 }
 981
 982
 983 /*
 984  * Start both clocks running.
 985  */
 986 void
 987 cpu_initclocks()
 988 {
 989         int diag;
 990 #ifdef APIC_IO
 991         int apic_8254_trial;
 992         struct intrec *clkdesc;
 993 #endif /* APIC_IO */
 994
 995         if (statclock_disable) {
 996                 /*
 997                  * The stat interrupt mask is different without the
 998                  * statistics clock.  Also, don't set the interrupt
 999                  * flag which would normally cause the RTC to generate
1000                  * interrupts.
1001                  */
1002                 stat_imask = HWI_MASK | SWI_MASK;
1003                 rtc_statusb = RTCSB_24HR;
1004         } else {
1005                 /* Setting stathz to nonzero early helps avoid races. */
1006                 stathz = RTC_NOPROFRATE;
1007                 profhz = RTC_PROFRATE;
1008         }
1009
1010         /* Finish initializing 8253 timer 0. */
1011 #ifdef APIC_IO
1012
1013         apic_8254_intr = isa_apic_irq(0);
1014         apic_8254_trial = 0;
1015         if (apic_8254_intr >= 0 ) {
1016                 if (apic_int_type(0, 0) == 3)
1017                         apic_8254_trial = 1;
1018         } else {
1019                 /* look for ExtInt on pin 0 */
1020                 if (apic_int_type(0, 0) == 3) {
1021                         apic_8254_intr = apic_irq(0, 0);
1022                         setup_8254_mixed_mode();
1023                 } else
1024                         panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1025         }
1026
1027         clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
1028                               NULL, &clk_imask, INTR_EXCL);
1029         INTREN(1 << apic_8254_intr);
1030
1031 #else /* APIC_IO */
1032
1033         inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
1034                     INTR_EXCL);
1035         INTREN(IRQ0);
1036
1037 #endif /* APIC_IO */
1038
1039         /* Initialize RTC. */
1040         writertc(RTC_STATUSA, rtc_statusa);
1041         writertc(RTC_STATUSB, RTCSB_24HR);
1042
1043         /* Don't bother enabling the statistics clock. */
1044         if (statclock_disable)
1045                 return;
1046         diag = rtcin(RTC_DIAG);
1047         if (diag != 0)
1048                 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1049
1050 #ifdef APIC_IO
1051         if (isa_apic_irq(8) != 8)
1052                 panic("APIC RTC != 8");
1053 #endif /* APIC_IO */
1054
1055         inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
1056                     INTR_EXCL);
1057
1058 #ifdef APIC_IO
1059         INTREN(APIC_IRQ8);
1060 #else
1061         INTREN(IRQ8);
1062 #endif /* APIC_IO */
1063
1064         writertc(RTC_STATUSB, rtc_statusb);
1065
1066 #ifdef APIC_IO
1067         if (apic_8254_trial) {
1068
1069                 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1070                 while (read_intr_count(8) < 6)
1071                         ;       /* nothing */
1072                 if (read_intr_count(apic_8254_intr) < 3) {
1073                         /*
1074                          * The MP table is broken.
1075                          * The 8254 was not connected to the specified pin
1076                          * on the IO APIC.
1077                          * Workaround: Limited variant of mixed mode.
1078                          */
1079                         INTRDIS(1 << apic_8254_intr);
1080                         inthand_remove(clkdesc);
1081                         printf("APIC_IO: Broken MP table detected: "
1082                                "8254 is not connected to "
1083                                "IOAPIC #%d intpin %d\n",
1084                                int_to_apicintpin[apic_8254_intr].ioapic,
1085                                int_to_apicintpin[apic_8254_intr].int_pin);
1086                         /*
1087                          * Revoke current ISA IRQ 0 assignment and
1088                          * configure a fallback interrupt routing from
1089                          * the 8254 Timer via the 8259 PIC to the
1090                          * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1091                          * We reuse the low level interrupt handler number.
1092                          */
1093                         if (apic_irq(0, 0) < 0) {
1094                                 revoke_apic_irq(apic_8254_intr);
1095                                 assign_apic_irq(0, 0, apic_8254_intr);
1096                         }
1097                         apic_8254_intr = apic_irq(0, 0);
1098                         setup_8254_mixed_mode();
1099                         inthand_add("clk", apic_8254_intr,
1100                                     (inthand2_t *)clkintr,
1101                                     NULL, &clk_imask, INTR_EXCL);
1102                         INTREN(1 << apic_8254_intr);
1103                 }
1104
1105         }
1106         if (apic_int_type(0, 0) != 3 ||
1107             int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1108             int_to_apicintpin[apic_8254_intr].int_pin != 0)
1109                 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1110                        int_to_apicintpin[apic_8254_intr].ioapic,
1111                        int_to_apicintpin[apic_8254_intr].int_pin);
1112         else
1113                 printf("APIC_IO: "
1114                        "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1115 #endif
1116
1117 }
1118
1119 #ifdef APIC_IO
1120 static u_long
1121 read_intr_count(int vec)
1122 {
1123         u_long *up;
1124         up = intr_countp[vec];
1125         if (up)
1126                 return *up;
1127         return 0UL;
1128 }
1129
1130 static void
1131 setup_8254_mixed_mode()
1132 {
1133         /*
1134          * Allow 8254 timer to INTerrupt 8259:
1135          *  re-initialize master 8259:
1136          *   reset; prog 4 bytes, single ICU, edge triggered
1137          */
1138         outb(IO_ICU1, 0x13);
1139         outb(IO_ICU1 + 1, NRSVIDT);     /* start vector (unused) */
1140         outb(IO_ICU1 + 1, 0x00);        /* ignore slave */
1141         outb(IO_ICU1 + 1, 0x03);        /* auto EOI, 8086 */
1142         outb(IO_ICU1 + 1, 0xfe);        /* unmask INT0 */
1143
1144         /* program IO APIC for type 3 INT on INT0 */
1145         if (ext_int_setup(0, 0) < 0)
1146                 panic("8254 redirect via APIC pin0 impossible!");
1147 }
1148 #endif
1149
1150 void
1151 setstatclockrate(int newhz)
1152 {
1153         if (newhz == RTC_PROFRATE)
1154                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1155         else
1156                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1157         writertc(RTC_STATUSA, rtc_statusa);
1158 }
1159
1160 static int
1161 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1162 {
1163         int error;
1164         u_int freq;
1165
1166         /*
1167          * Use `i8254' instead of `timer' in external names because `timer'
1168          * is is too generic.  Should use it everywhere.
1169          */
1170         freq = timer_freq;
1171         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1172         if (error == 0 && req->newptr != NULL) {
1173                 if (timer0_state != RELEASED)
1174                         return (EBUSY); /* too much trouble to handle */
1175                 set_timer_freq(freq, hz);
1176                 i8254_timecounter.tc_frequency = freq;
1177                 update_timecounter(&i8254_timecounter);
1178         }
1179         return (error);
1180 }
1181
1182 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1183     0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1184
1185 static int
1186 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1187 {
1188         int error;
1189         u_int freq;
1190
1191         if (tsc_timecounter.tc_frequency == 0)
1192                 return (EOPNOTSUPP);
1193         freq = tsc_freq;
1194         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1195         if (error == 0 && req->newptr != NULL) {
1196                 tsc_freq = freq;
1197                 tsc_timecounter.tc_frequency = tsc_freq;
1198                 update_timecounter(&tsc_timecounter);
1199         }
1200         return (error);
1201 }
1202
1203 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1204     0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", "");
1205
1206 static unsigned
1207 i8254_get_timecount(struct timecounter *tc)
1208 {
1209         u_int count;
1210         u_long ef;
1211         u_int high, low;
1212
1213         ef = read_eflags();
1214         disable_intr();
1215
1216         /* Select timer0 and latch counter value. */
1217         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1218
1219         low = inb(TIMER_CNTR0);
1220         high = inb(TIMER_CNTR0);
1221         count = timer0_max_count - ((high << 8) | low);
1222         if (count < i8254_lastcount ||
1223             (!i8254_ticked && (clkintr_pending ||
1224             ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
1225 #ifdef APIC_IO
1226 #define lapic_irr1      ((volatile u_int *)&lapic)[0x210 / 4]   /* XXX XXX */
1227             /* XXX this assumes that apic_8254_intr is < 24. */
1228             (lapic_irr1 & (1 << apic_8254_intr))))
1229 #else
1230             (inb(IO_ICU1) & 1)))
1231 #endif
1232             )) {
1233                 i8254_ticked = 1;
1234                 i8254_offset += timer0_max_count;
1235         }
1236         i8254_lastcount = count;
1237         count += i8254_offset;
1238         CLOCK_UNLOCK();
1239         write_eflags(ef);
1240         return (count);
1241 }
1242
1243 static unsigned
1244 tsc_get_timecount(struct timecounter *tc)
1245 {
1246         return (rdtsc());
1247 }
1248
1249 #ifdef KERN_TIMESTAMP
1250 #define KERN_TIMESTAMP_SIZE 16384
1251 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1252 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1253         sizeof(tsc), "LU", "Kernel timestamps");
1254 void
1255 _TSTMP(u_int32_t x)
1256 {
1257         static int i;
1258
1259         tsc[i] = (u_int32_t)rdtsc();
1260         tsc[i+1] = x;
1261         i = i + 2;
1262         if (i >= KERN_TIMESTAMP_SIZE)
1263                 i = 0;
1264         tsc[i] = 0; /* mark last entry */
1265 }
1266 #endif KERN_TIMESTAMP
1267