2 * Copyright (c) 2001 Cubical Solutions Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
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25 * capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
27 * $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
33 /* max 4 units supported per machine */
35 #define IAVC_MAXUNIT 4
39 // The software context of one AVM T1 controller.
42 #define IAVC_IO_BASES 1
44 typedef struct i4b_info {
45 struct resource * io_base[IAVC_IO_BASES];
46 int io_rid [IAVC_IO_BASES];
47 struct resource * irq;
49 struct resource * mem;
53 typedef struct iavc_softc {
59 bus_space_handle_t sc_mem_bh;
60 bus_space_tag_t sc_mem_bt;
62 bus_space_handle_t sc_io_bh;
63 bus_space_tag_t sc_io_bt;
77 char sc_sendbuf[128+2048];
78 char sc_recvbuf[128+2048];
81 struct ifqueue sc_txq;
83 i4b_info_t sc_resources;
86 extern iavc_softc_t iavc_sc[];
88 #define iavc_find_sc(unit) (&iavc_sc[(unit)])
91 // {b1,b1dma,t1}_{detect,reset}
92 // Routines to detect and manage the specific type of card.
95 extern int b1_detect(iavc_softc_t *sc);
96 extern void b1_disable_irq(iavc_softc_t *sc);
97 extern void b1_reset(iavc_softc_t *sc);
99 extern int b1dma_detect(iavc_softc_t *sc);
100 extern void b1dma_reset(iavc_softc_t *sc);
102 extern int t1_detect(iavc_softc_t *sc);
103 extern void t1_disable_irq(iavc_softc_t *sc);
104 extern void t1_reset(iavc_softc_t *sc);
108 // Routines to access the memory mapped registers of the
109 // S5933 DMA controller.
112 static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
114 return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
117 static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
119 bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
123 // amcc_{put,get}_{byte,word}
124 // Routines to access the DMA buffers byte- or wordwise.
127 static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
133 static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
139 static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
141 *buf++ = (value & 0xff);
142 *buf++ = (value >> 8) & 0xff;
143 *buf++ = (value >> 16) & 0xff;
144 *buf++ = (value >> 24) & 0xff;
148 static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
151 *value |= (*buf++ << 8);
152 *value |= (*buf++ << 16);
153 *value |= (*buf++ << 24);
158 // Controller LLI message numbers.
161 #define SEND_POLL 0x72
162 #define SEND_INIT 0x11
163 #define SEND_REGISTER 0x12
164 #define SEND_DATA_B3_REQ 0x13
165 #define SEND_RELEASE 0x14
166 #define SEND_MESSAGE 0x15
167 #define SEND_CONFIG 0x71
168 #define SEND_POLLACK 0x73
170 #define RECEIVE_POLL 0x32
171 #define RECEIVE_INIT 0x27
172 #define RECEIVE_MESSAGE 0x21
173 #define RECEIVE_DATA_B3_IND 0x22
174 #define RECEIVE_START 0x23
175 #define RECEIVE_STOP 0x24
176 #define RECEIVE_NEW_NCCI 0x25
177 #define RECEIVE_FREE_NCCI 0x26
178 #define RECEIVE_RELEASE 0x26
179 #define RECEIVE_TASK_READY 0x31
180 #define RECEIVE_DEBUGMSG 0x71
181 #define RECEIVE_POLLDWORD 0x75
183 /* Operation constants */
185 #define WRITE_REGISTER 0x00
186 #define READ_REGISTER 0x01
188 /* Port offsets in I/O space */
191 #define B1_WRITE 0x01
192 #define B1_INSTAT 0x02
193 #define B1_OUTSTAT 0x03
194 #define B1_ANALYSE 0x04
195 #define B1_REVISION 0x05
196 #define B1_RESET 0x10
198 #define T1_FASTLINK 0x00
199 #define T1_SLOWLINK 0x08
201 #define T1_READ B1_READ
202 #define T1_WRITE B1_WRITE
203 #define T1_INSTAT B1_INSTAT
204 #define T1_OUTSTAT B1_OUTSTAT
205 #define T1_IRQENABLE 0x05
206 #define T1_FIFOSTAT 0x06
207 #define T1_RESETLINK 0x10
208 #define T1_ANALYSE 0x11
209 #define T1_IRQMASTER 0x12
210 #define T1_IDENT 0x17
211 #define T1_RESETBOARD 0x1f
213 #define T1F_IREADY 0x01
214 #define T1F_IHALF 0x02
215 #define T1F_IFULL 0x04
216 #define T1F_IEMPTY 0x08
217 #define T1F_IFLAGS 0xf0
219 #define T1F_OREADY 0x10
220 #define T1F_OHALF 0x20
221 #define T1F_OEMPTY 0x40
222 #define T1F_OFULL 0x80
223 #define T1F_OFLAGS 0xf0
225 #define FIFO_OUTBSIZE 256
226 #define FIFO_INPBSIZE 512
228 #define HEMA_VERSION_ID 0
229 #define HEMA_PAL_ID 0
232 // S5933 DMA controller register offsets in memory, and bitmasks.
235 #define AMCC_RXPTR 0x24
236 #define AMCC_RXLEN 0x28
237 #define AMCC_TXPTR 0x2c
238 #define AMCC_TXLEN 0x30
240 #define AMCC_INTCSR 0x38
241 #define EN_READ_TC_INT 0x00008000
242 #define EN_WRITE_TC_INT 0x00004000
243 #define EN_TX_TC_INT EN_READ_TC_INT
244 #define EN_RX_TC_INT EN_WRITE_TC_INT
245 #define AVM_FLAG 0x30000000
247 #define ANY_S5933_INT 0x00800000
248 #define READ_TC_INT 0x00080000
249 #define WRITE_TC_INT 0x00040000
250 #define TX_TC_INT READ_TC_INT
251 #define RX_TC_INT WRITE_TC_INT
252 #define MASTER_ABORT_INT 0x00100000
253 #define TARGET_ABORT_INT 0x00200000
254 #define BUS_MASTER_INT 0x00200000
255 #define ALL_INT 0x000c0000
257 #define AMCC_MCSR 0x3c
258 #define A2P_HI_PRIORITY 0x00000100
259 #define EN_A2P_TRANSFERS 0x00000400
260 #define P2A_HI_PRIORITY 0x00001000
261 #define EN_P2A_TRANSFERS 0x00004000
262 #define RESET_A2P_FLAGS 0x04000000
263 #define RESET_P2A_FLAGS 0x02000000
266 // (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
267 // to become ready after an I/O operation. The default is 1 ms.
270 #define B1IO_WAIT_MAX 1000
271 #define B1IO_WAIT_DLY 1
275 // Diagnostic output routine, returns the written value via
276 // the device's analysis register.
279 // Returns nonzero if data is readable from the card via the
283 // Returns nonzero if data can be written to the card via the
287 static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
289 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
291 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
294 static __inline int b1io_rx_full(iavc_softc_t *sc)
296 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
300 static __inline int b1io_tx_empty(iavc_softc_t *sc)
302 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
307 // b1io_{get,put}_{byte,word}
308 // Routines to read and write the device I/O registers byte- or
311 // b1io_{get,put}_slice
312 // Routines to read and write sequential bytes to the device
316 static __inline u_int8_t b1io_get_byte(iavc_softc_t *sc)
319 while (!b1io_rx_full(sc) && spin < B1IO_WAIT_MAX) {
320 spin++; DELAY(B1IO_WAIT_DLY);
322 if (b1io_rx_full(sc))
323 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_READ);
324 printf("iavc%d: rx not completed\n", sc->sc_unit);
328 static __inline int b1io_put_byte(iavc_softc_t *sc, u_int8_t val)
331 while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
332 spin++; DELAY(B1IO_WAIT_DLY);
334 if (b1io_tx_empty(sc)) {
335 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, B1_WRITE, val);
338 printf("iavc%d: tx not emptied\n", sc->sc_unit);
342 static __inline int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val)
345 while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
346 spin++; DELAY(B1IO_WAIT_DLY);
348 if (b1io_tx_empty(sc)) {
349 b1io_outp(sc, B1_WRITE, val);
352 printf("iavc%d: tx not emptied\n", sc->sc_unit);
356 static __inline u_int32_t b1io_get_word(iavc_softc_t *sc)
359 val |= b1io_get_byte(sc);
360 val |= (b1io_get_byte(sc) << 8);
361 val |= (b1io_get_byte(sc) << 16);
362 val |= (b1io_get_byte(sc) << 24);
366 static __inline void b1io_put_word(iavc_softc_t *sc, u_int32_t val)
368 b1io_put_byte(sc, (val & 0xff));
369 b1io_put_byte(sc, (val >> 8) & 0xff);
370 b1io_put_byte(sc, (val >> 16) & 0xff);
371 b1io_put_byte(sc, (val >> 24) & 0xff);
374 static __inline int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
377 len = i = b1io_get_word(sc);
378 while (i--) *dp++ = b1io_get_byte(sc);
382 static __inline void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
384 b1io_put_word(sc, len);
385 while (len--) b1io_put_byte(sc, *dp++);
389 // b1io_{read,write}_reg
390 // Routines to read and write the device registers via the I/O
394 static __inline u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg)
396 b1io_put_byte(sc, READ_REGISTER);
397 b1io_put_word(sc, reg);
398 return b1io_get_word(sc);
401 static __inline u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val)
403 b1io_put_byte(sc, WRITE_REGISTER);
404 b1io_put_word(sc, reg);
405 b1io_put_word(sc, val);
406 return b1io_get_word(sc);
411 // I/O port write operation for the T1, which does not seem
412 // to have the analysis port.
415 static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
417 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
420 static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
422 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
425 static __inline int t1io_isfastlink(iavc_softc_t *sc)
427 return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
430 static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
432 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
435 static __inline int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
438 len = i = b1io_get_word(sc);
439 if (t1io_isfastlink(sc)) {
442 status = t1io_fifostatus(sc) & (T1F_IREADY|T1F_IHALF);
443 if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
446 case T1F_IREADY|T1F_IHALF|T1F_IFULL:
447 bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
448 T1_READ, dp, FIFO_INPBSIZE);
453 case T1F_IREADY|T1F_IHALF:
454 bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
461 *dp++ = b1io_get_byte(sc);
465 } else { /* not fastlink */
466 if (i--) *dp++ = b1io_get_byte(sc);
471 static __inline void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
474 b1io_put_word(sc, i);
475 if (t1io_isfastlink(sc)) {
478 status = t1io_fifostatus(sc) & (T1F_OREADY|T1F_OHALF);
479 if (i >= FIFO_OUTBSIZE) status |= T1F_OFULL;
482 case T1F_OREADY|T1F_OHALF|T1F_OFULL:
483 bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
484 T1_WRITE, dp, FIFO_OUTBSIZE);
489 case T1F_OREADY|T1F_OHALF:
490 bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
497 b1io_put_byte(sc, *dp++);
502 while (i--) b1io_put_byte(sc, *dp++);
507 // An attempt to bring it all together:
508 // ------------------------------------
510 // iavc_{read,write}_reg
511 // Routines to access the device registers via the I/O port.
513 // iavc_{read,write}_port
514 // Routines to access the device I/O ports.
516 // iavc_tx_empty, iavc_rx_full
517 // Routines to check when the device has drained the last written
518 // byte, or produced a full byte to read.
520 // iavc_{get,put}_byte
521 // Routines to read/write byte values to the device via the I/O port.
523 // iavc_{get,put}_word
524 // Routines to read/write 32-bit words to the device via the I/O port.
526 // iavc_{get,put}_slice
527 // Routines to read/write {length, data} pairs to the device via the
528 // ubiquituous I/O port. Uses the HEMA FIFO on a T1.
531 #define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
532 #define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
534 #define iavc_read_port(sc, port) \
535 bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
536 #define iavc_write_port(sc, port, val) \
537 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
539 #define iavc_tx_empty(sc) b1io_tx_empty(sc)
540 #define iavc_rx_full(sc) b1io_rx_full(sc)
542 #define iavc_get_byte(sc) b1io_get_byte(sc)
543 #define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
544 #define iavc_get_word(sc) b1io_get_word(sc)
545 #define iavc_put_word(sc, val) b1io_put_word(sc, val)
547 static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
549 if (sc->sc_t1) return t1io_get_slice(sc, dp);
550 else return b1io_get_slice(sc, dp);
553 static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
555 if (sc->sc_t1) t1io_put_slice(sc, dp, len);
556 else b1io_put_slice(sc, dp, len);
561 // Interrupt handler, called by the bus specific interrupt routine
562 // in iavc_<bustype>.c module.
565 // CAPI callback. Resets device and loads firmware.
568 // CAPI callback. Registers an application id.
571 // CAPI callback. Releases an application id.
574 // CAPI callback. Sends a CAPI message. A B3_DATA_REQ message has
575 // m_next point to a data mbuf.
578 extern void iavc_handle_intr(iavc_softc_t *);
579 extern int iavc_load(capi_softc_t *, int, u_int8_t *);
580 extern int iavc_register(capi_softc_t *, int, int);
581 extern int iavc_release(capi_softc_t *, int);
582 extern int iavc_send(capi_softc_t *, struct mbuf *);
584 extern void b1isa_setup_irq(struct iavc_softc *sc);
586 #endif /* _CAPI_IAVC_H_ */