2 * Copyright (c) 1999, 2000 Dave Boyce. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_iwic - isdn4bsd Winbond W6692 driver
28 * ----------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/iwic/i4b_w6692.h,v 1.2.2.1 2001/08/10 14:08:40 obrien Exp $
32 * last edit-date: [Sun Jan 21 11:09:46 2001]
34 *---------------------------------------------------------------------------*/
39 #define IWIC_BCH_A 0 /* channel A */
40 #define IWIC_BCH_B 1 /* channel B */
42 /*---------------------------------------------------------------------------*
44 *---------------------------------------------------------------------------*/
45 #define IWIC_DCHAN_FIFO_LEN 64
46 #define IWIC_BCHAN_FIFO_LEN 64
48 /*---------------------------------------------------------------------------*
49 * D-Channel register offsets
50 *---------------------------------------------------------------------------*/
51 #define D_RFIFO 0x00 /* D channel receive FIFO */
52 #define D_XFIFO 0x04 /* D channel transmit FIFO */
53 #define D_CMDR 0x08 /* D channel command register */
54 #define D_MODE 0x0c /* D channel mode control */
55 #define D_TIMR 0x10 /* D channel timer control */
56 #define D_EXIR 0x1c /* D channel extended interrupt */
57 #define D_EXIM 0x20 /* D channel extended interrupt mask */
58 #define D_STAR 0x24 /* D channel status register */
59 #define D_RSTA 0x28 /* D channel receive status */
60 #define D_SAM 0x2c /* D channel address mask 1 */
61 #define D_SAP1 0x30 /* D channel individual SAPI 1 */
62 #define D_SAP2 0x34 /* D channel individual SAPI 2 */
63 #define D_TAM 0x38 /* D channel address mask 2 */
64 #define D_TEI1 0x3c /* D channel individual TEI 1 */
65 #define D_TEI2 0x40 /* D channel individual TEI 2 */
66 #define D_RBCH 0x44 /* D channel receive frame byte count high */
67 #define D_RBCL 0x48 /* D channel receive frame byte count low */
68 #define D_CTL 0x54 /* D channel control register */
70 /*---------------------------------------------------------------------------*
71 * B-channel base offsets
72 *---------------------------------------------------------------------------*/
73 #define B1_CHAN_OFFSET 0x80 /* B1 channel offset */
74 #define B2_CHAN_OFFSET 0xc0 /* B2 channel offset */
76 /*---------------------------------------------------------------------------*
77 * B-channel register offsets, from base
78 *---------------------------------------------------------------------------*/
79 #define B_RFIFO 0x00 /* B channel receive FIFO */
80 #define B_XFIFO 0x04 /* B channel transmit FIFO */
81 #define B_CMDR 0x08 /* B channel command register */
82 #define B_MODE 0x0c /* B channel mode control */
83 #define B_EXIR 0x10 /* B channel extended interrupt */
84 #define B_EXIM 0x14 /* B channel extended interrupt mask */
85 #define B_STAR 0x18 /* B channel status register */
86 #define B_ADM1 0x1c /* B channel address mask 1 */
87 #define B_ADM2 0x20 /* B channel address mask 2 */
88 #define B_ADR1 0x24 /* B channel address 1 */
89 #define B_ADR2 0x28 /* B channel address 2 */
90 #define B_RBCL 0x2c /* B channel receive frame byte count high */
91 #define B_RBCH 0x30 /* B channel receive frame byte count low */
93 /*---------------------------------------------------------------------------*
94 * Remaining control register offsets.
95 *---------------------------------------------------------------------------*/
96 #define ISTA 0x14 /* Interrupt status register */
97 #define IMASK 0x18 /* Interrupt mask register */
98 #define TIMR2 0x4c /* Timer 2 */
99 #define L1_RC 0x50 /* GCI layer 1 ready code */
100 #define CIR 0x58 /* Command/Indication receive */
101 #define CIX 0x5c /* Command/Indication transmit */
102 #define SQR 0x60 /* S/Q channel receive register */
103 #define SQX 0x64 /* S/Q channel transmit register */
104 #define PCTL 0x68 /* Peripheral control register */
105 #define MOR 0x6c /* Monitor receive channel */
106 #define MOX 0x70 /* Monitor transmit channel */
107 #define MOSR 0x74 /* Monitor channel status register */
108 #define MOCR 0x78 /* Monitor channel control register */
109 #define GCR 0x7c /* GCI mode control register */
110 #define XADDR 0xf4 /* Peripheral address register */
111 #define XDATA 0xf8 /* Peripheral data register */
112 #define EPCTL 0xfc /* Serial EEPROM control */
114 /*---------------------------------------------------------------------------*
116 *---------------------------------------------------------------------------*/
117 #define D_CMDR_RACK 0x80
118 #define D_CMDR_RRST 0x40
119 #define D_CMDR_STT 0x10
120 #define D_CMDR_XMS 0x08
121 #define D_CMDR_XME 0x02
122 #define D_CMDR_XRST 0x01
124 #define D_MODE_MMS 0x80
125 #define D_MODE_RACT 0x40
126 #define D_MODE_TMS 0x10
127 #define D_MODE_TEE 0x08
128 #define D_MODE_MFD 0x04
129 #define D_MODE_DLP 0x02
130 #define D_MODE_RLP 0x01
132 #define D_TIMR_CNT(i) (((i) >> 5) & 0x07)
133 #define D_TIMR_VAL(i) ((i) & 0x1f)
135 #define ISTA_D_RMR 0x80
136 #define ISTA_D_RME 0x40
137 #define ISTA_D_XFR 0x20
138 #define ISTA_XINT1 0x10
139 #define ISTA_XINT0 0x08
140 #define ISTA_D_EXI 0x04
141 #define ISTA_B1_EXI 0x02
142 #define ISTA_B2_EXI 0x01
144 #define IMASK_D_RMR 0x80
145 #define IMASK_D_RME 0x40
146 #define IMASK_D_XFR 0x20
147 #define IMASK_XINT1 0x10
148 #define IMASK_XINT0 0x08
149 #define IMASK_D_EXI 0x04
150 #define IMASK_B1_EXI 0x02
151 #define IMASK_B2_EXI 0x01
153 #define D_EXIR_RDOV 0x80
154 #define D_EXIR_XDUN 0x40
155 #define D_EXIR_XCOL 0x20
156 #define D_EXIR_TIN2 0x10
157 #define D_EXIR_MOC 0x08
158 #define D_EXIR_ISC 0x04
159 #define D_EXIR_TEXP 0x02
160 #define D_EXIR_WEXP 0x01
162 #define D_EXIM_RDOV 0x80
163 #define D_EXIM_XDUN 0x40
164 #define D_EXIM_XCOL 0x20
165 #define D_EXIM_TIM2 0x10
166 #define D_EXIM_MOC 0x08
167 #define D_EXIM_ISC 0x04
168 #define D_EXIM_TEXP 0x02
169 #define D_EXIM_WEXP 0x01
171 #define D_STAR_XDOW 0x80
172 #define D_STAR_XBZ 0x20
173 #define D_STAR_DRDY 0x10
175 #define D_RSTA_RDOV 0x40
176 #define D_RSTA_CRCE 0x20
177 #define D_RSTA_RMB 0x10
179 #define D_RBCH_VN(i) (((i) >> 6) & 0x03)
180 #define D_RBCH_LOV 0x20
181 #define D_RBC(h,l) (((((h) & 0x1f)) << 8) + (l))
183 #define D_TIMR2_TMD 0x80
184 #define D_TIMR2_TBCN(i) ((i) & 0x3f)
186 #define L1_RC_RC(i) ((i) & 0x0f)
188 #define D_CTL_WTT(i) (((i) > 6) & 0x03)
189 #define D_CTL_SRST 0x20
190 #define D_CTL_TPS 0x04
191 #define D_CTL_OPS(i) ((i) & 0x03)
195 #define CIR_CODR(i) ((i) & 0x0f)
202 #define CIX_AR10 0x09
213 #define CIR_AI10 0x0d
216 #define SQR_XIND1 0x80
217 #define SQR_XIND0 0x40
218 #define SQR_MSYN 0x20
219 #define SQR_SCIE 0x10
220 #define SQR_S(i) ((i) & 0x0f)
222 #define SQX_SCIE 0x10
223 #define SQX_Q(i) ((i) & 0x0f)
226 #define B_CMDR_RACK 0x80
227 #define B_CMDR_RRST 0x40
228 #define B_CMDR_RACT 0x20
229 #define B_CMDR_XMS 0x04
230 #define B_CMDR_XME 0x02
231 #define B_CMDR_XRST 0x01
233 #define B_MODE_MMS 0x80
234 #define B_MODE_ITF 0x40
235 #define B_MODE_EPCM 0x20
236 #define B_MODE_BSW1 0x10
237 #define B_MODE_BSW0 0x08
238 #define B_MODE_SW56 0x04
239 #define B_MODE_FTS1 0x02
240 #define B_MODE_FTS0 0x01
242 #define B_EXIR_RMR 0x40
243 #define B_EXIR_RME 0x20
244 #define B_EXIR_RDOV 0x10
245 #define B_EXIR_XFR 0x02
246 #define B_EXIR_XDUN 0x01
248 #define B_EXIM_RMR 0x40
249 #define B_EXIM_RME 0x20
250 #define B_EXIM_RDOV 0x10
251 #define B_EXIM_XFR 0x02
252 #define B_EXIM_XDUN 0x01
254 #define B_STAR_RDOV 0x40
255 #define B_STAR_CRCE 0x20
256 #define B_STAR_RMB 0x10
257 #define B_STAR_XDOW 0x04
258 #define B_STAR_XBZ 0x01
260 #define B_RBC(h,l) (((((h) & 0x1f)) << 8) + (l))
262 #endif /* _I4B_W6692_H_ */