sys/dev/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  *
  32  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_object.c 254885 2013-08-25 19:37:15Z dumbbell $
  33  */
  34 #include <drm/drmP.h>
  35 #include <uapi_drm/radeon_drm.h>
  36 #include "radeon.h"
  37 #ifdef DUMBBELL_WIP
  38 #include "radeon_trace.h"
  39 #endif /* DUMBBELL_WIP */
  40 #include <linux/io.h>
  41
  42
  43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  44
  45 /*
  46  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  47  * function are calling it.
  48  */
  49
  50 static void radeon_bo_clear_va(struct radeon_bo *bo)
  51 {
  52         struct radeon_bo_va *bo_va, *tmp;
  53
  54         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
  55                 /* remove from all vm address space */
  56                 radeon_vm_bo_rmv(bo->rdev, bo_va);
  57         }
  58 }
  59
  60 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  61 {
  62         struct radeon_bo *bo;
  63
  64         bo = container_of(tbo, struct radeon_bo, tbo);
  65         spin_lock(&bo->rdev->gem.mutex);
  66         list_del_init(&bo->list);
  67         spin_unlock(&bo->rdev->gem.mutex);
  68         radeon_bo_clear_surface_reg(bo);
  69         radeon_bo_clear_va(bo);
  70         drm_gem_object_release(&bo->gem_base);
  71         kfree(bo);
  72 }
  73
  74 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  75 {
  76         if (bo->destroy == &radeon_ttm_bo_destroy)
  77                 return true;
  78         return false;
  79 }
  80
  81 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  82 {
  83         u32 c = 0;
  84
  85         rbo->placement.fpfn = 0;
  86         rbo->placement.lpfn = 0;
  87         rbo->placement.placement = rbo->placements;
  88         rbo->placement.busy_placement = rbo->placements;
  89         if (domain & RADEON_GEM_DOMAIN_VRAM)
  90                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  91                                         TTM_PL_FLAG_VRAM;
  92         if (domain & RADEON_GEM_DOMAIN_GTT) {
  93                 if (rbo->rdev->flags & RADEON_IS_AGP) {
  94                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
  95                 } else {
  96                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
  97                 }
  98         }
  99         if (domain & RADEON_GEM_DOMAIN_CPU) {
 100                 if (rbo->rdev->flags & RADEON_IS_AGP) {
 101                         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
 102                 } else {
 103                         rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 104                 }
 105         }
 106         if (!c)
 107                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 108         rbo->placement.num_placement = c;
 109         rbo->placement.num_busy_placement = c;
 110 }
 111
 112 int radeon_bo_create(struct radeon_device *rdev,
 113                      unsigned long size, int byte_align, bool kernel, u32 domain,
 114                      struct sg_table *sg, struct radeon_bo **bo_ptr)
 115 {
 116         struct radeon_bo *bo;
 117         enum ttm_bo_type type;
 118         unsigned long page_align = roundup2(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 119         size_t acc_size;
 120         int r;
 121
 122         size = ALIGN(size, PAGE_SIZE);
 123
 124         if (kernel) {
 125                 type = ttm_bo_type_kernel;
 126         } else if (sg) {
 127                 type = ttm_bo_type_sg;
 128         } else {
 129                 type = ttm_bo_type_device;
 130         }
 131         *bo_ptr = NULL;
 132
 133         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
 134                                        sizeof(struct radeon_bo));
 135
 136         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 137         if (bo == NULL)
 138                 return -ENOMEM;
 139         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 140         if (unlikely(r)) {
 141                 kfree(bo);
 142                 return r;
 143         }
 144         bo->rdev = rdev;
 145         bo->surface_reg = -1;
 146         INIT_LIST_HEAD(&bo->list);
 147         INIT_LIST_HEAD(&bo->va);
 148         radeon_ttm_placement_from_domain(bo, domain);
 149         /* Kernel allocation are uninterruptible */
 150         lockmgr(&rdev->pm.mclk_lock, LK_SHARED);
 151         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 152                         &bo->placement, page_align, !kernel, NULL,
 153                         acc_size, sg, &radeon_ttm_bo_destroy);
 154         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE);
 155         if (unlikely(r != 0)) {
 156                 return r;
 157         }
 158         *bo_ptr = bo;
 159
 160 #ifdef DUMBBELL_WIP
 161         trace_radeon_bo_create(bo);
 162 #endif /* DUMBBELL_WIP */
 163
 164         return 0;
 165 }
 166
 167 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 168 {
 169         bool is_iomem;
 170         int r;
 171
 172         if (bo->kptr) {
 173                 if (ptr) {
 174                         *ptr = bo->kptr;
 175                 }
 176                 return 0;
 177         }
 178         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 179         if (r) {
 180                 return r;
 181         }
 182         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 183         if (ptr) {
 184                 *ptr = bo->kptr;
 185         }
 186         radeon_bo_check_tiling(bo, 0, 0);
 187         return 0;
 188 }
 189
 190 void radeon_bo_kunmap(struct radeon_bo *bo)
 191 {
 192         if (bo->kptr == NULL)
 193                 return;
 194         bo->kptr = NULL;
 195         radeon_bo_check_tiling(bo, 0, 0);
 196         ttm_bo_kunmap(&bo->kmap);
 197 }
 198
 199 void radeon_bo_unref(struct radeon_bo **bo)
 200 {
 201         struct ttm_buffer_object *tbo;
 202         struct radeon_device *rdev;
 203         struct radeon_bo *rbo;
 204
 205         if ((rbo = *bo) == NULL)
 206                 return;
 207         *bo = NULL;
 208         rdev = rbo->rdev;
 209         tbo = &rbo->tbo;
 210         lockmgr(&rdev->pm.mclk_lock, LK_SHARED);
 211         ttm_bo_unref(&tbo);
 212         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE);
 213 }
 214
 215 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
 216                              u64 *gpu_addr)
 217 {
 218         int r, i;
 219
 220         if (bo->pin_count) {
 221                 bo->pin_count++;
 222                 if (gpu_addr)
 223                         *gpu_addr = radeon_bo_gpu_offset(bo);
 224
 225                 if (max_offset != 0) {
 226                         u64 domain_start;
 227
 228                         if (domain == RADEON_GEM_DOMAIN_VRAM)
 229                                 domain_start = bo->rdev->mc.vram_start;
 230                         else
 231                                 domain_start = bo->rdev->mc.gtt_start;
 232                         if (max_offset < (radeon_bo_gpu_offset(bo) - domain_start)) {
 233                                 DRM_ERROR("radeon_bo_pin_restricted: "
 234                                     "max_offset(%ju) < "
 235                                     "(radeon_bo_gpu_offset(%ju) - "
 236                                     "domain_start(%ju)",
 237                                     (uintmax_t)max_offset, (uintmax_t)radeon_bo_gpu_offset(bo),
 238                                     (uintmax_t)domain_start);
 239                         }
 240                 }
 241
 242                 return 0;
 243         }
 244         radeon_ttm_placement_from_domain(bo, domain);
 245         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 246                 /* force to pin into visible video ram */
 247                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 248         }
 249         if (max_offset) {
 250                 u64 lpfn = max_offset >> PAGE_SHIFT;
 251
 252                 if (!bo->placement.lpfn)
 253                         bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
 254
 255                 if (lpfn < bo->placement.lpfn)
 256                         bo->placement.lpfn = lpfn;
 257         }
 258         for (i = 0; i < bo->placement.num_placement; i++)
 259                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 260         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 261         if (likely(r == 0)) {
 262                 bo->pin_count = 1;
 263                 if (gpu_addr != NULL)
 264                         *gpu_addr = radeon_bo_gpu_offset(bo);
 265         }
 266         if (unlikely(r != 0))
 267                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 268         return r;
 269 }
 270
 271 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 272 {
 273         return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
 274 }
 275
 276 int radeon_bo_unpin(struct radeon_bo *bo)
 277 {
 278         int r, i;
 279
 280         if (!bo->pin_count) {
 281                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 282                 return 0;
 283         }
 284         bo->pin_count--;
 285         if (bo->pin_count)
 286                 return 0;
 287         for (i = 0; i < bo->placement.num_placement; i++)
 288                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 289         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 290         if (unlikely(r != 0))
 291                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 292         return r;
 293 }
 294
 295 int radeon_bo_evict_vram(struct radeon_device *rdev)
 296 {
 297         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 298         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 299                 if (rdev->mc.igp_sideport_enabled == false)
 300                         /* Useless to evict on IGP chips */
 301                         return 0;
 302         }
 303         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 304 }
 305
 306 void radeon_bo_force_delete(struct radeon_device *rdev)
 307 {
 308         struct radeon_bo *bo, *n;
 309
 310         if (list_empty(&rdev->gem.objects)) {
 311                 return;
 312         }
 313         dev_err(rdev->dev, "Userspace still has active objects !\n");
 314         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 315                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 316                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
 317                         *((unsigned long *)&bo->gem_base.refcount));
 318                 spin_lock(&bo->rdev->gem.mutex);
 319                 list_del_init(&bo->list);
 320                 spin_unlock(&bo->rdev->gem.mutex);
 321                 /* this should unref the ttm bo */
 322                 drm_gem_object_unreference(&bo->gem_base);
 323         }
 324 }
 325
 326 int radeon_bo_init(struct radeon_device *rdev)
 327 {
 328         /* Add an MTRR for the VRAM */
 329         if (!rdev->fastfb_working) {
 330                 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, rdev->mc.aper_size);
 331         }
 332         DRM_INFO("Detected VRAM RAM=%juM, BAR=%juM\n",
 333                 rdev->mc.mc_vram_size >> 20,
 334                 (uintmax_t)rdev->mc.aper_size >> 20);
 335         DRM_INFO("RAM width %dbits %cDR\n",
 336                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 337         return radeon_ttm_init(rdev);
 338 }
 339
 340 void radeon_bo_fini(struct radeon_device *rdev)
 341 {
 342         radeon_ttm_fini(rdev);
 343         arch_phys_wc_del(rdev->mc.vram_mtrr);
 344 }
 345
 346 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 347                                 struct list_head *head)
 348 {
 349         if (lobj->written) {
 350                 list_add(&lobj->tv.head, head);
 351         } else {
 352                 list_add_tail(&lobj->tv.head, head);
 353         }
 354 }
 355
 356 int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
 357                             struct list_head *head, int ring)
 358 {
 359         struct radeon_bo_list *lobj;
 360         struct radeon_bo *bo;
 361         u32 domain;
 362         int r;
 363
 364         r = ttm_eu_reserve_buffers(ticket, head);
 365         if (unlikely(r != 0)) {
 366                 return r;
 367         }
 368         list_for_each_entry(lobj, head, tv.head) {
 369                 bo = lobj->bo;
 370                 if (!bo->pin_count) {
 371                         domain = lobj->domain;
 372
 373                 retry:
 374                         radeon_ttm_placement_from_domain(bo, domain);
 375                         if (ring == R600_RING_TYPE_UVD_INDEX)
 376                                 radeon_uvd_force_into_uvd_segment(bo);
 377                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 378                                                 true, false);
 379                         if (unlikely(r)) {
 380                                 if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
 381                                         domain = lobj->alt_domain;
 382                                         goto retry;
 383                                 }
 384                                 return r;
 385                         }
 386                 }
 387                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 388                 lobj->tiling_flags = bo->tiling_flags;
 389         }
 390         return 0;
 391 }
 392
 393 #ifdef DUMBBELL_WIP
 394 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 395                              struct vm_area_struct *vma)
 396 {
 397         return ttm_fbdev_mmap(vma, &bo->tbo);
 398 }
 399 #endif /* DUMBBELL_WIP */
 400
 401 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 402 {
 403         struct radeon_device *rdev = bo->rdev;
 404         struct radeon_surface_reg *reg;
 405         struct radeon_bo *old_object;
 406         int steal;
 407         int i;
 408
 409         KASSERT(radeon_bo_is_reserved(bo),
 410             ("radeon_bo_get_surface_reg: radeon_bo is not reserved"));
 411
 412         if (!bo->tiling_flags)
 413                 return 0;
 414
 415         if (bo->surface_reg >= 0) {
 416                 reg = &rdev->surface_regs[bo->surface_reg];
 417                 i = bo->surface_reg;
 418                 goto out;
 419         }
 420
 421         steal = -1;
 422         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 423
 424                 reg = &rdev->surface_regs[i];
 425                 if (!reg->bo)
 426                         break;
 427
 428                 old_object = reg->bo;
 429                 if (old_object->pin_count == 0)
 430                         steal = i;
 431         }
 432
 433         /* if we are all out */
 434         if (i == RADEON_GEM_MAX_SURFACES) {
 435                 if (steal == -1)
 436                         return -ENOMEM;
 437                 /* find someone with a surface reg and nuke their BO */
 438                 reg = &rdev->surface_regs[steal];
 439                 old_object = reg->bo;
 440                 /* blow away the mapping */
 441                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 442                 ttm_bo_unmap_virtual(&old_object->tbo);
 443                 old_object->surface_reg = -1;
 444                 i = steal;
 445         }
 446
 447         bo->surface_reg = i;
 448         reg->bo = bo;
 449
 450 out:
 451         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 452                                bo->tbo.mem.start << PAGE_SHIFT,
 453                                bo->tbo.num_pages << PAGE_SHIFT);
 454         return 0;
 455 }
 456
 457 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 458 {
 459         struct radeon_device *rdev = bo->rdev;
 460         struct radeon_surface_reg *reg;
 461
 462         if (bo->surface_reg == -1)
 463                 return;
 464
 465         reg = &rdev->surface_regs[bo->surface_reg];
 466         radeon_clear_surface_reg(rdev, bo->surface_reg);
 467
 468         reg->bo = NULL;
 469         bo->surface_reg = -1;
 470 }
 471
 472 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 473                                 uint32_t tiling_flags, uint32_t pitch)
 474 {
 475         struct radeon_device *rdev = bo->rdev;
 476         int r;
 477
 478         if (rdev->family >= CHIP_CEDAR) {
 479                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
 480
 481                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
 482                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
 483                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
 484                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
 485                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
 486                 switch (bankw) {
 487                 case 0:
 488                 case 1:
 489                 case 2:
 490                 case 4:
 491                 case 8:
 492                         break;
 493                 default:
 494                         return -EINVAL;
 495                 }
 496                 switch (bankh) {
 497                 case 0:
 498                 case 1:
 499                 case 2:
 500                 case 4:
 501                 case 8:
 502                         break;
 503                 default:
 504                         return -EINVAL;
 505                 }
 506                 switch (mtaspect) {
 507                 case 0:
 508                 case 1:
 509                 case 2:
 510                 case 4:
 511                 case 8:
 512                         break;
 513                 default:
 514                         return -EINVAL;
 515                 }
 516                 if (tilesplit > 6) {
 517                         return -EINVAL;
 518                 }
 519                 if (stilesplit > 6) {
 520                         return -EINVAL;
 521                 }
 522         }
 523         r = radeon_bo_reserve(bo, false);
 524         if (unlikely(r != 0))
 525                 return r;
 526         bo->tiling_flags = tiling_flags;
 527         bo->pitch = pitch;
 528         radeon_bo_unreserve(bo);
 529         return 0;
 530 }
 531
 532 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 533                                 uint32_t *tiling_flags,
 534                                 uint32_t *pitch)
 535 {
 536         KASSERT(radeon_bo_is_reserved(bo),
 537             ("radeon_bo_get_tiling_flags: radeon_bo is not reserved"));
 538         if (tiling_flags)
 539                 *tiling_flags = bo->tiling_flags;
 540         if (pitch)
 541                 *pitch = bo->pitch;
 542 }
 543
 544 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 545                                 bool force_drop)
 546 {
 547         KASSERT((radeon_bo_is_reserved(bo) || force_drop),
 548             ("radeon_bo_check_tiling: radeon_bo is not reserved && !force_drop"));
 549
 550         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 551                 return 0;
 552
 553         if (force_drop) {
 554                 radeon_bo_clear_surface_reg(bo);
 555                 return 0;
 556         }
 557
 558         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 559                 if (!has_moved)
 560                         return 0;
 561
 562                 if (bo->surface_reg >= 0)
 563                         radeon_bo_clear_surface_reg(bo);
 564                 return 0;
 565         }
 566
 567         if ((bo->surface_reg >= 0) && !has_moved)
 568                 return 0;
 569
 570         return radeon_bo_get_surface_reg(bo);
 571 }
 572
 573 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 574                            struct ttm_mem_reg *mem)
 575 {
 576         struct radeon_bo *rbo;
 577         if (!radeon_ttm_bo_is_radeon_bo(bo))
 578                 return;
 579         rbo = container_of(bo, struct radeon_bo, tbo);
 580         radeon_bo_check_tiling(rbo, 0, 1);
 581         radeon_vm_bo_invalidate(rbo->rdev, rbo);
 582 }
 583
 584 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 585 {
 586         struct radeon_device *rdev;
 587         struct radeon_bo *rbo;
 588         unsigned long offset, size;
 589         int r;
 590
 591         if (!radeon_ttm_bo_is_radeon_bo(bo))
 592                 return 0;
 593         rbo = container_of(bo, struct radeon_bo, tbo);
 594         radeon_bo_check_tiling(rbo, 0, 0);
 595         rdev = rbo->rdev;
 596         if (bo->mem.mem_type == TTM_PL_VRAM) {
 597                 size = bo->mem.num_pages << PAGE_SHIFT;
 598                 offset = bo->mem.start << PAGE_SHIFT;
 599                 if ((offset + size) > rdev->mc.visible_vram_size) {
 600                         /* hurrah the memory is not visible ! */
 601                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 602                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 603                         r = ttm_bo_validate(bo, &rbo->placement, false, false);
 604                         if (unlikely(r != 0))
 605                                 return r;
 606                         offset = bo->mem.start << PAGE_SHIFT;
 607                         /* this should not happen */
 608                         if ((offset + size) > rdev->mc.visible_vram_size)
 609                                 return -EINVAL;
 610                 }
 611         }
 612         return 0;
 613 }
 614
 615 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
 616 {
 617         int r;
 618
 619         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
 620         if (unlikely(r != 0))
 621                 return r;
 622         lockmgr(&bo->tbo.bdev->fence_lock, LK_EXCLUSIVE);
 623         if (mem_type)
 624                 *mem_type = bo->tbo.mem.mem_type;
 625         if (bo->tbo.sync_obj)
 626                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
 627         lockmgr(&bo->tbo.bdev->fence_lock, LK_RELEASE);
 628         ttm_bo_unreserve(&bo->tbo);
 629         return r;
 630 }
 631
 632
 633 /**
 634  * radeon_bo_reserve - reserve bo
 635  * @bo:         bo structure
 636  * @no_intr:    don't return -ERESTARTSYS on pending signal
 637  *
 638  * Returns:
 639  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
 640  * a signal. Release all buffer reservations and return to user-space.
 641  */
 642 int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr)
 643 {
 644         int r;
 645
 646         r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
 647         if (unlikely(r != 0)) {
 648                 if (r != -ERESTARTSYS)
 649                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
 650                 return r;
 651         }
 652         return 0;
 653 }