2 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/dev/coretemp/coretemp.c,v 1.14 2011/05/05 19:15:15 delphij Exp $
30 * Device driver for Intel's On Die thermal sensor via MSR.
31 * First introduced in Intel's Core line of processors.
34 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/module.h>
39 #include <sys/cpu_topology.h>
40 #include <sys/kernel.h>
41 #include <sys/sensors.h>
42 #include <sys/proc.h> /* for curthread */
43 #include <sys/sched.h>
44 #include <sys/thread2.h>
45 #include <sys/bitops.h>
47 #include <machine/specialreg.h>
48 #include <machine/cpufunc.h>
49 #include <machine/cputypes.h>
50 #include <machine/md_var.h>
52 #define MSR_THERM_STATUS_TM_STATUS __BIT64(0)
53 #define MSR_THERM_STATUS_TM_STATUS_LOG __BIT64(1)
54 #define MSR_THERM_STATUS_PROCHOT __BIT64(2)
55 #define MSR_THERM_STATUS_PROCHOT_LOG __BIT64(3)
56 #define MSR_THERM_STATUS_CRIT __BIT64(4)
57 #define MSR_THERM_STATUS_CRIT_LOG __BIT64(5)
58 #define MSR_THERM_STATUS_THRESH1 __BIT64(6)
59 #define MSR_THERM_STATUS_THRESH1_LOG __BIT64(7)
60 #define MSR_THERM_STATUS_THRESH2 __BIT64(8)
61 #define MSR_THERM_STATUS_THRESH2_LOG __BIT64(9)
62 #define MSR_THERM_STATUS_PWRLIM __BIT64(10)
63 #define MSR_THERM_STATUS_PWRLIM_LOG __BIT64(11)
64 #define MSR_THERM_STATUS_READ __BITS64(16, 22)
65 #define MSR_THERM_STATUS_RES __BITS64(27, 30)
66 #define MSR_THERM_STATUS_READ_VALID __BIT64(31)
68 #define MSR_THERM_STATUS_HAS_STATUS(msr) \
69 (((msr) & (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG)) ==\
70 (MSR_THERM_STATUS_TM_STATUS | MSR_THERM_STATUS_TM_STATUS_LOG))
72 #define MSR_THERM_STATUS_IS_CRITICAL(msr) \
73 (((msr) & (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG)) == \
74 (MSR_THERM_STATUS_CRIT | MSR_THERM_STATUS_CRIT_LOG))
76 #define MSR_PKGTM_STATUS_TM_STATUS __BIT64(0)
77 #define MSR_PKGTM_STATUS_TM_STATUS_LOG __BIT64(1)
78 #define MSR_PKGTM_STATUS_PROCHOT __BIT64(2)
79 #define MSR_PKGTM_STATUS_PROCHOT_LOG __BIT64(3)
80 #define MSR_PKGTM_STATUS_CRIT __BIT64(4)
81 #define MSR_PKGTM_STATUS_CRIT_LOG __BIT64(5)
82 #define MSR_PKGTM_STATUS_THRESH1 __BIT64(6)
83 #define MSR_PKGTM_STATUS_THRESH1_LOG __BIT64(7)
84 #define MSR_PKGTM_STATUS_THRESH2 __BIT64(8)
85 #define MSR_PKGTM_STATUS_THRESH2_LOG __BIT64(9)
86 #define MSR_PKGTM_STATUS_PWRLIM __BIT64(10)
87 #define MSR_PKGTM_STATUS_PWRLIM_LOG __BIT64(11)
88 #define MSR_PKGTM_STATUS_READ __BITS64(16, 22)
90 #define MSR_PKGTM_STATUS_HAS_STATUS(msr) \
91 (((msr) & (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG)) ==\
92 (MSR_PKGTM_STATUS_TM_STATUS | MSR_PKGTM_STATUS_TM_STATUS_LOG))
94 #define MSR_PKGTM_STATUS_IS_CRITICAL(msr) \
95 (((msr) & (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG)) == \
96 (MSR_PKGTM_STATUS_CRIT | MSR_PKGTM_STATUS_CRIT_LOG))
98 #define CORETEMP_TEMP_INVALID -1
99 #define CORETEMP_TEMP_NOUPDATE -2
101 struct coretemp_sensor {
102 struct ksensordev c_sensdev;
103 struct ksensor c_sens;
106 struct coretemp_softc {
111 struct coretemp_sensor *sc_sens;
112 struct coretemp_sensor *sc_pkg_sens;
114 struct globaldata *sc_gd;
116 volatile uint32_t sc_flags; /* CORETEMP_FLAG_ */
117 volatile uint64_t sc_msr;
118 volatile uint64_t sc_pkg_msr;
121 #define CORETEMP_FLAG_INITED 0x1
122 #define CORETEMP_FLAG_PENDING 0x2
123 #define CORETEMP_FLAG_CRIT 0x4
124 #define CORETEMP_FLAG_PKGCRIT 0x8
126 #define CORETEMP_HAS_PKGSENSOR(sc) ((sc)->sc_pkg_sens != NULL)
131 static void coretemp_identify(driver_t *driver, device_t parent);
132 static int coretemp_probe(device_t dev);
133 static int coretemp_attach(device_t dev);
134 static int coretemp_detach(device_t dev);
136 static void coretemp_ipi_func(void *sc);
137 static void coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags);
138 static boolean_t coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr,
140 static int coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr);
141 static void coretemp_sensor_update(struct coretemp_softc *sc, int temp);
142 static void coretemp_sensor_task(void *arg);
144 static void coretemp_pkg_sensor_task(void *arg);
145 static void coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp);
146 static int coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr);
148 static device_method_t coretemp_methods[] = {
149 /* Device interface */
150 DEVMETHOD(device_identify, coretemp_identify),
151 DEVMETHOD(device_probe, coretemp_probe),
152 DEVMETHOD(device_attach, coretemp_attach),
153 DEVMETHOD(device_detach, coretemp_detach),
158 static driver_t coretemp_driver = {
161 sizeof(struct coretemp_softc),
164 static devclass_t coretemp_devclass;
165 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, NULL);
166 MODULE_VERSION(coretemp, 1);
169 coretemp_sensor_set_invalid(struct ksensor *sens)
171 sens->status = SENSOR_S_UNSPEC;
172 sens->flags &= ~SENSOR_FUNKNOWN;
173 sens->flags |= SENSOR_FINVALID;
178 coretemp_sensor_set_unknown(struct ksensor *sens)
180 sens->status = SENSOR_S_UNSPEC;
181 sens->flags &= ~SENSOR_FINVALID;
182 sens->flags |= SENSOR_FUNKNOWN;
187 coretemp_sensor_set(struct ksensor *sens, const struct coretemp_softc *sc,
188 uint32_t crit_flag, int temp)
190 if (sc->sc_flags & crit_flag)
191 sens->status = SENSOR_S_CRIT;
193 sens->status = SENSOR_S_OK;
194 sens->flags &= ~(SENSOR_FINVALID | SENSOR_FUNKNOWN);
195 sens->value = temp * 1000000 + 273150000;
199 coretemp_identify(driver_t *driver, device_t parent)
203 /* Make sure we're not being doubly invoked. */
204 if (device_find_child(parent, "coretemp", -1) != NULL)
207 /* Check that the vendor is Intel. */
208 if (cpu_vendor_id != CPU_VENDOR_INTEL)
212 * Some Intel CPUs, namely the PIII, don't have thermal sensors,
213 * but report them in cpu_thermal_feature. This leads to a later
214 * GPF when the sensor is queried via a MSR, so we stop here.
216 if (CPUID_TO_MODEL(cpu_id) < 0xe)
219 if ((cpu_thermal_feature & CPUID_THERMAL_SENSOR) == 0)
223 * We add a child for each CPU since settings must be performed
224 * on each CPU in the SMP case.
226 child = device_add_child(parent, "coretemp", -1);
228 device_printf(parent, "add coretemp child failed\n");
232 coretemp_probe(device_t dev)
234 if (resource_disabled("coretemp", 0))
237 device_set_desc(dev, "CPU On-Die Thermal Sensors");
239 return (BUS_PROBE_GENERIC);
243 coretemp_attach(device_t dev)
245 struct coretemp_softc *sc = device_get_softc(dev);
246 const struct cpu_node *node, *start_node;
250 int cpu_model, cpu_stepping;
251 int ret, tjtarget, cpu, sens_idx;
253 struct coretemp_sensor *csens;
256 pdev = device_get_parent(dev);
257 cpu_model = CPUID_TO_MODEL(cpu_id);
258 cpu_stepping = cpu_id & CPUID_STEPPING;
262 * XXXrpaulo: I have this CPU model and when it returns from C3
263 * coretemp continues to function properly.
267 * Check for errata AE18.
268 * "Processor Digital Thermal Sensor (DTS) Readout stops
269 * updating upon returning from C3/C4 state."
271 * Adapted from the Linux coretemp driver.
273 if (cpu_model == 0xe && cpu_stepping < 0xc) {
274 msr = rdmsr(MSR_BIOS_SIGN);
277 device_printf(dev, "not supported (Intel errata "
278 "AE18), try updating your BIOS\n");
285 * Use 100C as the initial value.
289 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) {
291 * On some Core 2 CPUs, there's an undocumented MSR that
292 * can tell us if Tj(max) is 100 or 85.
294 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG
295 * was adapted from the Linux coretemp driver.
297 msr = rdmsr(MSR_IA32_EXT_CONFIG);
300 } else if (cpu_model == 0x17) {
301 switch (cpu_stepping) {
302 case 0x6: /* Mobile Core 2 Duo */
305 default: /* Unknown stepping */
308 } else if (cpu_model == 0x1c) {
309 switch (cpu_stepping) {
310 case 0xa: /* 45nm Atom D400, N400 and D500 series */
319 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET.
321 * This method is described in Intel white paper "CPU
322 * Monitoring With DTS/PECI". (#322683)
324 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr);
326 tjtarget = (msr >> 16) & 0xff;
329 * On earlier generation of processors, the value
330 * obtained from IA32_TEMPERATURE_TARGET register is
331 * an offset that needs to be summed with a model
332 * specific base. It is however not clear what
333 * these numbers are, with the publicly available
334 * documents from Intel.
336 * For now, we consider [70, 110]C range, as
337 * described in #322683, as "reasonable" and accept
338 * these values whenever the MSR is available for
339 * read, regardless the CPU model.
341 if (tjtarget >= 70 && tjtarget <= 110)
342 sc->sc_tjmax = tjtarget;
344 device_printf(dev, "Tj(target) value %d "
345 "does not seem right.\n", tjtarget);
347 device_printf(dev, "Can not get Tj(target) "
348 "from your CPU, using 100C.\n");
352 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax);
354 sc->sc_cpu = device_get_unit(device_get_parent(dev));
355 sc->sc_gd = globaldata_find(sc->sc_cpu);
357 start_node = get_cpu_node_by_cpuid(sc->sc_cpu);
360 while (node != NULL) {
361 if (node->type == CORE_LEVEL) {
362 if (node->child_no == 0)
366 node = node->parent_node;
369 master_cpu = BSRCPUMASK(node->members);
371 device_printf(dev, "master cpu%d, count %u\n",
372 master_cpu, node->child_no);
374 if (sc->sc_cpu != master_cpu)
377 KKASSERT(node->child_no > 0);
378 sc->sc_nsens = node->child_no;
379 cpu_mask = node->members;
382 CPUMASK_ASSBIT(cpu_mask, sc->sc_cpu);
384 sc->sc_sens = kmalloc(sizeof(struct coretemp_sensor) * sc->sc_nsens,
385 M_DEVBUF, M_WAITOK | M_ZERO);
388 CPUSET_FOREACH(cpu, cpu_mask) {
389 KKASSERT(sens_idx < sc->sc_nsens);
390 csens = &sc->sc_sens[sens_idx];
393 * Add hw.sensors.cpuN.temp0 MIB.
395 ksnprintf(csens->c_sensdev.xname,
396 sizeof(csens->c_sensdev.xname), "cpu%d", cpu);
397 ksnprintf(csens->c_sens.desc, sizeof(csens->c_sens.desc),
398 "node%d core%d", get_chip_ID(cpu),
399 get_core_number_within_chip(cpu));
400 csens->c_sens.type = SENSOR_TEMP;
401 coretemp_sensor_set_unknown(&csens->c_sens);
402 sensor_attach(&csens->c_sensdev, &csens->c_sens);
403 sensordev_install(&csens->c_sensdev);
408 if (cpu_thermal_feature & CPUID_THERMAL_PTM) {
409 boolean_t pkg_sens = TRUE;
412 * Package thermal sensor
416 while (node != NULL) {
417 if (node->type == CHIP_LEVEL) {
418 if (node->child_no == 0)
422 node = node->parent_node;
425 master_cpu = BSRCPUMASK(node->members);
427 device_printf(dev, "pkg master cpu%d\n",
430 if (sc->sc_cpu != master_cpu)
435 csens = sc->sc_pkg_sens =
436 kmalloc(sizeof(struct coretemp_sensor), M_DEVBUF,
440 * Add hw.sensors.cpu_nodeN.temp0 MIB.
442 ksnprintf(csens->c_sensdev.xname,
443 sizeof(csens->c_sensdev.xname), "cpu_node%d",
444 get_chip_ID(sc->sc_cpu));
445 ksnprintf(csens->c_sens.desc,
446 sizeof(csens->c_sens.desc), "node%d",
447 get_chip_ID(sc->sc_cpu));
448 csens->c_sens.type = SENSOR_TEMP;
449 coretemp_sensor_set_unknown(&csens->c_sens);
450 sensor_attach(&csens->c_sensdev, &csens->c_sens);
451 sensordev_install(&csens->c_sensdev);
455 if (CORETEMP_HAS_PKGSENSOR(sc))
456 sensor_task_register(sc, coretemp_pkg_sensor_task, 2);
458 sensor_task_register(sc, coretemp_sensor_task, 2);
464 coretemp_detach(device_t dev)
466 struct coretemp_softc *sc = device_get_softc(dev);
468 if (sc->sc_nsens > 0) {
471 sensor_task_unregister(sc);
472 lwkt_synchronize_ipiqs("coretemp");
474 for (i = 0; i < sc->sc_nsens; ++i)
475 sensordev_deinstall(&sc->sc_sens[i].c_sensdev);
476 kfree(sc->sc_sens, M_DEVBUF);
478 if (sc->sc_pkg_sens != NULL) {
479 sensordev_deinstall(&sc->sc_pkg_sens->c_sensdev);
480 kfree(sc->sc_pkg_sens, M_DEVBUF);
487 coretemp_ipi_func(void *xsc)
489 struct coretemp_softc *sc = xsc;
491 sc->sc_msr = rdmsr(MSR_THERM_STATUS);
492 if (CORETEMP_HAS_PKGSENSOR(sc))
493 sc->sc_pkg_msr = rdmsr(MSR_PKG_THERM_STATUS);
495 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PENDING);
499 coretemp_ipi_send(struct coretemp_softc *sc, uint32_t flags)
501 KASSERT((sc->sc_flags & CORETEMP_FLAG_PENDING) == 0,
502 ("coretemp: cpu%d ipi is still pending", sc->sc_cpu));
503 atomic_set_int(&sc->sc_flags, flags | CORETEMP_FLAG_PENDING);
505 lwkt_send_ipiq_passive(sc->sc_gd, coretemp_ipi_func, sc);
509 coretemp_msr_temp(struct coretemp_softc *sc, uint64_t msr)
514 * Check for Thermal Status and Thermal Status Log.
516 if (MSR_THERM_STATUS_HAS_STATUS(msr))
517 device_printf(sc->sc_dev, "PROCHOT asserted\n");
519 if (msr & MSR_THERM_STATUS_READ_VALID)
520 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_THERM_STATUS_READ);
522 temp = CORETEMP_TEMP_INVALID;
525 * Check for Critical Temperature Status and Critical
527 * It doesn't really matter if the current temperature is
528 * invalid because the "Critical Temperature Log" bit will
529 * tell us if the Critical Temperature has been reached in
530 * past. It's not directly related to the current temperature.
532 * If we reach a critical level, allow devctl(4) to catch this
533 * and shutdown the system.
535 if (MSR_THERM_STATUS_IS_CRITICAL(msr)) {
536 if ((sc->sc_flags & CORETEMP_FLAG_CRIT) == 0) {
539 device_printf(sc->sc_dev,
540 "critical temperature detected, "
541 "suggest system shutdown\n");
542 ksnprintf(stemp, sizeof(stemp), "%d", temp);
543 devctl_notify("coretemp", "Thermal", stemp,
544 "notify=0xcc"); /* TODO: add node and core */
545 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
547 } else if (sc->sc_flags & CORETEMP_FLAG_CRIT) {
548 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_CRIT);
555 coretemp_pkg_msr_temp(struct coretemp_softc *sc, uint64_t msr)
560 * Check for Thermal Status and Thermal Status Log.
562 if (MSR_PKGTM_STATUS_HAS_STATUS(msr))
563 device_printf(sc->sc_dev, "package PROCHOT asserted\n");
565 temp = sc->sc_tjmax - __SHIFTOUT(msr, MSR_PKGTM_STATUS_READ);
568 * Check for Critical Temperature Status and Critical
570 * It doesn't really matter if the current temperature is
571 * invalid because the "Critical Temperature Log" bit will
572 * tell us if the Critical Temperature has been reached in
573 * past. It's not directly related to the current temperature.
575 * If we reach a critical level, allow devctl(4) to catch this
576 * and shutdown the system.
578 if (MSR_PKGTM_STATUS_IS_CRITICAL(msr)) {
579 if ((sc->sc_flags & CORETEMP_FLAG_PKGCRIT) == 0) {
582 device_printf(sc->sc_dev,
583 "critical temperature detected, "
584 "suggest system shutdown\n");
585 ksnprintf(stemp, sizeof(stemp), "%d", temp);
586 devctl_notify("coretemp", "Thermal", stemp,
587 "notify=0xcc"); /* TODO: add node */
588 atomic_set_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT);
590 } else if (sc->sc_flags & CORETEMP_FLAG_PKGCRIT) {
591 atomic_clear_int(&sc->sc_flags, CORETEMP_FLAG_PKGCRIT);
598 coretemp_msr_fetch(struct coretemp_softc *sc, uint64_t *msr, uint64_t *pkg_msr)
601 * Send IPI to the specific CPU to read the correct temperature.
602 * If the IPI does not complete yet, i.e. CORETEMP_FLAG_PENDING,
605 if (sc->sc_cpu != mycpuid) {
606 if ((sc->sc_flags & CORETEMP_FLAG_INITED) == 0) {
607 coretemp_ipi_send(sc, CORETEMP_FLAG_INITED);
610 if (sc->sc_flags & CORETEMP_FLAG_PENDING) {
611 /* IPI does not complete yet */
616 *pkg_msr = sc->sc_pkg_msr;
617 coretemp_ipi_send(sc, 0);
620 *msr = rdmsr(MSR_THERM_STATUS);
622 *pkg_msr = rdmsr(MSR_PKG_THERM_STATUS);
628 coretemp_sensor_update(struct coretemp_softc *sc, int temp)
632 if (temp == CORETEMP_TEMP_NOUPDATE) {
633 /* No updates; keep the previous value */
634 } else if (temp == CORETEMP_TEMP_INVALID) {
635 for (i = 0; i < sc->sc_nsens; ++i)
636 coretemp_sensor_set_invalid(&sc->sc_sens[i].c_sens);
638 for (i = 0; i < sc->sc_nsens; ++i) {
639 coretemp_sensor_set(&sc->sc_sens[i].c_sens, sc,
640 CORETEMP_FLAG_CRIT, temp);
646 coretemp_pkg_sensor_update(struct coretemp_softc *sc, int temp)
648 KKASSERT(sc->sc_pkg_sens != NULL);
649 if (temp == CORETEMP_TEMP_NOUPDATE) {
650 /* No updates; keep the previous value */
651 } else if (temp == CORETEMP_TEMP_INVALID) {
652 coretemp_sensor_set_invalid(&sc->sc_pkg_sens->c_sens);
654 coretemp_sensor_set(&sc->sc_pkg_sens->c_sens, sc,
655 CORETEMP_FLAG_PKGCRIT, temp);
660 coretemp_sensor_task(void *arg)
662 struct coretemp_softc *sc = arg;
666 if (!coretemp_msr_fetch(sc, &msr, NULL))
667 temp = CORETEMP_TEMP_NOUPDATE;
669 temp = coretemp_msr_temp(sc, msr);
671 coretemp_sensor_update(sc, temp);
675 coretemp_pkg_sensor_task(void *arg)
677 struct coretemp_softc *sc = arg;
678 uint64_t msr, pkg_msr;
681 if (!coretemp_msr_fetch(sc, &msr, &pkg_msr)) {
682 temp = CORETEMP_TEMP_NOUPDATE;
683 pkg_temp = CORETEMP_TEMP_NOUPDATE;
685 temp = coretemp_msr_temp(sc, msr);
686 pkg_temp = coretemp_pkg_msr_temp(sc, pkg_msr);
689 coretemp_sensor_update(sc, temp);
690 coretemp_pkg_sensor_update(sc, pkg_temp);