sys/dev/drm/i915/i915_debug.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_debug.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35
  36 #include <sys/sysctl.h>
  37
  38 enum {
  39         ACTIVE_LIST,
  40         FLUSHING_LIST,
  41         INACTIVE_LIST,
  42         PINNED_LIST,
  43         DEFERRED_FREE_LIST,
  44 };
  45
  46 static const char *
  47 yesno(int v)
  48 {
  49         return (v ? "yes" : "no");
  50 }
  51
  52 static int
  53 i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data)
  54 {
  55         const struct intel_device_info *info = INTEL_INFO(dev);
  56
  57         sbuf_printf(m, "gen: %d\n", info->gen);
  58         if (HAS_PCH_SPLIT(dev))
  59                 sbuf_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  60 #define B(x) sbuf_printf(m, #x ": %s\n", yesno(info->x))
  61         B(is_mobile);
  62         B(is_i85x);
  63         B(is_i915g);
  64         B(is_i945gm);
  65         B(is_g33);
  66         B(need_gfx_hws);
  67         B(is_g4x);
  68         B(is_pineview);
  69         B(has_fbc);
  70         B(has_pipe_cxsr);
  71         B(has_hotplug);
  72         B(cursor_needs_physical);
  73         B(has_overlay);
  74         B(overlay_needs_physical);
  75         B(supports_tv);
  76         B(has_bsd_ring);
  77         B(has_blt_ring);
  78         B(has_llc);
  79 #undef B
  80
  81         return (0);
  82 }
  83
  84 static const char *
  85 get_pin_flag(struct drm_i915_gem_object *obj)
  86 {
  87         if (obj->user_pin_count > 0)
  88                 return "P";
  89         else if (obj->pin_count > 0)
  90                 return "p";
  91         else
  92                 return " ";
  93 }
  94
  95 static const char *
  96 get_tiling_flag(struct drm_i915_gem_object *obj)
  97 {
  98         switch (obj->tiling_mode) {
  99         default:
 100         case I915_TILING_NONE: return (" ");
 101         case I915_TILING_X: return ("X");
 102         case I915_TILING_Y: return ("Y");
 103         }
 104 }
 105
 106 static const char *
 107 cache_level_str(int type)
 108 {
 109         switch (type) {
 110         case I915_CACHE_NONE: return " uncached";
 111         case I915_CACHE_LLC: return " snooped (LLC)";
 112         case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
 113         default: return ("");
 114         }
 115 }
 116
 117 static void
 118 describe_obj(struct sbuf *m, struct drm_i915_gem_object *obj)
 119 {
 120
 121         sbuf_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
 122                    &obj->base,
 123                    get_pin_flag(obj),
 124                    get_tiling_flag(obj),
 125                    obj->base.size / 1024,
 126                    obj->base.read_domains,
 127                    obj->base.write_domain,
 128                    obj->last_rendering_seqno,
 129                    obj->last_fenced_seqno,
 130                    cache_level_str(obj->cache_level),
 131                    obj->dirty ? " dirty" : "",
 132                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 133         if (obj->base.name)
 134                 sbuf_printf(m, " (name: %d)", obj->base.name);
 135         if (obj->fence_reg != I915_FENCE_REG_NONE)
 136                 sbuf_printf(m, " (fence: %d)", obj->fence_reg);
 137         if (obj->gtt_space != NULL)
 138                 sbuf_printf(m, " (gtt offset: %08x, size: %08x)",
 139                            obj->gtt_offset, (unsigned int)obj->gtt_space->size);
 140         if (obj->pin_mappable || obj->fault_mappable) {
 141                 char s[3], *t = s;
 142                 if (obj->pin_mappable)
 143                         *t++ = 'p';
 144                 if (obj->fault_mappable)
 145                         *t++ = 'f';
 146                 *t = '\0';
 147                 sbuf_printf(m, " (%s mappable)", s);
 148         }
 149         if (obj->ring != NULL)
 150                 sbuf_printf(m, " (%s)", obj->ring->name);
 151 }
 152
 153 static int
 154 i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data)
 155 {
 156         uintptr_t list = (uintptr_t)data;
 157         struct list_head *head;
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         struct drm_i915_gem_object *obj;
 160         size_t total_obj_size, total_gtt_size;
 161         int count;
 162
 163         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 164                 return (EINTR);
 165
 166         switch (list) {
 167         case ACTIVE_LIST:
 168                 sbuf_printf(m, "Active:\n");
 169                 head = &dev_priv->mm.active_list;
 170                 break;
 171         case INACTIVE_LIST:
 172                 sbuf_printf(m, "Inactive:\n");
 173                 head = &dev_priv->mm.inactive_list;
 174                 break;
 175         case PINNED_LIST:
 176                 sbuf_printf(m, "Pinned:\n");
 177                 head = &dev_priv->mm.pinned_list;
 178                 break;
 179         case FLUSHING_LIST:
 180                 sbuf_printf(m, "Flushing:\n");
 181                 head = &dev_priv->mm.flushing_list;
 182                 break;
 183         case DEFERRED_FREE_LIST:
 184                 sbuf_printf(m, "Deferred free:\n");
 185                 head = &dev_priv->mm.deferred_free_list;
 186                 break;
 187         default:
 188                 DRM_UNLOCK(dev);
 189                 return (EINVAL);
 190         }
 191
 192         total_obj_size = total_gtt_size = count = 0;
 193         list_for_each_entry(obj, head, mm_list) {
 194                 sbuf_printf(m, "   ");
 195                 describe_obj(m, obj);
 196                 sbuf_printf(m, "\n");
 197                 total_obj_size += obj->base.size;
 198                 total_gtt_size += obj->gtt_space->size;
 199                 count++;
 200         }
 201         DRM_UNLOCK(dev);
 202
 203         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 204                    count, total_obj_size, total_gtt_size);
 205         return (0);
 206 }
 207
 208 #define count_objects(list, member) do { \
 209         list_for_each_entry(obj, list, member) { \
 210                 size += obj->gtt_space->size; \
 211                 ++count; \
 212                 if (obj->map_and_fenceable) { \
 213                         mappable_size += obj->gtt_space->size; \
 214                         ++mappable_count; \
 215                 } \
 216         } \
 217 } while (0)
 218
 219 static int
 220 i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         u32 count, mappable_count;
 224         size_t size, mappable_size;
 225         struct drm_i915_gem_object *obj;
 226
 227         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 228                 return (EINTR);
 229         sbuf_printf(m, "%u objects, %zu bytes\n",
 230                    dev_priv->mm.object_count,
 231                    dev_priv->mm.object_memory);
 232
 233         size = count = mappable_size = mappable_count = 0;
 234         count_objects(&dev_priv->mm.gtt_list, gtt_list);
 235         sbuf_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 236                    count, mappable_count, size, mappable_size);
 237
 238         size = count = mappable_size = mappable_count = 0;
 239         count_objects(&dev_priv->mm.active_list, mm_list);
 240         count_objects(&dev_priv->mm.flushing_list, mm_list);
 241         sbuf_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 242                    count, mappable_count, size, mappable_size);
 243
 244         size = count = mappable_size = mappable_count = 0;
 245         count_objects(&dev_priv->mm.pinned_list, mm_list);
 246         sbuf_printf(m, "  %u [%u] pinned objects, %zu [%zu] bytes\n",
 247                    count, mappable_count, size, mappable_size);
 248
 249         size = count = mappable_size = mappable_count = 0;
 250         count_objects(&dev_priv->mm.inactive_list, mm_list);
 251         sbuf_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 252                    count, mappable_count, size, mappable_size);
 253
 254         size = count = mappable_size = mappable_count = 0;
 255         count_objects(&dev_priv->mm.deferred_free_list, mm_list);
 256         sbuf_printf(m, "  %u [%u] freed objects, %zu [%zu] bytes\n",
 257                    count, mappable_count, size, mappable_size);
 258
 259         size = count = mappable_size = mappable_count = 0;
 260         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 261                 if (obj->fault_mappable) {
 262                         size += obj->gtt_space->size;
 263                         ++count;
 264                 }
 265                 if (obj->pin_mappable) {
 266                         mappable_size += obj->gtt_space->size;
 267                         ++mappable_count;
 268                 }
 269         }
 270         sbuf_printf(m, "%u pinned mappable objects, %zu bytes\n",
 271                    mappable_count, mappable_size);
 272         sbuf_printf(m, "%u fault mappable objects, %zu bytes\n",
 273                    count, size);
 274
 275         sbuf_printf(m, "%zu [%zu] gtt total\n",
 276                    dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
 277         DRM_UNLOCK(dev);
 278
 279         return (0);
 280 }
 281
 282 static int
 283 i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void* data)
 284 {
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         struct drm_i915_gem_object *obj;
 287         size_t total_obj_size, total_gtt_size;
 288         int count;
 289
 290         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 291                 return (EINTR);
 292
 293         total_obj_size = total_gtt_size = count = 0;
 294         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 295                 sbuf_printf(m, "   ");
 296                 describe_obj(m, obj);
 297                 sbuf_printf(m, "\n");
 298                 total_obj_size += obj->base.size;
 299                 total_gtt_size += obj->gtt_space->size;
 300                 count++;
 301         }
 302
 303         DRM_UNLOCK(dev);
 304
 305         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 306                    count, total_obj_size, total_gtt_size);
 307
 308         return (0);
 309 }
 310
 311 static int
 312 i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data)
 313 {
 314         struct intel_crtc *crtc;
 315         struct drm_i915_gem_object *obj;
 316         struct intel_unpin_work *work;
 317         char pipe;
 318         char plane;
 319
 320         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
 321                 return (0);
 322         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 323                 pipe = pipe_name(crtc->pipe);
 324                 plane = plane_name(crtc->plane);
 325
 326                 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 327                 work = crtc->unpin_work;
 328                 if (work == NULL) {
 329                         sbuf_printf(m, "No flip due on pipe %c (plane %c)\n",
 330                                    pipe, plane);
 331                 } else {
 332                         if (!atomic_read(&work->pending)) {
 333                                 sbuf_printf(m, "Flip queued on pipe %c (plane %c)\n",
 334                                            pipe, plane);
 335                         } else {
 336                                 sbuf_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 337                                            pipe, plane);
 338                         }
 339                         if (work->enable_stall_check)
 340                                 sbuf_printf(m, "Stall check enabled, ");
 341                         else
 342                                 sbuf_printf(m, "Stall check waiting for page flip ioctl, ");
 343                         sbuf_printf(m, "%d prepares\n", atomic_read(&work->pending));
 344
 345                         if (work->old_fb_obj) {
 346                                 obj = work->old_fb_obj;
 347                                 if (obj)
 348                                         sbuf_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 349                         }
 350                         if (work->pending_flip_obj) {
 351                                 obj = work->pending_flip_obj;
 352                                 if (obj)
 353                                         sbuf_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 354                         }
 355                 }
 356                 lockmgr(&dev->event_lock, LK_RELEASE);
 357         }
 358
 359         return (0);
 360 }
 361
 362 static int
 363 i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         struct drm_i915_gem_request *gem_request;
 367         int count;
 368
 369         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 370                 return (EINTR);
 371
 372         count = 0;
 373         if (!list_empty(&dev_priv->ring[RCS].request_list)) {
 374                 sbuf_printf(m, "Render requests:\n");
 375                 list_for_each_entry(gem_request,
 376                                     &dev_priv->ring[RCS].request_list,
 377                                     list) {
 378                         sbuf_printf(m, "    %d @ %d\n",
 379                                    gem_request->seqno,
 380                                    (int) (jiffies - gem_request->emitted_jiffies));
 381                 }
 382                 count++;
 383         }
 384         if (!list_empty(&dev_priv->ring[VCS].request_list)) {
 385                 sbuf_printf(m, "BSD requests:\n");
 386                 list_for_each_entry(gem_request,
 387                                     &dev_priv->ring[VCS].request_list,
 388                                     list) {
 389                         sbuf_printf(m, "    %d @ %d\n",
 390                                    gem_request->seqno,
 391                                    (int) (jiffies - gem_request->emitted_jiffies));
 392                 }
 393                 count++;
 394         }
 395         if (!list_empty(&dev_priv->ring[BCS].request_list)) {
 396                 sbuf_printf(m, "BLT requests:\n");
 397                 list_for_each_entry(gem_request,
 398                                     &dev_priv->ring[BCS].request_list,
 399                                     list) {
 400                         sbuf_printf(m, "    %d @ %d\n",
 401                                    gem_request->seqno,
 402                                    (int) (jiffies - gem_request->emitted_jiffies));
 403                 }
 404                 count++;
 405         }
 406         DRM_UNLOCK(dev);
 407
 408         if (count == 0)
 409                 sbuf_printf(m, "No requests\n");
 410
 411         return 0;
 412 }
 413
 414 static void
 415 i915_ring_seqno_info(struct sbuf *m, struct intel_ring_buffer *ring)
 416 {
 417         if (ring->get_seqno) {
 418                 sbuf_printf(m, "Current sequence (%s): %d\n",
 419                            ring->name, ring->get_seqno(ring, false));
 420         }
 421 }
 422
 423 static int
 424 i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data)
 425 {
 426         drm_i915_private_t *dev_priv = dev->dev_private;
 427         int i;
 428
 429         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 430                 return (EINTR);
 431         for (i = 0; i < I915_NUM_RINGS; i++)
 432                 i915_ring_seqno_info(m, &dev_priv->ring[i]);
 433         DRM_UNLOCK(dev);
 434         return (0);
 435 }
 436
 437
 438 static int
 439 i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data)
 440 {
 441         drm_i915_private_t *dev_priv = dev->dev_private;
 442         int i, pipe;
 443
 444         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 445                 return (EINTR);
 446
 447         if (!HAS_PCH_SPLIT(dev)) {
 448                 sbuf_printf(m, "Interrupt enable:    %08x\n",
 449                            I915_READ(IER));
 450                 sbuf_printf(m, "Interrupt identity:  %08x\n",
 451                            I915_READ(IIR));
 452                 sbuf_printf(m, "Interrupt mask:      %08x\n",
 453                            I915_READ(IMR));
 454                 for_each_pipe(pipe)
 455                         sbuf_printf(m, "Pipe %c stat:         %08x\n",
 456                                    pipe_name(pipe),
 457                                    I915_READ(PIPESTAT(pipe)));
 458         } else {
 459                 sbuf_printf(m, "North Display Interrupt enable:         %08x\n",
 460                            I915_READ(DEIER));
 461                 sbuf_printf(m, "North Display Interrupt identity:       %08x\n",
 462                            I915_READ(DEIIR));
 463                 sbuf_printf(m, "North Display Interrupt mask:           %08x\n",
 464                            I915_READ(DEIMR));
 465                 sbuf_printf(m, "South Display Interrupt enable:         %08x\n",
 466                            I915_READ(SDEIER));
 467                 sbuf_printf(m, "South Display Interrupt identity:       %08x\n",
 468                            I915_READ(SDEIIR));
 469                 sbuf_printf(m, "South Display Interrupt mask:           %08x\n",
 470                            I915_READ(SDEIMR));
 471                 sbuf_printf(m, "Graphics Interrupt enable:              %08x\n",
 472                            I915_READ(GTIER));
 473                 sbuf_printf(m, "Graphics Interrupt identity:            %08x\n",
 474                            I915_READ(GTIIR));
 475                 sbuf_printf(m, "Graphics Interrupt mask:                %08x\n",
 476                            I915_READ(GTIMR));
 477         }
 478         sbuf_printf(m, "Interrupts received: %d\n",
 479                    atomic_read(&dev_priv->irq_received));
 480         for (i = 0; i < I915_NUM_RINGS; i++) {
 481                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 482                         sbuf_printf(m, "Graphics Interrupt mask (%s):   %08x\n",
 483                                    dev_priv->ring[i].name,
 484                                    I915_READ_IMR(&dev_priv->ring[i]));
 485                 }
 486                 i915_ring_seqno_info(m, &dev_priv->ring[i]);
 487         }
 488         DRM_UNLOCK(dev);
 489
 490         return (0);
 491 }
 492
 493 static int
 494 i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data)
 495 {
 496         drm_i915_private_t *dev_priv = dev->dev_private;
 497         int i;
 498
 499         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 500                 return (EINTR);
 501
 502         sbuf_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 503         sbuf_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 504         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 505                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 506
 507                 sbuf_printf(m, "Fenced object[%2d] = ", i);
 508                 if (obj == NULL)
 509                         sbuf_printf(m, "unused");
 510                 else
 511                         describe_obj(m, obj);
 512                 sbuf_printf(m, "\n");
 513         }
 514
 515         DRM_UNLOCK(dev);
 516         return (0);
 517 }
 518
 519 static int
 520 i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data)
 521 {
 522         drm_i915_private_t *dev_priv = dev->dev_private;
 523         struct intel_ring_buffer *ring;
 524         const volatile u32 *hws;
 525         int i;
 526
 527         ring = &dev_priv->ring[(uintptr_t)data];
 528         hws = (volatile u32 *)ring->status_page.page_addr;
 529         if (hws == NULL)
 530                 return (0);
 531
 532         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 533                 sbuf_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 534                            i * 4,
 535                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 536         }
 537         return (0);
 538 }
 539
 540 static int
 541 i915_ringbuffer_data(struct drm_device *dev, struct sbuf *m, void *data)
 542 {
 543         drm_i915_private_t *dev_priv = dev->dev_private;
 544         struct intel_ring_buffer *ring;
 545
 546         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 547                 return (EINTR);
 548         ring = &dev_priv->ring[(uintptr_t)data];
 549         if (!ring->obj) {
 550                 sbuf_printf(m, "No ringbuffer setup\n");
 551         } else {
 552                 u8 *virt = ring->virtual_start;
 553                 uint32_t off;
 554
 555                 for (off = 0; off < ring->size; off += 4) {
 556                         uint32_t *ptr = (uint32_t *)(virt + off);
 557                         sbuf_printf(m, "%08x :  %08x\n", off, *ptr);
 558                 }
 559         }
 560         DRM_UNLOCK(dev);
 561         return (0);
 562 }
 563
 564 static int
 565 i915_ringbuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
 566 {
 567         drm_i915_private_t *dev_priv = dev->dev_private;
 568         struct intel_ring_buffer *ring;
 569
 570         ring = &dev_priv->ring[(uintptr_t)data];
 571         if (ring->size == 0)
 572                 return (0);
 573
 574         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 575                 return (EINTR);
 576
 577         sbuf_printf(m, "Ring %s:\n", ring->name);
 578         sbuf_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
 579         sbuf_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
 580         sbuf_printf(m, "  Size :    %08x\n", ring->size);
 581         sbuf_printf(m, "  Active :  %08x\n", intel_ring_get_active_head(ring));
 582         sbuf_printf(m, "  NOPID :   %08x\n", I915_READ_NOPID(ring));
 583         if (IS_GEN6(dev) || IS_GEN7(dev)) {
 584                 sbuf_printf(m, "  Sync 0 :   %08x\n", I915_READ_SYNC_0(ring));
 585                 sbuf_printf(m, "  Sync 1 :   %08x\n", I915_READ_SYNC_1(ring));
 586         }
 587         sbuf_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));
 588         sbuf_printf(m, "  Start :   %08x\n", I915_READ_START(ring));
 589
 590         DRM_UNLOCK(dev);
 591
 592         return (0);
 593 }
 594
 595 static const char *
 596 ring_str(int ring)
 597 {
 598         switch (ring) {
 599         case RCS: return (" render");
 600         case VCS: return (" bsd");
 601         case BCS: return (" blt");
 602         default: return ("");
 603         }
 604 }
 605
 606 static const char *
 607 pin_flag(int pinned)
 608 {
 609         if (pinned > 0)
 610                 return (" P");
 611         else if (pinned < 0)
 612                 return (" p");
 613         else
 614                 return ("");
 615 }
 616
 617 static const char *tiling_flag(int tiling)
 618 {
 619         switch (tiling) {
 620         default:
 621         case I915_TILING_NONE: return "";
 622         case I915_TILING_X: return " X";
 623         case I915_TILING_Y: return " Y";
 624         }
 625 }
 626
 627 static const char *dirty_flag(int dirty)
 628 {
 629         return dirty ? " dirty" : "";
 630 }
 631
 632 static const char *purgeable_flag(int purgeable)
 633 {
 634         return purgeable ? " purgeable" : "";
 635 }
 636
 637 static void print_error_buffers(struct sbuf *m, const char *name,
 638     struct drm_i915_error_buffer *err, int count)
 639 {
 640
 641         sbuf_printf(m, "%s [%d]:\n", name, count);
 642
 643         while (count--) {
 644                 sbuf_printf(m, "  %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
 645                            err->gtt_offset,
 646                            err->size,
 647                            err->read_domains,
 648                            err->write_domain,
 649                            err->seqno,
 650                            pin_flag(err->pinned),
 651                            tiling_flag(err->tiling),
 652                            dirty_flag(err->dirty),
 653                            purgeable_flag(err->purgeable),
 654                            err->ring != -1 ? " " : "",
 655                            ring_str(err->ring),
 656                            cache_level_str(err->cache_level));
 657
 658                 if (err->name)
 659                         sbuf_printf(m, " (name: %d)", err->name);
 660                 if (err->fence_reg != I915_FENCE_REG_NONE)
 661                         sbuf_printf(m, " (fence: %d)", err->fence_reg);
 662
 663                 sbuf_printf(m, "\n");
 664                 err++;
 665         }
 666 }
 667
 668 static void
 669 i915_ring_error_state(struct sbuf *m, struct drm_device *dev,
 670     struct drm_i915_error_state *error, unsigned ring)
 671 {
 672
 673         sbuf_printf(m, "%s command stream:\n", ring_str(ring));
 674         sbuf_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
 675         sbuf_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
 676         sbuf_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
 677         sbuf_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
 678         sbuf_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
 679         sbuf_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
 680         if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
 681                 sbuf_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
 682                 sbuf_printf(m, "  BBADDR: 0x%08jx\n", (uintmax_t)error->bbaddr);
 683         }
 684         if (INTEL_INFO(dev)->gen >= 4)
 685                 sbuf_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
 686         sbuf_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
 687         if (INTEL_INFO(dev)->gen >= 6) {
 688                 sbuf_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
 689                 sbuf_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
 690                 sbuf_printf(m, "  SYNC_0: 0x%08x\n",
 691                            error->semaphore_mboxes[ring][0]);
 692                 sbuf_printf(m, "  SYNC_1: 0x%08x\n",
 693                            error->semaphore_mboxes[ring][1]);
 694         }
 695         sbuf_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
 696         sbuf_printf(m, "  waiting: %s\n", yesno(error->waiting[ring]));
 697         sbuf_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
 698         sbuf_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
 699 }
 700
 701 static int i915_error_state(struct drm_device *dev, struct sbuf *m,
 702     void *unused)
 703 {
 704         drm_i915_private_t *dev_priv = dev->dev_private;
 705         struct drm_i915_error_state *error;
 706         int i, j, page, offset, elt;
 707
 708         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
 709         if (!dev_priv->first_error) {
 710                 sbuf_printf(m, "no error state collected\n");
 711                 goto out;
 712         }
 713
 714         error = dev_priv->first_error;
 715
 716         sbuf_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
 717             (intmax_t)error->time.tv_usec);
 718         sbuf_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
 719         sbuf_printf(m, "EIR: 0x%08x\n", error->eir);
 720         sbuf_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 721
 722         for (i = 0; i < dev_priv->num_fence_regs; i++)
 723                 sbuf_printf(m, "  fence[%d] = %08jx\n", i,
 724                     (uintmax_t)error->fence[i]);
 725
 726         if (INTEL_INFO(dev)->gen >= 6) {
 727                 sbuf_printf(m, "ERROR: 0x%08x\n", error->error);
 728                 sbuf_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 729         }
 730
 731         i915_ring_error_state(m, dev, error, RCS);
 732         if (HAS_BLT(dev))
 733                 i915_ring_error_state(m, dev, error, BCS);
 734         if (HAS_BSD(dev))
 735                 i915_ring_error_state(m, dev, error, VCS);
 736
 737         if (error->active_bo)
 738                 print_error_buffers(m, "Active",
 739                                     error->active_bo,
 740                                     error->active_bo_count);
 741
 742         if (error->pinned_bo)
 743                 print_error_buffers(m, "Pinned",
 744                                     error->pinned_bo,
 745                                     error->pinned_bo_count);
 746
 747         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
 748                 struct drm_i915_error_object *obj;
 749
 750                 if ((obj = error->ring[i].batchbuffer)) {
 751                         sbuf_printf(m, "%s --- gtt_offset = 0x%08x\n",
 752                                    dev_priv->ring[i].name,
 753                                    obj->gtt_offset);
 754                         offset = 0;
 755                         for (page = 0; page < obj->page_count; page++) {
 756                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 757                                         sbuf_printf(m, "%08x :  %08x\n",
 758                                             offset, obj->pages[page][elt]);
 759                                         offset += 4;
 760                                 }
 761                         }
 762                 }
 763
 764                 if (error->ring[i].num_requests) {
 765                         sbuf_printf(m, "%s --- %d requests\n",
 766                                    dev_priv->ring[i].name,
 767                                    error->ring[i].num_requests);
 768                         for (j = 0; j < error->ring[i].num_requests; j++) {
 769                                 sbuf_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 770                                            error->ring[i].requests[j].seqno,
 771                                            error->ring[i].requests[j].jiffies,
 772                                            error->ring[i].requests[j].tail);
 773                         }
 774                 }
 775
 776                 if ((obj = error->ring[i].ringbuffer)) {
 777                         sbuf_printf(m, "%s --- ringbuffer = 0x%08x\n",
 778                                    dev_priv->ring[i].name,
 779                                    obj->gtt_offset);
 780                         offset = 0;
 781                         for (page = 0; page < obj->page_count; page++) {
 782                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 783                                         sbuf_printf(m, "%08x :  %08x\n",
 784                                                    offset,
 785                                                    obj->pages[page][elt]);
 786                                         offset += 4;
 787                                 }
 788                         }
 789                 }
 790         }
 791
 792         if (error->overlay)
 793                 intel_overlay_print_error_state(m, error->overlay);
 794
 795         if (error->display)
 796                 intel_display_print_error_state(m, dev, error->display);
 797
 798 out:
 799         lockmgr(&dev_priv->error_lock, LK_RELEASE);
 800
 801         return (0);
 802 }
 803
 804 static int
 805 i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused)
 806 {
 807         drm_i915_private_t *dev_priv = dev->dev_private;
 808         u16 crstanddelay;
 809
 810         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 811                 return (EINTR);
 812         crstanddelay = I915_READ16(CRSTANDVID);
 813         DRM_UNLOCK(dev);
 814
 815         sbuf_printf(m, "w/ctx: %d, w/o ctx: %d\n",
 816             (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 817
 818         return 0;
 819 }
 820
 821 static int
 822 i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused)
 823 {
 824         drm_i915_private_t *dev_priv = dev->dev_private;
 825
 826         if (IS_GEN5(dev)) {
 827                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 828                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 829
 830                 sbuf_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 831                 sbuf_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 832                 sbuf_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 833                            MEMSTAT_VID_SHIFT);
 834                 sbuf_printf(m, "Current P-state: %d\n",
 835                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 836         } else if (IS_GEN6(dev)) {
 837                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 838                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 839                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 840                 u32 rpstat;
 841                 u32 rpupei, rpcurup, rpprevup;
 842                 u32 rpdownei, rpcurdown, rpprevdown;
 843                 int max_freq;
 844
 845                 /* RPSTAT1 is in the GT power well */
 846                 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 847                         return (EINTR);
 848                 gen6_gt_force_wake_get(dev_priv);
 849
 850                 rpstat = I915_READ(GEN6_RPSTAT1);
 851                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 852                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 853                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 854                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 855                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 856                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 857
 858                 gen6_gt_force_wake_put(dev_priv);
 859                 DRM_UNLOCK(dev);
 860
 861                 sbuf_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 862                 sbuf_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 863                 sbuf_printf(m, "Render p-state ratio: %d\n",
 864                            (gt_perf_status & 0xff00) >> 8);
 865                 sbuf_printf(m, "Render p-state VID: %d\n",
 866                            gt_perf_status & 0xff);
 867                 sbuf_printf(m, "Render p-state limit: %d\n",
 868                            rp_state_limits & 0xff);
 869                 sbuf_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
 870                                                 GEN6_CAGF_SHIFT) * 50);
 871                 sbuf_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 872                            GEN6_CURICONT_MASK);
 873                 sbuf_printf(m, "RP CUR UP: %dus\n", rpcurup &
 874                            GEN6_CURBSYTAVG_MASK);
 875                 sbuf_printf(m, "RP PREV UP: %dus\n", rpprevup &
 876                            GEN6_CURBSYTAVG_MASK);
 877                 sbuf_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 878                            GEN6_CURIAVG_MASK);
 879                 sbuf_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 880                            GEN6_CURBSYTAVG_MASK);
 881                 sbuf_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 882                            GEN6_CURBSYTAVG_MASK);
 883
 884                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 885                 sbuf_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 886                            max_freq * 50);
 887
 888                 max_freq = (rp_state_cap & 0xff00) >> 8;
 889                 sbuf_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 890                            max_freq * 50);
 891
 892                 max_freq = rp_state_cap & 0xff;
 893                 sbuf_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 894                            max_freq * 50);
 895         } else {
 896                 sbuf_printf(m, "no P-state info available\n");
 897         }
 898
 899         return 0;
 900 }
 901
 902 static int
 903 i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused)
 904 {
 905         drm_i915_private_t *dev_priv = dev->dev_private;
 906         u32 delayfreq;
 907         int i;
 908
 909         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 910                 return (EINTR);
 911         for (i = 0; i < 16; i++) {
 912                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 913                 sbuf_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 914                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 915         }
 916         DRM_UNLOCK(dev);
 917         return (0);
 918 }
 919
 920 static inline int
 921 MAP_TO_MV(int map)
 922 {
 923         return 1250 - (map * 25);
 924 }
 925
 926 static int
 927 i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused)
 928 {
 929         drm_i915_private_t *dev_priv = dev->dev_private;
 930         u32 inttoext;
 931         int i;
 932
 933         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 934                 return (EINTR);
 935         for (i = 1; i <= 32; i++) {
 936                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 937                 sbuf_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 938         }
 939         DRM_UNLOCK(dev);
 940
 941         return (0);
 942 }
 943
 944 static int
 945 ironlake_drpc_info(struct drm_device *dev, struct sbuf *m)
 946 {
 947         drm_i915_private_t *dev_priv = dev->dev_private;
 948         u32 rgvmodectl;
 949         u32 rstdbyctl;
 950         u16 crstandvid;
 951
 952         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 953                 return (EINTR);
 954         rgvmodectl = I915_READ(MEMMODECTL);
 955         rstdbyctl = I915_READ(RSTDBYCTL);
 956         crstandvid = I915_READ16(CRSTANDVID);
 957         DRM_UNLOCK(dev);
 958
 959         sbuf_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 960                    "yes" : "no");
 961         sbuf_printf(m, "Boost freq: %d\n",
 962                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 963                    MEMMODE_BOOST_FREQ_SHIFT);
 964         sbuf_printf(m, "HW control enabled: %s\n",
 965                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 966         sbuf_printf(m, "SW control enabled: %s\n",
 967                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 968         sbuf_printf(m, "Gated voltage change: %s\n",
 969                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 970         sbuf_printf(m, "Starting frequency: P%d\n",
 971                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 972         sbuf_printf(m, "Max P-state: P%d\n",
 973                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 974         sbuf_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 975         sbuf_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 976         sbuf_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 977         sbuf_printf(m, "Render standby enabled: %s\n",
 978                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 979         sbuf_printf(m, "Current RS state: ");
 980         switch (rstdbyctl & RSX_STATUS_MASK) {
 981         case RSX_STATUS_ON:
 982                 sbuf_printf(m, "on\n");
 983                 break;
 984         case RSX_STATUS_RC1:
 985                 sbuf_printf(m, "RC1\n");
 986                 break;
 987         case RSX_STATUS_RC1E:
 988                 sbuf_printf(m, "RC1E\n");
 989                 break;
 990         case RSX_STATUS_RS1:
 991                 sbuf_printf(m, "RS1\n");
 992                 break;
 993         case RSX_STATUS_RS2:
 994                 sbuf_printf(m, "RS2 (RC6)\n");
 995                 break;
 996         case RSX_STATUS_RS3:
 997                 sbuf_printf(m, "RC3 (RC6+)\n");
 998                 break;
 999         default:
1000                 sbuf_printf(m, "unknown\n");
1001                 break;
1002         }
1003
1004         return 0;
1005 }
1006
1007 static int
1008 gen6_drpc_info(struct drm_device *dev, struct sbuf *m)
1009 {
1010         drm_i915_private_t *dev_priv = dev->dev_private;
1011         u32 rpmodectl1, gt_core_status, rcctl1;
1012         unsigned forcewake_count;
1013         int count=0;
1014
1015         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1016                 return (EINTR);
1017
1018         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1019         forcewake_count = dev_priv->forcewake_count;
1020         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1021
1022         if (forcewake_count) {
1023                 sbuf_printf(m, "RC information inaccurate because userspace "
1024                               "holds a reference \n");
1025         } else {
1026                 /* NB: we cannot use forcewake, else we read the wrong values */
1027                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1028                         DRM_UDELAY(10);
1029                 sbuf_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1030         }
1031
1032         gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS);
1033         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1034
1035         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1036         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1037         DRM_UNLOCK(dev);
1038
1039         sbuf_printf(m, "Video Turbo Mode: %s\n",
1040                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1041         sbuf_printf(m, "HW control enabled: %s\n",
1042                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1043         sbuf_printf(m, "SW control enabled: %s\n",
1044                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1045                           GEN6_RP_MEDIA_SW_MODE));
1046         sbuf_printf(m, "RC1e Enabled: %s\n",
1047                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1048         sbuf_printf(m, "RC6 Enabled: %s\n",
1049                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1050         sbuf_printf(m, "Deep RC6 Enabled: %s\n",
1051                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1052         sbuf_printf(m, "Deepest RC6 Enabled: %s\n",
1053                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1054         sbuf_printf(m, "Current RC state: ");
1055         switch (gt_core_status & GEN6_RCn_MASK) {
1056         case GEN6_RC0:
1057                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1058                         sbuf_printf(m, "Core Power Down\n");
1059                 else
1060                         sbuf_printf(m, "on\n");
1061                 break;
1062         case GEN6_RC3:
1063                 sbuf_printf(m, "RC3\n");
1064                 break;
1065         case GEN6_RC6:
1066                 sbuf_printf(m, "RC6\n");
1067                 break;
1068         case GEN6_RC7:
1069                 sbuf_printf(m, "RC7\n");
1070                 break;
1071         default:
1072                 sbuf_printf(m, "Unknown\n");
1073                 break;
1074         }
1075
1076         sbuf_printf(m, "Core Power Down: %s\n",
1077                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1078         return 0;
1079 }
1080
1081 static int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused)
1082 {
1083
1084         if (IS_GEN6(dev) || IS_GEN7(dev))
1085                 return (gen6_drpc_info(dev, m));
1086         else
1087                 return (ironlake_drpc_info(dev, m));
1088 }
1089 static int
1090 i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused)
1091 {
1092         drm_i915_private_t *dev_priv = dev->dev_private;
1093
1094         if (!I915_HAS_FBC(dev)) {
1095                 sbuf_printf(m, "FBC unsupported on this chipset");
1096                 return 0;
1097         }
1098
1099         if (intel_fbc_enabled(dev)) {
1100                 sbuf_printf(m, "FBC enabled");
1101         } else {
1102                 sbuf_printf(m, "FBC disabled: ");
1103                 switch (dev_priv->no_fbc_reason) {
1104                 case FBC_NO_OUTPUT:
1105                         sbuf_printf(m, "no outputs");
1106                         break;
1107                 case FBC_STOLEN_TOO_SMALL:
1108                         sbuf_printf(m, "not enough stolen memory");
1109                         break;
1110                 case FBC_UNSUPPORTED_MODE:
1111                         sbuf_printf(m, "mode not supported");
1112                         break;
1113                 case FBC_MODE_TOO_LARGE:
1114                         sbuf_printf(m, "mode too large");
1115                         break;
1116                 case FBC_BAD_PLANE:
1117                         sbuf_printf(m, "FBC unsupported on plane");
1118                         break;
1119                 case FBC_NOT_TILED:
1120                         sbuf_printf(m, "scanout buffer not tiled");
1121                         break;
1122                 case FBC_MULTIPLE_PIPES:
1123                         sbuf_printf(m, "multiple pipes are enabled");
1124                         break;
1125                 default:
1126                         sbuf_printf(m, "unknown reason");
1127                 }
1128         }
1129         return 0;
1130 }
1131
1132 static int
1133 i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused)
1134 {
1135         drm_i915_private_t *dev_priv = dev->dev_private;
1136         bool sr_enabled = false;
1137
1138         if (HAS_PCH_SPLIT(dev))
1139                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1140         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1141                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1142         else if (IS_I915GM(dev))
1143                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1144         else if (IS_PINEVIEW(dev))
1145                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1146
1147         sbuf_printf(m, "self-refresh: %s",
1148                    sr_enabled ? "enabled" : "disabled");
1149
1150         return (0);
1151 }
1152
1153 static int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m,
1154     void *unused)
1155 {
1156         drm_i915_private_t *dev_priv = dev->dev_private;
1157         int gpu_freq, ia_freq;
1158
1159         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1160                 sbuf_printf(m, "unsupported on this chipset");
1161                 return (0);
1162         }
1163
1164         if (lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1165                 return -EINTR;
1166
1167         sbuf_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1168
1169         for (gpu_freq = dev_priv->rps.min_delay;
1170              gpu_freq <= dev_priv->rps.max_delay;
1171              gpu_freq++) {
1172                 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1173                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1174                            GEN6_PCODE_READ_MIN_FREQ_TABLE);
1175                 if (_intel_wait_for(dev,
1176                     (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1177                     10, 1, "915frq")) {
1178                         DRM_ERROR("pcode read of freq table timed out\n");
1179                         continue;
1180                 }
1181                 ia_freq = I915_READ(GEN6_PCODE_DATA);
1182                 sbuf_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1183         }
1184
1185         lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE);
1186
1187         return 0;
1188 }
1189
1190 static int
1191 i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused)
1192 {
1193         drm_i915_private_t *dev_priv = dev->dev_private;
1194         unsigned long temp, chipset, gfx;
1195
1196         if (!IS_GEN5(dev)) {
1197                 sbuf_printf(m, "Not supported\n");
1198                 return (0);
1199         }
1200
1201         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1202                 return (EINTR);
1203         temp = i915_mch_val(dev_priv);
1204         chipset = i915_chipset_val(dev_priv);
1205         gfx = i915_gfx_val(dev_priv);
1206         DRM_UNLOCK(dev);
1207
1208         sbuf_printf(m, "GMCH temp: %ld\n", temp);
1209         sbuf_printf(m, "Chipset power: %ld\n", chipset);
1210         sbuf_printf(m, "GFX power: %ld\n", gfx);
1211         sbuf_printf(m, "Total power: %ld\n", chipset + gfx);
1212
1213         return (0);
1214 }
1215
1216 static int
1217 i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused)
1218 {
1219         drm_i915_private_t *dev_priv = dev->dev_private;
1220
1221         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1222                 return (EINTR);
1223         sbuf_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1224         DRM_UNLOCK(dev);
1225
1226         return (0);
1227 }
1228
1229 #if 0
1230 static int
1231 i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused)
1232 {
1233         drm_i915_private_t *dev_priv = dev->dev_private;
1234         struct intel_opregion *opregion = &dev_priv->opregion;
1235
1236         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1237                 return (EINTR);
1238         if (opregion->header)
1239                 seq_write(m, opregion->header, OPREGION_SIZE);
1240         DRM_UNLOCK(dev);
1241
1242         return 0;
1243 }
1244 #endif
1245
1246 static int
1247 i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
1248 {
1249         drm_i915_private_t *dev_priv = dev->dev_private;
1250         struct intel_fbdev *ifbdev;
1251         struct intel_framebuffer *fb;
1252
1253         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1254                 return (EINTR);
1255
1256         ifbdev = dev_priv->fbdev;
1257         if (ifbdev == NULL) {
1258                 DRM_UNLOCK(dev);
1259                 return (0);
1260         }
1261         fb = to_intel_framebuffer(ifbdev->helper.fb);
1262
1263         sbuf_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1264                    fb->base.width,
1265                    fb->base.height,
1266                    fb->base.depth,
1267                    fb->base.bits_per_pixel);
1268         describe_obj(m, fb->obj);
1269         sbuf_printf(m, "\n");
1270
1271         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1272                 if (&fb->base == ifbdev->helper.fb)
1273                         continue;
1274
1275                 sbuf_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1276                            fb->base.width,
1277                            fb->base.height,
1278                            fb->base.depth,
1279                            fb->base.bits_per_pixel);
1280                 describe_obj(m, fb->obj);
1281                 sbuf_printf(m, "\n");
1282         }
1283
1284         DRM_UNLOCK(dev);
1285
1286         return (0);
1287 }
1288
1289 static int
1290 i915_context_status(struct drm_device *dev, struct sbuf *m, void *data)
1291 {
1292         drm_i915_private_t *dev_priv;
1293         int ret;
1294
1295         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
1296                 return (0);
1297
1298         dev_priv = dev->dev_private;
1299         ret = lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
1300         if (ret != 0)
1301                 return (EINTR);
1302
1303         if (dev_priv->pwrctx != NULL) {
1304                 sbuf_printf(m, "power context ");
1305                 describe_obj(m, dev_priv->pwrctx);
1306                 sbuf_printf(m, "\n");
1307         }
1308
1309         if (dev_priv->renderctx != NULL) {
1310                 sbuf_printf(m, "render context ");
1311                 describe_obj(m, dev_priv->renderctx);
1312                 sbuf_printf(m, "\n");
1313         }
1314
1315         lockmgr(&dev->mode_config.mutex, LK_RELEASE);
1316
1317         return (0);
1318 }
1319
1320 static int
1321 i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m,
1322     void *data)
1323 {
1324         struct drm_i915_private *dev_priv;
1325         unsigned forcewake_count;
1326
1327         dev_priv = dev->dev_private;
1328         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1329         forcewake_count = dev_priv->forcewake_count;
1330         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1331
1332         sbuf_printf(m, "forcewake count = %u\n", forcewake_count);
1333
1334         return (0);
1335 }
1336
1337 static const char *
1338 swizzle_string(unsigned swizzle)
1339 {
1340
1341         switch(swizzle) {
1342         case I915_BIT_6_SWIZZLE_NONE:
1343                 return "none";
1344         case I915_BIT_6_SWIZZLE_9:
1345                 return "bit9";
1346         case I915_BIT_6_SWIZZLE_9_10:
1347                 return "bit9/bit10";
1348         case I915_BIT_6_SWIZZLE_9_11:
1349                 return "bit9/bit11";
1350         case I915_BIT_6_SWIZZLE_9_10_11:
1351                 return "bit9/bit10/bit11";
1352         case I915_BIT_6_SWIZZLE_9_17:
1353                 return "bit9/bit17";
1354         case I915_BIT_6_SWIZZLE_9_10_17:
1355                 return "bit9/bit10/bit17";
1356         case I915_BIT_6_SWIZZLE_UNKNOWN:
1357                 return "unknown";
1358         }
1359
1360         return "bug";
1361 }
1362
1363 static int
1364 i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data)
1365 {
1366         struct drm_i915_private *dev_priv;
1367         int ret;
1368
1369         dev_priv = dev->dev_private;
1370         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1371         if (ret != 0)
1372                 return (EINTR);
1373
1374         sbuf_printf(m, "bit6 swizzle for X-tiling = %s\n",
1375                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1376         sbuf_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1377                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1378
1379         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1380                 sbuf_printf(m, "DDC = 0x%08x\n",
1381                            I915_READ(DCC));
1382                 sbuf_printf(m, "C0DRB3 = 0x%04x\n",
1383                            I915_READ16(C0DRB3));
1384                 sbuf_printf(m, "C1DRB3 = 0x%04x\n",
1385                            I915_READ16(C1DRB3));
1386         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1387                 sbuf_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1388                            I915_READ(MAD_DIMM_C0));
1389                 sbuf_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1390                            I915_READ(MAD_DIMM_C1));
1391                 sbuf_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1392                            I915_READ(MAD_DIMM_C2));
1393                 sbuf_printf(m, "TILECTL = 0x%08x\n",
1394                            I915_READ(TILECTL));
1395                 sbuf_printf(m, "ARB_MODE = 0x%08x\n",
1396                            I915_READ(ARB_MODE));
1397                 sbuf_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1398                            I915_READ(DISP_ARB_CTL));
1399         }
1400         DRM_UNLOCK(dev);
1401
1402         return (0);
1403 }
1404
1405 static int
1406 i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data)
1407 {
1408         struct drm_i915_private *dev_priv;
1409         struct intel_ring_buffer *ring;
1410         int i, ret;
1411
1412         dev_priv = dev->dev_private;
1413
1414         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1415         if (ret != 0)
1416                 return (EINTR);
1417         if (INTEL_INFO(dev)->gen == 6)
1418                 sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1419
1420         for (i = 0; i < I915_NUM_RINGS; i++) {
1421                 ring = &dev_priv->ring[i];
1422
1423                 sbuf_printf(m, "%s\n", ring->name);
1424                 if (INTEL_INFO(dev)->gen == 7)
1425                         sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1426                 sbuf_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1427                 sbuf_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1428                 sbuf_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1429         }
1430         if (dev_priv->mm.aliasing_ppgtt) {
1431                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1432
1433                 sbuf_printf(m, "aliasing PPGTT:\n");
1434                 sbuf_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1435         }
1436         sbuf_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1437         DRM_UNLOCK(dev);
1438
1439         return (0);
1440 }
1441
1442 static int
1443 i915_max_freq(SYSCTL_HANDLER_ARGS)
1444 {
1445         struct drm_device *dev;
1446         drm_i915_private_t *dev_priv;
1447         int error, max_freq;
1448
1449         dev = arg1;
1450         dev_priv = dev->dev_private;
1451         if (dev_priv == NULL)
1452                 return (EBUSY);
1453         max_freq = dev_priv->rps.max_delay * 50;
1454         error = sysctl_handle_int(oidp, &max_freq, 0, req);
1455         if (error || !req->newptr)
1456                 return (error);
1457         DRM_DEBUG("Manually setting max freq to %d\n", max_freq);
1458
1459         if (lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1460                 return -EINTR;
1461
1462         /*
1463          * Turbo will still be enabled, but won't go above the set value.
1464          */
1465         dev_priv->rps.max_delay = max_freq / 50;
1466
1467         gen6_set_rps(dev, max_freq / 50);
1468         lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE);
1469
1470         return (error);
1471 }
1472
1473 static int
1474 i915_cache_sharing(SYSCTL_HANDLER_ARGS)
1475 {
1476         struct drm_device *dev;
1477         drm_i915_private_t *dev_priv;
1478         int error, snpcr, cache_sharing;
1479
1480         dev = arg1;
1481         dev_priv = dev->dev_private;
1482         if (dev_priv == NULL)
1483                 return (EBUSY);
1484         DRM_LOCK(dev);
1485         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1486         DRM_UNLOCK(dev);
1487         cache_sharing = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1488         error = sysctl_handle_int(oidp, &cache_sharing, 0, req);
1489         if (error || !req->newptr)
1490                 return (error);
1491         if (cache_sharing < 0 || cache_sharing > 3)
1492                 return (EINVAL);
1493         DRM_DEBUG("Manually setting uncore sharing to %d\n", cache_sharing);
1494
1495         DRM_LOCK(dev);
1496         /* Update the cache sharing policy here as well */
1497         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1498         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1499         snpcr |= (cache_sharing << GEN6_MBC_SNPCR_SHIFT);
1500         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1501         DRM_UNLOCK(dev);
1502         return (0);
1503 }
1504
1505 static struct i915_info_sysctl_list {
1506         const char *name;
1507         int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data);
1508         int flags;
1509         void *data;
1510 } i915_info_sysctl_list[] = {
1511         {"i915_capabilities", i915_capabilities, 0},
1512         {"i915_gem_objects", i915_gem_object_info, 0},
1513         {"i915_gem_gtt", i915_gem_gtt_info, 0},
1514         {"i915_gem_active", i915_gem_object_list_info, 0, (void *)ACTIVE_LIST},
1515         {"i915_gem_flushing", i915_gem_object_list_info, 0,
1516             (void *)FLUSHING_LIST},
1517         {"i915_gem_inactive", i915_gem_object_list_info, 0,
1518             (void *)INACTIVE_LIST},
1519         {"i915_gem_pinned", i915_gem_object_list_info, 0,
1520             (void *)PINNED_LIST},
1521         {"i915_gem_deferred_free", i915_gem_object_list_info, 0,
1522             (void *)DEFERRED_FREE_LIST},
1523         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1524         {"i915_gem_request", i915_gem_request_info, 0},
1525         {"i915_gem_seqno", i915_gem_seqno_info, 0},
1526         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1527         {"i915_gem_interrupt", i915_interrupt_info, 0},
1528         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1529         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1530         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1531         {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1532         {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1533         {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1534         {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1535         {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1536         {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1537         {"i915_error_state", i915_error_state, 0},
1538         {"i915_rstdby_delays", i915_rstdby_delays, 0},
1539         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1540         {"i915_delayfreq_table", i915_delayfreq_table, 0},
1541         {"i915_inttoext_table", i915_inttoext_table, 0},
1542         {"i915_drpc_info", i915_drpc_info, 0},
1543         {"i915_emon_status", i915_emon_status, 0},
1544         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1545         {"i915_gfxec", i915_gfxec, 0},
1546         {"i915_fbc_status", i915_fbc_status, 0},
1547         {"i915_sr_status", i915_sr_status, 0},
1548 #if 0
1549         {"i915_opregion", i915_opregion, 0},
1550 #endif
1551         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1552         {"i915_context_status", i915_context_status, 0},
1553         {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info, 0},
1554         {"i915_swizzle_info", i915_swizzle_info, 0},
1555         {"i915_ppgtt_info", i915_ppgtt_info, 0},
1556 };
1557
1558 struct i915_info_sysctl_thunk {
1559         struct drm_device *dev;
1560         int idx;
1561         void *arg;
1562 };
1563
1564 static int
1565 i915_info_sysctl_handler(SYSCTL_HANDLER_ARGS)
1566 {
1567 #if 0
1568         struct sbuf m;
1569 #endif
1570         struct i915_info_sysctl_thunk *thunk;
1571         struct drm_device *dev;
1572         drm_i915_private_t *dev_priv;
1573         int error;
1574
1575         thunk = arg1;
1576         dev = thunk->dev;
1577         dev_priv = dev->dev_private;
1578         if (dev_priv == NULL)
1579                 return (EBUSY);
1580 #if 0
1581         error = sysctl_wire_old_buffer(req, 0);
1582         if (error != 0)
1583                 return (error);
1584         sbuf_new_for_sysctl(&m, NULL, 128, req);
1585         error = i915_info_sysctl_list[thunk->idx].ptr(dev, &m,
1586             thunk->arg);
1587         if (error == 0)
1588                 error = sbuf_finish(&m);
1589         sbuf_delete(&m);
1590 #else
1591         error = 0;
1592 #endif
1593         return (error);
1594 }
1595
1596 extern int i915_gem_sync_exec_requests;
1597 extern int i915_fix_mi_batchbuffer_end;
1598 extern int i915_intr_pf;
1599 extern long i915_gem_wired_pages_cnt;
1600
1601 int
1602 i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1603     struct sysctl_oid *top)
1604 {
1605         struct sysctl_oid *oid, *info;
1606         struct i915_info_sysctl_thunk *thunks;
1607         int i, error;
1608
1609         thunks = kmalloc(sizeof(*thunks) * DRM_ARRAY_SIZE(i915_info_sysctl_list),
1610             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1611         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1612                 thunks[i].dev = dev;
1613                 thunks[i].idx = i;
1614                 thunks[i].arg = i915_info_sysctl_list[i].data;
1615         }
1616         dev->sysctl_private = thunks;
1617         info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info",
1618             CTLFLAG_RW, NULL, NULL);
1619         if (info == NULL)
1620                 return (ENOMEM);
1621         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1622                 oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1623                     i915_info_sysctl_list[i].name, CTLTYPE_STRING | CTLFLAG_RD,
1624                     &thunks[i], 0, i915_info_sysctl_handler, "A", NULL);
1625                 if (oid == NULL)
1626                         return (ENOMEM);
1627         }
1628         oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1629             "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt,
1630             NULL);
1631         if (oid == NULL)
1632                 return (ENOMEM);
1633         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq",
1634             CTLTYPE_INT | CTLFLAG_RW, dev, 0, i915_max_freq,
1635             "I", NULL);
1636         if (oid == NULL)
1637                 return (ENOMEM);
1638         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1639             "cache_sharing", CTLTYPE_INT | CTLFLAG_RW, dev,
1640             0, i915_cache_sharing, "I", NULL);
1641         if (oid == NULL)
1642                 return (ENOMEM);
1643         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "sync_exec",
1644             CTLFLAG_RW, &i915_gem_sync_exec_requests, 0, NULL);
1645         if (oid == NULL)
1646                 return (ENOMEM);
1647         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "fix_mi",
1648             CTLFLAG_RW, &i915_fix_mi_batchbuffer_end, 0, NULL);
1649         if (oid == NULL)
1650                 return (ENOMEM);
1651         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf",
1652             CTLFLAG_RW, &i915_intr_pf, 0, NULL);
1653         if (oid == NULL)
1654                 return (ENOMEM);
1655
1656         error = drm_add_busid_modesetting(dev, ctx, top);
1657         if (error != 0)
1658                 return (error);
1659
1660         return (0);
1661 }
1662
1663 void
1664 i915_sysctl_cleanup(struct drm_device *dev)
1665 {
1666
1667         drm_free(dev->sysctl_private, DRM_MEM_DRIVER);
1668 }