sys/dev/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *
  27  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_combios.c 254885 2013-08-25 19:37:15Z dumbbell $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <uapi_drm/radeon_drm.h>
  32 #include "radeon.h"
  33 #include "atom.h"
  34
  35 #ifdef CONFIG_PPC_PMAC
  36 /* not sure which of these are needed */
  37 #include <asm/machdep.h>
  38 #include <asm/pmac_feature.h>
  39 #include <asm/prom.h>
  40 #include <asm/pci-bridge.h>
  41 #endif /* CONFIG_PPC_PMAC */
  42
  43 /* old legacy ATI BIOS routines */
  44
  45 /* COMBIOS table offsets */
  46 enum radeon_combios_table_offset {
  47         /* absolute offset tables */
  48         COMBIOS_ASIC_INIT_1_TABLE,
  49         COMBIOS_BIOS_SUPPORT_TABLE,
  50         COMBIOS_DAC_PROGRAMMING_TABLE,
  51         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  52         COMBIOS_CRTC_INFO_TABLE,
  53         COMBIOS_PLL_INFO_TABLE,
  54         COMBIOS_TV_INFO_TABLE,
  55         COMBIOS_DFP_INFO_TABLE,
  56         COMBIOS_HW_CONFIG_INFO_TABLE,
  57         COMBIOS_MULTIMEDIA_INFO_TABLE,
  58         COMBIOS_TV_STD_PATCH_TABLE,
  59         COMBIOS_LCD_INFO_TABLE,
  60         COMBIOS_MOBILE_INFO_TABLE,
  61         COMBIOS_PLL_INIT_TABLE,
  62         COMBIOS_MEM_CONFIG_TABLE,
  63         COMBIOS_SAVE_MASK_TABLE,
  64         COMBIOS_HARDCODED_EDID_TABLE,
  65         COMBIOS_ASIC_INIT_2_TABLE,
  66         COMBIOS_CONNECTOR_INFO_TABLE,
  67         COMBIOS_DYN_CLK_1_TABLE,
  68         COMBIOS_RESERVED_MEM_TABLE,
  69         COMBIOS_EXT_TMDS_INFO_TABLE,
  70         COMBIOS_MEM_CLK_INFO_TABLE,
  71         COMBIOS_EXT_DAC_INFO_TABLE,
  72         COMBIOS_MISC_INFO_TABLE,
  73         COMBIOS_CRT_INFO_TABLE,
  74         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  75         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  76         COMBIOS_FAN_SPEED_INFO_TABLE,
  77         COMBIOS_OVERDRIVE_INFO_TABLE,
  78         COMBIOS_OEM_INFO_TABLE,
  79         COMBIOS_DYN_CLK_2_TABLE,
  80         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  81         COMBIOS_I2C_INFO_TABLE,
  82         /* relative offset tables */
  83         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
  84         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
  85         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
  86         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
  87         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
  88         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
  89         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
  90         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
  91         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
  92         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
  93         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
  94 };
  95
  96 enum radeon_combios_ddc {
  97         DDC_NONE_DETECTED,
  98         DDC_MONID,
  99         DDC_DVI,
 100         DDC_VGA,
 101         DDC_CRT2,
 102         DDC_LCD,
 103         DDC_GPIO,
 104 };
 105
 106 enum radeon_combios_connector {
 107         CONNECTOR_NONE_LEGACY,
 108         CONNECTOR_PROPRIETARY_LEGACY,
 109         CONNECTOR_CRT_LEGACY,
 110         CONNECTOR_DVI_I_LEGACY,
 111         CONNECTOR_DVI_D_LEGACY,
 112         CONNECTOR_CTV_LEGACY,
 113         CONNECTOR_STV_LEGACY,
 114         CONNECTOR_UNSUPPORTED_LEGACY
 115 };
 116
 117 const int legacy_connector_convert[] = {
 118         DRM_MODE_CONNECTOR_Unknown,
 119         DRM_MODE_CONNECTOR_DVID,
 120         DRM_MODE_CONNECTOR_VGA,
 121         DRM_MODE_CONNECTOR_DVII,
 122         DRM_MODE_CONNECTOR_DVID,
 123         DRM_MODE_CONNECTOR_Composite,
 124         DRM_MODE_CONNECTOR_SVIDEO,
 125         DRM_MODE_CONNECTOR_Unknown,
 126 };
 127
 128 static uint16_t combios_get_table_offset(struct drm_device *dev,
 129                                          enum radeon_combios_table_offset table)
 130 {
 131         struct radeon_device *rdev = dev->dev_private;
 132         int rev;
 133         uint16_t offset = 0, check_offset;
 134
 135         if (!rdev->bios)
 136                 return 0;
 137
 138         switch (table) {
 139                 /* absolute offset tables */
 140         case COMBIOS_ASIC_INIT_1_TABLE:
 141                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 142                 if (check_offset)
 143                         offset = check_offset;
 144                 break;
 145         case COMBIOS_BIOS_SUPPORT_TABLE:
 146                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 147                 if (check_offset)
 148                         offset = check_offset;
 149                 break;
 150         case COMBIOS_DAC_PROGRAMMING_TABLE:
 151                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 152                 if (check_offset)
 153                         offset = check_offset;
 154                 break;
 155         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 156                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 157                 if (check_offset)
 158                         offset = check_offset;
 159                 break;
 160         case COMBIOS_CRTC_INFO_TABLE:
 161                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 162                 if (check_offset)
 163                         offset = check_offset;
 164                 break;
 165         case COMBIOS_PLL_INFO_TABLE:
 166                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 167                 if (check_offset)
 168                         offset = check_offset;
 169                 break;
 170         case COMBIOS_TV_INFO_TABLE:
 171                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 172                 if (check_offset)
 173                         offset = check_offset;
 174                 break;
 175         case COMBIOS_DFP_INFO_TABLE:
 176                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 177                 if (check_offset)
 178                         offset = check_offset;
 179                 break;
 180         case COMBIOS_HW_CONFIG_INFO_TABLE:
 181                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 182                 if (check_offset)
 183                         offset = check_offset;
 184                 break;
 185         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 186                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 187                 if (check_offset)
 188                         offset = check_offset;
 189                 break;
 190         case COMBIOS_TV_STD_PATCH_TABLE:
 191                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 192                 if (check_offset)
 193                         offset = check_offset;
 194                 break;
 195         case COMBIOS_LCD_INFO_TABLE:
 196                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 197                 if (check_offset)
 198                         offset = check_offset;
 199                 break;
 200         case COMBIOS_MOBILE_INFO_TABLE:
 201                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 202                 if (check_offset)
 203                         offset = check_offset;
 204                 break;
 205         case COMBIOS_PLL_INIT_TABLE:
 206                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 207                 if (check_offset)
 208                         offset = check_offset;
 209                 break;
 210         case COMBIOS_MEM_CONFIG_TABLE:
 211                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 212                 if (check_offset)
 213                         offset = check_offset;
 214                 break;
 215         case COMBIOS_SAVE_MASK_TABLE:
 216                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 217                 if (check_offset)
 218                         offset = check_offset;
 219                 break;
 220         case COMBIOS_HARDCODED_EDID_TABLE:
 221                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 222                 if (check_offset)
 223                         offset = check_offset;
 224                 break;
 225         case COMBIOS_ASIC_INIT_2_TABLE:
 226                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 227                 if (check_offset)
 228                         offset = check_offset;
 229                 break;
 230         case COMBIOS_CONNECTOR_INFO_TABLE:
 231                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 232                 if (check_offset)
 233                         offset = check_offset;
 234                 break;
 235         case COMBIOS_DYN_CLK_1_TABLE:
 236                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 237                 if (check_offset)
 238                         offset = check_offset;
 239                 break;
 240         case COMBIOS_RESERVED_MEM_TABLE:
 241                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 242                 if (check_offset)
 243                         offset = check_offset;
 244                 break;
 245         case COMBIOS_EXT_TMDS_INFO_TABLE:
 246                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 247                 if (check_offset)
 248                         offset = check_offset;
 249                 break;
 250         case COMBIOS_MEM_CLK_INFO_TABLE:
 251                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 252                 if (check_offset)
 253                         offset = check_offset;
 254                 break;
 255         case COMBIOS_EXT_DAC_INFO_TABLE:
 256                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 257                 if (check_offset)
 258                         offset = check_offset;
 259                 break;
 260         case COMBIOS_MISC_INFO_TABLE:
 261                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 262                 if (check_offset)
 263                         offset = check_offset;
 264                 break;
 265         case COMBIOS_CRT_INFO_TABLE:
 266                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 267                 if (check_offset)
 268                         offset = check_offset;
 269                 break;
 270         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 271                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 272                 if (check_offset)
 273                         offset = check_offset;
 274                 break;
 275         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 276                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 277                 if (check_offset)
 278                         offset = check_offset;
 279                 break;
 280         case COMBIOS_FAN_SPEED_INFO_TABLE:
 281                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 282                 if (check_offset)
 283                         offset = check_offset;
 284                 break;
 285         case COMBIOS_OVERDRIVE_INFO_TABLE:
 286                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 287                 if (check_offset)
 288                         offset = check_offset;
 289                 break;
 290         case COMBIOS_OEM_INFO_TABLE:
 291                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 292                 if (check_offset)
 293                         offset = check_offset;
 294                 break;
 295         case COMBIOS_DYN_CLK_2_TABLE:
 296                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 297                 if (check_offset)
 298                         offset = check_offset;
 299                 break;
 300         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 301                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 302                 if (check_offset)
 303                         offset = check_offset;
 304                 break;
 305         case COMBIOS_I2C_INFO_TABLE:
 306                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 307                 if (check_offset)
 308                         offset = check_offset;
 309                 break;
 310                 /* relative offset tables */
 311         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 312                 check_offset =
 313                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 314                 if (check_offset) {
 315                         rev = RBIOS8(check_offset);
 316                         if (rev > 0) {
 317                                 check_offset = RBIOS16(check_offset + 0x3);
 318                                 if (check_offset)
 319                                         offset = check_offset;
 320                         }
 321                 }
 322                 break;
 323         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 324                 check_offset =
 325                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 326                 if (check_offset) {
 327                         rev = RBIOS8(check_offset);
 328                         if (rev > 0) {
 329                                 check_offset = RBIOS16(check_offset + 0x5);
 330                                 if (check_offset)
 331                                         offset = check_offset;
 332                         }
 333                 }
 334                 break;
 335         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 336                 check_offset =
 337                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 338                 if (check_offset) {
 339                         rev = RBIOS8(check_offset);
 340                         if (rev > 0) {
 341                                 check_offset = RBIOS16(check_offset + 0x7);
 342                                 if (check_offset)
 343                                         offset = check_offset;
 344                         }
 345                 }
 346                 break;
 347         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 348                 check_offset =
 349                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 350                 if (check_offset) {
 351                         rev = RBIOS8(check_offset);
 352                         if (rev == 2) {
 353                                 check_offset = RBIOS16(check_offset + 0x9);
 354                                 if (check_offset)
 355                                         offset = check_offset;
 356                         }
 357                 }
 358                 break;
 359         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 360                 check_offset =
 361                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 362                 if (check_offset) {
 363                         while (RBIOS8(check_offset++));
 364                         check_offset += 2;
 365                         if (check_offset)
 366                                 offset = check_offset;
 367                 }
 368                 break;
 369         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 370                 check_offset =
 371                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 372                 if (check_offset) {
 373                         check_offset = RBIOS16(check_offset + 0x11);
 374                         if (check_offset)
 375                                 offset = check_offset;
 376                 }
 377                 break;
 378         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 379                 check_offset =
 380                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 381                 if (check_offset) {
 382                         check_offset = RBIOS16(check_offset + 0x13);
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x15);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x17);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x2);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x4);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         default:
 424                 break;
 425         }
 426
 427         return offset;
 428
 429 }
 430
 431 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 432 {
 433         int edid_info, size;
 434         struct edid *edid;
 435         unsigned char *raw;
 436         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 437         if (!edid_info)
 438                 return false;
 439
 440         raw = rdev->bios + edid_info;
 441         size = EDID_LENGTH * (raw[0x7e] + 1);
 442         edid = kmalloc(size, M_DRM, M_WAITOK);
 443         if (edid == NULL)
 444                 return false;
 445
 446         memcpy((unsigned char *)edid, raw, size);
 447
 448         if (!drm_edid_is_valid(edid)) {
 449                 drm_free(edid, M_DRM);
 450                 return false;
 451         }
 452
 453         rdev->mode_info.bios_hardcoded_edid = edid;
 454         rdev->mode_info.bios_hardcoded_edid_size = size;
 455         return true;
 456 }
 457
 458 /* this is used for atom LCDs as well */
 459 struct edid *
 460 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
 461 {
 462         struct edid *edid;
 463
 464         if (rdev->mode_info.bios_hardcoded_edid) {
 465                 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size,
 466                                M_DRM, M_WAITOK);
 467                 if (edid) {
 468                         memcpy((unsigned char *)edid,
 469                                (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
 470                                rdev->mode_info.bios_hardcoded_edid_size);
 471                         return edid;
 472                 }
 473         }
 474         return NULL;
 475 }
 476
 477 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 478                                                        enum radeon_combios_ddc ddc,
 479                                                        u32 clk_mask,
 480                                                        u32 data_mask)
 481 {
 482         struct radeon_i2c_bus_rec i2c;
 483         int ddc_line = 0;
 484
 485         /* ddc id            = mask reg
 486          * DDC_NONE_DETECTED = none
 487          * DDC_DVI           = RADEON_GPIO_DVI_DDC
 488          * DDC_VGA           = RADEON_GPIO_VGA_DDC
 489          * DDC_LCD           = RADEON_GPIOPAD_MASK
 490          * DDC_GPIO          = RADEON_MDGPIO_MASK
 491          * r1xx
 492          * DDC_MONID         = RADEON_GPIO_MONID
 493          * DDC_CRT2          = RADEON_GPIO_CRT2_DDC
 494          * r200
 495          * DDC_MONID         = RADEON_GPIO_MONID
 496          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 497          * r300/r350
 498          * DDC_MONID         = RADEON_GPIO_DVI_DDC
 499          * DDC_CRT2          = RADEON_GPIO_DVI_DDC
 500          * rv2xx/rv3xx
 501          * DDC_MONID         = RADEON_GPIO_MONID
 502          * DDC_CRT2          = RADEON_GPIO_MONID
 503          * rs3xx/rs4xx
 504          * DDC_MONID         = RADEON_GPIOPAD_MASK
 505          * DDC_CRT2          = RADEON_GPIO_MONID
 506          */
 507         switch (ddc) {
 508         case DDC_NONE_DETECTED:
 509         default:
 510                 ddc_line = 0;
 511                 break;
 512         case DDC_DVI:
 513                 ddc_line = RADEON_GPIO_DVI_DDC;
 514                 break;
 515         case DDC_VGA:
 516                 ddc_line = RADEON_GPIO_VGA_DDC;
 517                 break;
 518         case DDC_LCD:
 519                 ddc_line = RADEON_GPIOPAD_MASK;
 520                 break;
 521         case DDC_GPIO:
 522                 ddc_line = RADEON_MDGPIO_MASK;
 523                 break;
 524         case DDC_MONID:
 525                 if (rdev->family == CHIP_RS300 ||
 526                     rdev->family == CHIP_RS400 ||
 527                     rdev->family == CHIP_RS480)
 528                         ddc_line = RADEON_GPIOPAD_MASK;
 529                 else if (rdev->family == CHIP_R300 ||
 530                          rdev->family == CHIP_R350) {
 531                         ddc_line = RADEON_GPIO_DVI_DDC;
 532                         ddc = DDC_DVI;
 533                 } else
 534                         ddc_line = RADEON_GPIO_MONID;
 535                 break;
 536         case DDC_CRT2:
 537                 if (rdev->family == CHIP_R200 ||
 538                     rdev->family == CHIP_R300 ||
 539                     rdev->family == CHIP_R350) {
 540                         ddc_line = RADEON_GPIO_DVI_DDC;
 541                         ddc = DDC_DVI;
 542                 } else if (rdev->family == CHIP_RS300 ||
 543                            rdev->family == CHIP_RS400 ||
 544                            rdev->family == CHIP_RS480)
 545                         ddc_line = RADEON_GPIO_MONID;
 546                 else if (rdev->family >= CHIP_RV350) {
 547                         ddc_line = RADEON_GPIO_MONID;
 548                         ddc = DDC_MONID;
 549                 } else
 550                         ddc_line = RADEON_GPIO_CRT2_DDC;
 551                 break;
 552         }
 553
 554         if (ddc_line == RADEON_GPIOPAD_MASK) {
 555                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 556                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 557                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 558                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 559                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 560                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 561                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 562                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 563         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 564                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 565                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 566                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 567                 i2c.a_data_reg = RADEON_MDGPIO_A;
 568                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 569                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 570                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 571                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 572         } else {
 573                 i2c.mask_clk_reg = ddc_line;
 574                 i2c.mask_data_reg = ddc_line;
 575                 i2c.a_clk_reg = ddc_line;
 576                 i2c.a_data_reg = ddc_line;
 577                 i2c.en_clk_reg = ddc_line;
 578                 i2c.en_data_reg = ddc_line;
 579                 i2c.y_clk_reg = ddc_line;
 580                 i2c.y_data_reg = ddc_line;
 581         }
 582
 583         if (clk_mask && data_mask) {
 584                 /* system specific masks */
 585                 i2c.mask_clk_mask = clk_mask;
 586                 i2c.mask_data_mask = data_mask;
 587                 i2c.a_clk_mask = clk_mask;
 588                 i2c.a_data_mask = data_mask;
 589                 i2c.en_clk_mask = clk_mask;
 590                 i2c.en_data_mask = data_mask;
 591                 i2c.y_clk_mask = clk_mask;
 592                 i2c.y_data_mask = data_mask;
 593         } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
 594                    (ddc_line == RADEON_MDGPIO_MASK)) {
 595                 /* default gpiopad masks */
 596                 i2c.mask_clk_mask = (0x20 << 8);
 597                 i2c.mask_data_mask = 0x80;
 598                 i2c.a_clk_mask = (0x20 << 8);
 599                 i2c.a_data_mask = 0x80;
 600                 i2c.en_clk_mask = (0x20 << 8);
 601                 i2c.en_data_mask = 0x80;
 602                 i2c.y_clk_mask = (0x20 << 8);
 603                 i2c.y_data_mask = 0x80;
 604         } else {
 605                 /* default masks for ddc pads */
 606                 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
 607                 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
 608                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 609                 i2c.a_data_mask = RADEON_GPIO_A_0;
 610                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 611                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 612                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 613                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 614         }
 615
 616         switch (rdev->family) {
 617         case CHIP_R100:
 618         case CHIP_RV100:
 619         case CHIP_RS100:
 620         case CHIP_RV200:
 621         case CHIP_RS200:
 622         case CHIP_RS300:
 623                 switch (ddc_line) {
 624                 case RADEON_GPIO_DVI_DDC:
 625                         i2c.hw_capable = true;
 626                         break;
 627                 default:
 628                         i2c.hw_capable = false;
 629                         break;
 630                 }
 631                 break;
 632         case CHIP_R200:
 633                 switch (ddc_line) {
 634                 case RADEON_GPIO_DVI_DDC:
 635                 case RADEON_GPIO_MONID:
 636                         i2c.hw_capable = true;
 637                         break;
 638                 default:
 639                         i2c.hw_capable = false;
 640                         break;
 641                 }
 642                 break;
 643         case CHIP_RV250:
 644         case CHIP_RV280:
 645                 switch (ddc_line) {
 646                 case RADEON_GPIO_VGA_DDC:
 647                 case RADEON_GPIO_DVI_DDC:
 648                 case RADEON_GPIO_CRT2_DDC:
 649                         i2c.hw_capable = true;
 650                         break;
 651                 default:
 652                         i2c.hw_capable = false;
 653                         break;
 654                 }
 655                 break;
 656         case CHIP_R300:
 657         case CHIP_R350:
 658                 switch (ddc_line) {
 659                 case RADEON_GPIO_VGA_DDC:
 660                 case RADEON_GPIO_DVI_DDC:
 661                         i2c.hw_capable = true;
 662                         break;
 663                 default:
 664                         i2c.hw_capable = false;
 665                         break;
 666                 }
 667                 break;
 668         case CHIP_RV350:
 669         case CHIP_RV380:
 670         case CHIP_RS400:
 671         case CHIP_RS480:
 672                 switch (ddc_line) {
 673                 case RADEON_GPIO_VGA_DDC:
 674                 case RADEON_GPIO_DVI_DDC:
 675                         i2c.hw_capable = true;
 676                         break;
 677                 case RADEON_GPIO_MONID:
 678                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 679                          * reliably on some pre-r4xx hardware; not sure why.
 680                          */
 681                         i2c.hw_capable = false;
 682                         break;
 683                 default:
 684                         i2c.hw_capable = false;
 685                         break;
 686                 }
 687                 break;
 688         default:
 689                 i2c.hw_capable = false;
 690                 break;
 691         }
 692         i2c.mm_i2c = false;
 693
 694         i2c.i2c_id = ddc;
 695         i2c.hpd = RADEON_HPD_NONE;
 696
 697         if (ddc_line)
 698                 i2c.valid = true;
 699         else
 700                 i2c.valid = false;
 701
 702         return i2c;
 703 }
 704
 705 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)
 706 {
 707         struct drm_device *dev = rdev->ddev;
 708         struct radeon_i2c_bus_rec i2c;
 709         u16 offset;
 710         u8 id, blocks, clk, data;
 711         int i;
 712
 713         i2c.valid = false;
 714
 715         offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
 716         if (offset) {
 717                 blocks = RBIOS8(offset + 2);
 718                 for (i = 0; i < blocks; i++) {
 719                         id = RBIOS8(offset + 3 + (i * 5) + 0);
 720                         if (id == 136) {
 721                                 clk = RBIOS8(offset + 3 + (i * 5) + 3);
 722                                 data = RBIOS8(offset + 3 + (i * 5) + 4);
 723                                 /* gpiopad */
 724                                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
 725                                                             (1 << clk), (1 << data));
 726                                 break;
 727                         }
 728                 }
 729         }
 730         return i2c;
 731 }
 732
 733 void radeon_combios_i2c_init(struct radeon_device *rdev)
 734 {
 735         struct drm_device *dev = rdev->ddev;
 736         struct radeon_i2c_bus_rec i2c;
 737
 738         /* actual hw pads
 739          * r1xx/rs2xx/rs3xx
 740          * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
 741          * r200
 742          * 0x60, 0x64, 0x68, mm
 743          * r300/r350
 744          * 0x60, 0x64, mm
 745          * rv2xx/rv3xx/rs4xx
 746          * 0x60, 0x64, 0x68, gpiopads, mm
 747          */
 748
 749         /* 0x60 */
 750         i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
 751         rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
 752         /* 0x64 */
 753         i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
 754         rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
 755
 756         /* mm i2c */
 757         i2c.valid = true;
 758         i2c.hw_capable = true;
 759         i2c.mm_i2c = true;
 760         i2c.i2c_id = 0xa0;
 761         rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
 762
 763         if (rdev->family == CHIP_R300 ||
 764             rdev->family == CHIP_R350) {
 765                 /* only 2 sw i2c pads */
 766         } else if (rdev->family == CHIP_RS300 ||
 767                    rdev->family == CHIP_RS400 ||
 768                    rdev->family == CHIP_RS480) {
 769                 /* 0x68 */
 770                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 771                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 772
 773                 /* gpiopad */
 774                 i2c = radeon_combios_get_i2c_info_from_table(rdev);
 775                 if (i2c.valid)
 776                         rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
 777         } else if ((rdev->family == CHIP_R200) ||
 778                    (rdev->family >= CHIP_R300)) {
 779                 /* 0x68 */
 780                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 781                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 782         } else {
 783                 /* 0x68 */
 784                 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
 785                 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
 786                 /* 0x6c */
 787                 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
 788                 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
 789         }
 790 }
 791
 792 bool radeon_combios_get_clock_info(struct drm_device *dev)
 793 {
 794         struct radeon_device *rdev = dev->dev_private;
 795         uint16_t pll_info;
 796         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 797         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 798         struct radeon_pll *spll = &rdev->clock.spll;
 799         struct radeon_pll *mpll = &rdev->clock.mpll;
 800         int8_t rev;
 801         uint16_t sclk, mclk;
 802
 803         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 804         if (pll_info) {
 805                 rev = RBIOS8(pll_info);
 806
 807                 /* pixel clocks */
 808                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 809                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 810                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 811                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 812                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 813                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 814
 815                 if (rev > 9) {
 816                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 817                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 818                 } else {
 819                         p1pll->pll_in_min = 40;
 820                         p1pll->pll_in_max = 500;
 821                 }
 822                 *p2pll = *p1pll;
 823
 824                 /* system clock */
 825                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 826                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 827                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 828                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 829
 830                 if (rev > 10) {
 831                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 832                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 833                 } else {
 834                         /* ??? */
 835                         spll->pll_in_min = 40;
 836                         spll->pll_in_max = 500;
 837                 }
 838
 839                 /* memory clock */
 840                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 841                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 842                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 843                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 844
 845                 if (rev > 10) {
 846                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 847                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 848                 } else {
 849                         /* ??? */
 850                         mpll->pll_in_min = 40;
 851                         mpll->pll_in_max = 500;
 852                 }
 853
 854                 /* default sclk/mclk */
 855                 sclk = RBIOS16(pll_info + 0xa);
 856                 mclk = RBIOS16(pll_info + 0x8);
 857                 if (sclk == 0)
 858                         sclk = 200 * 100;
 859                 if (mclk == 0)
 860                         mclk = 200 * 100;
 861
 862                 rdev->clock.default_sclk = sclk;
 863                 rdev->clock.default_mclk = mclk;
 864
 865                 if (RBIOS32(pll_info + 0x16))
 866                         rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
 867                 else
 868                         rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
 869
 870                 return true;
 871         }
 872         return false;
 873 }
 874
 875 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 876 {
 877         struct drm_device *dev = rdev->ddev;
 878         u16 igp_info;
 879
 880         /* sideport is AMD only */
 881         if (rdev->family == CHIP_RS400)
 882                 return false;
 883
 884         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 885
 886         if (igp_info) {
 887                 if (RBIOS16(igp_info + 0x4))
 888                         return true;
 889         }
 890         return false;
 891 }
 892
 893 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 894         0x00000808,             /* r100  */
 895         0x00000808,             /* rv100 */
 896         0x00000808,             /* rs100 */
 897         0x00000808,             /* rv200 */
 898         0x00000808,             /* rs200 */
 899         0x00000808,             /* r200  */
 900         0x00000808,             /* rv250 */
 901         0x00000000,             /* rs300 */
 902         0x00000808,             /* rv280 */
 903         0x00000808,             /* r300  */
 904         0x00000808,             /* r350  */
 905         0x00000808,             /* rv350 */
 906         0x00000808,             /* rv380 */
 907         0x00000808,             /* r420  */
 908         0x00000808,             /* r423  */
 909         0x00000808,             /* rv410 */
 910         0x00000000,             /* rs400 */
 911         0x00000000,             /* rs480 */
 912 };
 913
 914 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 915                                                           struct radeon_encoder_primary_dac *p_dac)
 916 {
 917         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 918         return;
 919 }
 920
 921 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 922                                                                        radeon_encoder
 923                                                                        *encoder)
 924 {
 925         struct drm_device *dev = encoder->base.dev;
 926         struct radeon_device *rdev = dev->dev_private;
 927         uint16_t dac_info;
 928         uint8_t rev, bg, dac;
 929         struct radeon_encoder_primary_dac *p_dac = NULL;
 930         int found = 0;
 931
 932         p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac),
 933                         M_DRM, M_WAITOK | M_ZERO);
 934
 935         if (!p_dac)
 936                 return NULL;
 937
 938         /* check CRT table */
 939         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 940         if (dac_info) {
 941                 rev = RBIOS8(dac_info) & 0x3;
 942                 if (rev < 2) {
 943                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 944                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 945                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 946                 } else {
 947                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 948                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 949                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 950                 }
 951                 /* if the values are all zeros, use the table */
 952                 if (p_dac->ps2_pdac_adj)
 953                         found = 1;
 954         }
 955
 956         /* quirks */
 957         /* Radeon 9100 (R200) */
 958         if ((rdev->ddev->pci_device == 0x514D) &&
 959             (rdev->ddev->pci_subvendor == 0x174B) &&
 960             (rdev->ddev->pci_subdevice == 0x7149)) {
 961                 /* vbios value is bad, use the default */
 962                 found = 0;
 963         }
 964
 965         if (!found) /* fallback to defaults */
 966                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 967
 968         return p_dac;
 969 }
 970
 971 enum radeon_tv_std
 972 radeon_combios_get_tv_info(struct radeon_device *rdev)
 973 {
 974         struct drm_device *dev = rdev->ddev;
 975         uint16_t tv_info;
 976         enum radeon_tv_std tv_std = TV_STD_NTSC;
 977
 978         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 979         if (tv_info) {
 980                 if (RBIOS8(tv_info + 6) == 'T') {
 981                         switch (RBIOS8(tv_info + 7) & 0xf) {
 982                         case 1:
 983                                 tv_std = TV_STD_NTSC;
 984                                 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
 985                                 break;
 986                         case 2:
 987                                 tv_std = TV_STD_PAL;
 988                                 DRM_DEBUG_KMS("Default TV standard: PAL\n");
 989                                 break;
 990                         case 3:
 991                                 tv_std = TV_STD_PAL_M;
 992                                 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
 993                                 break;
 994                         case 4:
 995                                 tv_std = TV_STD_PAL_60;
 996                                 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
 997                                 break;
 998                         case 5:
 999                                 tv_std = TV_STD_NTSC_J;
1000                                 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1001                                 break;
1002                         case 6:
1003                                 tv_std = TV_STD_SCART_PAL;
1004                                 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1005                                 break;
1006                         default:
1007                                 tv_std = TV_STD_NTSC;
1008                                 DRM_DEBUG_KMS
1009                                     ("Unknown TV standard; defaulting to NTSC\n");
1010                                 break;
1011                         }
1012
1013                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1014                         case 0:
1015                                 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1016                                 break;
1017                         case 1:
1018                                 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1019                                 break;
1020                         case 2:
1021                                 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1022                                 break;
1023                         case 3:
1024                                 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1025                                 break;
1026                         default:
1027                                 break;
1028                         }
1029                 }
1030         }
1031         return tv_std;
1032 }
1033
1034 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1035         0x00000000,             /* r100  */
1036         0x00280000,             /* rv100 */
1037         0x00000000,             /* rs100 */
1038         0x00880000,             /* rv200 */
1039         0x00000000,             /* rs200 */
1040         0x00000000,             /* r200  */
1041         0x00770000,             /* rv250 */
1042         0x00290000,             /* rs300 */
1043         0x00560000,             /* rv280 */
1044         0x00780000,             /* r300  */
1045         0x00770000,             /* r350  */
1046         0x00780000,             /* rv350 */
1047         0x00780000,             /* rv380 */
1048         0x01080000,             /* r420  */
1049         0x01080000,             /* r423  */
1050         0x01080000,             /* rv410 */
1051         0x00780000,             /* rs400 */
1052         0x00780000,             /* rs480 */
1053 };
1054
1055 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1056                                                      struct radeon_encoder_tv_dac *tv_dac)
1057 {
1058         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1059         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1060                 tv_dac->ps2_tvdac_adj = 0x00880000;
1061         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1062         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1063         return;
1064 }
1065
1066 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1067                                                              radeon_encoder
1068                                                              *encoder)
1069 {
1070         struct drm_device *dev = encoder->base.dev;
1071         struct radeon_device *rdev = dev->dev_private;
1072         uint16_t dac_info;
1073         uint8_t rev, bg, dac;
1074         struct radeon_encoder_tv_dac *tv_dac = NULL;
1075         int found = 0;
1076
1077         tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac),
1078                          M_DRM, M_WAITOK | M_ZERO);
1079         if (!tv_dac)
1080                 return NULL;
1081
1082         /* first check TV table */
1083         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1084         if (dac_info) {
1085                 rev = RBIOS8(dac_info + 0x3);
1086                 if (rev > 4) {
1087                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1088                         dac = RBIOS8(dac_info + 0xd) & 0xf;
1089                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1090
1091                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1092                         dac = RBIOS8(dac_info + 0xf) & 0xf;
1093                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1094
1095                         bg = RBIOS8(dac_info + 0x10) & 0xf;
1096                         dac = RBIOS8(dac_info + 0x11) & 0xf;
1097                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1098                         /* if the values are all zeros, use the table */
1099                         if (tv_dac->ps2_tvdac_adj)
1100                                 found = 1;
1101                 } else if (rev > 1) {
1102                         bg = RBIOS8(dac_info + 0xc) & 0xf;
1103                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1104                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1105
1106                         bg = RBIOS8(dac_info + 0xd) & 0xf;
1107                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1108                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1109
1110                         bg = RBIOS8(dac_info + 0xe) & 0xf;
1111                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1112                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1113                         /* if the values are all zeros, use the table */
1114                         if (tv_dac->ps2_tvdac_adj)
1115                                 found = 1;
1116                 }
1117                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1118         }
1119         if (!found) {
1120                 /* then check CRT table */
1121                 dac_info =
1122                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1123                 if (dac_info) {
1124                         rev = RBIOS8(dac_info) & 0x3;
1125                         if (rev < 2) {
1126                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
1127                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1128                                 tv_dac->ps2_tvdac_adj =
1129                                     (bg << 16) | (dac << 20);
1130                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1131                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1132                                 /* if the values are all zeros, use the table */
1133                                 if (tv_dac->ps2_tvdac_adj)
1134                                         found = 1;
1135                         } else {
1136                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
1137                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
1138                                 tv_dac->ps2_tvdac_adj =
1139                                     (bg << 16) | (dac << 20);
1140                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1141                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1142                                 /* if the values are all zeros, use the table */
1143                                 if (tv_dac->ps2_tvdac_adj)
1144                                         found = 1;
1145                         }
1146                 } else {
1147                         DRM_INFO("No TV DAC info found in BIOS\n");
1148                 }
1149         }
1150
1151         if (!found) /* fallback to defaults */
1152                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1153
1154         return tv_dac;
1155 }
1156
1157 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1158                                                                          radeon_device
1159                                                                          *rdev)
1160 {
1161         struct radeon_encoder_lvds *lvds = NULL;
1162         uint32_t fp_vert_stretch, fp_horz_stretch;
1163         uint32_t ppll_div_sel, ppll_val;
1164         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1165
1166         lvds = kmalloc(sizeof(struct radeon_encoder_lvds), M_DRM,
1167                        M_WAITOK | M_ZERO);
1168
1169         if (!lvds)
1170                 return NULL;
1171
1172         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1173         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1174
1175         /* These should be fail-safe defaults, fingers crossed */
1176         lvds->panel_pwr_delay = 200;
1177         lvds->panel_vcc_delay = 2000;
1178
1179         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1180         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1181         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1182
1183         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1184                 lvds->native_mode.vdisplay =
1185                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1186                      RADEON_VERT_PANEL_SHIFT) + 1;
1187         else
1188                 lvds->native_mode.vdisplay =
1189                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1190
1191         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1192                 lvds->native_mode.hdisplay =
1193                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1194                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1195         else
1196                 lvds->native_mode.hdisplay =
1197                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1198
1199         if ((lvds->native_mode.hdisplay < 640) ||
1200             (lvds->native_mode.vdisplay < 480)) {
1201                 lvds->native_mode.hdisplay = 640;
1202                 lvds->native_mode.vdisplay = 480;
1203         }
1204
1205         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1206         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1207         if ((ppll_val & 0x000707ff) == 0x1bb)
1208                 lvds->use_bios_dividers = false;
1209         else {
1210                 lvds->panel_ref_divider =
1211                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1212                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1213                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1214
1215                 if ((lvds->panel_ref_divider != 0) &&
1216                     (lvds->panel_fb_divider > 3))
1217                         lvds->use_bios_dividers = true;
1218         }
1219         lvds->panel_vcc_delay = 200;
1220
1221         DRM_INFO("Panel info derived from registers\n");
1222         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1223                  lvds->native_mode.vdisplay);
1224
1225         return lvds;
1226 }
1227
1228 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1229                                                          *encoder)
1230 {
1231         struct drm_device *dev = encoder->base.dev;
1232         struct radeon_device *rdev = dev->dev_private;
1233         uint16_t lcd_info;
1234         uint32_t panel_setup;
1235         char stmp[30];
1236         int tmp, i;
1237         struct radeon_encoder_lvds *lvds = NULL;
1238
1239         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1240
1241         if (lcd_info) {
1242                 lvds = kmalloc(sizeof(struct radeon_encoder_lvds),
1243                                M_DRM, M_WAITOK | M_ZERO);
1244
1245                 if (!lvds)
1246                         return NULL;
1247
1248                 for (i = 0; i < 24; i++)
1249                         stmp[i] = RBIOS8(lcd_info + i + 1);
1250                 stmp[24] = 0;
1251
1252                 DRM_INFO("Panel ID String: %s\n", stmp);
1253
1254                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1255                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1256
1257                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1258                          lvds->native_mode.vdisplay);
1259
1260                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1261                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1262
1263                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1264                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1265                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1266
1267                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1268                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1269                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1270                 if ((lvds->panel_ref_divider != 0) &&
1271                     (lvds->panel_fb_divider > 3))
1272                         lvds->use_bios_dividers = true;
1273
1274                 panel_setup = RBIOS32(lcd_info + 0x39);
1275                 lvds->lvds_gen_cntl = 0xff00;
1276                 if (panel_setup & 0x1)
1277                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1278
1279                 if ((panel_setup >> 4) & 0x1)
1280                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1281
1282                 switch ((panel_setup >> 8) & 0x7) {
1283                 case 0:
1284                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1285                         break;
1286                 case 1:
1287                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1288                         break;
1289                 case 2:
1290                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1291                         break;
1292                 default:
1293                         break;
1294                 }
1295
1296                 if ((panel_setup >> 16) & 0x1)
1297                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1298
1299                 if ((panel_setup >> 17) & 0x1)
1300                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1301
1302                 if ((panel_setup >> 18) & 0x1)
1303                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1304
1305                 if ((panel_setup >> 23) & 0x1)
1306                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1307
1308                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1309
1310                 for (i = 0; i < 32; i++) {
1311                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1312                         if (tmp == 0)
1313                                 break;
1314
1315                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1316                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1317                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1318                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1319                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1320                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1321                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1322                                         (RBIOS8(tmp + 23) * 8);
1323
1324                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1325                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1326                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1327                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1328                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1329                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1330
1331                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1332                                 lvds->native_mode.flags = 0;
1333                                 /* set crtc values */
1334                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1335
1336                         }
1337                 }
1338         } else {
1339                 DRM_INFO("No panel info found in BIOS\n");
1340                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1341         }
1342
1343         if (lvds)
1344                 encoder->native_mode = lvds->native_mode;
1345         return lvds;
1346 }
1347
1348 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1349         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1350         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1351         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1352         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1353         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1354         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1355         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1356         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1357         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1358         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1359         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1360         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1361         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1362         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1363         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1364         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1365         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1366         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1367 };
1368
1369 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1370                                             struct radeon_encoder_int_tmds *tmds)
1371 {
1372         struct drm_device *dev = encoder->base.dev;
1373         struct radeon_device *rdev = dev->dev_private;
1374         int i;
1375
1376         for (i = 0; i < 4; i++) {
1377                 tmds->tmds_pll[i].value =
1378                         default_tmds_pll[rdev->family][i].value;
1379                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1380         }
1381
1382         return true;
1383 }
1384
1385 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1386                                               struct radeon_encoder_int_tmds *tmds)
1387 {
1388         struct drm_device *dev = encoder->base.dev;
1389         struct radeon_device *rdev = dev->dev_private;
1390         uint16_t tmds_info;
1391         int i, n;
1392         uint8_t ver;
1393
1394         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1395
1396         if (tmds_info) {
1397                 ver = RBIOS8(tmds_info);
1398                 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1399                 if (ver == 3) {
1400                         n = RBIOS8(tmds_info + 5) + 1;
1401                         if (n > 4)
1402                                 n = 4;
1403                         for (i = 0; i < n; i++) {
1404                                 tmds->tmds_pll[i].value =
1405                                     RBIOS32(tmds_info + i * 10 + 0x08);
1406                                 tmds->tmds_pll[i].freq =
1407                                     RBIOS16(tmds_info + i * 10 + 0x10);
1408                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1409                                           tmds->tmds_pll[i].freq,
1410                                           tmds->tmds_pll[i].value);
1411                         }
1412                 } else if (ver == 4) {
1413                         int stride = 0;
1414                         n = RBIOS8(tmds_info + 5) + 1;
1415                         if (n > 4)
1416                                 n = 4;
1417                         for (i = 0; i < n; i++) {
1418                                 tmds->tmds_pll[i].value =
1419                                     RBIOS32(tmds_info + stride + 0x08);
1420                                 tmds->tmds_pll[i].freq =
1421                                     RBIOS16(tmds_info + stride + 0x10);
1422                                 if (i == 0)
1423                                         stride += 10;
1424                                 else
1425                                         stride += 6;
1426                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1427                                           tmds->tmds_pll[i].freq,
1428                                           tmds->tmds_pll[i].value);
1429                         }
1430                 }
1431         } else {
1432                 DRM_INFO("No TMDS info found in BIOS\n");
1433                 return false;
1434         }
1435         return true;
1436 }
1437
1438 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1439                                                 struct radeon_encoder_ext_tmds *tmds)
1440 {
1441         struct drm_device *dev = encoder->base.dev;
1442         struct radeon_device *rdev = dev->dev_private;
1443         struct radeon_i2c_bus_rec i2c_bus;
1444
1445         /* default for macs */
1446         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1447         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1448
1449         /* XXX some macs have duallink chips */
1450         switch (rdev->mode_info.connector_table) {
1451         case CT_POWERBOOK_EXTERNAL:
1452         case CT_MINI_EXTERNAL:
1453         default:
1454                 tmds->dvo_chip = DVO_SIL164;
1455                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1456                 break;
1457         }
1458
1459         return true;
1460 }
1461
1462 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1463                                                   struct radeon_encoder_ext_tmds *tmds)
1464 {
1465         struct drm_device *dev = encoder->base.dev;
1466         struct radeon_device *rdev = dev->dev_private;
1467         uint16_t offset;
1468         uint8_t ver;
1469         enum radeon_combios_ddc gpio;
1470         struct radeon_i2c_bus_rec i2c_bus;
1471
1472         tmds->i2c_bus = NULL;
1473         if (rdev->flags & RADEON_IS_IGP) {
1474                 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1475                 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1476                 tmds->dvo_chip = DVO_SIL164;
1477                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1478         } else {
1479                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1480                 if (offset) {
1481                         ver = RBIOS8(offset);
1482                         DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1483                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1484                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1485                         gpio = RBIOS8(offset + 4 + 3);
1486                         if (gpio == DDC_LCD) {
1487                                 /* MM i2c */
1488                                 i2c_bus.valid = true;
1489                                 i2c_bus.hw_capable = true;
1490                                 i2c_bus.mm_i2c = true;
1491                                 i2c_bus.i2c_id = 0xa0;
1492                         } else
1493                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1494                         tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1495                 }
1496         }
1497
1498         if (!tmds->i2c_bus) {
1499                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1500                 return false;
1501         }
1502
1503         return true;
1504 }
1505
1506 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1507 {
1508         struct radeon_device *rdev = dev->dev_private;
1509         struct radeon_i2c_bus_rec ddc_i2c;
1510         struct radeon_hpd hpd;
1511
1512         rdev->mode_info.connector_table = radeon_connector_table;
1513         if (rdev->mode_info.connector_table == CT_NONE) {
1514 #ifdef CONFIG_PPC_PMAC
1515                 if (of_machine_is_compatible("PowerBook3,3")) {
1516                         /* powerbook with VGA */
1517                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1518                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1519                            of_machine_is_compatible("PowerBook3,5")) {
1520                         /* powerbook with internal tmds */
1521                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1522                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1523                            of_machine_is_compatible("PowerBook5,2") ||
1524                            of_machine_is_compatible("PowerBook5,3") ||
1525                            of_machine_is_compatible("PowerBook5,4") ||
1526                            of_machine_is_compatible("PowerBook5,5")) {
1527                         /* powerbook with external single link tmds (sil164) */
1528                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1529                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1530                         /* powerbook with external dual or single link tmds */
1531                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1532                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1533                            of_machine_is_compatible("PowerBook5,8") ||
1534                            of_machine_is_compatible("PowerBook5,9")) {
1535                         /* PowerBook6,2 ? */
1536                         /* powerbook with external dual link tmds (sil1178?) */
1537                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1538                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1539                            of_machine_is_compatible("PowerBook4,2") ||
1540                            of_machine_is_compatible("PowerBook4,3") ||
1541                            of_machine_is_compatible("PowerBook6,3") ||
1542                            of_machine_is_compatible("PowerBook6,5") ||
1543                            of_machine_is_compatible("PowerBook6,7")) {
1544                         /* ibook */
1545                         rdev->mode_info.connector_table = CT_IBOOK;
1546                 } else if (of_machine_is_compatible("PowerMac3,5")) {
1547                         /* PowerMac G4 Silver radeon 7500 */
1548                         rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1549                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1550                         /* emac */
1551                         rdev->mode_info.connector_table = CT_EMAC;
1552                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1553                         /* mini with internal tmds */
1554                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1555                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1556                         /* mini with external tmds */
1557                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1558                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1559                         /* PowerMac8,1 ? */
1560                         /* imac g5 isight */
1561                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1562                 } else if ((dev->pci_device == 0x4a48) &&
1563                            (dev->pci_subvendor == 0x1002) &&
1564                            (dev->pci_subdevice == 0x4a48)) {
1565                         /* Mac X800 */
1566                         rdev->mode_info.connector_table = CT_MAC_X800;
1567                 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1568                             of_machine_is_compatible("PowerMac7,3")) &&
1569                            (dev->pci_device == 0x4150) &&
1570                            (dev->pci_subvendor == 0x1002) &&
1571                            (dev->pci_subdevice == 0x4150)) {
1572                         /* Mac G5 tower 9600 */
1573                         rdev->mode_info.connector_table = CT_MAC_G5_9600;
1574                 } else if ((dev->pci_device == 0x4c66) &&
1575                            (dev->pci_subvendor == 0x1002) &&
1576                            (dev->pci_subdevice == 0x4c66)) {
1577                         /* SAM440ep RV250 embedded board */
1578                         rdev->mode_info.connector_table = CT_SAM440EP;
1579                 } else
1580 #endif /* CONFIG_PPC_PMAC */
1581 #ifdef CONFIG_PPC64
1582                 if (ASIC_IS_RN50(rdev))
1583                         rdev->mode_info.connector_table = CT_RN50_POWER;
1584                 else
1585 #endif
1586                         rdev->mode_info.connector_table = CT_GENERIC;
1587         }
1588
1589         switch (rdev->mode_info.connector_table) {
1590         case CT_GENERIC:
1591                 DRM_INFO("Connector Table: %d (generic)\n",
1592                          rdev->mode_info.connector_table);
1593                 /* these are the most common settings */
1594                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1595                         /* VGA - primary dac */
1596                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1597                         hpd.hpd = RADEON_HPD_NONE;
1598                         radeon_add_legacy_encoder(dev,
1599                                                   radeon_get_encoder_enum(dev,
1600                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1601                                                                         1),
1602                                                   ATOM_DEVICE_CRT1_SUPPORT);
1603                         radeon_add_legacy_connector(dev, 0,
1604                                                     ATOM_DEVICE_CRT1_SUPPORT,
1605                                                     DRM_MODE_CONNECTOR_VGA,
1606                                                     &ddc_i2c,
1607                                                     CONNECTOR_OBJECT_ID_VGA,
1608                                                     &hpd);
1609                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1610                         /* LVDS */
1611                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1612                         hpd.hpd = RADEON_HPD_NONE;
1613                         radeon_add_legacy_encoder(dev,
1614                                                   radeon_get_encoder_enum(dev,
1615                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1616                                                                         0),
1617                                                   ATOM_DEVICE_LCD1_SUPPORT);
1618                         radeon_add_legacy_connector(dev, 0,
1619                                                     ATOM_DEVICE_LCD1_SUPPORT,
1620                                                     DRM_MODE_CONNECTOR_LVDS,
1621                                                     &ddc_i2c,
1622                                                     CONNECTOR_OBJECT_ID_LVDS,
1623                                                     &hpd);
1624
1625                         /* VGA - primary dac */
1626                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1627                         hpd.hpd = RADEON_HPD_NONE;
1628                         radeon_add_legacy_encoder(dev,
1629                                                   radeon_get_encoder_enum(dev,
1630                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1631                                                                         1),
1632                                                   ATOM_DEVICE_CRT1_SUPPORT);
1633                         radeon_add_legacy_connector(dev, 1,
1634                                                     ATOM_DEVICE_CRT1_SUPPORT,
1635                                                     DRM_MODE_CONNECTOR_VGA,
1636                                                     &ddc_i2c,
1637                                                     CONNECTOR_OBJECT_ID_VGA,
1638                                                     &hpd);
1639                 } else {
1640                         /* DVI-I - tv dac, int tmds */
1641                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1642                         hpd.hpd = RADEON_HPD_1;
1643                         radeon_add_legacy_encoder(dev,
1644                                                   radeon_get_encoder_enum(dev,
1645                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1646                                                                         0),
1647                                                   ATOM_DEVICE_DFP1_SUPPORT);
1648                         radeon_add_legacy_encoder(dev,
1649                                                   radeon_get_encoder_enum(dev,
1650                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1651                                                                         2),
1652                                                   ATOM_DEVICE_CRT2_SUPPORT);
1653                         radeon_add_legacy_connector(dev, 0,
1654                                                     ATOM_DEVICE_DFP1_SUPPORT |
1655                                                     ATOM_DEVICE_CRT2_SUPPORT,
1656                                                     DRM_MODE_CONNECTOR_DVII,
1657                                                     &ddc_i2c,
1658                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1659                                                     &hpd);
1660
1661                         /* VGA - primary dac */
1662                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1663                         hpd.hpd = RADEON_HPD_NONE;
1664                         radeon_add_legacy_encoder(dev,
1665                                                   radeon_get_encoder_enum(dev,
1666                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1667                                                                         1),
1668                                                   ATOM_DEVICE_CRT1_SUPPORT);
1669                         radeon_add_legacy_connector(dev, 1,
1670                                                     ATOM_DEVICE_CRT1_SUPPORT,
1671                                                     DRM_MODE_CONNECTOR_VGA,
1672                                                     &ddc_i2c,
1673                                                     CONNECTOR_OBJECT_ID_VGA,
1674                                                     &hpd);
1675                 }
1676
1677                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1678                         /* TV - tv dac */
1679                         ddc_i2c.valid = false;
1680                         hpd.hpd = RADEON_HPD_NONE;
1681                         radeon_add_legacy_encoder(dev,
1682                                                   radeon_get_encoder_enum(dev,
1683                                                                         ATOM_DEVICE_TV1_SUPPORT,
1684                                                                         2),
1685                                                   ATOM_DEVICE_TV1_SUPPORT);
1686                         radeon_add_legacy_connector(dev, 2,
1687                                                     ATOM_DEVICE_TV1_SUPPORT,
1688                                                     DRM_MODE_CONNECTOR_SVIDEO,
1689                                                     &ddc_i2c,
1690                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1691                                                     &hpd);
1692                 }
1693                 break;
1694         case CT_IBOOK:
1695                 DRM_INFO("Connector Table: %d (ibook)\n",
1696                          rdev->mode_info.connector_table);
1697                 /* LVDS */
1698                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1699                 hpd.hpd = RADEON_HPD_NONE;
1700                 radeon_add_legacy_encoder(dev,
1701                                           radeon_get_encoder_enum(dev,
1702                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1703                                                                 0),
1704                                           ATOM_DEVICE_LCD1_SUPPORT);
1705                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1706                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1707                                             CONNECTOR_OBJECT_ID_LVDS,
1708                                             &hpd);
1709                 /* VGA - TV DAC */
1710                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1711                 hpd.hpd = RADEON_HPD_NONE;
1712                 radeon_add_legacy_encoder(dev,
1713                                           radeon_get_encoder_enum(dev,
1714                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1715                                                                 2),
1716                                           ATOM_DEVICE_CRT2_SUPPORT);
1717                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1718                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1719                                             CONNECTOR_OBJECT_ID_VGA,
1720                                             &hpd);
1721                 /* TV - TV DAC */
1722                 ddc_i2c.valid = false;
1723                 hpd.hpd = RADEON_HPD_NONE;
1724                 radeon_add_legacy_encoder(dev,
1725                                           radeon_get_encoder_enum(dev,
1726                                                                 ATOM_DEVICE_TV1_SUPPORT,
1727                                                                 2),
1728                                           ATOM_DEVICE_TV1_SUPPORT);
1729                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1730                                             DRM_MODE_CONNECTOR_SVIDEO,
1731                                             &ddc_i2c,
1732                                             CONNECTOR_OBJECT_ID_SVIDEO,
1733                                             &hpd);
1734                 break;
1735         case CT_POWERBOOK_EXTERNAL:
1736                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1737                          rdev->mode_info.connector_table);
1738                 /* LVDS */
1739                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1740                 hpd.hpd = RADEON_HPD_NONE;
1741                 radeon_add_legacy_encoder(dev,
1742                                           radeon_get_encoder_enum(dev,
1743                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1744                                                                 0),
1745                                           ATOM_DEVICE_LCD1_SUPPORT);
1746                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1747                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1748                                             CONNECTOR_OBJECT_ID_LVDS,
1749                                             &hpd);
1750                 /* DVI-I - primary dac, ext tmds */
1751                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1752                 hpd.hpd = RADEON_HPD_2; /* ??? */
1753                 radeon_add_legacy_encoder(dev,
1754                                           radeon_get_encoder_enum(dev,
1755                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1756                                                                 0),
1757                                           ATOM_DEVICE_DFP2_SUPPORT);
1758                 radeon_add_legacy_encoder(dev,
1759                                           radeon_get_encoder_enum(dev,
1760                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1761                                                                 1),
1762                                           ATOM_DEVICE_CRT1_SUPPORT);
1763                 /* XXX some are SL */
1764                 radeon_add_legacy_connector(dev, 1,
1765                                             ATOM_DEVICE_DFP2_SUPPORT |
1766                                             ATOM_DEVICE_CRT1_SUPPORT,
1767                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1768                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1769                                             &hpd);
1770                 /* TV - TV DAC */
1771                 ddc_i2c.valid = false;
1772                 hpd.hpd = RADEON_HPD_NONE;
1773                 radeon_add_legacy_encoder(dev,
1774                                           radeon_get_encoder_enum(dev,
1775                                                                 ATOM_DEVICE_TV1_SUPPORT,
1776                                                                 2),
1777                                           ATOM_DEVICE_TV1_SUPPORT);
1778                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1779                                             DRM_MODE_CONNECTOR_SVIDEO,
1780                                             &ddc_i2c,
1781                                             CONNECTOR_OBJECT_ID_SVIDEO,
1782                                             &hpd);
1783                 break;
1784         case CT_POWERBOOK_INTERNAL:
1785                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1786                          rdev->mode_info.connector_table);
1787                 /* LVDS */
1788                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1789                 hpd.hpd = RADEON_HPD_NONE;
1790                 radeon_add_legacy_encoder(dev,
1791                                           radeon_get_encoder_enum(dev,
1792                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1793                                                                 0),
1794                                           ATOM_DEVICE_LCD1_SUPPORT);
1795                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1796                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1797                                             CONNECTOR_OBJECT_ID_LVDS,
1798                                             &hpd);
1799                 /* DVI-I - primary dac, int tmds */
1800                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1801                 hpd.hpd = RADEON_HPD_1; /* ??? */
1802                 radeon_add_legacy_encoder(dev,
1803                                           radeon_get_encoder_enum(dev,
1804                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1805                                                                 0),
1806                                           ATOM_DEVICE_DFP1_SUPPORT);
1807                 radeon_add_legacy_encoder(dev,
1808                                           radeon_get_encoder_enum(dev,
1809                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1810                                                                 1),
1811                                           ATOM_DEVICE_CRT1_SUPPORT);
1812                 radeon_add_legacy_connector(dev, 1,
1813                                             ATOM_DEVICE_DFP1_SUPPORT |
1814                                             ATOM_DEVICE_CRT1_SUPPORT,
1815                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1816                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1817                                             &hpd);
1818                 /* TV - TV DAC */
1819                 ddc_i2c.valid = false;
1820                 hpd.hpd = RADEON_HPD_NONE;
1821                 radeon_add_legacy_encoder(dev,
1822                                           radeon_get_encoder_enum(dev,
1823                                                                 ATOM_DEVICE_TV1_SUPPORT,
1824                                                                 2),
1825                                           ATOM_DEVICE_TV1_SUPPORT);
1826                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1827                                             DRM_MODE_CONNECTOR_SVIDEO,
1828                                             &ddc_i2c,
1829                                             CONNECTOR_OBJECT_ID_SVIDEO,
1830                                             &hpd);
1831                 break;
1832         case CT_POWERBOOK_VGA:
1833                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1834                          rdev->mode_info.connector_table);
1835                 /* LVDS */
1836                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1837                 hpd.hpd = RADEON_HPD_NONE;
1838                 radeon_add_legacy_encoder(dev,
1839                                           radeon_get_encoder_enum(dev,
1840                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1841                                                                 0),
1842                                           ATOM_DEVICE_LCD1_SUPPORT);
1843                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1844                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1845                                             CONNECTOR_OBJECT_ID_LVDS,
1846                                             &hpd);
1847                 /* VGA - primary dac */
1848                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1849                 hpd.hpd = RADEON_HPD_NONE;
1850                 radeon_add_legacy_encoder(dev,
1851                                           radeon_get_encoder_enum(dev,
1852                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1853                                                                 1),
1854                                           ATOM_DEVICE_CRT1_SUPPORT);
1855                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1856                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1857                                             CONNECTOR_OBJECT_ID_VGA,
1858                                             &hpd);
1859                 /* TV - TV DAC */
1860                 ddc_i2c.valid = false;
1861                 hpd.hpd = RADEON_HPD_NONE;
1862                 radeon_add_legacy_encoder(dev,
1863                                           radeon_get_encoder_enum(dev,
1864                                                                 ATOM_DEVICE_TV1_SUPPORT,
1865                                                                 2),
1866                                           ATOM_DEVICE_TV1_SUPPORT);
1867                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1868                                             DRM_MODE_CONNECTOR_SVIDEO,
1869                                             &ddc_i2c,
1870                                             CONNECTOR_OBJECT_ID_SVIDEO,
1871                                             &hpd);
1872                 break;
1873         case CT_MINI_EXTERNAL:
1874                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1875                          rdev->mode_info.connector_table);
1876                 /* DVI-I - tv dac, ext tmds */
1877                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1878                 hpd.hpd = RADEON_HPD_2; /* ??? */
1879                 radeon_add_legacy_encoder(dev,
1880                                           radeon_get_encoder_enum(dev,
1881                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1882                                                                 0),
1883                                           ATOM_DEVICE_DFP2_SUPPORT);
1884                 radeon_add_legacy_encoder(dev,
1885                                           radeon_get_encoder_enum(dev,
1886                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1887                                                                 2),
1888                                           ATOM_DEVICE_CRT2_SUPPORT);
1889                 /* XXX are any DL? */
1890                 radeon_add_legacy_connector(dev, 0,
1891                                             ATOM_DEVICE_DFP2_SUPPORT |
1892                                             ATOM_DEVICE_CRT2_SUPPORT,
1893                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1894                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1895                                             &hpd);
1896                 /* TV - TV DAC */
1897                 ddc_i2c.valid = false;
1898                 hpd.hpd = RADEON_HPD_NONE;
1899                 radeon_add_legacy_encoder(dev,
1900                                           radeon_get_encoder_enum(dev,
1901                                                                 ATOM_DEVICE_TV1_SUPPORT,
1902                                                                 2),
1903                                           ATOM_DEVICE_TV1_SUPPORT);
1904                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1905                                             DRM_MODE_CONNECTOR_SVIDEO,
1906                                             &ddc_i2c,
1907                                             CONNECTOR_OBJECT_ID_SVIDEO,
1908                                             &hpd);
1909                 break;
1910         case CT_MINI_INTERNAL:
1911                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1912                          rdev->mode_info.connector_table);
1913                 /* DVI-I - tv dac, int tmds */
1914                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1915                 hpd.hpd = RADEON_HPD_1; /* ??? */
1916                 radeon_add_legacy_encoder(dev,
1917                                           radeon_get_encoder_enum(dev,
1918                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1919                                                                 0),
1920                                           ATOM_DEVICE_DFP1_SUPPORT);
1921                 radeon_add_legacy_encoder(dev,
1922                                           radeon_get_encoder_enum(dev,
1923                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1924                                                                 2),
1925                                           ATOM_DEVICE_CRT2_SUPPORT);
1926                 radeon_add_legacy_connector(dev, 0,
1927                                             ATOM_DEVICE_DFP1_SUPPORT |
1928                                             ATOM_DEVICE_CRT2_SUPPORT,
1929                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1930                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1931                                             &hpd);
1932                 /* TV - TV DAC */
1933                 ddc_i2c.valid = false;
1934                 hpd.hpd = RADEON_HPD_NONE;
1935                 radeon_add_legacy_encoder(dev,
1936                                           radeon_get_encoder_enum(dev,
1937                                                                 ATOM_DEVICE_TV1_SUPPORT,
1938                                                                 2),
1939                                           ATOM_DEVICE_TV1_SUPPORT);
1940                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1941                                             DRM_MODE_CONNECTOR_SVIDEO,
1942                                             &ddc_i2c,
1943                                             CONNECTOR_OBJECT_ID_SVIDEO,
1944                                             &hpd);
1945                 break;
1946         case CT_IMAC_G5_ISIGHT:
1947                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1948                          rdev->mode_info.connector_table);
1949                 /* DVI-D - int tmds */
1950                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1951                 hpd.hpd = RADEON_HPD_1; /* ??? */
1952                 radeon_add_legacy_encoder(dev,
1953                                           radeon_get_encoder_enum(dev,
1954                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1955                                                                 0),
1956                                           ATOM_DEVICE_DFP1_SUPPORT);
1957                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1958                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1959                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1960                                             &hpd);
1961                 /* VGA - tv dac */
1962                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1963                 hpd.hpd = RADEON_HPD_NONE;
1964                 radeon_add_legacy_encoder(dev,
1965                                           radeon_get_encoder_enum(dev,
1966                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1967                                                                 2),
1968                                           ATOM_DEVICE_CRT2_SUPPORT);
1969                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1970                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1971                                             CONNECTOR_OBJECT_ID_VGA,
1972                                             &hpd);
1973                 /* TV - TV DAC */
1974                 ddc_i2c.valid = false;
1975                 hpd.hpd = RADEON_HPD_NONE;
1976                 radeon_add_legacy_encoder(dev,
1977                                           radeon_get_encoder_enum(dev,
1978                                                                 ATOM_DEVICE_TV1_SUPPORT,
1979                                                                 2),
1980                                           ATOM_DEVICE_TV1_SUPPORT);
1981                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1982                                             DRM_MODE_CONNECTOR_SVIDEO,
1983                                             &ddc_i2c,
1984                                             CONNECTOR_OBJECT_ID_SVIDEO,
1985                                             &hpd);
1986                 break;
1987         case CT_EMAC:
1988                 DRM_INFO("Connector Table: %d (emac)\n",
1989                          rdev->mode_info.connector_table);
1990                 /* VGA - primary dac */
1991                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1992                 hpd.hpd = RADEON_HPD_NONE;
1993                 radeon_add_legacy_encoder(dev,
1994                                           radeon_get_encoder_enum(dev,
1995                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1996                                                                 1),
1997                                           ATOM_DEVICE_CRT1_SUPPORT);
1998                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1999                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2000                                             CONNECTOR_OBJECT_ID_VGA,
2001                                             &hpd);
2002                 /* VGA - tv dac */
2003                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2004                 hpd.hpd = RADEON_HPD_NONE;
2005                 radeon_add_legacy_encoder(dev,
2006                                           radeon_get_encoder_enum(dev,
2007                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2008                                                                 2),
2009                                           ATOM_DEVICE_CRT2_SUPPORT);
2010                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2011                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2012                                             CONNECTOR_OBJECT_ID_VGA,
2013                                             &hpd);
2014                 /* TV - TV DAC */
2015                 ddc_i2c.valid = false;
2016                 hpd.hpd = RADEON_HPD_NONE;
2017                 radeon_add_legacy_encoder(dev,
2018                                           radeon_get_encoder_enum(dev,
2019                                                                 ATOM_DEVICE_TV1_SUPPORT,
2020                                                                 2),
2021                                           ATOM_DEVICE_TV1_SUPPORT);
2022                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2023                                             DRM_MODE_CONNECTOR_SVIDEO,
2024                                             &ddc_i2c,
2025                                             CONNECTOR_OBJECT_ID_SVIDEO,
2026                                             &hpd);
2027                 break;
2028         case CT_RN50_POWER:
2029                 DRM_INFO("Connector Table: %d (rn50-power)\n",
2030                          rdev->mode_info.connector_table);
2031                 /* VGA - primary dac */
2032                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2033                 hpd.hpd = RADEON_HPD_NONE;
2034                 radeon_add_legacy_encoder(dev,
2035                                           radeon_get_encoder_enum(dev,
2036                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2037                                                                 1),
2038                                           ATOM_DEVICE_CRT1_SUPPORT);
2039                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2040                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2041                                             CONNECTOR_OBJECT_ID_VGA,
2042                                             &hpd);
2043                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2044                 hpd.hpd = RADEON_HPD_NONE;
2045                 radeon_add_legacy_encoder(dev,
2046                                           radeon_get_encoder_enum(dev,
2047                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2048                                                                 2),
2049                                           ATOM_DEVICE_CRT2_SUPPORT);
2050                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2051                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2052                                             CONNECTOR_OBJECT_ID_VGA,
2053                                             &hpd);
2054                 break;
2055         case CT_MAC_X800:
2056                 DRM_INFO("Connector Table: %d (mac x800)\n",
2057                          rdev->mode_info.connector_table);
2058                 /* DVI - primary dac, internal tmds */
2059                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2060                 hpd.hpd = RADEON_HPD_1; /* ??? */
2061                 radeon_add_legacy_encoder(dev,
2062                                           radeon_get_encoder_enum(dev,
2063                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2064                                                                   0),
2065                                           ATOM_DEVICE_DFP1_SUPPORT);
2066                 radeon_add_legacy_encoder(dev,
2067                                           radeon_get_encoder_enum(dev,
2068                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2069                                                                   1),
2070                                           ATOM_DEVICE_CRT1_SUPPORT);
2071                 radeon_add_legacy_connector(dev, 0,
2072                                             ATOM_DEVICE_DFP1_SUPPORT |
2073                                             ATOM_DEVICE_CRT1_SUPPORT,
2074                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2075                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2076                                             &hpd);
2077                 /* DVI - tv dac, dvo */
2078                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2079                 hpd.hpd = RADEON_HPD_2; /* ??? */
2080                 radeon_add_legacy_encoder(dev,
2081                                           radeon_get_encoder_enum(dev,
2082                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2083                                                                   0),
2084                                           ATOM_DEVICE_DFP2_SUPPORT);
2085                 radeon_add_legacy_encoder(dev,
2086                                           radeon_get_encoder_enum(dev,
2087                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2088                                                                   2),
2089                                           ATOM_DEVICE_CRT2_SUPPORT);
2090                 radeon_add_legacy_connector(dev, 1,
2091                                             ATOM_DEVICE_DFP2_SUPPORT |
2092                                             ATOM_DEVICE_CRT2_SUPPORT,
2093                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2094                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2095                                             &hpd);
2096                 break;
2097         case CT_MAC_G5_9600:
2098                 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2099                          rdev->mode_info.connector_table);
2100                 /* DVI - tv dac, dvo */
2101                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2102                 hpd.hpd = RADEON_HPD_1; /* ??? */
2103                 radeon_add_legacy_encoder(dev,
2104                                           radeon_get_encoder_enum(dev,
2105                                                                   ATOM_DEVICE_DFP2_SUPPORT,
2106                                                                   0),
2107                                           ATOM_DEVICE_DFP2_SUPPORT);
2108                 radeon_add_legacy_encoder(dev,
2109                                           radeon_get_encoder_enum(dev,
2110                                                                   ATOM_DEVICE_CRT2_SUPPORT,
2111                                                                   2),
2112                                           ATOM_DEVICE_CRT2_SUPPORT);
2113                 radeon_add_legacy_connector(dev, 0,
2114                                             ATOM_DEVICE_DFP2_SUPPORT |
2115                                             ATOM_DEVICE_CRT2_SUPPORT,
2116                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2117                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2118                                             &hpd);
2119                 /* ADC - primary dac, internal tmds */
2120                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2121                 hpd.hpd = RADEON_HPD_2; /* ??? */
2122                 radeon_add_legacy_encoder(dev,
2123                                           radeon_get_encoder_enum(dev,
2124                                                                   ATOM_DEVICE_DFP1_SUPPORT,
2125                                                                   0),
2126                                           ATOM_DEVICE_DFP1_SUPPORT);
2127                 radeon_add_legacy_encoder(dev,
2128                                           radeon_get_encoder_enum(dev,
2129                                                                   ATOM_DEVICE_CRT1_SUPPORT,
2130                                                                   1),
2131                                           ATOM_DEVICE_CRT1_SUPPORT);
2132                 radeon_add_legacy_connector(dev, 1,
2133                                             ATOM_DEVICE_DFP1_SUPPORT |
2134                                             ATOM_DEVICE_CRT1_SUPPORT,
2135                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2136                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2137                                             &hpd);
2138                 /* TV - TV DAC */
2139                 ddc_i2c.valid = false;
2140                 hpd.hpd = RADEON_HPD_NONE;
2141                 radeon_add_legacy_encoder(dev,
2142                                           radeon_get_encoder_enum(dev,
2143                                                                 ATOM_DEVICE_TV1_SUPPORT,
2144                                                                 2),
2145                                           ATOM_DEVICE_TV1_SUPPORT);
2146                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2147                                             DRM_MODE_CONNECTOR_SVIDEO,
2148                                             &ddc_i2c,
2149                                             CONNECTOR_OBJECT_ID_SVIDEO,
2150                                             &hpd);
2151                 break;
2152         case CT_SAM440EP:
2153                 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2154                          rdev->mode_info.connector_table);
2155                 /* LVDS */
2156                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2157                 hpd.hpd = RADEON_HPD_NONE;
2158                 radeon_add_legacy_encoder(dev,
2159                                           radeon_get_encoder_enum(dev,
2160                                                                 ATOM_DEVICE_LCD1_SUPPORT,
2161                                                                 0),
2162                                           ATOM_DEVICE_LCD1_SUPPORT);
2163                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2164                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2165                                             CONNECTOR_OBJECT_ID_LVDS,
2166                                             &hpd);
2167                 /* DVI-I - secondary dac, int tmds */
2168                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2169                 hpd.hpd = RADEON_HPD_1; /* ??? */
2170                 radeon_add_legacy_encoder(dev,
2171                                           radeon_get_encoder_enum(dev,
2172                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2173                                                                 0),
2174                                           ATOM_DEVICE_DFP1_SUPPORT);
2175                 radeon_add_legacy_encoder(dev,
2176                                           radeon_get_encoder_enum(dev,
2177                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2178                                                                 2),
2179                                           ATOM_DEVICE_CRT2_SUPPORT);
2180                 radeon_add_legacy_connector(dev, 1,
2181                                             ATOM_DEVICE_DFP1_SUPPORT |
2182                                             ATOM_DEVICE_CRT2_SUPPORT,
2183                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2184                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2185                                             &hpd);
2186                 /* VGA - primary dac */
2187                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2188                 hpd.hpd = RADEON_HPD_NONE;
2189                 radeon_add_legacy_encoder(dev,
2190                                           radeon_get_encoder_enum(dev,
2191                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2192                                                                 1),
2193                                           ATOM_DEVICE_CRT1_SUPPORT);
2194                 radeon_add_legacy_connector(dev, 2,
2195                                             ATOM_DEVICE_CRT1_SUPPORT,
2196                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2197                                             CONNECTOR_OBJECT_ID_VGA,
2198                                             &hpd);
2199                 /* TV - TV DAC */
2200                 ddc_i2c.valid = false;
2201                 hpd.hpd = RADEON_HPD_NONE;
2202                 radeon_add_legacy_encoder(dev,
2203                                           radeon_get_encoder_enum(dev,
2204                                                                 ATOM_DEVICE_TV1_SUPPORT,
2205                                                                 2),
2206                                           ATOM_DEVICE_TV1_SUPPORT);
2207                 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2208                                             DRM_MODE_CONNECTOR_SVIDEO,
2209                                             &ddc_i2c,
2210                                             CONNECTOR_OBJECT_ID_SVIDEO,
2211                                             &hpd);
2212                 break;
2213         case CT_MAC_G4_SILVER:
2214                 DRM_INFO("Connector Table: %d (mac g4 silver)\n",
2215                          rdev->mode_info.connector_table);
2216                 /* DVI-I - tv dac, int tmds */
2217                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2218                 hpd.hpd = RADEON_HPD_1; /* ??? */
2219                 radeon_add_legacy_encoder(dev,
2220                                           radeon_get_encoder_enum(dev,
2221                                                                 ATOM_DEVICE_DFP1_SUPPORT,
2222                                                                 0),
2223                                           ATOM_DEVICE_DFP1_SUPPORT);
2224                 radeon_add_legacy_encoder(dev,
2225                                           radeon_get_encoder_enum(dev,
2226                                                                 ATOM_DEVICE_CRT2_SUPPORT,
2227                                                                 2),
2228                                           ATOM_DEVICE_CRT2_SUPPORT);
2229                 radeon_add_legacy_connector(dev, 0,
2230                                             ATOM_DEVICE_DFP1_SUPPORT |
2231                                             ATOM_DEVICE_CRT2_SUPPORT,
2232                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2233                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2234                                             &hpd);
2235                 /* VGA - primary dac */
2236                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2237                 hpd.hpd = RADEON_HPD_NONE;
2238                 radeon_add_legacy_encoder(dev,
2239                                           radeon_get_encoder_enum(dev,
2240                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2241                                                                 1),
2242                                           ATOM_DEVICE_CRT1_SUPPORT);
2243                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
2244                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2245                                             CONNECTOR_OBJECT_ID_VGA,
2246                                             &hpd);
2247                 /* TV - TV DAC */
2248                 ddc_i2c.valid = false;
2249                 hpd.hpd = RADEON_HPD_NONE;
2250                 radeon_add_legacy_encoder(dev,
2251                                           radeon_get_encoder_enum(dev,
2252                                                                 ATOM_DEVICE_TV1_SUPPORT,
2253                                                                 2),
2254                                           ATOM_DEVICE_TV1_SUPPORT);
2255                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2256                                             DRM_MODE_CONNECTOR_SVIDEO,
2257                                             &ddc_i2c,
2258                                             CONNECTOR_OBJECT_ID_SVIDEO,
2259                                             &hpd);
2260                 break;
2261         default:
2262                 DRM_INFO("Connector table: %d (invalid)\n",
2263                          rdev->mode_info.connector_table);
2264                 return false;
2265         }
2266
2267         radeon_link_encoder_connector(dev);
2268
2269         return true;
2270 }
2271
2272 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2273                                        int bios_index,
2274                                        enum radeon_combios_connector
2275                                        *legacy_connector,
2276                                        struct radeon_i2c_bus_rec *ddc_i2c,
2277                                        struct radeon_hpd *hpd)
2278 {
2279
2280         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
2281            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2282         if (dev->pci_device == 0x515e &&
2283             dev->pci_subvendor == 0x1014) {
2284                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2285                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2286                         return false;
2287         }
2288
2289         /* X300 card with extra non-existent DVI port */
2290         if (dev->pci_device == 0x5B60 &&
2291             dev->pci_subvendor == 0x17af &&
2292             dev->pci_subdevice == 0x201e && bios_index == 2) {
2293                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2294                         return false;
2295         }
2296
2297         return true;
2298 }
2299
2300 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2301 {
2302         /* Acer 5102 has non-existent TV port */
2303         if (dev->pci_device == 0x5975 &&
2304             dev->pci_subvendor == 0x1025 &&
2305             dev->pci_subdevice == 0x009f)
2306                 return false;
2307
2308         /* HP dc5750 has non-existent TV port */
2309         if (dev->pci_device == 0x5974 &&
2310             dev->pci_subvendor == 0x103c &&
2311             dev->pci_subdevice == 0x280a)
2312                 return false;
2313
2314         /* MSI S270 has non-existent TV port */
2315         if (dev->pci_device == 0x5955 &&
2316             dev->pci_subvendor == 0x1462 &&
2317             dev->pci_subdevice == 0x0131)
2318                 return false;
2319
2320         return true;
2321 }
2322
2323 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2324 {
2325         struct radeon_device *rdev = dev->dev_private;
2326         uint32_t ext_tmds_info;
2327
2328         if (rdev->flags & RADEON_IS_IGP) {
2329                 if (is_dvi_d)
2330                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2331                 else
2332                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2333         }
2334         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2335         if (ext_tmds_info) {
2336                 uint8_t rev = RBIOS8(ext_tmds_info);
2337                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2338                 if (rev >= 3) {
2339                         if (is_dvi_d)
2340                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2341                         else
2342                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2343                 } else {
2344                         if (flags & 1) {
2345                                 if (is_dvi_d)
2346                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2347                                 else
2348                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2349                         }
2350                 }
2351         }
2352         if (is_dvi_d)
2353                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2354         else
2355                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2356 }
2357
2358 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2359 {
2360         struct radeon_device *rdev = dev->dev_private;
2361         uint32_t conn_info, entry, devices;
2362         uint16_t tmp, connector_object_id;
2363         enum radeon_combios_ddc ddc_type;
2364         enum radeon_combios_connector connector;
2365         int i = 0;
2366         struct radeon_i2c_bus_rec ddc_i2c;
2367         struct radeon_hpd hpd;
2368
2369         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2370         if (conn_info) {
2371                 for (i = 0; i < 4; i++) {
2372                         entry = conn_info + 2 + i * 2;
2373
2374                         if (!RBIOS16(entry))
2375                                 break;
2376
2377                         tmp = RBIOS16(entry);
2378
2379                         connector = (tmp >> 12) & 0xf;
2380
2381                         ddc_type = (tmp >> 8) & 0xf;
2382                         if (ddc_type == 5)
2383                                 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);
2384                         else
2385                                 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2386
2387                         switch (connector) {
2388                         case CONNECTOR_PROPRIETARY_LEGACY:
2389                         case CONNECTOR_DVI_I_LEGACY:
2390                         case CONNECTOR_DVI_D_LEGACY:
2391                                 if ((tmp >> 4) & 0x1)
2392                                         hpd.hpd = RADEON_HPD_2;
2393                                 else
2394                                         hpd.hpd = RADEON_HPD_1;
2395                                 break;
2396                         default:
2397                                 hpd.hpd = RADEON_HPD_NONE;
2398                                 break;
2399                         }
2400
2401                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2402                                                         &ddc_i2c, &hpd))
2403                                 continue;
2404
2405                         switch (connector) {
2406                         case CONNECTOR_PROPRIETARY_LEGACY:
2407                                 if ((tmp >> 4) & 0x1)
2408                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2409                                 else
2410                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2411                                 radeon_add_legacy_encoder(dev,
2412                                                           radeon_get_encoder_enum
2413                                                           (dev, devices, 0),
2414                                                           devices);
2415                                 radeon_add_legacy_connector(dev, i, devices,
2416                                                             legacy_connector_convert
2417                                                             [connector],
2418                                                             &ddc_i2c,
2419                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2420                                                             &hpd);
2421                                 break;
2422                         case CONNECTOR_CRT_LEGACY:
2423                                 if (tmp & 0x1) {
2424                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2425                                         radeon_add_legacy_encoder(dev,
2426                                                                   radeon_get_encoder_enum
2427                                                                   (dev,
2428                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2429                                                                    2),
2430                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2431                                 } else {
2432                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2433                                         radeon_add_legacy_encoder(dev,
2434                                                                   radeon_get_encoder_enum
2435                                                                   (dev,
2436                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2437                                                                    1),
2438                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2439                                 }
2440                                 radeon_add_legacy_connector(dev,
2441                                                             i,
2442                                                             devices,
2443                                                             legacy_connector_convert
2444                                                             [connector],
2445                                                             &ddc_i2c,
2446                                                             CONNECTOR_OBJECT_ID_VGA,
2447                                                             &hpd);
2448                                 break;
2449                         case CONNECTOR_DVI_I_LEGACY:
2450                                 devices = 0;
2451                                 if (tmp & 0x1) {
2452                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2453                                         radeon_add_legacy_encoder(dev,
2454                                                                   radeon_get_encoder_enum
2455                                                                   (dev,
2456                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2457                                                                    2),
2458                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2459                                 } else {
2460                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2461                                         radeon_add_legacy_encoder(dev,
2462                                                                   radeon_get_encoder_enum
2463                                                                   (dev,
2464                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2465                                                                    1),
2466                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2467                                 }
2468                                 /* RV100 board with external TDMS bit mis-set.
2469                                  * Actually uses internal TMDS, clear the bit.
2470                                  */
2471                                 if (dev->pci_device == 0x5159 &&
2472                                     dev->pci_subvendor == 0x1014 &&
2473                                     dev->pci_subdevice == 0x029A) {
2474                                         tmp &= ~(1 << 4);
2475                                 }
2476                                 if ((tmp >> 4) & 0x1) {
2477                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2478                                         radeon_add_legacy_encoder(dev,
2479                                                                   radeon_get_encoder_enum
2480                                                                   (dev,
2481                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2482                                                                    0),
2483                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2484                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2485                                 } else {
2486                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2487                                         radeon_add_legacy_encoder(dev,
2488                                                                   radeon_get_encoder_enum
2489                                                                   (dev,
2490                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2491                                                                    0),
2492                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2493                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2494                                 }
2495                                 radeon_add_legacy_connector(dev,
2496                                                             i,
2497                                                             devices,
2498                                                             legacy_connector_convert
2499                                                             [connector],
2500                                                             &ddc_i2c,
2501                                                             connector_object_id,
2502                                                             &hpd);
2503                                 break;
2504                         case CONNECTOR_DVI_D_LEGACY:
2505                                 if ((tmp >> 4) & 0x1) {
2506                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2507                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2508                                 } else {
2509                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2510                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2511                                 }
2512                                 radeon_add_legacy_encoder(dev,
2513                                                           radeon_get_encoder_enum
2514                                                           (dev, devices, 0),
2515                                                           devices);
2516                                 radeon_add_legacy_connector(dev, i, devices,
2517                                                             legacy_connector_convert
2518                                                             [connector],
2519                                                             &ddc_i2c,
2520                                                             connector_object_id,
2521                                                             &hpd);
2522                                 break;
2523                         case CONNECTOR_CTV_LEGACY:
2524                         case CONNECTOR_STV_LEGACY:
2525                                 radeon_add_legacy_encoder(dev,
2526                                                           radeon_get_encoder_enum
2527                                                           (dev,
2528                                                            ATOM_DEVICE_TV1_SUPPORT,
2529                                                            2),
2530                                                           ATOM_DEVICE_TV1_SUPPORT);
2531                                 radeon_add_legacy_connector(dev, i,
2532                                                             ATOM_DEVICE_TV1_SUPPORT,
2533                                                             legacy_connector_convert
2534                                                             [connector],
2535                                                             &ddc_i2c,
2536                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2537                                                             &hpd);
2538                                 break;
2539                         default:
2540                                 DRM_ERROR("Unknown connector type: %d\n",
2541                                           connector);
2542                                 continue;
2543                         }
2544
2545                 }
2546         } else {
2547                 uint16_t tmds_info =
2548                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2549                 if (tmds_info) {
2550                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2551
2552                         radeon_add_legacy_encoder(dev,
2553                                                   radeon_get_encoder_enum(dev,
2554                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2555                                                                         1),
2556                                                   ATOM_DEVICE_CRT1_SUPPORT);
2557                         radeon_add_legacy_encoder(dev,
2558                                                   radeon_get_encoder_enum(dev,
2559                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2560                                                                         0),
2561                                                   ATOM_DEVICE_DFP1_SUPPORT);
2562
2563                         ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2564                         hpd.hpd = RADEON_HPD_1;
2565                         radeon_add_legacy_connector(dev,
2566                                                     0,
2567                                                     ATOM_DEVICE_CRT1_SUPPORT |
2568                                                     ATOM_DEVICE_DFP1_SUPPORT,
2569                                                     DRM_MODE_CONNECTOR_DVII,
2570                                                     &ddc_i2c,
2571                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2572                                                     &hpd);
2573                 } else {
2574                         uint16_t crt_info =
2575                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2576                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2577                         if (crt_info) {
2578                                 radeon_add_legacy_encoder(dev,
2579                                                           radeon_get_encoder_enum(dev,
2580                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2581                                                                                 1),
2582                                                           ATOM_DEVICE_CRT1_SUPPORT);
2583                                 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2584                                 hpd.hpd = RADEON_HPD_NONE;
2585                                 radeon_add_legacy_connector(dev,
2586                                                             0,
2587                                                             ATOM_DEVICE_CRT1_SUPPORT,
2588                                                             DRM_MODE_CONNECTOR_VGA,
2589                                                             &ddc_i2c,
2590                                                             CONNECTOR_OBJECT_ID_VGA,
2591                                                             &hpd);
2592                         } else {
2593                                 DRM_DEBUG_KMS("No connector info found\n");
2594                                 return false;
2595                         }
2596                 }
2597         }
2598
2599         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2600                 uint16_t lcd_info =
2601                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2602                 if (lcd_info) {
2603                         uint16_t lcd_ddc_info =
2604                             combios_get_table_offset(dev,
2605                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2606
2607                         radeon_add_legacy_encoder(dev,
2608                                                   radeon_get_encoder_enum(dev,
2609                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2610                                                                         0),
2611                                                   ATOM_DEVICE_LCD1_SUPPORT);
2612
2613                         if (lcd_ddc_info) {
2614                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2615                                 switch (ddc_type) {
2616                                 case DDC_LCD:
2617                                         ddc_i2c =
2618                                                 combios_setup_i2c_bus(rdev,
2619                                                                       DDC_LCD,
2620                                                                       RBIOS32(lcd_ddc_info + 3),
2621                                                                       RBIOS32(lcd_ddc_info + 7));
2622                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2623                                         break;
2624                                 case DDC_GPIO:
2625                                         ddc_i2c =
2626                                                 combios_setup_i2c_bus(rdev,
2627                                                                       DDC_GPIO,
2628                                                                       RBIOS32(lcd_ddc_info + 3),
2629                                                                       RBIOS32(lcd_ddc_info + 7));
2630                                         radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2631                                         break;
2632                                 default:
2633                                         ddc_i2c =
2634                                                 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2635                                         break;
2636                                 }
2637                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2638                         } else
2639                                 ddc_i2c.valid = false;
2640
2641                         hpd.hpd = RADEON_HPD_NONE;
2642                         radeon_add_legacy_connector(dev,
2643                                                     5,
2644                                                     ATOM_DEVICE_LCD1_SUPPORT,
2645                                                     DRM_MODE_CONNECTOR_LVDS,
2646                                                     &ddc_i2c,
2647                                                     CONNECTOR_OBJECT_ID_LVDS,
2648                                                     &hpd);
2649                 }
2650         }
2651
2652         /* check TV table */
2653         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2654                 uint32_t tv_info =
2655                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2656                 if (tv_info) {
2657                         if (RBIOS8(tv_info + 6) == 'T') {
2658                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2659                                         hpd.hpd = RADEON_HPD_NONE;
2660                                         ddc_i2c.valid = false;
2661                                         radeon_add_legacy_encoder(dev,
2662                                                                   radeon_get_encoder_enum
2663                                                                   (dev,
2664                                                                    ATOM_DEVICE_TV1_SUPPORT,
2665                                                                    2),
2666                                                                   ATOM_DEVICE_TV1_SUPPORT);
2667                                         radeon_add_legacy_connector(dev, 6,
2668                                                                     ATOM_DEVICE_TV1_SUPPORT,
2669                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2670                                                                     &ddc_i2c,
2671                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2672                                                                     &hpd);
2673                                 }
2674                         }
2675                 }
2676         }
2677
2678         radeon_link_encoder_connector(dev);
2679
2680         return true;
2681 }
2682
2683 static const char *thermal_controller_names[] = {
2684         "NONE",
2685         "lm63",
2686         "adm1032",
2687 };
2688
2689 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2690 {
2691         struct drm_device *dev = rdev->ddev;
2692         u16 offset, misc, misc2 = 0;
2693         u8 rev, blocks, tmp;
2694         int state_index = 0;
2695         struct radeon_i2c_bus_rec i2c_bus;
2696
2697         rdev->pm.default_power_state_index = -1;
2698
2699         /* allocate 2 power states */
2700         rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * 2,
2701                                        M_DRM, M_WAITOK | M_ZERO);
2702         if (rdev->pm.power_state) {
2703                 /* allocate 1 clock mode per state */
2704                 rdev->pm.power_state[0].clock_info =
2705                         kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
2706                                 M_DRM, M_WAITOK | M_ZERO);
2707                 rdev->pm.power_state[1].clock_info =
2708                         kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
2709                                 M_DRM, M_WAITOK | M_ZERO);
2710                 if (!rdev->pm.power_state[0].clock_info ||
2711                     !rdev->pm.power_state[1].clock_info)
2712                         goto pm_failed;
2713         } else
2714                 goto pm_failed;
2715
2716         /* check for a thermal chip */
2717         offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2718         if (offset) {
2719                 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2720
2721                 rev = RBIOS8(offset);
2722
2723                 if (rev == 0) {
2724                         thermal_controller = RBIOS8(offset + 3);
2725                         gpio = RBIOS8(offset + 4) & 0x3f;
2726                         i2c_addr = RBIOS8(offset + 5);
2727                 } else if (rev == 1) {
2728                         thermal_controller = RBIOS8(offset + 4);
2729                         gpio = RBIOS8(offset + 5) & 0x3f;
2730                         i2c_addr = RBIOS8(offset + 6);
2731                 } else if (rev == 2) {
2732                         thermal_controller = RBIOS8(offset + 4);
2733                         gpio = RBIOS8(offset + 5) & 0x3f;
2734                         i2c_addr = RBIOS8(offset + 6);
2735                         clk_bit = RBIOS8(offset + 0xa);
2736                         data_bit = RBIOS8(offset + 0xb);
2737                 }
2738                 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2739                         DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2740                                  thermal_controller_names[thermal_controller],
2741                                  i2c_addr >> 1);
2742                         if (gpio == DDC_LCD) {
2743                                 /* MM i2c */
2744                                 i2c_bus.valid = true;
2745                                 i2c_bus.hw_capable = true;
2746                                 i2c_bus.mm_i2c = true;
2747                                 i2c_bus.i2c_id = 0xa0;
2748                         } else if (gpio == DDC_GPIO)
2749                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2750                         else
2751                                 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2752                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2753                         if (rdev->pm.i2c_bus) {
2754 #ifdef DUMBBELL_WIP
2755                                 struct i2c_board_info info = { };
2756                                 const char *name = thermal_controller_names[thermal_controller];
2757                                 info.addr = i2c_addr >> 1;
2758                                 strlcpy(info.type, name, sizeof(info.type));
2759                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2760 #endif /* DUMBBELL_WIP */
2761                         }
2762                 }
2763         } else {
2764                 /* boards with a thermal chip, but no overdrive table */
2765
2766                 /* Asus 9600xt has an f75375 on the monid bus */
2767                 if ((dev->pci_device == 0x4152) &&
2768                     (dev->pci_subvendor == 0x1043) &&
2769                     (dev->pci_subdevice == 0xc002)) {
2770                         i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2771                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2772                         if (rdev->pm.i2c_bus) {
2773 #ifdef DUMBBELL_WIP
2774                                 struct i2c_board_info info = { };
2775                                 const char *name = "f75375";
2776                                 info.addr = 0x28;
2777                                 strlcpy(info.type, name, sizeof(info.type));
2778                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2779                                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2780                                          name, info.addr);
2781 #endif /* DUMBBELL_WIP */
2782                         }
2783                 }
2784         }
2785
2786         if (rdev->flags & RADEON_IS_MOBILITY) {
2787                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2788                 if (offset) {
2789                         rev = RBIOS8(offset);
2790                         blocks = RBIOS8(offset + 0x2);
2791                         /* power mode 0 tends to be the only valid one */
2792                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2793                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2794                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2795                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2796                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2797                                 goto default_mode;
2798                         rdev->pm.power_state[state_index].type =
2799                                 POWER_STATE_TYPE_BATTERY;
2800                         misc = RBIOS16(offset + 0x5 + 0x0);
2801                         if (rev > 4)
2802                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2803                         rdev->pm.power_state[state_index].misc = misc;
2804                         rdev->pm.power_state[state_index].misc2 = misc2;
2805                         if (misc & 0x4) {
2806                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2807                                 if (misc & 0x8)
2808                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2809                                                 true;
2810                                 else
2811                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2812                                                 false;
2813                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2814                                 if (rev < 6) {
2815                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2816                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2817                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2818                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2819                                 } else {
2820                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2821                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2822                                         if (entries && voltage_table_offset) {
2823                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2824                                                         RBIOS16(voltage_table_offset) * 4;
2825                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2826                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2827                                         } else
2828                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2829                                 }
2830                                 switch ((misc2 & 0x700) >> 8) {
2831                                 case 0:
2832                                 default:
2833                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2834                                         break;
2835                                 case 1:
2836                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2837                                         break;
2838                                 case 2:
2839                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2840                                         break;
2841                                 case 3:
2842                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2843                                         break;
2844                                 case 4:
2845                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2846                                         break;
2847                                 }
2848                         } else
2849                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2850                         if (rev > 6)
2851                                 rdev->pm.power_state[state_index].pcie_lanes =
2852                                         RBIOS8(offset + 0x5 + 0x10);
2853                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2854                         state_index++;
2855                 } else {
2856                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2857                 }
2858         } else {
2859                 /* XXX figure out some good default low power mode for desktop cards */
2860         }
2861
2862 default_mode:
2863         /* add the default mode */
2864         rdev->pm.power_state[state_index].type =
2865                 POWER_STATE_TYPE_DEFAULT;
2866         rdev->pm.power_state[state_index].num_clock_modes = 1;
2867         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2868         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2869         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2870         if ((state_index > 0) &&
2871             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2872                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2873                         rdev->pm.power_state[0].clock_info[0].voltage;
2874         else
2875                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2876         rdev->pm.power_state[state_index].pcie_lanes = 16;
2877         rdev->pm.power_state[state_index].flags = 0;
2878         rdev->pm.default_power_state_index = state_index;
2879         rdev->pm.num_power_states = state_index + 1;
2880
2881         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2882         rdev->pm.current_clock_mode_index = 0;
2883         return;
2884
2885 pm_failed:
2886         rdev->pm.default_power_state_index = state_index;
2887         rdev->pm.num_power_states = 0;
2888
2889         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2890         rdev->pm.current_clock_mode_index = 0;
2891 }
2892
2893 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2894 {
2895         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2896         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2897
2898         if (!tmds)
2899                 return;
2900
2901         switch (tmds->dvo_chip) {
2902         case DVO_SIL164:
2903                 /* sil 164 */
2904                 radeon_i2c_put_byte(tmds->i2c_bus,
2905                                     tmds->slave_addr,
2906                                     0x08, 0x30);
2907                 radeon_i2c_put_byte(tmds->i2c_bus,
2908                                        tmds->slave_addr,
2909                                        0x09, 0x00);
2910                 radeon_i2c_put_byte(tmds->i2c_bus,
2911                                     tmds->slave_addr,
2912                                     0x0a, 0x90);
2913                 radeon_i2c_put_byte(tmds->i2c_bus,
2914                                     tmds->slave_addr,
2915                                     0x0c, 0x89);
2916                 radeon_i2c_put_byte(tmds->i2c_bus,
2917                                        tmds->slave_addr,
2918                                        0x08, 0x3b);
2919                 break;
2920         case DVO_SIL1178:
2921                 /* sil 1178 - untested */
2922                 /*
2923                  * 0x0f, 0x44
2924                  * 0x0f, 0x4c
2925                  * 0x0e, 0x01
2926                  * 0x0a, 0x80
2927                  * 0x09, 0x30
2928                  * 0x0c, 0xc9
2929                  * 0x0d, 0x70
2930                  * 0x08, 0x32
2931                  * 0x08, 0x33
2932                  */
2933                 break;
2934         default:
2935                 break;
2936         }
2937
2938 }
2939
2940 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2941 {
2942         struct drm_device *dev = encoder->dev;
2943         struct radeon_device *rdev = dev->dev_private;
2944         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2945         uint16_t offset;
2946         uint8_t blocks, slave_addr, rev;
2947         uint32_t index, id;
2948         uint32_t reg, val, and_mask, or_mask;
2949         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2950
2951         if (!tmds)
2952                 return false;
2953
2954         if (rdev->flags & RADEON_IS_IGP) {
2955                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2956                 rev = RBIOS8(offset);
2957                 if (offset) {
2958                         rev = RBIOS8(offset);
2959                         if (rev > 1) {
2960                                 blocks = RBIOS8(offset + 3);
2961                                 index = offset + 4;
2962                                 while (blocks > 0) {
2963                                         id = RBIOS16(index);
2964                                         index += 2;
2965                                         switch (id >> 13) {
2966                                         case 0:
2967                                                 reg = (id & 0x1fff) * 4;
2968                                                 val = RBIOS32(index);
2969                                                 index += 4;
2970                                                 WREG32(reg, val);
2971                                                 break;
2972                                         case 2:
2973                                                 reg = (id & 0x1fff) * 4;
2974                                                 and_mask = RBIOS32(index);
2975                                                 index += 4;
2976                                                 or_mask = RBIOS32(index);
2977                                                 index += 4;
2978                                                 val = RREG32(reg);
2979                                                 val = (val & and_mask) | or_mask;
2980                                                 WREG32(reg, val);
2981                                                 break;
2982                                         case 3:
2983                                                 val = RBIOS16(index);
2984                                                 index += 2;
2985                                                 DRM_UDELAY(val);
2986                                                 break;
2987                                         case 4:
2988                                                 val = RBIOS16(index);
2989                                                 index += 2;
2990                                                 DRM_MDELAY(val);
2991                                                 break;
2992                                         case 6:
2993                                                 slave_addr = id & 0xff;
2994                                                 slave_addr >>= 1; /* 7 bit addressing */
2995                                                 index++;
2996                                                 reg = RBIOS8(index);
2997                                                 index++;
2998                                                 val = RBIOS8(index);
2999                                                 index++;
3000                                                 radeon_i2c_put_byte(tmds->i2c_bus,
3001                                                                     slave_addr,
3002                                                                     reg, val);
3003                                                 break;
3004                                         default:
3005                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
3006                                                 break;
3007                                         }
3008                                         blocks--;
3009                                 }
3010                                 return true;
3011                         }
3012                 }
3013         } else {
3014                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
3015                 if (offset) {
3016                         index = offset + 10;
3017                         id = RBIOS16(index);
3018                         while (id != 0xffff) {
3019                                 index += 2;
3020                                 switch (id >> 13) {
3021                                 case 0:
3022                                         reg = (id & 0x1fff) * 4;
3023                                         val = RBIOS32(index);
3024                                         WREG32(reg, val);
3025                                         break;
3026                                 case 2:
3027                                         reg = (id & 0x1fff) * 4;
3028                                         and_mask = RBIOS32(index);
3029                                         index += 4;
3030                                         or_mask = RBIOS32(index);
3031                                         index += 4;
3032                                         val = RREG32(reg);
3033                                         val = (val & and_mask) | or_mask;
3034                                         WREG32(reg, val);
3035                                         break;
3036                                 case 4:
3037                                         val = RBIOS16(index);
3038                                         index += 2;
3039                                         DRM_UDELAY(val);
3040                                         break;
3041                                 case 5:
3042                                         reg = id & 0x1fff;
3043                                         and_mask = RBIOS32(index);
3044                                         index += 4;
3045                                         or_mask = RBIOS32(index);
3046                                         index += 4;
3047                                         val = RREG32_PLL(reg);
3048                                         val = (val & and_mask) | or_mask;
3049                                         WREG32_PLL(reg, val);
3050                                         break;
3051                                 case 6:
3052                                         reg = id & 0x1fff;
3053                                         val = RBIOS8(index);
3054                                         index += 1;
3055                                         radeon_i2c_put_byte(tmds->i2c_bus,
3056                                                             tmds->slave_addr,
3057                                                             reg, val);
3058                                         break;
3059                                 default:
3060                                         DRM_ERROR("Unknown id %d\n", id >> 13);
3061                                         break;
3062                                 }
3063                                 id = RBIOS16(index);
3064                         }
3065                         return true;
3066                 }
3067         }
3068         return false;
3069 }
3070
3071 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
3072 {
3073         struct radeon_device *rdev = dev->dev_private;
3074
3075         if (offset) {
3076                 while (RBIOS16(offset)) {
3077                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3078                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
3079                         uint32_t val, and_mask, or_mask;
3080                         uint32_t tmp;
3081
3082                         offset += 2;
3083                         switch (cmd) {
3084                         case 0:
3085                                 val = RBIOS32(offset);
3086                                 offset += 4;
3087                                 WREG32(addr, val);
3088                                 break;
3089                         case 1:
3090                                 val = RBIOS32(offset);
3091                                 offset += 4;
3092                                 WREG32(addr, val);
3093                                 break;
3094                         case 2:
3095                                 and_mask = RBIOS32(offset);
3096                                 offset += 4;
3097                                 or_mask = RBIOS32(offset);
3098                                 offset += 4;
3099                                 tmp = RREG32(addr);
3100                                 tmp &= and_mask;
3101                                 tmp |= or_mask;
3102                                 WREG32(addr, tmp);
3103                                 break;
3104                         case 3:
3105                                 and_mask = RBIOS32(offset);
3106                                 offset += 4;
3107                                 or_mask = RBIOS32(offset);
3108                                 offset += 4;
3109                                 tmp = RREG32(addr);
3110                                 tmp &= and_mask;
3111                                 tmp |= or_mask;
3112                                 WREG32(addr, tmp);
3113                                 break;
3114                         case 4:
3115                                 val = RBIOS16(offset);
3116                                 offset += 2;
3117                                 DRM_UDELAY(val);
3118                                 break;
3119                         case 5:
3120                                 val = RBIOS16(offset);
3121                                 offset += 2;
3122                                 switch (addr) {
3123                                 case 8:
3124                                         while (val--) {
3125                                                 if (!
3126                                                     (RREG32_PLL
3127                                                      (RADEON_CLK_PWRMGT_CNTL) &
3128                                                      RADEON_MC_BUSY))
3129                                                         break;
3130                                         }
3131                                         break;
3132                                 case 9:
3133                                         while (val--) {
3134                                                 if ((RREG32(RADEON_MC_STATUS) &
3135                                                      RADEON_MC_IDLE))
3136                                                         break;
3137                                         }
3138                                         break;
3139                                 default:
3140                                         break;
3141                                 }
3142                                 break;
3143                         default:
3144                                 break;
3145                         }
3146                 }
3147         }
3148 }
3149
3150 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3151 {
3152         struct radeon_device *rdev = dev->dev_private;
3153
3154         if (offset) {
3155                 while (RBIOS8(offset)) {
3156                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3157                         uint8_t addr = (RBIOS8(offset) & 0x3f);
3158                         uint32_t val, shift, tmp;
3159                         uint32_t and_mask, or_mask;
3160
3161                         offset++;
3162                         switch (cmd) {
3163                         case 0:
3164                                 val = RBIOS32(offset);
3165                                 offset += 4;
3166                                 WREG32_PLL(addr, val);
3167                                 break;
3168                         case 1:
3169                                 shift = RBIOS8(offset) * 8;
3170                                 offset++;
3171                                 and_mask = RBIOS8(offset) << shift;
3172                                 and_mask |= ~(0xff << shift);
3173                                 offset++;
3174                                 or_mask = RBIOS8(offset) << shift;
3175                                 offset++;
3176                                 tmp = RREG32_PLL(addr);
3177                                 tmp &= and_mask;
3178                                 tmp |= or_mask;
3179                                 WREG32_PLL(addr, tmp);
3180                                 break;
3181                         case 2:
3182                         case 3:
3183                                 tmp = 1000;
3184                                 switch (addr) {
3185                                 case 1:
3186                                         DRM_UDELAY(150);
3187                                         break;
3188                                 case 2:
3189                                         DRM_MDELAY(1);
3190                                         break;
3191                                 case 3:
3192                                         while (tmp--) {
3193                                                 if (!
3194                                                     (RREG32_PLL
3195                                                      (RADEON_CLK_PWRMGT_CNTL) &
3196                                                      RADEON_MC_BUSY))
3197                                                         break;
3198                                         }
3199                                         break;
3200                                 case 4:
3201                                         while (tmp--) {
3202                                                 if (RREG32_PLL
3203                                                     (RADEON_CLK_PWRMGT_CNTL) &
3204                                                     RADEON_DLL_READY)
3205                                                         break;
3206                                         }
3207                                         break;
3208                                 case 5:
3209                                         tmp =
3210                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3211                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
3212 #if 0
3213                                                 uint32_t mclk_cntl =
3214                                                     RREG32_PLL
3215                                                     (RADEON_MCLK_CNTL);
3216                                                 mclk_cntl &= 0xffff0000;
3217                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
3218                                                 WREG32_PLL(RADEON_MCLK_CNTL,
3219                                                            mclk_cntl);
3220                                                 DRM_MDELAY(10);
3221 #endif
3222                                                 WREG32_PLL
3223                                                     (RADEON_CLK_PWRMGT_CNTL,
3224                                                      tmp &
3225                                                      ~RADEON_CG_NO1_DEBUG_0);
3226                                                 DRM_MDELAY(10);
3227                                         }
3228                                         break;
3229                                 default:
3230                                         break;
3231                                 }
3232                                 break;
3233                         default:
3234                                 break;
3235                         }
3236                 }
3237         }
3238 }
3239
3240 static void combios_parse_ram_reset_table(struct drm_device *dev,
3241                                           uint16_t offset)
3242 {
3243         struct radeon_device *rdev = dev->dev_private;
3244         uint32_t tmp;
3245
3246         if (offset) {
3247                 uint8_t val = RBIOS8(offset);
3248                 while (val != 0xff) {
3249                         offset++;
3250
3251                         if (val == 0x0f) {
3252                                 uint32_t channel_complete_mask;
3253
3254                                 if (ASIC_IS_R300(rdev))
3255                                         channel_complete_mask =
3256                                             R300_MEM_PWRUP_COMPLETE;
3257                                 else
3258                                         channel_complete_mask =
3259                                             RADEON_MEM_PWRUP_COMPLETE;
3260                                 tmp = 20000;
3261                                 while (tmp--) {
3262                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
3263                                              channel_complete_mask) ==
3264                                             channel_complete_mask)
3265                                                 break;
3266                                 }
3267                         } else {
3268                                 uint32_t or_mask = RBIOS16(offset);
3269                                 offset += 2;
3270
3271                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3272                                 tmp &= RADEON_SDRAM_MODE_MASK;
3273                                 tmp |= or_mask;
3274                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3275
3276                                 or_mask = val << 24;
3277                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3278                                 tmp &= RADEON_B3MEM_RESET_MASK;
3279                                 tmp |= or_mask;
3280                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3281                         }
3282                         val = RBIOS8(offset);
3283                 }
3284         }
3285 }
3286
3287 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3288                                    int mem_addr_mapping)
3289 {
3290         struct radeon_device *rdev = dev->dev_private;
3291         uint32_t mem_cntl;
3292         uint32_t mem_size;
3293         uint32_t addr = 0;
3294
3295         mem_cntl = RREG32(RADEON_MEM_CNTL);
3296         if (mem_cntl & RV100_HALF_MODE)
3297                 ram /= 2;
3298         mem_size = ram;
3299         mem_cntl &= ~(0xff << 8);
3300         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3301         WREG32(RADEON_MEM_CNTL, mem_cntl);
3302         RREG32(RADEON_MEM_CNTL);
3303
3304         /* sdram reset ? */
3305
3306         /* something like this????  */
3307         while (ram--) {
3308                 addr = ram * 1024 * 1024;
3309                 /* write to each page */
3310                 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);
3311                 /* read back and verify */
3312                 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)
3313                         return 0;
3314         }
3315
3316         return mem_size;
3317 }
3318
3319 static void combios_write_ram_size(struct drm_device *dev)
3320 {
3321         struct radeon_device *rdev = dev->dev_private;
3322         uint8_t rev;
3323         uint16_t offset;
3324         uint32_t mem_size = 0;
3325         uint32_t mem_cntl = 0;
3326
3327         /* should do something smarter here I guess... */
3328         if (rdev->flags & RADEON_IS_IGP)
3329                 return;
3330
3331         /* first check detected mem table */
3332         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3333         if (offset) {
3334                 rev = RBIOS8(offset);
3335                 if (rev < 3) {
3336                         mem_cntl = RBIOS32(offset + 1);
3337                         mem_size = RBIOS16(offset + 5);
3338                         if ((rdev->family < CHIP_R200) &&
3339                             !ASIC_IS_RN50(rdev))
3340                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
3341                 }
3342         }
3343
3344         if (!mem_size) {
3345                 offset =
3346                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3347                 if (offset) {
3348                         rev = RBIOS8(offset - 1);
3349                         if (rev < 1) {
3350                                 if ((rdev->family < CHIP_R200)
3351                                     && !ASIC_IS_RN50(rdev)) {
3352                                         int ram = 0;
3353                                         int mem_addr_mapping = 0;
3354
3355                                         while (RBIOS8(offset)) {
3356                                                 ram = RBIOS8(offset);
3357                                                 mem_addr_mapping =
3358                                                     RBIOS8(offset + 1);
3359                                                 if (mem_addr_mapping != 0x25)
3360                                                         ram *= 2;
3361                                                 mem_size =
3362                                                     combios_detect_ram(dev, ram,
3363                                                                        mem_addr_mapping);
3364                                                 if (mem_size)
3365                                                         break;
3366                                                 offset += 2;
3367                                         }
3368                                 } else
3369                                         mem_size = RBIOS8(offset);
3370                         } else {
3371                                 mem_size = RBIOS8(offset);
3372                                 mem_size *= 2;  /* convert to MB */
3373                         }
3374                 }
3375         }
3376
3377         mem_size *= (1024 * 1024);      /* convert to bytes */
3378         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3379 }
3380
3381 void radeon_combios_asic_init(struct drm_device *dev)
3382 {
3383         struct radeon_device *rdev = dev->dev_private;
3384         uint16_t table;
3385
3386         /* port hardcoded mac stuff from radeonfb */
3387         if (rdev->bios == NULL)
3388                 return;
3389
3390         /* ASIC INIT 1 */
3391         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3392         if (table)
3393                 combios_parse_mmio_table(dev, table);
3394
3395         /* PLL INIT */
3396         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3397         if (table)
3398                 combios_parse_pll_table(dev, table);
3399
3400         /* ASIC INIT 2 */
3401         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3402         if (table)
3403                 combios_parse_mmio_table(dev, table);
3404
3405         if (!(rdev->flags & RADEON_IS_IGP)) {
3406                 /* ASIC INIT 4 */
3407                 table =
3408                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3409                 if (table)
3410                         combios_parse_mmio_table(dev, table);
3411
3412                 /* RAM RESET */
3413                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3414                 if (table)
3415                         combios_parse_ram_reset_table(dev, table);
3416
3417                 /* ASIC INIT 3 */
3418                 table =
3419                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3420                 if (table)
3421                         combios_parse_mmio_table(dev, table);
3422
3423                 /* write CONFIG_MEMSIZE */
3424                 combios_write_ram_size(dev);
3425         }
3426
3427         /* quirk for rs4xx HP nx6125 laptop to make it resume
3428          * - it hangs on resume inside the dynclk 1 table.
3429          */
3430         if (rdev->family == CHIP_RS480 &&
3431             dev->pci_subvendor == 0x103c &&
3432             dev->pci_subdevice == 0x308b)
3433                 return;
3434
3435         /* quirk for rs4xx HP dv5000 laptop to make it resume
3436          * - it hangs on resume inside the dynclk 1 table.
3437          */
3438         if (rdev->family == CHIP_RS480 &&
3439             dev->pci_subvendor == 0x103c &&
3440             dev->pci_subdevice == 0x30a4)
3441                 return;
3442
3443         /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume
3444          * - it hangs on resume inside the dynclk 1 table.
3445          */
3446         if (rdev->family == CHIP_RS480 &&
3447             dev->pci_subvendor == 0x103c &&
3448             dev->pci_subdevice == 0x30ae)
3449                 return;
3450
3451         /* DYN CLK 1 */
3452         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3453         if (table)
3454                 combios_parse_pll_table(dev, table);
3455
3456 }
3457
3458 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3459 {
3460         struct radeon_device *rdev = dev->dev_private;
3461         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3462
3463         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3464         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3465         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3466
3467         /* let the bios control the backlight */
3468         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3469
3470         /* tell the bios not to handle mode switching */
3471         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3472                            RADEON_ACC_MODE_CHANGE);
3473
3474         /* tell the bios a driver is loaded */
3475         bios_7_scratch |= RADEON_DRV_LOADED;
3476
3477         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3478         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3479         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3480 }
3481
3482 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3483 {
3484         struct drm_device *dev = encoder->dev;
3485         struct radeon_device *rdev = dev->dev_private;
3486         uint32_t bios_6_scratch;
3487
3488         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3489
3490         if (lock)
3491                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3492         else
3493                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3494
3495         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3496 }
3497
3498 void
3499 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3500                                       struct drm_encoder *encoder,
3501                                       bool connected)
3502 {
3503         struct drm_device *dev = connector->dev;
3504         struct radeon_device *rdev = dev->dev_private;
3505         struct radeon_connector *radeon_connector =
3506             to_radeon_connector(connector);
3507         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3508         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3509         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3510
3511         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3512             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3513                 if (connected) {
3514                         DRM_DEBUG_KMS("TV1 connected\n");
3515                         /* fix me */
3516                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3517                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3518                         bios_5_scratch |= RADEON_TV1_ON;
3519                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3520                 } else {
3521                         DRM_DEBUG_KMS("TV1 disconnected\n");
3522                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3523                         bios_5_scratch &= ~RADEON_TV1_ON;
3524                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3525                 }
3526         }
3527         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3528             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3529                 if (connected) {
3530                         DRM_DEBUG_KMS("LCD1 connected\n");
3531                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3532                         bios_5_scratch |= RADEON_LCD1_ON;
3533                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3534                 } else {
3535                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3536                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3537                         bios_5_scratch &= ~RADEON_LCD1_ON;
3538                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3539                 }
3540         }
3541         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3542             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3543                 if (connected) {
3544                         DRM_DEBUG_KMS("CRT1 connected\n");
3545                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3546                         bios_5_scratch |= RADEON_CRT1_ON;
3547                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3548                 } else {
3549                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3550                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3551                         bios_5_scratch &= ~RADEON_CRT1_ON;
3552                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3553                 }
3554         }
3555         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3556             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3557                 if (connected) {
3558                         DRM_DEBUG_KMS("CRT2 connected\n");
3559                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3560                         bios_5_scratch |= RADEON_CRT2_ON;
3561                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3562                 } else {
3563                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3564                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3565                         bios_5_scratch &= ~RADEON_CRT2_ON;
3566                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3567                 }
3568         }
3569         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3570             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3571                 if (connected) {
3572                         DRM_DEBUG_KMS("DFP1 connected\n");
3573                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3574                         bios_5_scratch |= RADEON_DFP1_ON;
3575                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3576                 } else {
3577                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3578                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3579                         bios_5_scratch &= ~RADEON_DFP1_ON;
3580                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3581                 }
3582         }
3583         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3584             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3585                 if (connected) {
3586                         DRM_DEBUG_KMS("DFP2 connected\n");
3587                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3588                         bios_5_scratch |= RADEON_DFP2_ON;
3589                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3590                 } else {
3591                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3592                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3593                         bios_5_scratch &= ~RADEON_DFP2_ON;
3594                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3595                 }
3596         }
3597         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3598         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3599 }
3600
3601 void
3602 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3603 {
3604         struct drm_device *dev = encoder->dev;
3605         struct radeon_device *rdev = dev->dev_private;
3606         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3607         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3608
3609         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3610                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3611                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3612         }
3613         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3614                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3615                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3616         }
3617         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3618                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3619                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3620         }
3621         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3622                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3623                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3624         }
3625         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3626                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3627                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3628         }
3629         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3630                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3631                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3632         }
3633         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3634 }
3635
3636 void
3637 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3638 {
3639         struct drm_device *dev = encoder->dev;
3640         struct radeon_device *rdev = dev->dev_private;
3641         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3642         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3643
3644         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3645                 if (on)
3646                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3647                 else
3648                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3649         }
3650         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3651                 if (on)
3652                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3653                 else
3654                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3655         }
3656         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3657                 if (on)
3658                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3659                 else
3660                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3661         }
3662         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3663                 if (on)
3664                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3665                 else
3666                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3667         }
3668         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3669 }