2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
26 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cursor.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <uapi_drm/radeon_drm.h>
33 #define CURSOR_WIDTH 64
34 #define CURSOR_HEIGHT 64
36 static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
38 struct radeon_device *rdev = crtc->dev->dev_private;
39 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 if (ASIC_IS_DCE4(rdev)) {
43 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
45 cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
47 cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
48 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
49 } else if (ASIC_IS_AVIVO(rdev)) {
50 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
52 cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
54 cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
55 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
57 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
59 cur_lock |= RADEON_CUR_LOCK;
61 cur_lock &= ~RADEON_CUR_LOCK;
62 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
66 static void radeon_hide_cursor(struct drm_crtc *crtc)
68 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
69 struct radeon_device *rdev = crtc->dev->dev_private;
71 if (ASIC_IS_DCE4(rdev)) {
72 WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
73 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
74 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
75 } else if (ASIC_IS_AVIVO(rdev)) {
76 WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
77 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
80 switch (radeon_crtc->crtc_id) {
82 reg = RADEON_CRTC_GEN_CNTL;
85 reg = RADEON_CRTC2_GEN_CNTL;
90 WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
94 static void radeon_show_cursor(struct drm_crtc *crtc)
96 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
97 struct radeon_device *rdev = crtc->dev->dev_private;
99 if (ASIC_IS_DCE4(rdev)) {
100 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
101 WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
102 EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
103 EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
104 } else if (ASIC_IS_AVIVO(rdev)) {
105 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
106 WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
107 (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
109 switch (radeon_crtc->crtc_id) {
111 WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
114 WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
120 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
121 (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
122 ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
126 static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
129 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
130 struct radeon_device *rdev = crtc->dev->dev_private;
132 if (ASIC_IS_DCE4(rdev)) {
133 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
134 upper_32_bits(gpu_addr));
135 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
136 gpu_addr & 0xffffffff);
137 } else if (ASIC_IS_AVIVO(rdev)) {
138 if (rdev->family >= CHIP_RV770) {
139 if (radeon_crtc->crtc_id)
140 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
142 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, upper_32_bits(gpu_addr));
144 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
145 gpu_addr & 0xffffffff);
147 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
148 /* offset is from DISP(2)_BASE_ADDRESS */
149 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
153 int radeon_crtc_cursor_set(struct drm_crtc *crtc,
154 struct drm_file *file_priv,
159 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
160 struct radeon_device *rdev = crtc->dev->dev_private;
161 struct drm_gem_object *obj;
162 struct radeon_bo *robj;
167 /* turn off cursor */
168 radeon_hide_cursor(crtc);
173 if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
174 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
178 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
180 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
184 robj = gem_to_radeon_bo(obj);
185 ret = radeon_bo_reserve(robj, false);
186 if (unlikely(ret != 0))
188 /* Only 27 bit offset for legacy cursor */
189 ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
190 ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
192 radeon_bo_unreserve(robj);
196 radeon_crtc->cursor_width = width;
197 radeon_crtc->cursor_height = height;
199 radeon_lock_cursor(crtc, true);
200 radeon_set_cursor(crtc, obj, gpu_addr);
201 radeon_show_cursor(crtc);
202 radeon_lock_cursor(crtc, false);
205 if (radeon_crtc->cursor_bo) {
206 robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
207 ret = radeon_bo_reserve(robj, false);
208 if (likely(ret == 0)) {
209 radeon_bo_unpin(robj);
210 radeon_bo_unreserve(robj);
212 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
215 radeon_crtc->cursor_bo = obj;
218 drm_gem_object_unreference_unlocked(obj);
223 int radeon_crtc_cursor_move(struct drm_crtc *crtc,
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct radeon_device *rdev = crtc->dev->dev_private;
228 int xorigin = 0, yorigin = 0;
229 int w = radeon_crtc->cursor_width;
231 if (ASIC_IS_AVIVO(rdev)) {
232 /* avivo cursor are offset into the total surface */
236 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
239 xorigin = min(-x, CURSOR_WIDTH - 1);
243 yorigin = min(-y, CURSOR_HEIGHT - 1);
247 /* fixed on DCE6 and newer */
248 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
250 struct drm_crtc *crtc_p;
253 * avivo cursor image can't end on 128 pixel boundary or
254 * go past the end of the frame if both crtcs are enabled
256 * NOTE: It is safe to access crtc->enabled of other crtcs
257 * without holding either the mode_config lock or the other
258 * crtc's lock as long as write access to this flag _always_
261 list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
266 int cursor_end, frame_end;
268 cursor_end = x - xorigin + w;
269 frame_end = crtc->x + crtc->mode.crtc_hdisplay;
270 if (cursor_end >= frame_end) {
271 w = w - (cursor_end - frame_end);
272 if (!(frame_end & 0x7f))
275 if (!(cursor_end & 0x7f))
280 cursor_end = x - xorigin + w;
281 if (!(cursor_end & 0x7f)) {
284 DRM_ERROR("%s: x(%d) < 0", __func__, x);
291 radeon_lock_cursor(crtc, true);
292 if (ASIC_IS_DCE4(rdev)) {
293 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
294 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
295 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
296 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
297 } else if (ASIC_IS_AVIVO(rdev)) {
298 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
299 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
300 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
301 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
303 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
306 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
310 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
314 /* offset is from DISP(2)_BASE_ADDRESS */
315 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
318 radeon_lock_cursor(crtc, false);