2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * $FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.50.2.2.4.1 2009/04/15 03:14:26 kensmith Exp $
34 * PCI:PCI bridge support.
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
40 #include <sys/module.h>
43 #include <sys/sysctl.h>
44 #include <machine_base/apic/ioapic.h>
46 #include <bus/pci/pcivar.h>
47 #include <bus/pci/pcireg.h>
48 #include <bus/pci/pcib_private.h>
52 static int pcib_probe(device_t dev);
54 static device_method_t pcib_methods[] = {
55 /* Device interface */
56 DEVMETHOD(device_probe, pcib_probe),
57 DEVMETHOD(device_attach, pcib_attach),
58 DEVMETHOD(device_detach, bus_generic_detach),
59 DEVMETHOD(device_shutdown, bus_generic_shutdown),
60 DEVMETHOD(device_suspend, bus_generic_suspend),
61 DEVMETHOD(device_resume, bus_generic_resume),
64 DEVMETHOD(bus_print_child, bus_generic_print_child),
65 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
66 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
67 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
68 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
69 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
70 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
71 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
72 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
75 DEVMETHOD(pcib_maxslots, pcib_maxslots),
76 DEVMETHOD(pcib_read_config, pcib_read_config),
77 DEVMETHOD(pcib_write_config, pcib_write_config),
78 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
79 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
80 DEVMETHOD(pcib_release_msi, pcib_release_msi),
81 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
82 DEVMETHOD(pcib_release_msix, pcib_release_msix),
83 DEVMETHOD(pcib_map_msi, pcib_map_msi),
88 static devclass_t pcib_devclass;
90 DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
91 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);
94 * Is the prefetch window open (eg, can we allocate memory in it?)
97 pcib_is_prefetch_open(struct pcib_softc *sc)
99 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
103 * Is the nonprefetch window open (eg, can we allocate memory in it?)
106 pcib_is_nonprefetch_open(struct pcib_softc *sc)
108 return (sc->membase > 0 && sc->membase < sc->memlimit);
112 * Is the io window open (eg, can we allocate ports in it?)
115 pcib_is_io_open(struct pcib_softc *sc)
117 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
121 * Generic device interface
124 pcib_probe(device_t dev)
126 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
127 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
128 device_set_desc(dev, "PCI-PCI bridge");
129 #if defined(__i386__)
131 /* PCIBIOS PCI-PCI bridge is -2000 */
135 #elif defined(__x86_64__)
136 /* PCIBIOS PCI-PCI bridge is -2000 */
146 pcib_attach_common(device_t dev)
148 struct pcib_softc *sc;
151 sc = device_get_softc(dev);
155 * Get current bridge configuration.
157 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
158 sc->domain = pci_get_domain(dev);
159 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
160 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
161 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
162 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
163 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
166 * Determine current I/O decode.
168 if (sc->command & PCIM_CMD_PORTEN) {
169 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
170 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
171 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
172 pci_read_config(dev, PCIR_IOBASEL_1, 1));
174 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
177 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
178 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
179 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
180 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
182 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
187 * Determine current memory decode.
189 if (sc->command & PCIM_CMD_MEMEN) {
190 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
191 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
192 iolow = pci_read_config(dev, PCIR_PMBASEL_1, 1);
193 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
194 sc->pmembase = PCI_PPBMEMBASE(
195 pci_read_config(dev, PCIR_PMBASEH_1, 4),
196 pci_read_config(dev, PCIR_PMBASEL_1, 2));
198 sc->pmembase = PCI_PPBMEMBASE(0,
199 pci_read_config(dev, PCIR_PMBASEL_1, 2));
200 iolow = pci_read_config(dev, PCIR_PMLIMITL_1, 1);
201 if ((iolow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
202 sc->pmemlimit = PCI_PPBMEMLIMIT(
203 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
204 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
206 sc->pmemlimit = PCI_PPBMEMLIMIT(0,
207 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
213 switch (pci_get_devid(dev)) {
214 case 0x12258086: /* Intel 82454KX/GX (Orion) */
218 supbus = pci_read_config(dev, 0x41, 1);
219 if (supbus != 0xff) {
220 sc->secbus = supbus + 1;
221 sc->subbus = supbus + 1;
227 * The i82380FB mobile docking controller is a PCI-PCI bridge,
228 * and it is a subtractive bridge. However, the ProgIf is wrong
229 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
230 * happen. There's also a Toshiba bridge that behaves this
233 case 0x124b8086: /* Intel 82380FB Mobile */
234 case 0x060513d7: /* Toshiba ???? */
235 sc->flags |= PCIB_SUBTRACTIVE;
238 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
243 if ((cp = kgetenv("smbios.planar.maker")) == NULL)
245 if (strncmp(cp, "Compal", 6) != 0) {
250 if ((cp = kgetenv("smbios.planar.product")) == NULL)
252 if (strncmp(cp, "08A0", 4) != 0) {
257 if (sc->subbus < 0xa) {
258 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
259 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
265 if (pci_msi_device_blacklisted(dev))
266 sc->flags |= PCIB_DISABLE_MSI;
269 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
270 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
271 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
272 * This means they act as if they were subtractively decoding
273 * bridges and pass all transactions. Mark them and real ProgIf 1
274 * parts as subtractive.
276 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
277 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
278 sc->flags |= PCIB_SUBTRACTIVE;
281 device_printf(dev, " domain %d\n", sc->domain);
282 device_printf(dev, " secondary bus %d\n", sc->secbus);
283 device_printf(dev, " subordinate bus %d\n", sc->subbus);
284 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
285 if (pcib_is_nonprefetch_open(sc))
286 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
287 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
288 if (pcib_is_prefetch_open(sc))
289 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
290 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
292 device_printf(dev, " no prefetched decode\n");
293 if (sc->flags & PCIB_SUBTRACTIVE)
294 device_printf(dev, " Subtractively decoded bridge.\n");
297 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) {
303 * Before proper PCI Express hot-plug support is in place,
304 * disable all hot-plug interrupts on the PCI Express root
305 * port or down stream port for now.
307 #define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN)
309 ptr = pci_get_pciecap_ptr(dev);
310 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTRL, 2);
311 if (slot_ctrl & HPINTRS) {
312 device_printf(dev, "Disable PCI Express hot-plug "
313 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS);
314 slot_ctrl &= ~HPINTRS;
315 pci_write_config(dev, ptr + PCIER_SLOTCTRL, slot_ctrl, 2);
322 * XXX If the secondary bus number is zero, we should assign a bus number
323 * since the BIOS hasn't, then initialise the bridge.
327 * XXX If the subordinate bus number is less than the secondary bus number,
328 * we should pick a better value. One sensible alternative would be to
329 * pick 255; the only tradeoff here is that configuration transactions
330 * would be more widely routed than absolutely necessary.
335 pcib_attach(device_t dev)
337 struct pcib_softc *sc;
340 pcib_attach_common(dev);
341 sc = device_get_softc(dev);
342 if (sc->secbus != 0) {
343 child = device_add_child(dev, "pci", sc->secbus);
345 return(bus_generic_attach(dev));
348 /* no secondary bus; we should have fixed this */
353 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
355 struct pcib_softc *sc = device_get_softc(dev);
358 case PCIB_IVAR_DOMAIN:
359 *result = sc->domain;
362 *result = sc->secbus;
369 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
371 struct pcib_softc *sc = device_get_softc(dev);
374 case PCIB_IVAR_DOMAIN:
384 * We have to trap resource allocation requests and ensure that the bridge
385 * is set up to, or capable of handling them.
388 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
389 u_long start, u_long end, u_long count, u_int flags)
391 struct pcib_softc *sc = device_get_softc(dev);
392 const char *name, *suffix;
396 * Fail the allocation for this range if it's not supported.
398 name = device_get_nameunit(child);
407 if (!pcib_is_io_open(sc))
409 ok = (start >= sc->iobase && end <= sc->iolimit);
412 * Make sure we allow access to VGA I/O addresses when the
413 * bridge has the "VGA Enable" bit set.
415 if (!ok && pci_is_vga_ioport_range(start, end))
416 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
418 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
420 if (start < sc->iobase)
422 if (end > sc->iolimit)
430 if (start < sc->iobase && end > sc->iolimit) {
437 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
444 device_printf(dev, "%s%srequested unsupported I/O "
445 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
446 name, suffix, start, end, sc->iobase, sc->iolimit);
451 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
452 name, suffix, start, end);
457 if (pcib_is_nonprefetch_open(sc))
458 ok = ok || (start >= sc->membase && end <= sc->memlimit);
459 if (pcib_is_prefetch_open(sc))
460 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
463 * Make sure we allow access to VGA memory addresses when the
464 * bridge has the "VGA Enable" bit set.
466 if (!ok && pci_is_vga_memory_range(start, end))
467 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
469 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
472 if (flags & RF_PREFETCHABLE) {
473 if (pcib_is_prefetch_open(sc)) {
474 if (start < sc->pmembase)
475 start = sc->pmembase;
476 if (end > sc->pmemlimit)
481 } else { /* non-prefetchable */
482 if (pcib_is_nonprefetch_open(sc)) {
483 if (start < sc->membase)
485 if (end > sc->memlimit)
493 ok = 1; /* subtractive bridge: always ok */
495 if (pcib_is_nonprefetch_open(sc)) {
496 if (start < sc->membase && end > sc->memlimit) {
501 if (pcib_is_prefetch_open(sc)) {
502 if (start < sc->pmembase && end > sc->pmemlimit) {
503 start = sc->pmembase;
510 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
516 if (!ok && bootverbose)
518 "%s%srequested unsupported memory range %#lx-%#lx "
519 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
520 name, suffix, start, end,
521 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
522 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
526 device_printf(dev,"%s%srequested memory range "
527 "0x%lx-0x%lx: good\n",
528 name, suffix, start, end);
535 * Bridge is OK decoding this resource, so pass it up.
537 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
545 pcib_maxslots(device_t dev)
551 * Since we are a child of a PCI bus, its parent must support the pcib interface.
554 pcib_read_config(device_t dev, int b, int s, int f, int reg, int width)
556 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, width));
560 pcib_write_config(device_t dev, int b, int s, int f, int reg, uint32_t val, int width)
562 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, reg, val, width);
566 * Route an interrupt across a PCI bridge.
569 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
577 * The PCI standard defines a swizzle of the child-side device/intpin to
578 * the parent-side intpin as follows.
580 * device = device on child bus
581 * child_intpin = intpin on child bus slot (0-3)
582 * parent_intpin = intpin on parent bus slot (0-3)
584 * parent_intpin = (device + child_intpin) % 4
586 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
589 * Our parent is a PCI bus. Its parent must export the pcib interface
590 * which includes the ability to route interrupts.
592 bus = device_get_parent(pcib);
593 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
594 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
595 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
596 pci_get_slot(dev), 'A' + pin - 1, intnum);
601 /* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
603 pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
605 struct pcib_softc *sc = device_get_softc(pcib);
608 if (sc->flags & PCIB_DISABLE_MSI)
610 bus = device_get_parent(pcib);
611 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
615 /* Pass request to release MSI/MSI-X messages up to the parent bridge. */
617 pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
621 bus = device_get_parent(pcib);
622 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
625 /* Pass request to alloc an MSI-X message up to the parent bridge. */
627 pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
629 struct pcib_softc *sc = device_get_softc(pcib);
632 if (sc->flags & PCIB_DISABLE_MSI)
634 bus = device_get_parent(pcib);
635 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
638 /* Pass request to release an MSI-X message up to the parent bridge. */
640 pcib_release_msix(device_t pcib, device_t dev, int irq)
644 bus = device_get_parent(pcib);
645 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
648 /* Pass request to map MSI/MSI-X message up to parent bridge. */
650 pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
656 bus = device_get_parent(pcib);
657 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
661 pci_ht_map_msi(pcib, *addr);
666 * Try to read the bus number of a host-PCI bridge using appropriate config
670 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
675 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
676 if (id == 0xffffffff)
682 /* XXX This is a guess */
683 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
687 /* Intel 82454KX/GX (Orion) */
688 *busnum = read_config(bus, slot, func, 0x4a, 1);
692 * For the 450nx chipset, there is a whole bundle of
693 * things pretending to be host bridges. The MIOC will
694 * be seen first and isn't really a pci bridge (the
695 * actual busses are attached to the PXB's). We need to
696 * read the registers of the MIOC to figure out the
697 * bus numbers for the PXB channels.
699 * Since the MIOC doesn't have a pci bus attached, we
700 * pretend it wasn't there.
706 /* Intel 82454NX PXB#0, Bus#A */
707 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
710 /* Intel 82454NX PXB#0, Bus#B */
711 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
714 /* Intel 82454NX PXB#1, Bus#A */
715 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
718 /* Intel 82454NX PXB#1, Bus#B */
719 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
724 /* ServerWorks -- vendor 0x1166 */
736 *busnum = read_config(bus, slot, func, 0x44, 1);
739 /* Compaq/HP -- vendor 0x0e11 */
741 *busnum = read_config(bus, slot, func, 0xc8, 1);
744 /* Don't know how to read bus number. */