sys/platform/pc32/apic/ioapic_abi.c

   1 /*
   2  * Copyright (c) 2005 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 1996, by Steve Passe.  All rights reserved.
   4  * Copyright (c) 1991 The Regents of the University of California.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to The DragonFly Project
   8  * by Matthew Dillon <dillon@backplane.com>
   9  *
  10  * This code is derived from software contributed to Berkeley by
  11  * William Jolitz.
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  * 3. Neither the name of The DragonFly Project nor the names of its
  24  *    contributors may be used to endorse or promote products derived
  25  *    from this software without specific, prior written permission.
  26  *
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  30  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  31  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  32  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  33  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  35  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  38  * SUCH DAMAGE.
  39  *
  40  * $DragonFly: src/sys/platform/pc32/apic/apic_abi.c,v 1.12 2007/04/30 16:45:55 dillon Exp $
  41  */
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/machintr.h>
  47 #include <sys/interrupt.h>
  48 #include <sys/bus.h>
  49
  50 #include <machine/smp.h>
  51 #include <machine/segments.h>
  52 #include <machine/md_var.h>
  53 #include <machine/intr_machdep.h>
  54 #include <machine/globaldata.h>
  55
  56 #include <sys/thread2.h>
  57
  58 #include <machine_base/icu/icu.h>
  59 #include <machine_base/icu/icu_var.h>
  60 #include <machine_base/apic/ioapic.h>
  61 #include <machine_base/apic/ioapic_abi.h>
  62 #include <machine_base/apic/ioapic_ipl.h>
  63
  64 extern inthand_t
  65         IDTVEC(ioapic_intr0),
  66         IDTVEC(ioapic_intr1),
  67         IDTVEC(ioapic_intr2),
  68         IDTVEC(ioapic_intr3),
  69         IDTVEC(ioapic_intr4),
  70         IDTVEC(ioapic_intr5),
  71         IDTVEC(ioapic_intr6),
  72         IDTVEC(ioapic_intr7),
  73         IDTVEC(ioapic_intr8),
  74         IDTVEC(ioapic_intr9),
  75         IDTVEC(ioapic_intr10),
  76         IDTVEC(ioapic_intr11),
  77         IDTVEC(ioapic_intr12),
  78         IDTVEC(ioapic_intr13),
  79         IDTVEC(ioapic_intr14),
  80         IDTVEC(ioapic_intr15),
  81         IDTVEC(ioapic_intr16),
  82         IDTVEC(ioapic_intr17),
  83         IDTVEC(ioapic_intr18),
  84         IDTVEC(ioapic_intr19),
  85         IDTVEC(ioapic_intr20),
  86         IDTVEC(ioapic_intr21),
  87         IDTVEC(ioapic_intr22),
  88         IDTVEC(ioapic_intr23),
  89         IDTVEC(ioapic_intr24),
  90         IDTVEC(ioapic_intr25),
  91         IDTVEC(ioapic_intr26),
  92         IDTVEC(ioapic_intr27),
  93         IDTVEC(ioapic_intr28),
  94         IDTVEC(ioapic_intr29),
  95         IDTVEC(ioapic_intr30),
  96         IDTVEC(ioapic_intr31),
  97         IDTVEC(ioapic_intr32),
  98         IDTVEC(ioapic_intr33),
  99         IDTVEC(ioapic_intr34),
 100         IDTVEC(ioapic_intr35),
 101         IDTVEC(ioapic_intr36),
 102         IDTVEC(ioapic_intr37),
 103         IDTVEC(ioapic_intr38),
 104         IDTVEC(ioapic_intr39),
 105         IDTVEC(ioapic_intr40),
 106         IDTVEC(ioapic_intr41),
 107         IDTVEC(ioapic_intr42),
 108         IDTVEC(ioapic_intr43),
 109         IDTVEC(ioapic_intr44),
 110         IDTVEC(ioapic_intr45),
 111         IDTVEC(ioapic_intr46),
 112         IDTVEC(ioapic_intr47),
 113         IDTVEC(ioapic_intr48),
 114         IDTVEC(ioapic_intr49),
 115         IDTVEC(ioapic_intr50),
 116         IDTVEC(ioapic_intr51),
 117         IDTVEC(ioapic_intr52),
 118         IDTVEC(ioapic_intr53),
 119         IDTVEC(ioapic_intr54),
 120         IDTVEC(ioapic_intr55),
 121         IDTVEC(ioapic_intr56),
 122         IDTVEC(ioapic_intr57),
 123         IDTVEC(ioapic_intr58),
 124         IDTVEC(ioapic_intr59),
 125         IDTVEC(ioapic_intr60),
 126         IDTVEC(ioapic_intr61),
 127         IDTVEC(ioapic_intr62),
 128         IDTVEC(ioapic_intr63),
 129         IDTVEC(ioapic_intr64),
 130         IDTVEC(ioapic_intr65),
 131         IDTVEC(ioapic_intr66),
 132         IDTVEC(ioapic_intr67),
 133         IDTVEC(ioapic_intr68),
 134         IDTVEC(ioapic_intr69),
 135         IDTVEC(ioapic_intr70),
 136         IDTVEC(ioapic_intr71),
 137         IDTVEC(ioapic_intr72),
 138         IDTVEC(ioapic_intr73),
 139         IDTVEC(ioapic_intr74),
 140         IDTVEC(ioapic_intr75),
 141         IDTVEC(ioapic_intr76),
 142         IDTVEC(ioapic_intr77),
 143         IDTVEC(ioapic_intr78),
 144         IDTVEC(ioapic_intr79),
 145         IDTVEC(ioapic_intr80),
 146         IDTVEC(ioapic_intr81),
 147         IDTVEC(ioapic_intr82),
 148         IDTVEC(ioapic_intr83),
 149         IDTVEC(ioapic_intr84),
 150         IDTVEC(ioapic_intr85),
 151         IDTVEC(ioapic_intr86),
 152         IDTVEC(ioapic_intr87),
 153         IDTVEC(ioapic_intr88),
 154         IDTVEC(ioapic_intr89),
 155         IDTVEC(ioapic_intr90),
 156         IDTVEC(ioapic_intr91),
 157         IDTVEC(ioapic_intr92),
 158         IDTVEC(ioapic_intr93),
 159         IDTVEC(ioapic_intr94),
 160         IDTVEC(ioapic_intr95),
 161         IDTVEC(ioapic_intr96),
 162         IDTVEC(ioapic_intr97),
 163         IDTVEC(ioapic_intr98),
 164         IDTVEC(ioapic_intr99),
 165         IDTVEC(ioapic_intr100),
 166         IDTVEC(ioapic_intr101),
 167         IDTVEC(ioapic_intr102),
 168         IDTVEC(ioapic_intr103),
 169         IDTVEC(ioapic_intr104),
 170         IDTVEC(ioapic_intr105),
 171         IDTVEC(ioapic_intr106),
 172         IDTVEC(ioapic_intr107),
 173         IDTVEC(ioapic_intr108),
 174         IDTVEC(ioapic_intr109),
 175         IDTVEC(ioapic_intr110),
 176         IDTVEC(ioapic_intr111),
 177         IDTVEC(ioapic_intr112),
 178         IDTVEC(ioapic_intr113),
 179         IDTVEC(ioapic_intr114),
 180         IDTVEC(ioapic_intr115),
 181         IDTVEC(ioapic_intr116),
 182         IDTVEC(ioapic_intr117),
 183         IDTVEC(ioapic_intr118),
 184         IDTVEC(ioapic_intr119),
 185         IDTVEC(ioapic_intr120),
 186         IDTVEC(ioapic_intr121),
 187         IDTVEC(ioapic_intr122),
 188         IDTVEC(ioapic_intr123),
 189         IDTVEC(ioapic_intr124),
 190         IDTVEC(ioapic_intr125),
 191         IDTVEC(ioapic_intr126),
 192         IDTVEC(ioapic_intr127),
 193         IDTVEC(ioapic_intr128),
 194         IDTVEC(ioapic_intr129),
 195         IDTVEC(ioapic_intr130),
 196         IDTVEC(ioapic_intr131),
 197         IDTVEC(ioapic_intr132),
 198         IDTVEC(ioapic_intr133),
 199         IDTVEC(ioapic_intr134),
 200         IDTVEC(ioapic_intr135),
 201         IDTVEC(ioapic_intr136),
 202         IDTVEC(ioapic_intr137),
 203         IDTVEC(ioapic_intr138),
 204         IDTVEC(ioapic_intr139),
 205         IDTVEC(ioapic_intr140),
 206         IDTVEC(ioapic_intr141),
 207         IDTVEC(ioapic_intr142),
 208         IDTVEC(ioapic_intr143),
 209         IDTVEC(ioapic_intr144),
 210         IDTVEC(ioapic_intr145),
 211         IDTVEC(ioapic_intr146),
 212         IDTVEC(ioapic_intr147),
 213         IDTVEC(ioapic_intr148),
 214         IDTVEC(ioapic_intr149),
 215         IDTVEC(ioapic_intr150),
 216         IDTVEC(ioapic_intr151),
 217         IDTVEC(ioapic_intr152),
 218         IDTVEC(ioapic_intr153),
 219         IDTVEC(ioapic_intr154),
 220         IDTVEC(ioapic_intr155),
 221         IDTVEC(ioapic_intr156),
 222         IDTVEC(ioapic_intr157),
 223         IDTVEC(ioapic_intr158),
 224         IDTVEC(ioapic_intr159),
 225         IDTVEC(ioapic_intr160),
 226         IDTVEC(ioapic_intr161),
 227         IDTVEC(ioapic_intr162),
 228         IDTVEC(ioapic_intr163),
 229         IDTVEC(ioapic_intr164),
 230         IDTVEC(ioapic_intr165),
 231         IDTVEC(ioapic_intr166),
 232         IDTVEC(ioapic_intr167),
 233         IDTVEC(ioapic_intr168),
 234         IDTVEC(ioapic_intr169),
 235         IDTVEC(ioapic_intr170),
 236         IDTVEC(ioapic_intr171),
 237         IDTVEC(ioapic_intr172),
 238         IDTVEC(ioapic_intr173),
 239         IDTVEC(ioapic_intr174),
 240         IDTVEC(ioapic_intr175),
 241         IDTVEC(ioapic_intr176),
 242         IDTVEC(ioapic_intr177),
 243         IDTVEC(ioapic_intr178),
 244         IDTVEC(ioapic_intr179),
 245         IDTVEC(ioapic_intr180),
 246         IDTVEC(ioapic_intr181),
 247         IDTVEC(ioapic_intr182),
 248         IDTVEC(ioapic_intr183),
 249         IDTVEC(ioapic_intr184),
 250         IDTVEC(ioapic_intr185),
 251         IDTVEC(ioapic_intr186),
 252         IDTVEC(ioapic_intr187),
 253         IDTVEC(ioapic_intr188),
 254         IDTVEC(ioapic_intr189),
 255         IDTVEC(ioapic_intr190),
 256         IDTVEC(ioapic_intr191);
 257
 258 static inthand_t *ioapic_intr[IOAPIC_HWI_VECTORS] = {
 259         &IDTVEC(ioapic_intr0),
 260         &IDTVEC(ioapic_intr1),
 261         &IDTVEC(ioapic_intr2),
 262         &IDTVEC(ioapic_intr3),
 263         &IDTVEC(ioapic_intr4),
 264         &IDTVEC(ioapic_intr5),
 265         &IDTVEC(ioapic_intr6),
 266         &IDTVEC(ioapic_intr7),
 267         &IDTVEC(ioapic_intr8),
 268         &IDTVEC(ioapic_intr9),
 269         &IDTVEC(ioapic_intr10),
 270         &IDTVEC(ioapic_intr11),
 271         &IDTVEC(ioapic_intr12),
 272         &IDTVEC(ioapic_intr13),
 273         &IDTVEC(ioapic_intr14),
 274         &IDTVEC(ioapic_intr15),
 275         &IDTVEC(ioapic_intr16),
 276         &IDTVEC(ioapic_intr17),
 277         &IDTVEC(ioapic_intr18),
 278         &IDTVEC(ioapic_intr19),
 279         &IDTVEC(ioapic_intr20),
 280         &IDTVEC(ioapic_intr21),
 281         &IDTVEC(ioapic_intr22),
 282         &IDTVEC(ioapic_intr23),
 283         &IDTVEC(ioapic_intr24),
 284         &IDTVEC(ioapic_intr25),
 285         &IDTVEC(ioapic_intr26),
 286         &IDTVEC(ioapic_intr27),
 287         &IDTVEC(ioapic_intr28),
 288         &IDTVEC(ioapic_intr29),
 289         &IDTVEC(ioapic_intr30),
 290         &IDTVEC(ioapic_intr31),
 291         &IDTVEC(ioapic_intr32),
 292         &IDTVEC(ioapic_intr33),
 293         &IDTVEC(ioapic_intr34),
 294         &IDTVEC(ioapic_intr35),
 295         &IDTVEC(ioapic_intr36),
 296         &IDTVEC(ioapic_intr37),
 297         &IDTVEC(ioapic_intr38),
 298         &IDTVEC(ioapic_intr39),
 299         &IDTVEC(ioapic_intr40),
 300         &IDTVEC(ioapic_intr41),
 301         &IDTVEC(ioapic_intr42),
 302         &IDTVEC(ioapic_intr43),
 303         &IDTVEC(ioapic_intr44),
 304         &IDTVEC(ioapic_intr45),
 305         &IDTVEC(ioapic_intr46),
 306         &IDTVEC(ioapic_intr47),
 307         &IDTVEC(ioapic_intr48),
 308         &IDTVEC(ioapic_intr49),
 309         &IDTVEC(ioapic_intr50),
 310         &IDTVEC(ioapic_intr51),
 311         &IDTVEC(ioapic_intr52),
 312         &IDTVEC(ioapic_intr53),
 313         &IDTVEC(ioapic_intr54),
 314         &IDTVEC(ioapic_intr55),
 315         &IDTVEC(ioapic_intr56),
 316         &IDTVEC(ioapic_intr57),
 317         &IDTVEC(ioapic_intr58),
 318         &IDTVEC(ioapic_intr59),
 319         &IDTVEC(ioapic_intr60),
 320         &IDTVEC(ioapic_intr61),
 321         &IDTVEC(ioapic_intr62),
 322         &IDTVEC(ioapic_intr63),
 323         &IDTVEC(ioapic_intr64),
 324         &IDTVEC(ioapic_intr65),
 325         &IDTVEC(ioapic_intr66),
 326         &IDTVEC(ioapic_intr67),
 327         &IDTVEC(ioapic_intr68),
 328         &IDTVEC(ioapic_intr69),
 329         &IDTVEC(ioapic_intr70),
 330         &IDTVEC(ioapic_intr71),
 331         &IDTVEC(ioapic_intr72),
 332         &IDTVEC(ioapic_intr73),
 333         &IDTVEC(ioapic_intr74),
 334         &IDTVEC(ioapic_intr75),
 335         &IDTVEC(ioapic_intr76),
 336         &IDTVEC(ioapic_intr77),
 337         &IDTVEC(ioapic_intr78),
 338         &IDTVEC(ioapic_intr79),
 339         &IDTVEC(ioapic_intr80),
 340         &IDTVEC(ioapic_intr81),
 341         &IDTVEC(ioapic_intr82),
 342         &IDTVEC(ioapic_intr83),
 343         &IDTVEC(ioapic_intr84),
 344         &IDTVEC(ioapic_intr85),
 345         &IDTVEC(ioapic_intr86),
 346         &IDTVEC(ioapic_intr87),
 347         &IDTVEC(ioapic_intr88),
 348         &IDTVEC(ioapic_intr89),
 349         &IDTVEC(ioapic_intr90),
 350         &IDTVEC(ioapic_intr91),
 351         &IDTVEC(ioapic_intr92),
 352         &IDTVEC(ioapic_intr93),
 353         &IDTVEC(ioapic_intr94),
 354         &IDTVEC(ioapic_intr95),
 355         &IDTVEC(ioapic_intr96),
 356         &IDTVEC(ioapic_intr97),
 357         &IDTVEC(ioapic_intr98),
 358         &IDTVEC(ioapic_intr99),
 359         &IDTVEC(ioapic_intr100),
 360         &IDTVEC(ioapic_intr101),
 361         &IDTVEC(ioapic_intr102),
 362         &IDTVEC(ioapic_intr103),
 363         &IDTVEC(ioapic_intr104),
 364         &IDTVEC(ioapic_intr105),
 365         &IDTVEC(ioapic_intr106),
 366         &IDTVEC(ioapic_intr107),
 367         &IDTVEC(ioapic_intr108),
 368         &IDTVEC(ioapic_intr109),
 369         &IDTVEC(ioapic_intr110),
 370         &IDTVEC(ioapic_intr111),
 371         &IDTVEC(ioapic_intr112),
 372         &IDTVEC(ioapic_intr113),
 373         &IDTVEC(ioapic_intr114),
 374         &IDTVEC(ioapic_intr115),
 375         &IDTVEC(ioapic_intr116),
 376         &IDTVEC(ioapic_intr117),
 377         &IDTVEC(ioapic_intr118),
 378         &IDTVEC(ioapic_intr119),
 379         &IDTVEC(ioapic_intr120),
 380         &IDTVEC(ioapic_intr121),
 381         &IDTVEC(ioapic_intr122),
 382         &IDTVEC(ioapic_intr123),
 383         &IDTVEC(ioapic_intr124),
 384         &IDTVEC(ioapic_intr125),
 385         &IDTVEC(ioapic_intr126),
 386         &IDTVEC(ioapic_intr127),
 387         &IDTVEC(ioapic_intr128),
 388         &IDTVEC(ioapic_intr129),
 389         &IDTVEC(ioapic_intr130),
 390         &IDTVEC(ioapic_intr131),
 391         &IDTVEC(ioapic_intr132),
 392         &IDTVEC(ioapic_intr133),
 393         &IDTVEC(ioapic_intr134),
 394         &IDTVEC(ioapic_intr135),
 395         &IDTVEC(ioapic_intr136),
 396         &IDTVEC(ioapic_intr137),
 397         &IDTVEC(ioapic_intr138),
 398         &IDTVEC(ioapic_intr139),
 399         &IDTVEC(ioapic_intr140),
 400         &IDTVEC(ioapic_intr141),
 401         &IDTVEC(ioapic_intr142),
 402         &IDTVEC(ioapic_intr143),
 403         &IDTVEC(ioapic_intr144),
 404         &IDTVEC(ioapic_intr145),
 405         &IDTVEC(ioapic_intr146),
 406         &IDTVEC(ioapic_intr147),
 407         &IDTVEC(ioapic_intr148),
 408         &IDTVEC(ioapic_intr149),
 409         &IDTVEC(ioapic_intr150),
 410         &IDTVEC(ioapic_intr151),
 411         &IDTVEC(ioapic_intr152),
 412         &IDTVEC(ioapic_intr153),
 413         &IDTVEC(ioapic_intr154),
 414         &IDTVEC(ioapic_intr155),
 415         &IDTVEC(ioapic_intr156),
 416         &IDTVEC(ioapic_intr157),
 417         &IDTVEC(ioapic_intr158),
 418         &IDTVEC(ioapic_intr159),
 419         &IDTVEC(ioapic_intr160),
 420         &IDTVEC(ioapic_intr161),
 421         &IDTVEC(ioapic_intr162),
 422         &IDTVEC(ioapic_intr163),
 423         &IDTVEC(ioapic_intr164),
 424         &IDTVEC(ioapic_intr165),
 425         &IDTVEC(ioapic_intr166),
 426         &IDTVEC(ioapic_intr167),
 427         &IDTVEC(ioapic_intr168),
 428         &IDTVEC(ioapic_intr169),
 429         &IDTVEC(ioapic_intr170),
 430         &IDTVEC(ioapic_intr171),
 431         &IDTVEC(ioapic_intr172),
 432         &IDTVEC(ioapic_intr173),
 433         &IDTVEC(ioapic_intr174),
 434         &IDTVEC(ioapic_intr175),
 435         &IDTVEC(ioapic_intr176),
 436         &IDTVEC(ioapic_intr177),
 437         &IDTVEC(ioapic_intr178),
 438         &IDTVEC(ioapic_intr179),
 439         &IDTVEC(ioapic_intr180),
 440         &IDTVEC(ioapic_intr181),
 441         &IDTVEC(ioapic_intr182),
 442         &IDTVEC(ioapic_intr183),
 443         &IDTVEC(ioapic_intr184),
 444         &IDTVEC(ioapic_intr185),
 445         &IDTVEC(ioapic_intr186),
 446         &IDTVEC(ioapic_intr187),
 447         &IDTVEC(ioapic_intr188),
 448         &IDTVEC(ioapic_intr189),
 449         &IDTVEC(ioapic_intr190),
 450         &IDTVEC(ioapic_intr191)
 451 };
 452
 453 #define IOAPIC_HWI_SYSCALL      (IDT_OFFSET_SYSCALL - IDT_OFFSET)
 454
 455 static struct ioapic_irqmap {
 456         int                     im_type;        /* IOAPIC_IMT_ */
 457         enum intr_trigger       im_trig;
 458         enum intr_polarity      im_pola;
 459         int                     im_gsi;
 460         uint32_t                im_flags;       /* IOAPIC_IMF_ */
 461 } ioapic_irqmaps[MAX_HARDINTS]; /* XXX MAX_HARDINTS may not be correct */
 462
 463 #define IOAPIC_IMT_UNUSED       0
 464 #define IOAPIC_IMT_RESERVED     1
 465 #define IOAPIC_IMT_LINE         2
 466 #define IOAPIC_IMT_SYSCALL      3
 467
 468 #define IOAPIC_IMF_CONF         0x1
 469
 470 extern void     IOAPIC_INTREN(int);
 471 extern void     IOAPIC_INTRDIS(int);
 472
 473 extern int      imcr_present;
 474
 475 static int      ioapic_setvar(int, const void *);
 476 static int      ioapic_getvar(int, void *);
 477 static int      ioapic_vectorctl(int, int, int);
 478 static void     ioapic_finalize(void);
 479 static void     ioapic_cleanup(void);
 480 static void     ioapic_setdefault(void);
 481 static void     ioapic_stabilize(void);
 482 static void     ioapic_initmap(void);
 483 static void     ioapic_intr_config(int, enum intr_trigger, enum intr_polarity);
 484 static void     ioapic_abi_intren(int);
 485 static void     ioapic_abi_intrdis(int);
 486
 487 struct machintr_abi MachIntrABI_IOAPIC = {
 488         MACHINTR_IOAPIC,
 489         .intrdis        = ioapic_abi_intrdis,
 490         .intren         = ioapic_abi_intren,
 491         .vectorctl      = ioapic_vectorctl,
 492         .setvar         = ioapic_setvar,
 493         .getvar         = ioapic_getvar,
 494         .finalize       = ioapic_finalize,
 495         .cleanup        = ioapic_cleanup,
 496         .setdefault     = ioapic_setdefault,
 497         .stabilize      = ioapic_stabilize,
 498         .initmap        = ioapic_initmap,
 499         .intr_config    = ioapic_intr_config
 500 };
 501
 502 static int      ioapic_abi_extint_irq = -1;
 503
 504 struct apic_intmapinfo  int_to_apicintpin[APIC_INTMAPSIZE];
 505
 506 static void
 507 ioapic_abi_intren(int irq)
 508 {
 509         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
 510                 kprintf("ioapic_abi_intren invalid irq %d\n", irq);
 511                 return;
 512         }
 513         IOAPIC_INTREN(irq);
 514 }
 515
 516 static void
 517 ioapic_abi_intrdis(int irq)
 518 {
 519         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS) {
 520                 kprintf("ioapic_abi_intrdis invalid irq %d\n", irq);
 521                 return;
 522         }
 523         IOAPIC_INTRDIS(irq);
 524 }
 525
 526 static int
 527 ioapic_setvar(int varid, const void *buf)
 528 {
 529         return ENOENT;
 530 }
 531
 532 static int
 533 ioapic_getvar(int varid, void *buf)
 534 {
 535         return ENOENT;
 536 }
 537
 538 static void
 539 ioapic_finalize(void)
 540 {
 541         KKASSERT(MachIntrABI.type == MACHINTR_IOAPIC);
 542         KKASSERT(ioapic_enable);
 543
 544         /*
 545          * If an IMCR is present, program bit 0 to disconnect the 8259
 546          * from the BSP.
 547          */
 548         if (imcr_present) {
 549                 outb(0x22, 0x70);       /* select IMCR */
 550                 outb(0x23, 0x01);       /* disconnect 8259 */
 551         }
 552 }
 553
 554 /*
 555  * This routine is called after physical interrupts are enabled but before
 556  * the critical section is released.  We need to clean out any interrupts
 557  * that had already been posted to the cpu.
 558  */
 559 static void
 560 ioapic_cleanup(void)
 561 {
 562         bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
 563 }
 564
 565 /* Must never be called */
 566 static void
 567 ioapic_stabilize(void)
 568 {
 569         panic("ioapic_stabilize() is called\n");
 570 }
 571
 572 static int
 573 ioapic_vectorctl(int op, int intr, int flags)
 574 {
 575         int error;
 576         int vector;
 577         int select;
 578         uint32_t value;
 579         u_long ef;
 580
 581         if (intr < 0 || intr >= IOAPIC_HWI_VECTORS ||
 582             intr == IOAPIC_HWI_SYSCALL)
 583                 return EINVAL;
 584
 585         ef = read_eflags();
 586         cpu_disable_intr();
 587         error = 0;
 588
 589         switch(op) {
 590         case MACHINTR_VECTOR_SETUP:
 591                 vector = IDT_OFFSET + intr;
 592                 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT,
 593                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 594
 595                 /*
 596                  * Now reprogram the vector in the IO APIC.  In order to avoid
 597                  * losing an EOI for a level interrupt, which is vector based,
 598                  * make sure that the IO APIC is programmed for edge-triggering
 599                  * first, then reprogrammed with the new vector.  This should
 600                  * clear the IRR bit.
 601                  */
 602                 if (int_to_apicintpin[intr].ioapic >= 0) {
 603                         imen_lock();
 604
 605                         select = int_to_apicintpin[intr].redirindex;
 606                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
 607                                             select);
 608                         value |= IOART_INTMSET;
 609
 610                         ioapic_write(int_to_apicintpin[intr].apic_address,
 611                                      select, (value & ~APIC_TRIGMOD_MASK));
 612                         ioapic_write(int_to_apicintpin[intr].apic_address,
 613                                      select, (value & ~IOART_INTVEC) | vector);
 614
 615                         imen_unlock();
 616                 }
 617
 618                 machintr_intren(intr);
 619                 break;
 620
 621         case MACHINTR_VECTOR_TEARDOWN:
 622                 /*
 623                  * Teardown an interrupt vector.  The vector should already be
 624                  * installed in the cpu's IDT, but make sure.
 625                  */
 626                 machintr_intrdis(intr);
 627
 628                 vector = IDT_OFFSET + intr;
 629                 setidt(vector, ioapic_intr[intr], SDT_SYS386IGT, SEL_KPL,
 630                        GSEL(GCODE_SEL, SEL_KPL));
 631
 632                 /*
 633                  * In order to avoid losing an EOI for a level interrupt, which
 634                  * is vector based, make sure that the IO APIC is programmed for
 635                  * edge-triggering first, then reprogrammed with the new vector.
 636                  * This should clear the IRR bit.
 637                  */
 638                 if (int_to_apicintpin[intr].ioapic >= 0) {
 639                         imen_lock();
 640
 641                         select = int_to_apicintpin[intr].redirindex;
 642                         value = ioapic_read(int_to_apicintpin[intr].apic_address,
 643                                             select);
 644
 645                         ioapic_write(int_to_apicintpin[intr].apic_address,
 646                                      select, (value & ~APIC_TRIGMOD_MASK));
 647                         ioapic_write(int_to_apicintpin[intr].apic_address,
 648                                      select, (value & ~IOART_INTVEC) | vector);
 649
 650                         imen_unlock();
 651                 }
 652                 break;
 653
 654         default:
 655                 error = EOPNOTSUPP;
 656                 break;
 657         }
 658
 659         write_eflags(ef);
 660         return error;
 661 }
 662
 663 static void
 664 ioapic_setdefault(void)
 665 {
 666         int intr;
 667
 668         for (intr = 0; intr < IOAPIC_HWI_VECTORS; ++intr) {
 669                 if (intr == IOAPIC_HWI_SYSCALL)
 670                         continue;
 671                 setidt(IDT_OFFSET + intr, ioapic_intr[intr], SDT_SYS386IGT,
 672                        SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
 673         }
 674 }
 675
 676 static void
 677 ioapic_initmap(void)
 678 {
 679         int i;
 680
 681         for (i = 0; i < IOAPIC_HWI_VECTORS; ++i)
 682                 ioapic_irqmaps[i].im_gsi = -1;
 683         ioapic_irqmaps[IOAPIC_HWI_SYSCALL].im_type = IOAPIC_IMT_SYSCALL;
 684 }
 685
 686 void
 687 ioapic_abi_set_irqmap(int irq, int gsi, enum intr_trigger trig,
 688     enum intr_polarity pola)
 689 {
 690         struct apic_intmapinfo *info;
 691         struct ioapic_irqmap *map;
 692         void *ioaddr;
 693         int pin;
 694
 695         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 696         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 697
 698         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 699         map = &ioapic_irqmaps[irq];
 700
 701         KKASSERT(map->im_type == IOAPIC_IMT_UNUSED);
 702         map->im_type = IOAPIC_IMT_LINE;
 703
 704         map->im_gsi = gsi;
 705         map->im_trig = trig;
 706         map->im_pola = pola;
 707
 708         if (bootverbose) {
 709                 kprintf("IOAPIC: irq %d -> gsi %d %s/%s\n",
 710                         irq, map->im_gsi,
 711                         intr_str_trigger(map->im_trig),
 712                         intr_str_polarity(map->im_pola));
 713         }
 714
 715         pin = ioapic_gsi_pin(map->im_gsi);
 716         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 717
 718         info = &int_to_apicintpin[irq];
 719
 720         imen_lock();
 721
 722         info->ioapic = 0; /* XXX unused */
 723         info->int_pin = pin;
 724         info->apic_address = ioaddr;
 725         info->redirindex = IOAPIC_REDTBL + (2 * pin);
 726         info->flags = IOAPIC_IM_FLAG_MASKED;
 727         if (map->im_trig == INTR_TRIGGER_LEVEL)
 728                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
 729
 730         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 731             map->im_trig, map->im_pola);
 732
 733         imen_unlock();
 734 }
 735
 736 void
 737 ioapic_abi_fixup_irqmap(void)
 738 {
 739         int i;
 740
 741         for (i = 0; i < 16; ++i) {
 742                 struct ioapic_irqmap *map = &ioapic_irqmaps[i];
 743
 744                 if (map->im_type == IOAPIC_IMT_UNUSED) {
 745                         map->im_type = IOAPIC_IMT_RESERVED;
 746                         if (bootverbose)
 747                                 kprintf("IOAPIC: irq %d reserved\n", i);
 748                 }
 749         }
 750 }
 751
 752 int
 753 ioapic_abi_find_gsi(int gsi, enum intr_trigger trig, enum intr_polarity pola)
 754 {
 755         int irq;
 756
 757         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 758         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 759
 760         for (irq = 0; irq < IOAPIC_HWI_VECTORS; ++irq) {
 761                 const struct ioapic_irqmap *map = &ioapic_irqmaps[irq];
 762
 763                 if (map->im_gsi == gsi) {
 764                         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
 765
 766                         if (map->im_flags & IOAPIC_IMF_CONF) {
 767                                 if (map->im_trig != trig ||
 768                                     map->im_pola != pola)
 769                                         return -1;
 770                         }
 771                         return irq;
 772                 }
 773         }
 774         return -1;
 775 }
 776
 777 int
 778 ioapic_abi_find_irq(int irq, enum intr_trigger trig, enum intr_polarity pola)
 779 {
 780         const struct ioapic_irqmap *map;
 781
 782         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 783         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 784
 785         if (irq < 0 || irq >= IOAPIC_HWI_VECTORS)
 786                 return -1;
 787         map = &ioapic_irqmaps[irq];
 788
 789         if (map->im_type != IOAPIC_IMT_LINE)
 790                 return -1;
 791
 792         if (map->im_flags & IOAPIC_IMF_CONF) {
 793                 if (map->im_trig != trig || map->im_pola != pola)
 794                         return -1;
 795         }
 796         return irq;
 797 }
 798
 799 static void
 800 ioapic_intr_config(int irq, enum intr_trigger trig, enum intr_polarity pola)
 801 {
 802         struct apic_intmapinfo *info;
 803         struct ioapic_irqmap *map;
 804         void *ioaddr;
 805         int pin;
 806
 807         KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
 808         KKASSERT(pola == INTR_POLARITY_HIGH || pola == INTR_POLARITY_LOW);
 809
 810         KKASSERT(irq >= 0 && irq < IOAPIC_HWI_VECTORS);
 811         map = &ioapic_irqmaps[irq];
 812
 813         KKASSERT(map->im_type == IOAPIC_IMT_LINE);
 814
 815 #ifdef notyet
 816         if (map->im_flags & IOAPIC_IMF_CONF) {
 817                 if (trig != map->im_trig) {
 818                         panic("ioapic_intr_config: trig %s -> %s\n",
 819                               intr_str_trigger(map->im_trig),
 820                               intr_str_trigger(trig));
 821                 }
 822                 if (pola != map->im_pola) {
 823                         panic("ioapic_intr_config: pola %s -> %s\n",
 824                               intr_str_polarity(map->im_pola),
 825                               intr_str_polarity(pola));
 826                 }
 827                 return;
 828         }
 829 #endif
 830         map->im_flags |= IOAPIC_IMF_CONF;
 831
 832         if (trig == map->im_trig && pola == map->im_pola)
 833                 return;
 834
 835         if (bootverbose) {
 836                 kprintf("IOAPIC: irq %d, gsi %d %s/%s -> %s/%s\n",
 837                         irq, map->im_gsi,
 838                         intr_str_trigger(map->im_trig),
 839                         intr_str_polarity(map->im_pola),
 840                         intr_str_trigger(trig),
 841                         intr_str_polarity(pola));
 842         }
 843         map->im_trig = trig;
 844         map->im_pola = pola;
 845
 846         pin = ioapic_gsi_pin(map->im_gsi);
 847         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 848
 849         info = &int_to_apicintpin[irq];
 850
 851         imen_lock();
 852
 853         info->flags &= ~IOAPIC_IM_FLAG_LEVEL;
 854         if (map->im_trig == INTR_TRIGGER_LEVEL)
 855                 info->flags |= IOAPIC_IM_FLAG_LEVEL;
 856
 857         ioapic_pin_setup(ioaddr, pin, IDT_OFFSET + irq,
 858             map->im_trig, map->im_pola);
 859
 860         imen_unlock();
 861 }
 862
 863 int
 864 ioapic_abi_extint_irqmap(int irq)
 865 {
 866         struct apic_intmapinfo *info;
 867         struct ioapic_irqmap *map;
 868         void *ioaddr;
 869         int pin, error, vec;
 870
 871         vec = IDT_OFFSET + irq;
 872
 873         if (ioapic_abi_extint_irq == irq)
 874                 return 0;
 875         else if (ioapic_abi_extint_irq >= 0)
 876                 return EEXIST;
 877
 878         error = icu_ioapic_extint(irq, vec);
 879         if (error)
 880                 return error;
 881
 882         map = &ioapic_irqmaps[irq];
 883
 884         KKASSERT(map->im_type == IOAPIC_IMT_RESERVED ||
 885                  map->im_type == IOAPIC_IMT_LINE);
 886         if (map->im_type == IOAPIC_IMT_LINE) {
 887                 if (map->im_flags & IOAPIC_IMF_CONF)
 888                         return EEXIST;
 889         }
 890         ioapic_abi_extint_irq = irq;
 891
 892         map->im_type = IOAPIC_IMT_LINE;
 893         map->im_trig = INTR_TRIGGER_EDGE;
 894         map->im_pola = INTR_POLARITY_HIGH;
 895         map->im_flags = IOAPIC_IMF_CONF;
 896
 897         map->im_gsi = ioapic_extpin_gsi();
 898         KKASSERT(map->im_gsi >= 0);
 899
 900         if (bootverbose) {
 901                 kprintf("IOAPIC: irq %d -> extint gsi %d %s/%s\n",
 902                         irq, map->im_gsi,
 903                         intr_str_trigger(map->im_trig),
 904                         intr_str_polarity(map->im_pola));
 905         }
 906
 907         pin = ioapic_gsi_pin(map->im_gsi);
 908         ioaddr = ioapic_gsi_ioaddr(map->im_gsi);
 909
 910         info = &int_to_apicintpin[irq];
 911
 912         imen_lock();
 913
 914         info->ioapic = 0; /* XXX unused */
 915         info->int_pin = pin;
 916         info->apic_address = ioaddr;
 917         info->redirindex = IOAPIC_REDTBL + (2 * pin);
 918         info->flags = IOAPIC_IM_FLAG_MASKED;
 919
 920         ioapic_extpin_setup(ioaddr, pin, vec);
 921
 922         imen_unlock();
 923
 924         return 0;
 925 }