2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/isa/intr_machdep.h> /* IPIs */
69 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
71 #define WARMBOOT_TARGET 0
72 #define WARMBOOT_OFF (KERNBASE + 0x0467)
73 #define WARMBOOT_SEG (KERNBASE + 0x0469)
75 #define BIOS_BASE (0xf0000)
76 #define BIOS_SIZE (0x10000)
77 #define BIOS_COUNT (BIOS_SIZE/4)
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
84 #define PROCENTRY_FLAG_EN 0x01
85 #define PROCENTRY_FLAG_BP 0x02
86 #define IOAPICENTRY_FLAG_EN 0x01
89 /* MP Floating Pointer Structure */
90 typedef struct MPFPS {
103 /* MP Configuration Table Header */
104 typedef struct MPCTH {
106 u_short base_table_length;
110 u_char product_id[12];
111 u_int32_t oem_table_pointer;
112 u_short oem_table_size;
114 u_int32_t apic_address;
115 u_short extended_table_length;
116 u_char extended_table_checksum;
121 typedef struct PROCENTRY {
126 u_int32_t cpu_signature;
127 u_int32_t feature_flags;
132 typedef struct BUSENTRY {
138 typedef struct IOAPICENTRY {
143 u_int32_t apic_address;
144 } *io_apic_entry_ptr;
146 typedef struct INTENTRY {
156 /* descriptions of MP basetable entries */
157 typedef struct BASETABLE_ENTRY {
166 vm_size_t mp_cth_mapsz;
169 typedef int (*mptable_iter_func)(void *, const void *, int);
172 * this code MUST be enabled here and in mpboot.s.
173 * it follows the very early stages of AP boot by placing values in CMOS ram.
174 * it NORMALLY will never be needed and thus the primitive method for enabling.
177 #if defined(CHECK_POINTS)
178 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
179 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
181 #define CHECK_INIT(D); \
182 CHECK_WRITE(0x34, (D)); \
183 CHECK_WRITE(0x35, (D)); \
184 CHECK_WRITE(0x36, (D)); \
185 CHECK_WRITE(0x37, (D)); \
186 CHECK_WRITE(0x38, (D)); \
187 CHECK_WRITE(0x39, (D));
189 #define CHECK_PRINT(S); \
190 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
199 #else /* CHECK_POINTS */
201 #define CHECK_INIT(D)
202 #define CHECK_PRINT(S)
204 #endif /* CHECK_POINTS */
207 * Values to send to the POST hardware.
209 #define MP_BOOTADDRESS_POST 0x10
210 #define MP_PROBE_POST 0x11
211 #define MPTABLE_PASS1_POST 0x12
213 #define MP_START_POST 0x13
214 #define MP_ENABLE_POST 0x14
215 #define MPTABLE_PASS2_POST 0x15
217 #define START_ALL_APS_POST 0x16
218 #define INSTALL_AP_TRAMP_POST 0x17
219 #define START_AP_POST 0x18
221 #define MP_ANNOUNCE_POST 0x19
223 static int madt_probe_test;
224 TUNABLE_INT("hw.madt_probe_test", &madt_probe_test);
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
237 static vm_offset_t cpu_apic_address;
239 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
240 u_int32_t *io_apic_versions;
244 u_int32_t cpu_apic_versions[MAXCPU];
246 extern int64_t tsc_offsets[];
248 extern u_long ebda_addr;
251 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
255 * APIC ID logical/physical mapping structures.
256 * We oversize these to simplify boot-time config.
258 int cpu_num_to_apic_id[NAPICID];
260 int io_num_to_apic_id[NAPICID];
262 int apic_id_to_logical[NAPICID];
264 /* AP uses this during bootstrap. Do not staticize. */
269 * SMP page table page. Setup by locore to point to a page table
270 * page from which we allocate per-cpu privatespace areas io_apics,
274 #define IO_MAPPING_START_INDEX \
275 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
277 extern pt_entry_t *SMPpt;
279 struct pcb stoppcbs[MAXCPU];
281 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
283 static basetable_entry basetable_entry_types[] =
285 {0, 20, "Processor"},
293 * Local data and functions.
296 static u_int boot_address;
297 static u_int base_memory;
298 static int mp_finish;
300 static void mp_enable(u_int boot_addr);
302 static int mptable_iterate_entries(const mpcth_t,
303 mptable_iter_func, void *);
304 static int mptable_probe(void);
305 static int mptable_check(vm_paddr_t);
306 static long mptable_search_sig(u_int32_t target, int count);
307 static int mptable_hyperthread_fixup(u_int, int);
308 static void mptable_pass1(struct mptable_pos *);
309 static int mptable_pass2(struct mptable_pos *);
310 static void mptable_default(int type);
311 static void mptable_fix(void);
312 static int mptable_map(struct mptable_pos *, vm_paddr_t);
313 static void mptable_unmap(struct mptable_pos *);
314 static void mptable_lapic_enumerate(struct mptable_pos *);
315 static void mptable_lapic_default(void);
318 static void setup_apic_irq_mapping(void);
319 static int apic_int_is_bus_type(int intr, int bus_type);
321 static int start_all_aps(u_int boot_addr);
323 static void install_ap_tramp(u_int boot_addr);
325 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
326 static void lapic_init(vm_offset_t);
327 static int smitest(void);
329 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
330 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
331 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
332 static u_int bootMP_size;
335 * Calculate usable address in base memory for AP trampoline code.
338 mp_bootaddress(u_int basemem)
340 POSTCODE(MP_BOOTADDRESS_POST);
342 base_memory = basemem;
344 bootMP_size = mptramp_end - mptramp_start;
345 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
346 if (((basemem * 1024) - boot_address) < bootMP_size)
347 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
348 /* 3 levels of page table pages */
349 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
351 return mptramp_pagetables;
356 * Look for an Intel MP spec table (ie, SMP capable hardware).
365 * Make sure our SMPpt[] page table is big enough to hold all the
368 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
370 POSTCODE(MP_PROBE_POST);
372 /* see if EBDA exists */
373 if (ebda_addr != 0) {
374 /* search first 1K of EBDA */
375 target = (u_int32_t)ebda_addr;
376 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
379 /* last 1K of base memory, effective 'top of base' passed in */
380 target = (u_int32_t)(base_memory - 0x400);
381 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
385 /* search the BIOS */
386 target = (u_int32_t)BIOS_BASE;
387 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
394 struct mptable_check_cbarg {
400 mptable_check_callback(void *xarg, const void *pos, int type)
402 const struct PROCENTRY *ent;
403 struct mptable_check_cbarg *arg = xarg;
409 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
413 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
414 if (arg->found_bsp) {
415 kprintf("more than one BSP in base MP table\n");
424 mptable_check(vm_paddr_t mpfps_paddr)
426 struct mptable_pos mpt;
427 struct mptable_check_cbarg arg;
431 if (mpfps_paddr == 0)
434 error = mptable_map(&mpt, mpfps_paddr);
438 if (mpt.mp_fps->mpfb1 != 0)
446 if (cth->apic_address == 0)
449 bzero(&arg, sizeof(arg));
450 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
452 if (arg.cpu_count == 0) {
453 kprintf("MP table contains no processor entries\n");
455 } else if (!arg.found_bsp) {
456 kprintf("MP table does not contains BSP entry\n");
466 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
468 int count, total_size;
469 const void *position;
471 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
472 total_size = cth->base_table_length - sizeof(struct MPCTH);
473 position = (const uint8_t *)cth + sizeof(struct MPCTH);
474 count = cth->entry_count;
479 KKASSERT(total_size >= 0);
480 if (total_size == 0) {
481 kprintf("invalid base MP table, "
482 "entry count and length mismatch\n");
486 type = *(const uint8_t *)position;
488 case 0: /* processor_entry */
489 case 1: /* bus_entry */
490 case 2: /* io_apic_entry */
491 case 3: /* int_entry */
492 case 4: /* int_entry */
495 kprintf("unknown base MP table entry type %d\n", type);
499 if (total_size < basetable_entry_types[type].length) {
500 kprintf("invalid base MP table length, "
501 "does not contain all entries\n");
504 total_size -= basetable_entry_types[type].length;
506 error = func(arg, position, type);
510 position = (const uint8_t *)position +
511 basetable_entry_types[type].length;
518 * Startup the SMP processors.
523 POSTCODE(MP_START_POST);
524 mp_enable(boot_address);
529 * Print various information about the SMP system hardware and setup.
536 POSTCODE(MP_ANNOUNCE_POST);
538 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
539 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
540 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
541 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
542 for (x = 1; x <= mp_naps; ++x) {
543 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
544 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
545 kprintf(", at 0x%08jx\n", (intmax_t)cpu_apic_address);
549 for (x = 0; x < mp_napics; ++x) {
550 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
551 kprintf(", version: 0x%08x", io_apic_versions[x]);
552 kprintf(", at 0x%08lx\n", io_apic_address[x]);
555 kprintf(" Warning: APIC I/O disabled\n");
560 * AP cpu's call this to sync up protected mode.
562 * WARNING! %gs is not set up on entry. This routine sets up %gs.
568 int x, myid = bootAP;
570 struct mdglobaldata *md;
571 struct privatespace *ps;
573 ps = &CPU_prvspace[myid];
575 gdt_segs[GPROC0_SEL].ssd_base =
576 (long) &ps->mdglobaldata.gd_common_tss;
577 ps->mdglobaldata.mi.gd_prvspace = ps;
579 /* We fill the 32-bit segment descriptors */
580 for (x = 0; x < NGDT; x++) {
581 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
582 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
584 /* And now a 64-bit one */
585 ssdtosyssd(&gdt_segs[GPROC0_SEL],
586 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
588 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
589 r_gdt.rd_base = (long) &gdt[myid * NGDT];
590 lgdt(&r_gdt); /* does magic intra-segment return */
592 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
593 wrmsr(MSR_FSBASE, 0); /* User value */
594 wrmsr(MSR_GSBASE, (u_int64_t)ps);
595 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
601 mdcpu->gd_currentldt = _default_ldt;
604 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
605 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
607 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
609 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
611 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
613 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
614 md->gd_common_tssd = *md->gd_tss_gdt;
616 md->gd_common_tss.tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
621 * Set to a known state:
622 * Set by mpboot.s: CR0_PG, CR0_PE
623 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
626 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
629 /* Set up the fast syscall stuff */
630 msr = rdmsr(MSR_EFER) | EFER_SCE;
631 wrmsr(MSR_EFER, msr);
632 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
633 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
634 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
635 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
636 wrmsr(MSR_STAR, msr);
637 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
639 pmap_set_opt(); /* PSE/4MB pages, etc */
641 /* Initialize the PAT MSR. */
645 /* set up CPU registers and state */
648 /* set up SSE/NX registers */
651 /* set up FPU state on the AP */
652 npxinit(__INITIAL_NPXCW__);
654 /* disable the APIC, just to be SURE */
655 lapic->svr &= ~APIC_SVR_ENABLE;
657 /* data returned to BSP */
658 cpu_apic_versions[0] = lapic->version;
661 /*******************************************************************
662 * local functions and data
666 * start the SMP system
669 mp_enable(u_int boot_addr)
676 vm_paddr_t mpfps_paddr;
678 POSTCODE(MP_ENABLE_POST);
680 if (madt_probe_test) {
683 mpfps_paddr = mptable_probe();
684 if (mptable_check(mpfps_paddr))
689 struct mptable_pos mpt;
691 mptable_map(&mpt, mpfps_paddr);
693 mptable_lapic_enumerate(&mpt);
697 * We can safely map physical memory into SMPpt after
698 * mptable_pass1() completes.
703 * Examine the MP table for needed info
705 x = mptable_pass2(&mpt);
710 * Can't process default configs till the
711 * CPU APIC is pmapped
716 /* post scan cleanup */
720 vm_paddr_t madt_paddr;
721 vm_offset_t lapic_addr;
724 madt_paddr = madt_probe();
726 panic("mp_enable: madt_probe failed\n");
728 lapic_addr = madt_pass1(madt_paddr);
730 panic("mp_enable: no local apic (madt)!\n");
732 lapic_init(lapic_addr);
734 bsp_apic_id = APIC_ID(lapic->id);
735 if (madt_pass2(madt_paddr, bsp_apic_id))
736 panic("mp_enable: madt_pass2 failed\n");
741 setup_apic_irq_mapping();
743 /* fill the LOGICAL io_apic_versions table */
744 for (apic = 0; apic < mp_napics; ++apic) {
745 ux = io_apic_read(apic, IOAPIC_VER);
746 io_apic_versions[apic] = ux;
747 io_apic_set_id(apic, IO_TO_ID(apic));
750 /* program each IO APIC in the system */
751 for (apic = 0; apic < mp_napics; ++apic)
752 if (io_apic_setup(apic) < 0)
753 panic("IO APIC setup failure");
758 * These are required for SMP operation
761 /* install a 'Spurious INTerrupt' vector */
762 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
763 SDT_SYSIGT, SEL_KPL, 0);
765 /* install an inter-CPU IPI for TLB invalidation */
766 setidt(XINVLTLB_OFFSET, Xinvltlb,
767 SDT_SYSIGT, SEL_KPL, 0);
769 /* install an inter-CPU IPI for IPIQ messaging */
770 setidt(XIPIQ_OFFSET, Xipiq,
771 SDT_SYSIGT, SEL_KPL, 0);
773 /* install a timer vector */
774 setidt(XTIMER_OFFSET, Xtimer,
775 SDT_SYSIGT, SEL_KPL, 0);
777 /* install an inter-CPU IPI for CPU stop/restart */
778 setidt(XCPUSTOP_OFFSET, Xcpustop,
779 SDT_SYSIGT, SEL_KPL, 0);
781 /* start each Application Processor */
782 start_all_aps(boot_addr);
787 * look for the MP spec signature
790 /* string defined by the Intel MP Spec as identifying the MP table */
791 #define MP_SIG 0x5f504d5f /* _MP_ */
792 #define NEXT(X) ((X) += 4)
794 mptable_search_sig(u_int32_t target, int count)
800 KKASSERT(target != 0);
802 map_size = count * sizeof(u_int32_t);
803 addr = pmap_mapdev((vm_paddr_t)target, map_size);
806 for (x = 0; x < count; NEXT(x)) {
807 if (addr[x] == MP_SIG) {
808 /* make array index a byte index */
809 ret = target + (x * sizeof(u_int32_t));
814 pmap_unmapdev((vm_offset_t)addr, map_size);
819 typedef struct BUSDATA {
821 enum busTypes bus_type;
824 typedef struct INTDATA {
834 typedef struct BUSTYPENAME {
841 static bus_type_name bus_type_table[] =
847 {UNKNOWN_BUSTYPE, "---"},
850 {UNKNOWN_BUSTYPE, "---"},
851 {UNKNOWN_BUSTYPE, "---"},
852 {UNKNOWN_BUSTYPE, "---"},
853 {UNKNOWN_BUSTYPE, "---"},
854 {UNKNOWN_BUSTYPE, "---"},
856 {UNKNOWN_BUSTYPE, "---"},
857 {UNKNOWN_BUSTYPE, "---"},
858 {UNKNOWN_BUSTYPE, "---"},
859 {UNKNOWN_BUSTYPE, "---"},
861 {UNKNOWN_BUSTYPE, "---"}
864 /* from MP spec v1.4, table 5-1 */
865 static int default_data[7][5] =
867 /* nbus, id0, type0, id1, type1 */
868 {1, 0, ISA, 255, 255},
869 {1, 0, EISA, 255, 255},
870 {1, 0, EISA, 255, 255},
871 {1, 0, MCA, 255, 255},
873 {2, 0, EISA, 1, PCI},
878 static bus_datum *bus_data;
880 /* the IO INT data, one entry per possible APIC INTerrupt */
881 static io_int *io_apic_ints;
886 static int processor_entry (const struct PROCENTRY *entry, int cpu);
888 static int bus_entry (bus_entry_ptr entry, int bus);
889 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
890 static int int_entry (int_entry_ptr entry, int intr);
891 static int lookup_bus_type (char *name);
897 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
899 const struct IOAPICENTRY *ioapic_ent;
902 case 1: /* bus_entry */
906 case 2: /* io_apic_entry */
908 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
909 io_apic_address[mp_napics++] =
910 (vm_offset_t)ioapic_ent->apic_address;
914 case 3: /* int_entry */
924 * 1st pass on motherboard's Intel MP specification table.
933 mptable_pass1(struct mptable_pos *mpt)
939 POSTCODE(MPTABLE_PASS1_POST);
942 KKASSERT(fps != NULL);
944 /* clear various tables */
945 for (x = 0; x < NAPICID; ++x)
946 io_apic_address[x] = ~0; /* IO APIC address table */
952 /* check for use of 'default' configuration */
953 if (fps->mpfb1 != 0) {
954 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
955 mp_nbusses = default_data[fps->mpfb1 - 1][0];
961 error = mptable_iterate_entries(mpt->mp_cth,
962 mptable_ioapic_pass1_callback, NULL);
964 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
971 * 2nd pass on motherboard's Intel MP specification table.
974 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
975 * IO_TO_ID(N), logical IO to APIC ID table
980 mptable_pass2(struct mptable_pos *mpt)
994 POSTCODE(MPTABLE_PASS2_POST);
997 KKASSERT(fps != NULL);
1000 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
1001 M_DEVBUF, M_WAITOK);
1002 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
1003 M_DEVBUF, M_WAITOK | M_ZERO);
1004 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
1005 M_DEVBUF, M_WAITOK);
1006 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1007 M_DEVBUF, M_WAITOK);
1011 for (i = 0; i < mp_napics; i++) {
1012 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
1016 /* clear various tables */
1017 for (x = 0; x < NAPICID; ++x) {
1019 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1020 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1025 /* clear bus data table */
1026 for (x = 0; x < mp_nbusses; ++x)
1027 bus_data[x].bus_id = 0xff;
1029 /* clear IO APIC INT table */
1030 for (x = 0; x < (nintrs + 1); ++x) {
1031 io_apic_ints[x].int_type = 0xff;
1032 io_apic_ints[x].int_vector = 0xff;
1036 /* record whether PIC or virtual-wire mode */
1037 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, fps->mpfb2 & 0x80);
1039 /* check for use of 'default' configuration */
1040 if (fps->mpfb1 != 0)
1041 return fps->mpfb1; /* return default configuration type */
1044 KKASSERT(cth != NULL);
1046 /* walk the table, recording info of interest */
1047 totalSize = cth->base_table_length - sizeof(struct MPCTH);
1048 position = (u_char *) cth + sizeof(struct MPCTH);
1049 count = cth->entry_count;
1050 apic = bus = intr = 0;
1053 switch (type = *(u_char *) position) {
1058 if (bus_entry(position, bus))
1064 if (io_apic_entry(position, apic))
1070 if (int_entry(position, intr))
1075 /* int_entry(position); */
1078 panic("mpfps Base Table HOSED!");
1082 totalSize -= basetable_entry_types[type].length;
1083 position = (uint8_t *)position + basetable_entry_types[type].length;
1086 /* report fact that its NOT a default configuration */
1092 * Check if we should perform a hyperthreading "fix-up" to
1093 * enumerate any logical CPU's that aren't already listed
1096 * XXX: We assume that all of the physical CPUs in the
1097 * system have the same number of logical CPUs.
1099 * XXX: We assume that APIC ID's are allocated such that
1100 * the APIC ID's for a physical processor are aligned
1101 * with the number of logical CPU's in the processor.
1104 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1106 int i, id, lcpus_max, logical_cpus;
1108 if ((cpu_feature & CPUID_HTT) == 0)
1111 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1115 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1117 * INSTRUCTION SET REFERENCE, A-M (#253666)
1118 * Page 3-181, Table 3-20
1119 * "The nearest power-of-2 integer that is not smaller
1120 * than EBX[23:16] is the number of unique initial APIC
1121 * IDs reserved for addressing different logical
1122 * processors in a physical package."
1124 for (i = 0; ; ++i) {
1125 if ((1 << i) >= lcpus_max) {
1132 KKASSERT(cpu_count != 0);
1133 if (cpu_count == lcpus_max) {
1134 /* We have nothing to fix */
1136 } else if (cpu_count == 1) {
1137 /* XXX this may be incorrect */
1138 logical_cpus = lcpus_max;
1140 int cur, prev, dist;
1143 * Calculate the distances between two nearest
1144 * APIC IDs. If all such distances are same,
1145 * then it is the number of missing cpus that
1146 * we are going to fill later.
1148 dist = cur = prev = -1;
1149 for (id = 0; id < MAXCPU; ++id) {
1150 if ((id_mask & 1 << id) == 0)
1155 int new_dist = cur - prev;
1161 * Make sure that all distances
1162 * between two nearest APIC IDs
1165 if (dist != new_dist)
1173 /* Must be power of 2 */
1174 if (dist & (dist - 1))
1177 /* Can't exceed CPU package capacity */
1178 if (dist > lcpus_max)
1179 logical_cpus = lcpus_max;
1181 logical_cpus = dist;
1185 * For each APIC ID of a CPU that is set in the mask,
1186 * scan the other candidate APIC ID's for this
1187 * physical processor. If any of those ID's are
1188 * already in the table, then kill the fixup.
1190 for (id = 0; id < MAXCPU; id++) {
1191 if ((id_mask & 1 << id) == 0)
1193 /* First, make sure we are on a logical_cpus boundary. */
1194 if (id % logical_cpus != 0)
1196 for (i = id + 1; i < id + logical_cpus; i++)
1197 if ((id_mask & 1 << i) != 0)
1200 return logical_cpus;
1204 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1208 vm_size_t cth_mapsz = 0;
1210 bzero(mpt, sizeof(*mpt));
1212 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1213 if (fps->pap != 0) {
1215 * Map configuration table header to get
1216 * the base table size
1218 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1219 cth_mapsz = cth->base_table_length;
1220 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1222 if (cth_mapsz < sizeof(*cth)) {
1223 kprintf("invalid base MP table length %d\n",
1225 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1230 * Map the base table
1232 cth = pmap_mapdev(fps->pap, cth_mapsz);
1237 mpt->mp_cth_mapsz = cth_mapsz;
1243 mptable_unmap(struct mptable_pos *mpt)
1245 if (mpt->mp_cth != NULL) {
1246 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1248 mpt->mp_cth_mapsz = 0;
1250 if (mpt->mp_fps != NULL) {
1251 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1259 assign_apic_irq(int apic, int intpin, int irq)
1263 if (int_to_apicintpin[irq].ioapic != -1)
1264 panic("assign_apic_irq: inconsistent table");
1266 int_to_apicintpin[irq].ioapic = apic;
1267 int_to_apicintpin[irq].int_pin = intpin;
1268 int_to_apicintpin[irq].apic_address = ioapic[apic];
1269 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1271 for (x = 0; x < nintrs; x++) {
1272 if ((io_apic_ints[x].int_type == 0 ||
1273 io_apic_ints[x].int_type == 3) &&
1274 io_apic_ints[x].int_vector == 0xff &&
1275 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1276 io_apic_ints[x].dst_apic_int == intpin)
1277 io_apic_ints[x].int_vector = irq;
1282 revoke_apic_irq(int irq)
1288 if (int_to_apicintpin[irq].ioapic == -1)
1289 panic("revoke_apic_irq: inconsistent table");
1291 oldapic = int_to_apicintpin[irq].ioapic;
1292 oldintpin = int_to_apicintpin[irq].int_pin;
1294 int_to_apicintpin[irq].ioapic = -1;
1295 int_to_apicintpin[irq].int_pin = 0;
1296 int_to_apicintpin[irq].apic_address = NULL;
1297 int_to_apicintpin[irq].redirindex = 0;
1299 for (x = 0; x < nintrs; x++) {
1300 if ((io_apic_ints[x].int_type == 0 ||
1301 io_apic_ints[x].int_type == 3) &&
1302 io_apic_ints[x].int_vector != 0xff &&
1303 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1304 io_apic_ints[x].dst_apic_int == oldintpin)
1305 io_apic_ints[x].int_vector = 0xff;
1313 allocate_apic_irq(int intr)
1319 if (io_apic_ints[intr].int_vector != 0xff)
1320 return; /* Interrupt handler already assigned */
1322 if (io_apic_ints[intr].int_type != 0 &&
1323 (io_apic_ints[intr].int_type != 3 ||
1324 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1325 io_apic_ints[intr].dst_apic_int == 0)))
1326 return; /* Not INT or ExtInt on != (0, 0) */
1329 while (irq < APIC_INTMAPSIZE &&
1330 int_to_apicintpin[irq].ioapic != -1)
1333 if (irq >= APIC_INTMAPSIZE)
1334 return; /* No free interrupt handlers */
1336 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1337 intpin = io_apic_ints[intr].dst_apic_int;
1339 assign_apic_irq(apic, intpin, irq);
1344 swap_apic_id(int apic, int oldid, int newid)
1351 return; /* Nothing to do */
1353 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1354 apic, oldid, newid);
1356 /* Swap physical APIC IDs in interrupt entries */
1357 for (x = 0; x < nintrs; x++) {
1358 if (io_apic_ints[x].dst_apic_id == oldid)
1359 io_apic_ints[x].dst_apic_id = newid;
1360 else if (io_apic_ints[x].dst_apic_id == newid)
1361 io_apic_ints[x].dst_apic_id = oldid;
1364 /* Swap physical APIC IDs in IO_TO_ID mappings */
1365 for (oapic = 0; oapic < mp_napics; oapic++)
1366 if (IO_TO_ID(oapic) == newid)
1369 if (oapic < mp_napics) {
1370 kprintf("Changing APIC ID for IO APIC #%d from "
1371 "%d to %d in MP table\n",
1372 oapic, newid, oldid);
1373 IO_TO_ID(oapic) = oldid;
1375 IO_TO_ID(apic) = newid;
1380 fix_id_to_io_mapping(void)
1384 for (x = 0; x < NAPICID; x++)
1387 for (x = 0; x <= mp_naps; x++)
1388 if (CPU_TO_ID(x) < NAPICID)
1389 ID_TO_IO(CPU_TO_ID(x)) = x;
1391 for (x = 0; x < mp_napics; x++)
1392 if (IO_TO_ID(x) < NAPICID)
1393 ID_TO_IO(IO_TO_ID(x)) = x;
1398 first_free_apic_id(void)
1402 for (freeid = 0; freeid < NAPICID; freeid++) {
1403 for (x = 0; x <= mp_naps; x++)
1404 if (CPU_TO_ID(x) == freeid)
1408 for (x = 0; x < mp_napics; x++)
1409 if (IO_TO_ID(x) == freeid)
1420 io_apic_id_acceptable(int apic, int id)
1422 int cpu; /* Logical CPU number */
1423 int oapic; /* Logical IO APIC number for other IO APIC */
1426 return 0; /* Out of range */
1428 for (cpu = 0; cpu <= mp_naps; cpu++)
1429 if (CPU_TO_ID(cpu) == id)
1430 return 0; /* Conflict with CPU */
1432 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1433 if (IO_TO_ID(oapic) == id)
1434 return 0; /* Conflict with other APIC */
1436 return 1; /* ID is acceptable for IO APIC */
1441 io_apic_find_int_entry(int apic, int pin)
1445 /* search each of the possible INTerrupt sources */
1446 for (x = 0; x < nintrs; ++x) {
1447 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1448 (pin == io_apic_ints[x].dst_apic_int))
1449 return (&io_apic_ints[x]);
1457 * parse an Intel MP specification table
1465 int apic; /* IO APIC unit number */
1466 int freeid; /* Free physical APIC ID */
1467 int physid; /* Current physical IO APIC ID */
1469 int bus_0 = 0; /* Stop GCC warning */
1470 int bus_pci = 0; /* Stop GCC warning */
1474 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1475 * did it wrong. The MP spec says that when more than 1 PCI bus
1476 * exists the BIOS must begin with bus entries for the PCI bus and use
1477 * actual PCI bus numbering. This implies that when only 1 PCI bus
1478 * exists the BIOS can choose to ignore this ordering, and indeed many
1479 * MP motherboards do ignore it. This causes a problem when the PCI
1480 * sub-system makes requests of the MP sub-system based on PCI bus
1481 * numbers. So here we look for the situation and renumber the
1482 * busses and associated INTs in an effort to "make it right".
1485 /* find bus 0, PCI bus, count the number of PCI busses */
1486 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1487 if (bus_data[x].bus_id == 0) {
1490 if (bus_data[x].bus_type == PCI) {
1496 * bus_0 == slot of bus with ID of 0
1497 * bus_pci == slot of last PCI bus encountered
1500 /* check the 1 PCI bus case for sanity */
1501 /* if it is number 0 all is well */
1502 if (num_pci_bus == 1 &&
1503 bus_data[bus_pci].bus_id != 0) {
1505 /* mis-numbered, swap with whichever bus uses slot 0 */
1507 /* swap the bus entry types */
1508 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1509 bus_data[bus_0].bus_type = PCI;
1511 /* swap each relavant INTerrupt entry */
1512 id = bus_data[bus_pci].bus_id;
1513 for (x = 0; x < nintrs; ++x) {
1514 if (io_apic_ints[x].src_bus_id == id) {
1515 io_apic_ints[x].src_bus_id = 0;
1517 else if (io_apic_ints[x].src_bus_id == 0) {
1518 io_apic_ints[x].src_bus_id = id;
1523 /* Assign IO APIC IDs.
1525 * First try the existing ID. If a conflict is detected, try
1526 * the ID in the MP table. If a conflict is still detected, find
1529 * We cannot use the ID_TO_IO table before all conflicts has been
1530 * resolved and the table has been corrected.
1532 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1534 /* First try to use the value set by the BIOS */
1535 physid = io_apic_get_id(apic);
1536 if (io_apic_id_acceptable(apic, physid)) {
1537 if (IO_TO_ID(apic) != physid)
1538 swap_apic_id(apic, IO_TO_ID(apic), physid);
1542 /* Then check if the value in the MP table is acceptable */
1543 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1546 /* Last resort, find a free APIC ID and use it */
1547 freeid = first_free_apic_id();
1548 if (freeid >= NAPICID)
1549 panic("No free physical APIC IDs found");
1551 if (io_apic_id_acceptable(apic, freeid)) {
1552 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1555 panic("Free physical APIC ID not usable");
1557 fix_id_to_io_mapping();
1559 /* detect and fix broken Compaq MP table */
1560 if (apic_int_type(0, 0) == -1) {
1561 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1562 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1563 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1564 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1565 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1566 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1568 } else if (apic_int_type(0, 0) == 0) {
1569 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1570 for (x = 0; x < nintrs; ++x)
1571 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1572 (0 == io_apic_ints[x].dst_apic_int)) {
1573 io_apic_ints[x].int_type = 3;
1574 io_apic_ints[x].int_vector = 0xff;
1580 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1581 * controllers universally come in pairs. If IRQ 14 is specified
1582 * as an ISA interrupt, then IRQ 15 had better be too.
1584 * [ Shuttle XPC / AMD Athlon X2 ]
1585 * The MPTable is missing an entry for IRQ 15. Note that the
1586 * ACPI table has an entry for both 14 and 15.
1588 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1589 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1590 io14 = io_apic_find_int_entry(0, 14);
1591 io_apic_ints[nintrs] = *io14;
1592 io_apic_ints[nintrs].src_bus_irq = 15;
1593 io_apic_ints[nintrs].dst_apic_int = 15;
1601 /* Assign low level interrupt handlers */
1603 setup_apic_irq_mapping(void)
1609 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1610 int_to_apicintpin[x].ioapic = -1;
1611 int_to_apicintpin[x].int_pin = 0;
1612 int_to_apicintpin[x].apic_address = NULL;
1613 int_to_apicintpin[x].redirindex = 0;
1616 /* First assign ISA/EISA interrupts */
1617 for (x = 0; x < nintrs; x++) {
1618 int_vector = io_apic_ints[x].src_bus_irq;
1619 if (int_vector < APIC_INTMAPSIZE &&
1620 io_apic_ints[x].int_vector == 0xff &&
1621 int_to_apicintpin[int_vector].ioapic == -1 &&
1622 (apic_int_is_bus_type(x, ISA) ||
1623 apic_int_is_bus_type(x, EISA)) &&
1624 io_apic_ints[x].int_type == 0) {
1625 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1626 io_apic_ints[x].dst_apic_int,
1631 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1632 for (x = 0; x < nintrs; x++) {
1633 if (io_apic_ints[x].dst_apic_int == 0 &&
1634 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1635 io_apic_ints[x].int_vector == 0xff &&
1636 int_to_apicintpin[0].ioapic == -1 &&
1637 io_apic_ints[x].int_type == 3) {
1638 assign_apic_irq(0, 0, 0);
1643 /* Assign PCI interrupts */
1644 for (x = 0; x < nintrs; ++x) {
1645 if (io_apic_ints[x].int_type == 0 &&
1646 io_apic_ints[x].int_vector == 0xff &&
1647 apic_int_is_bus_type(x, PCI))
1648 allocate_apic_irq(x);
1655 mp_set_cpuids(int cpu_id, int apic_id)
1657 CPU_TO_ID(cpu_id) = apic_id;
1658 ID_TO_CPU(apic_id) = cpu_id;
1662 processor_entry(const struct PROCENTRY *entry, int cpu)
1666 /* check for usability */
1667 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1670 /* check for BSP flag */
1671 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1672 mp_set_cpuids(0, entry->apic_id);
1673 return 0; /* its already been counted */
1676 /* add another AP to list, if less than max number of CPUs */
1677 else if (cpu < MAXCPU) {
1678 mp_set_cpuids(cpu, entry->apic_id);
1688 bus_entry(bus_entry_ptr entry, int bus)
1693 /* encode the name into an index */
1694 for (x = 0; x < 6; ++x) {
1695 if ((c = entry->bus_type[x]) == ' ')
1701 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1702 panic("unknown bus type: '%s'", name);
1704 bus_data[bus].bus_id = entry->bus_id;
1705 bus_data[bus].bus_type = x;
1711 io_apic_entry(io_apic_entry_ptr entry, int apic)
1713 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1716 IO_TO_ID(apic) = entry->apic_id;
1717 ID_TO_IO(entry->apic_id) = apic;
1723 lookup_bus_type(char *name)
1727 for (x = 0; x < MAX_BUSTYPE; ++x)
1728 if (strcmp(bus_type_table[x].name, name) == 0)
1729 return bus_type_table[x].type;
1731 return UNKNOWN_BUSTYPE;
1735 int_entry(int_entry_ptr entry, int intr)
1739 io_apic_ints[intr].int_type = entry->int_type;
1740 io_apic_ints[intr].int_flags = entry->int_flags;
1741 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1742 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1743 if (entry->dst_apic_id == 255) {
1744 /* This signal goes to all IO APICS. Select an IO APIC
1745 with sufficient number of interrupt pins */
1746 for (apic = 0; apic < mp_napics; apic++)
1747 if (((io_apic_read(apic, IOAPIC_VER) &
1748 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1749 entry->dst_apic_int)
1751 if (apic < mp_napics)
1752 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1754 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1756 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1757 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1763 apic_int_is_bus_type(int intr, int bus_type)
1767 for (bus = 0; bus < mp_nbusses; ++bus)
1768 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1769 && ((int) bus_data[bus].bus_type == bus_type))
1776 * Given a traditional ISA INT mask, return an APIC mask.
1779 isa_apic_mask(u_int isa_mask)
1784 #if defined(SKIP_IRQ15_REDIRECT)
1785 if (isa_mask == (1 << 15)) {
1786 kprintf("skipping ISA IRQ15 redirect\n");
1789 #endif /* SKIP_IRQ15_REDIRECT */
1791 isa_irq = ffs(isa_mask); /* find its bit position */
1792 if (isa_irq == 0) /* doesn't exist */
1794 --isa_irq; /* make it zero based */
1796 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1800 return (1 << apic_pin); /* convert pin# to a mask */
1804 * Determine which APIC pin an ISA/EISA INT is attached to.
1806 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1807 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1808 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1809 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1811 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1813 isa_apic_irq(int isa_irq)
1817 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1818 if (INTTYPE(intr) == 0) { /* standard INT */
1819 if (SRCBUSIRQ(intr) == isa_irq) {
1820 if (apic_int_is_bus_type(intr, ISA) ||
1821 apic_int_is_bus_type(intr, EISA)) {
1822 if (INTIRQ(intr) == 0xff)
1823 return -1; /* unassigned */
1824 return INTIRQ(intr); /* found */
1829 return -1; /* NOT found */
1834 * Determine which APIC pin a PCI INT is attached to.
1836 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1837 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1838 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1840 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1844 --pciInt; /* zero based */
1846 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1847 if ((INTTYPE(intr) == 0) /* standard INT */
1848 && (SRCBUSID(intr) == pciBus)
1849 && (SRCBUSDEVICE(intr) == pciDevice)
1850 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1851 if (apic_int_is_bus_type(intr, PCI)) {
1852 if (INTIRQ(intr) == 0xff) {
1853 kprintf("IOAPIC: pci_apic_irq() "
1855 return -1; /* unassigned */
1857 return INTIRQ(intr); /* exact match */
1862 return -1; /* NOT found */
1866 next_apic_irq(int irq)
1873 for (intr = 0; intr < nintrs; intr++) {
1874 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1876 bus = SRCBUSID(intr);
1877 bustype = apic_bus_type(bus);
1878 if (bustype != ISA &&
1884 if (intr >= nintrs) {
1887 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1888 if (INTTYPE(ointr) != 0)
1890 if (bus != SRCBUSID(ointr))
1892 if (bustype == PCI) {
1893 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1895 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1898 if (bustype == ISA || bustype == EISA) {
1899 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1902 if (INTPIN(intr) == INTPIN(ointr))
1906 if (ointr >= nintrs) {
1909 return INTIRQ(ointr);
1924 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1927 * Exactly what this means is unclear at this point. It is a solution
1928 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1929 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1930 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1934 undirect_isa_irq(int rirq)
1938 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1939 /** FIXME: tickle the MB redirector chip */
1943 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1950 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1953 undirect_pci_irq(int rirq)
1957 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1959 /** FIXME: tickle the MB redirector chip */
1963 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1973 * given a bus ID, return:
1974 * the bus type if found
1978 apic_bus_type(int id)
1982 for (x = 0; x < mp_nbusses; ++x)
1983 if (bus_data[x].bus_id == id)
1984 return bus_data[x].bus_type;
1990 * given a LOGICAL APIC# and pin#, return:
1991 * the associated src bus ID if found
1995 apic_src_bus_id(int apic, int pin)
1999 /* search each of the possible INTerrupt sources */
2000 for (x = 0; x < nintrs; ++x)
2001 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2002 (pin == io_apic_ints[x].dst_apic_int))
2003 return (io_apic_ints[x].src_bus_id);
2005 return -1; /* NOT found */
2009 * given a LOGICAL APIC# and pin#, return:
2010 * the associated src bus IRQ if found
2014 apic_src_bus_irq(int apic, int pin)
2018 for (x = 0; x < nintrs; x++)
2019 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2020 (pin == io_apic_ints[x].dst_apic_int))
2021 return (io_apic_ints[x].src_bus_irq);
2023 return -1; /* NOT found */
2028 * given a LOGICAL APIC# and pin#, return:
2029 * the associated INTerrupt type if found
2033 apic_int_type(int apic, int pin)
2037 /* search each of the possible INTerrupt sources */
2038 for (x = 0; x < nintrs; ++x) {
2039 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2040 (pin == io_apic_ints[x].dst_apic_int))
2041 return (io_apic_ints[x].int_type);
2043 return -1; /* NOT found */
2047 * Return the IRQ associated with an APIC pin
2050 apic_irq(int apic, int pin)
2055 for (x = 0; x < nintrs; ++x) {
2056 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2057 (pin == io_apic_ints[x].dst_apic_int)) {
2058 res = io_apic_ints[x].int_vector;
2061 if (apic != int_to_apicintpin[res].ioapic)
2062 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
2063 if (pin != int_to_apicintpin[res].int_pin)
2064 panic("apic_irq inconsistent table (2)");
2073 * given a LOGICAL APIC# and pin#, return:
2074 * the associated trigger mode if found
2078 apic_trigger(int apic, int pin)
2082 /* search each of the possible INTerrupt sources */
2083 for (x = 0; x < nintrs; ++x)
2084 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2085 (pin == io_apic_ints[x].dst_apic_int))
2086 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2088 return -1; /* NOT found */
2093 * given a LOGICAL APIC# and pin#, return:
2094 * the associated 'active' level if found
2098 apic_polarity(int apic, int pin)
2102 /* search each of the possible INTerrupt sources */
2103 for (x = 0; x < nintrs; ++x)
2104 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2105 (pin == io_apic_ints[x].dst_apic_int))
2106 return (io_apic_ints[x].int_flags & 0x03);
2108 return -1; /* NOT found */
2114 * set data according to MP defaults
2115 * FIXME: probably not complete yet...
2118 mptable_default(int type)
2120 #if defined(APIC_IO)
2125 kprintf(" MP default config type: %d\n", type);
2128 kprintf(" bus: ISA, APIC: 82489DX\n");
2131 kprintf(" bus: EISA, APIC: 82489DX\n");
2134 kprintf(" bus: EISA, APIC: 82489DX\n");
2137 kprintf(" bus: MCA, APIC: 82489DX\n");
2140 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2143 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2146 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2149 kprintf(" future type\n");
2155 /* one and only IO APIC */
2156 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2159 * sanity check, refer to MP spec section 3.6.6, last paragraph
2160 * necessary as some hardware isn't properly setting up the IO APIC
2162 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2163 if (io_apic_id != 2) {
2165 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2166 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2167 io_apic_set_id(0, 2);
2170 IO_TO_ID(0) = io_apic_id;
2171 ID_TO_IO(io_apic_id) = 0;
2173 /* fill out bus entries */
2182 bus_data[0].bus_id = default_data[type - 1][1];
2183 bus_data[0].bus_type = default_data[type - 1][2];
2184 bus_data[1].bus_id = default_data[type - 1][3];
2185 bus_data[1].bus_type = default_data[type - 1][4];
2188 /* case 4: case 7: MCA NOT supported */
2189 default: /* illegal/reserved */
2190 panic("BAD default MP config: %d", type);
2194 /* general cases from MP v1.4, table 5-2 */
2195 for (pin = 0; pin < 16; ++pin) {
2196 io_apic_ints[pin].int_type = 0;
2197 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2198 io_apic_ints[pin].src_bus_id = 0;
2199 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2200 io_apic_ints[pin].dst_apic_id = io_apic_id;
2201 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2204 /* special cases from MP v1.4, table 5-2 */
2206 io_apic_ints[2].int_type = 0xff; /* N/C */
2207 io_apic_ints[13].int_type = 0xff; /* N/C */
2208 #if !defined(APIC_MIXED_MODE)
2210 panic("sorry, can't support type 2 default yet");
2211 #endif /* APIC_MIXED_MODE */
2214 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2217 io_apic_ints[0].int_type = 0xff; /* N/C */
2219 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2220 #endif /* APIC_IO */
2224 * Map a physical memory address representing I/O into KVA. The I/O
2225 * block is assumed not to cross a page boundary.
2228 permanent_io_mapping(vm_paddr_t pa)
2230 KKASSERT(pa < 0x100000000LL);
2232 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2236 * start each AP in our list
2239 start_all_aps(u_int boot_addr)
2241 vm_offset_t va = boot_address + KERNBASE;
2242 u_int64_t *pt4, *pt3, *pt2;
2248 u_char mpbiosreason;
2249 u_long mpbioswarmvec;
2250 struct mdglobaldata *gd;
2251 struct privatespace *ps;
2253 POSTCODE(START_ALL_APS_POST);
2255 /* Initialize BSP's local APIC */
2256 apic_initialize(TRUE);
2258 /* install the AP 1st level boot code */
2259 pmap_kenter(va, boot_address);
2260 cpu_invlpg((void *)va); /* JG XXX */
2261 bcopy(mptramp_start, (void *)va, bootMP_size);
2263 /* Locate the page tables, they'll be below the trampoline */
2264 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2265 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2266 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2268 /* Create the initial 1GB replicated page tables */
2269 for (i = 0; i < 512; i++) {
2270 /* Each slot of the level 4 pages points to the same level 3 page */
2271 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2272 pt4[i] |= PG_V | PG_RW | PG_U;
2274 /* Each slot of the level 3 pages points to the same level 2 page */
2275 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2276 pt3[i] |= PG_V | PG_RW | PG_U;
2278 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2279 pt2[i] = i * (2 * 1024 * 1024);
2280 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2283 /* save the current value of the warm-start vector */
2284 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2285 outb(CMOS_REG, BIOS_RESET);
2286 mpbiosreason = inb(CMOS_DATA);
2288 /* setup a vector to our boot code */
2289 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2290 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2291 outb(CMOS_REG, BIOS_RESET);
2292 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2295 * If we have a TSC we can figure out the SMI interrupt rate.
2296 * The SMI does not necessarily use a constant rate. Spend
2297 * up to 250ms trying to figure it out.
2300 if (cpu_feature & CPUID_TSC) {
2301 set_apic_timer(275000);
2302 smilast = read_apic_timer();
2303 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2304 smicount = smitest();
2305 if (smibest == 0 || smilast - smicount < smibest)
2306 smibest = smilast - smicount;
2309 if (smibest > 250000)
2312 smibest = smibest * (int64_t)1000000 /
2313 get_apic_timer_frequency();
2317 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2318 1000000 / smibest, smibest);
2321 for (x = 1; x <= mp_naps; ++x) {
2323 /* This is a bit verbose, it will go away soon. */
2325 /* first page of AP's private space */
2326 pg = x * x86_64_btop(sizeof(struct privatespace));
2328 /* allocate new private data page(s) */
2329 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2330 MDGLOBALDATA_BASEALLOC_SIZE);
2332 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2333 bzero(gd, sizeof(*gd));
2334 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2336 /* prime data page for it to use */
2337 mi_gdinit(&gd->mi, x);
2339 gd->gd_CMAP1 = &SMPpt[pg + 0];
2340 gd->gd_CMAP2 = &SMPpt[pg + 1];
2341 gd->gd_CMAP3 = &SMPpt[pg + 2];
2342 gd->gd_PMAP1 = &SMPpt[pg + 3];
2343 gd->gd_CADDR1 = ps->CPAGE1;
2344 gd->gd_CADDR2 = ps->CPAGE2;
2345 gd->gd_CADDR3 = ps->CPAGE3;
2346 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2347 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2348 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2350 /* setup a vector to our boot code */
2351 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2352 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2353 outb(CMOS_REG, BIOS_RESET);
2354 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2357 * Setup the AP boot stack
2359 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2362 /* attempt to start the Application Processor */
2363 CHECK_INIT(99); /* setup checkpoints */
2364 if (!start_ap(gd, boot_addr, smibest)) {
2365 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2366 CHECK_PRINT("trace"); /* show checkpoints */
2367 /* better panic as the AP may be running loose */
2368 kprintf("panic y/n? [y] ");
2369 if (cngetc() != 'n')
2372 CHECK_PRINT("trace"); /* show checkpoints */
2374 /* record its version info */
2375 cpu_apic_versions[x] = cpu_apic_versions[0];
2378 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2381 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2382 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2385 ncpus2_shift = shift;
2386 ncpus2 = 1 << shift;
2387 ncpus2_mask = ncpus2 - 1;
2389 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2390 if ((1 << shift) < ncpus)
2392 ncpus_fit = 1 << shift;
2393 ncpus_fit_mask = ncpus_fit - 1;
2395 /* build our map of 'other' CPUs */
2396 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2397 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2398 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2400 /* fill in our (BSP) APIC version */
2401 cpu_apic_versions[0] = lapic->version;
2403 /* restore the warmstart vector */
2404 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2405 outb(CMOS_REG, BIOS_RESET);
2406 outb(CMOS_DATA, mpbiosreason);
2409 * NOTE! The idlestack for the BSP was setup by locore. Finish
2410 * up, clean out the P==V mapping we did earlier.
2414 /* number of APs actually started */
2420 * load the 1st level AP boot code into base memory.
2423 /* targets for relocation */
2424 extern void bigJump(void);
2425 extern void bootCodeSeg(void);
2426 extern void bootDataSeg(void);
2427 extern void MPentry(void);
2428 extern u_int MP_GDT;
2429 extern u_int mp_gdtbase;
2434 install_ap_tramp(u_int boot_addr)
2437 int size = *(int *) ((u_long) & bootMP_size);
2438 u_char *src = (u_char *) ((u_long) bootMP);
2439 u_char *dst = (u_char *) boot_addr + KERNBASE;
2440 u_int boot_base = (u_int) bootMP;
2445 POSTCODE(INSTALL_AP_TRAMP_POST);
2447 for (x = 0; x < size; ++x)
2451 * modify addresses in code we just moved to basemem. unfortunately we
2452 * need fairly detailed info about mpboot.s for this to work. changes
2453 * to mpboot.s might require changes here.
2456 /* boot code is located in KERNEL space */
2457 dst = (u_char *) boot_addr + KERNBASE;
2459 /* modify the lgdt arg */
2460 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2461 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2463 /* modify the ljmp target for MPentry() */
2464 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2465 *dst32 = ((u_int) MPentry - KERNBASE);
2467 /* modify the target for boot code segment */
2468 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2469 dst8 = (u_int8_t *) (dst16 + 1);
2470 *dst16 = (u_int) boot_addr & 0xffff;
2471 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2473 /* modify the target for boot data segment */
2474 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2475 dst8 = (u_int8_t *) (dst16 + 1);
2476 *dst16 = (u_int) boot_addr & 0xffff;
2477 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2483 * This function starts the AP (application processor) identified
2484 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2485 * to accomplish this. This is necessary because of the nuances
2486 * of the different hardware we might encounter. It ain't pretty,
2487 * but it seems to work.
2489 * NOTE: eventually an AP gets to ap_init(), which is called just
2490 * before the AP goes into the LWKT scheduler's idle loop.
2493 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2497 u_long icr_lo, icr_hi;
2499 POSTCODE(START_AP_POST);
2501 /* get the PHYSICAL APIC ID# */
2502 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2504 /* calculate the vector */
2505 vector = (boot_addr >> 12) & 0xff;
2507 /* We don't want anything interfering */
2510 /* Make sure the target cpu sees everything */
2514 * Try to detect when a SMI has occurred, wait up to 200ms.
2516 * If a SMI occurs during an AP reset but before we issue
2517 * the STARTUP command, the AP may brick. To work around
2518 * this problem we hold off doing the AP startup until
2519 * after we have detected the SMI. Hopefully another SMI
2520 * will not occur before we finish the AP startup.
2522 * Retries don't seem to help. SMIs have a window of opportunity
2523 * and if USB->legacy keyboard emulation is enabled in the BIOS
2524 * the interrupt rate can be quite high.
2526 * NOTE: Don't worry about the L1 cache load, it might bloat
2527 * ldelta a little but ndelta will be so huge when the SMI
2528 * occurs the detection logic will still work fine.
2531 set_apic_timer(200000);
2536 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2537 * and running the target CPU. OR this INIT IPI might be latched (P5
2538 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2541 * see apic/apicreg.h for icr bit definitions.
2543 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2547 * Setup the address for the target AP. We can setup
2548 * icr_hi once and then just trigger operations with
2551 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2552 icr_hi |= (physical_cpu << 24);
2553 icr_lo = lapic->icr_lo & 0xfff00000;
2554 lapic->icr_hi = icr_hi;
2557 * Do an INIT IPI: assert RESET
2559 * Use edge triggered mode to assert INIT
2561 lapic->icr_lo = icr_lo | 0x00004500;
2562 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2566 * The spec calls for a 10ms delay but we may have to use a
2567 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2568 * interrupt. We have other loops here too and dividing by 2
2569 * doesn't seem to be enough even after subtracting 350us,
2570 * so we divide by 4.
2572 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2573 * interrupt was detected we use the full 10ms.
2577 else if (smibest < 150 * 4 + 350)
2579 else if ((smibest - 350) / 4 < 10000)
2580 u_sleep((smibest - 350) / 4);
2585 * Do an INIT IPI: deassert RESET
2587 * Use level triggered mode to deassert. It is unclear
2588 * why we need to do this.
2590 lapic->icr_lo = icr_lo | 0x00008500;
2591 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2593 u_sleep(150); /* wait 150us */
2596 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2597 * latched, (P5 bug) this 1st STARTUP would then terminate
2598 * immediately, and the previously started INIT IPI would continue. OR
2599 * the previous INIT IPI has already run. and this STARTUP IPI will
2600 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2603 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2604 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2606 u_sleep(200); /* wait ~200uS */
2609 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2610 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2611 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2612 * recognized after hardware RESET or INIT IPI.
2614 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2615 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2618 /* Resume normal operation */
2621 /* wait for it to start, see ap_init() */
2622 set_apic_timer(5000000);/* == 5 seconds */
2623 while (read_apic_timer()) {
2624 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2625 return 1; /* return SUCCESS */
2628 return 0; /* return FAILURE */
2643 while (read_apic_timer()) {
2645 for (count = 0; count < 100; ++count)
2646 ntsc = rdtsc(); /* force loop to occur */
2648 ndelta = ntsc - ltsc;
2649 if (ldelta > ndelta)
2651 if (ndelta > ldelta * 2)
2654 ldelta = ntsc - ltsc;
2657 return(read_apic_timer());
2661 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2663 * If for some reason we were unable to start all cpus we cannot safely
2664 * use broadcast IPIs.
2670 if (smp_startup_mask == smp_active_mask) {
2671 all_but_self_ipi(XINVLTLB_OFFSET);
2673 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2674 APIC_DELMODE_FIXED);
2680 * When called the executing CPU will send an IPI to all other CPUs
2681 * requesting that they halt execution.
2683 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2685 * - Signals all CPUs in map to stop.
2686 * - Waits for each to stop.
2693 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2694 * from executing at same time.
2697 stop_cpus(u_int map)
2699 map &= smp_active_mask;
2701 /* send the Xcpustop IPI to all CPUs in map */
2702 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2704 while ((stopped_cpus & map) != map)
2712 * Called by a CPU to restart stopped CPUs.
2714 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2716 * - Signals all CPUs in map to restart.
2717 * - Waits for each to restart.
2725 restart_cpus(u_int map)
2727 /* signal other cpus to restart */
2728 started_cpus = map & smp_active_mask;
2730 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2737 * This is called once the mpboot code has gotten us properly relocated
2738 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2739 * and when it returns the scheduler will call the real cpu_idle() main
2740 * loop for the idlethread. Interrupts are disabled on entry and should
2741 * remain disabled at return.
2749 * Adjust smp_startup_mask to signal the BSP that we have started
2750 * up successfully. Note that we do not yet hold the BGL. The BSP
2751 * is waiting for our signal.
2753 * We can't set our bit in smp_active_mask yet because we are holding
2754 * interrupts physically disabled and remote cpus could deadlock
2755 * trying to send us an IPI.
2757 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2761 * Interlock for finalization. Wait until mp_finish is non-zero,
2762 * then get the MP lock.
2764 * Note: We are in a critical section.
2766 * Note: We have to synchronize td_mpcount to our desired MP state
2767 * before calling cpu_try_mplock().
2769 * Note: we are the idle thread, we can only spin.
2771 * Note: The load fence is memory volatile and prevents the compiler
2772 * from improperly caching mp_finish, and the cpu from improperly
2775 while (mp_finish == 0)
2777 ++curthread->td_mpcount;
2778 while (cpu_try_mplock() == 0)
2781 if (cpu_feature & CPUID_TSC) {
2783 * The BSP is constantly updating tsc0_offset, figure out the
2784 * relative difference to synchronize ktrdump.
2786 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2789 /* BSP may have changed PTD while we're waiting for the lock */
2792 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2796 /* Build our map of 'other' CPUs. */
2797 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2799 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2801 /* A quick check from sanity claus */
2802 apic_id = (apic_id_to_logical[(lapic->id & 0x0f000000) >> 24]);
2803 if (mycpu->gd_cpuid != apic_id) {
2804 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2805 kprintf("SMP: apic_id = %d\n", apic_id);
2807 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2809 panic("cpuid mismatch! boom!!");
2812 /* Initialize AP's local APIC for irq's */
2813 apic_initialize(FALSE);
2815 /* Set memory range attributes for this CPU to match the BSP */
2816 mem_range_AP_init();
2819 * Once we go active we must process any IPIQ messages that may
2820 * have been queued, because no actual IPI will occur until we
2821 * set our bit in the smp_active_mask. If we don't the IPI
2822 * message interlock could be left set which would also prevent
2825 * The idle loop doesn't expect the BGL to be held and while
2826 * lwkt_switch() normally cleans things up this is a special case
2827 * because we returning almost directly into the idle loop.
2829 * The idle thread is never placed on the runq, make sure
2830 * nothing we've done put it there.
2832 KKASSERT(curthread->td_mpcount == 1);
2833 smp_active_mask |= 1 << mycpu->gd_cpuid;
2836 * Enable interrupts here. idle_restore will also do it, but
2837 * doing it here lets us clean up any strays that got posted to
2838 * the CPU during the AP boot while we are still in a critical
2841 __asm __volatile("sti; pause; pause"::);
2842 mdcpu->gd_fpending = 0;
2844 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2845 lwkt_process_ipiq();
2848 * Releasing the mp lock lets the BSP finish up the SMP init
2851 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2855 * Get SMP fully working before we start initializing devices.
2863 kprintf("Finish MP startup\n");
2864 if (cpu_feature & CPUID_TSC)
2865 tsc0_offset = rdtsc();
2868 while (smp_active_mask != smp_startup_mask) {
2870 if (cpu_feature & CPUID_TSC)
2871 tsc0_offset = rdtsc();
2873 while (try_mplock() == 0)
2876 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2879 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2882 cpu_send_ipiq(int dcpu)
2884 if ((1 << dcpu) & smp_active_mask)
2885 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2888 #if 0 /* single_apic_ipi_passive() not working yet */
2890 * Returns 0 on failure, 1 on success
2893 cpu_send_ipiq_passive(int dcpu)
2896 if ((1 << dcpu) & smp_active_mask) {
2897 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2898 APIC_DELMODE_FIXED);
2904 struct mptable_lapic_cbarg1 {
2907 u_int ht_apicid_mask;
2911 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2913 const struct PROCENTRY *ent;
2914 struct mptable_lapic_cbarg1 *arg = xarg;
2920 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2924 if (ent->apic_id < 32) {
2925 arg->ht_apicid_mask |= 1 << ent->apic_id;
2926 } else if (arg->ht_fixup) {
2927 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2933 struct mptable_lapic_cbarg2 {
2940 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2942 const struct PROCENTRY *ent;
2943 struct mptable_lapic_cbarg2 *arg = xarg;
2949 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2950 KKASSERT(!arg->found_bsp);
2954 if (processor_entry(ent, arg->cpu))
2957 if (arg->logical_cpus) {
2958 struct PROCENTRY proc;
2962 * Create fake mptable processor entries
2963 * and feed them to processor_entry() to
2964 * enumerate the logical CPUs.
2966 bzero(&proc, sizeof(proc));
2968 proc.cpu_flags = PROCENTRY_FLAG_EN;
2969 proc.apic_id = ent->apic_id;
2971 for (i = 1; i < arg->logical_cpus; i++) {
2973 processor_entry(&proc, arg->cpu);
2981 mptable_lapic_default(void)
2983 int ap_apicid, bsp_apicid;
2985 mp_naps = 1; /* exclude BSP */
2987 /* Map local apic before the id field is accessed */
2988 lapic_init(DEFAULT_APIC_BASE);
2990 bsp_apicid = APIC_ID(lapic->id);
2991 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2994 mp_set_cpuids(0, bsp_apicid);
2995 /* one and only AP */
2996 mp_set_cpuids(1, ap_apicid);
3001 * cpu_apic_address (common to all CPUs)
3003 * ID_TO_CPU(N), APIC ID to logical CPU table
3004 * CPU_TO_ID(N), logical CPU to APIC ID table
3007 mptable_lapic_enumerate(struct mptable_pos *mpt)
3009 struct mptable_lapic_cbarg1 arg1;
3010 struct mptable_lapic_cbarg2 arg2;
3012 int error, logical_cpus = 0;
3013 vm_offset_t lapic_addr;
3015 KKASSERT(mpt->mp_fps != NULL);
3018 * Check for use of 'default' configuration
3020 if (mpt->mp_fps->mpfb1 != 0) {
3021 mptable_lapic_default();
3026 KKASSERT(cth != NULL);
3028 /* Save local apic address */
3029 lapic_addr = (vm_offset_t)cth->apic_address;
3030 KKASSERT(lapic_addr != 0);
3033 * Find out how many CPUs do we have
3035 bzero(&arg1, sizeof(arg1));
3036 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3038 error = mptable_iterate_entries(cth,
3039 mptable_lapic_pass1_callback, &arg1);
3041 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3042 KKASSERT(arg1.cpu_count != 0);
3044 /* See if we need to fixup HT logical CPUs. */
3045 if (arg1.ht_fixup) {
3046 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3048 if (logical_cpus != 0)
3049 arg1.cpu_count *= logical_cpus;
3051 mp_naps = arg1.cpu_count;
3053 /* Qualify the numbers again, after possible HT fixup */
3054 if (mp_naps > MAXCPU) {
3055 kprintf("Warning: only using %d of %d available CPUs!\n",
3060 --mp_naps; /* subtract the BSP */
3063 * Link logical CPU id to local apic id
3065 bzero(&arg2, sizeof(arg2));
3067 arg2.logical_cpus = logical_cpus;
3069 error = mptable_iterate_entries(cth,
3070 mptable_lapic_pass2_callback, &arg2);
3072 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3073 KKASSERT(arg2.found_bsp);
3075 /* Map local apic */
3076 lapic_init(lapic_addr);
3080 lapic_init(vm_offset_t lapic_addr)
3083 * lapic not mapped yet (pmap_init is called too late)
3085 lapic = pmap_mapdev_uncacheable(lapic_addr, sizeof(struct LAPIC));
3088 /* Local apic is mapped on last page */
3089 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
3090 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
3093 /* Just for printing */
3094 cpu_apic_address = lapic_addr;