2 * Copyright (c) 2003,2004,2008 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * pmap invalidation support code. Certain hardware requirements must
37 * be dealt with when manipulating page table entries and page directory
38 * entries within a pmap. In particular, we cannot safely manipulate
39 * page tables which are in active use by another cpu (even if it is
40 * running in userland) for two reasons: First, TLB writebacks will
41 * race against our own modifications and tests. Second, even if we
42 * were to use bus-locked instruction we can still screw up the
43 * target cpu's instruction pipeline due to Intel cpu errata.
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/vmmeter.h>
51 #include <sys/thread2.h>
55 #include <vm/vm_object.h>
57 #include <machine/cputypes.h>
58 #include <machine/md_var.h>
59 #include <machine/specialreg.h>
60 #include <machine/smp.h>
61 #include <machine/globaldata.h>
62 #include <machine/pmap.h>
63 #include <machine/pmap_inval.h>
68 _cpu_invltlb(void *dummy)
74 _cpu_invl1pg(void *data)
82 * Initialize for add or flush
85 pmap_inval_init(pmap_inval_info_t info)
91 * Add a (pmap, va) pair to the invalidation list and protect access
95 pmap_inval_add(pmap_inval_info_t info, pmap_t pmap, vm_offset_t va)
98 if ((info->pir_flags & PIRF_CPUSYNC) == 0) {
99 info->pir_flags |= PIRF_CPUSYNC;
100 info->pir_cpusync.cs_run_func = NULL;
101 info->pir_cpusync.cs_fin1_func = NULL;
102 info->pir_cpusync.cs_fin2_func = NULL;
103 lwkt_cpusync_start(pmap->pm_active, &info->pir_cpusync);
104 } else if (pmap->pm_active & ~info->pir_cpusync.cs_mask) {
105 lwkt_cpusync_add(pmap->pm_active, &info->pir_cpusync);
108 if (pmap->pm_active == 0)
111 if ((info->pir_flags & (PIRF_INVLTLB|PIRF_INVL1PG)) == 0) {
112 if (va == (vm_offset_t)-1) {
113 info->pir_flags |= PIRF_INVLTLB;
115 info->pir_cpusync.cs_fin2_func = _cpu_invltlb;
118 info->pir_flags |= PIRF_INVL1PG;
119 info->pir_cpusync.cs_data = (void *)va;
121 info->pir_cpusync.cs_fin2_func = _cpu_invl1pg;
125 info->pir_flags |= PIRF_INVLTLB;
127 info->pir_cpusync.cs_fin2_func = _cpu_invltlb;
133 * Synchronize changes with target cpus.
136 pmap_inval_flush(pmap_inval_info_t info)
139 if (info->pir_flags & PIRF_CPUSYNC)
140 lwkt_cpusync_finish(&info->pir_cpusync);
142 if (info->pir_flags & PIRF_INVLTLB)
144 else if (info->pir_flags & PIRF_INVL1PG)
145 cpu_invlpg(info->pir_cpusync.cs_data);