2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_ring.c 254885 2013-08-25 19:37:15Z dumbbell $
32 #include <uapi_drm/radeon_drm.h>
33 #include "radeon_reg.h"
40 * IBs (Indirect Buffers) and areas of GPU accessible memory where
41 * commands are stored. You can put a pointer to the IB in the
42 * command ring and the hw will fetch the commands from the IB
43 * and execute them. Generally userspace acceleration drivers
44 * produce command buffers which are send to the kernel and
45 * put in IBs for execution by the requested ring.
47 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
48 #endif /* DUMBBELL_WIP */
51 * radeon_ib_get - request an IB (Indirect Buffer)
53 * @rdev: radeon_device pointer
54 * @ring: ring index the IB is associated with
55 * @ib: IB object returned
56 * @size: requested IB size
58 * Request an IB (all asics). IBs are allocated using the
60 * Returns 0 on success, error on failure.
62 int radeon_ib_get(struct radeon_device *rdev, int ring,
63 struct radeon_ib *ib, struct radeon_vm *vm,
68 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
70 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
74 r = radeon_semaphore_create(rdev, &ib->semaphore);
81 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
84 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
85 * space and soffset is the offset inside the pool bo
87 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
89 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
91 ib->is_const_ib = false;
92 for (i = 0; i < RADEON_NUM_RINGS; ++i)
93 ib->sync_to[i] = NULL;
99 * radeon_ib_free - free an IB (Indirect Buffer)
101 * @rdev: radeon_device pointer
102 * @ib: IB object to free
104 * Free an IB (all asics).
106 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
108 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
109 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
110 radeon_fence_unref(&ib->fence);
114 * radeon_ib_sync_to - sync to fence before executing the IB
116 * @ib: IB object to add fence to
117 * @fence: fence to sync to
119 * Sync to the fence before executing the IB
121 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
123 struct radeon_fence *other;
128 other = ib->sync_to[fence->ring];
129 ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
133 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
135 * @rdev: radeon_device pointer
136 * @ib: IB object to schedule
137 * @const_ib: Const IB to schedule (SI only)
139 * Schedule an IB on the associated ring (all asics).
140 * Returns 0 on success, error on failure.
142 * On SI, there are two parallel engines fed from the primary ring,
143 * the CE (Constant Engine) and the DE (Drawing Engine). Since
144 * resource descriptors have moved to memory, the CE allows you to
145 * prime the caches while the DE is updating register state so that
146 * the resource descriptors will be already in cache when the draw is
147 * processed. To accomplish this, the userspace driver submits two
148 * IBs, one for the CE and one for the DE. If there is a CE IB (called
149 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
150 * to SI there was just a DE IB.
152 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
153 struct radeon_ib *const_ib)
155 struct radeon_ring *ring = &rdev->ring[ib->ring];
156 bool need_sync = false;
159 if (!ib->length_dw || !ring->ready) {
160 /* TODO: Nothings in the ib we should report. */
161 dev_err(rdev->dev, "couldn't schedule ib\n");
165 /* 64 dwords should be enough for fence too */
166 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
168 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
171 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
172 struct radeon_fence *fence = ib->sync_to[i];
173 if (radeon_fence_need_sync(fence, ib->ring)) {
175 radeon_semaphore_sync_rings(rdev, ib->semaphore,
176 fence->ring, ib->ring);
177 radeon_fence_note_sync(fence, ib->ring);
180 /* immediately free semaphore when we don't need to sync */
182 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
184 /* if we can't remember our last VM flush then flush now! */
185 if (ib->vm && !ib->vm->last_flush) {
186 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
189 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
190 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
192 radeon_ring_ib_execute(rdev, ib->ring, ib);
193 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
195 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
196 radeon_ring_unlock_undo(rdev, ring);
200 const_ib->fence = radeon_fence_ref(ib->fence);
202 /* we just flushed the VM, remember that */
203 if (ib->vm && !ib->vm->last_flush) {
204 ib->vm->last_flush = radeon_fence_ref(ib->fence);
206 radeon_ring_unlock_commit(rdev, ring);
211 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
213 * @rdev: radeon_device pointer
215 * Initialize the suballocator to manage a pool of memory
216 * for use as IBs (all asics).
217 * Returns 0 on success, error on failure.
219 int radeon_ib_pool_init(struct radeon_device *rdev)
223 if (rdev->ib_pool_ready) {
226 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
227 RADEON_IB_POOL_SIZE*64*1024,
228 RADEON_GEM_DOMAIN_GTT);
233 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
238 rdev->ib_pool_ready = true;
240 if (radeon_debugfs_sa_init(rdev)) {
241 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
243 #endif /* DUMBBELL_WIP */
248 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
250 * @rdev: radeon_device pointer
252 * Tear down the suballocator managing the pool of memory
253 * for use as IBs (all asics).
255 void radeon_ib_pool_fini(struct radeon_device *rdev)
257 if (rdev->ib_pool_ready) {
258 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
259 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
260 rdev->ib_pool_ready = false;
265 * radeon_ib_ring_tests - test IBs on the rings
267 * @rdev: radeon_device pointer
269 * Test an IB (Indirect Buffer) on each ring.
270 * If the test fails, disable the ring.
271 * Returns 0 on success, error if the primary GFX ring
274 int radeon_ib_ring_tests(struct radeon_device *rdev)
279 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
280 struct radeon_ring *ring = &rdev->ring[i];
285 r = radeon_ib_test(rdev, i, ring);
289 if (i == RADEON_RING_TYPE_GFX_INDEX) {
290 /* oh, oh, that's really bad */
291 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
292 rdev->accel_working = false;
296 /* still not good, but we can live with it */
297 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
307 * Most engines on the GPU are fed via ring buffers. Ring
308 * buffers are areas of GPU accessible memory that the host
309 * writes commands into and the GPU reads commands out of.
310 * There is a rptr (read pointer) that determines where the
311 * GPU is currently reading, and a wptr (write pointer)
312 * which determines where the host has written. When the
313 * pointers are equal, the ring is idle. When the host
314 * writes commands to the ring buffer, it increments the
315 * wptr. The GPU then starts fetching commands and executes
316 * them until the pointers are equal again.
318 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
319 #endif /* DUMBBELL_WIP */
321 #if defined(DRM_DEBUG_CODE) && DRM_DEBUG_CODE != 0
323 * radeon_ring_write - write a value to the ring
325 * @ring: radeon_ring structure holding ring information
326 * @v: dword (dw) value to write
328 * Write a value to the requested ring buffer (all asics).
330 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
333 if (ring->count_dw <= 0) {
334 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
337 ring->ring[ring->wptr++] = v;
338 ring->wptr &= ring->ptr_mask;
340 ring->ring_free_dw--;
345 * radeon_ring_supports_scratch_reg - check if the ring supports
346 * writing to scratch registers
348 * @rdev: radeon_device pointer
349 * @ring: radeon_ring structure holding ring information
351 * Check if a specific ring supports writing to scratch registers (all asics).
352 * Returns true if the ring supports writing to scratch regs, false if not.
354 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
355 struct radeon_ring *ring)
358 case RADEON_RING_TYPE_GFX_INDEX:
359 case CAYMAN_RING_TYPE_CP1_INDEX:
360 case CAYMAN_RING_TYPE_CP2_INDEX:
368 * radeon_ring_free_size - update the free size
370 * @rdev: radeon_device pointer
371 * @ring: radeon_ring structure holding ring information
373 * Update the free dw slots in the ring buffer (all asics).
375 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
379 if (rdev->wb.enabled)
380 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
382 rptr = RREG32(ring->rptr_reg);
383 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
384 /* This works because ring_size is a power of 2 */
385 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
386 ring->ring_free_dw -= ring->wptr;
387 ring->ring_free_dw &= ring->ptr_mask;
388 if (!ring->ring_free_dw) {
389 ring->ring_free_dw = ring->ring_size / 4;
394 * radeon_ring_alloc - allocate space on the ring buffer
396 * @rdev: radeon_device pointer
397 * @ring: radeon_ring structure holding ring information
398 * @ndw: number of dwords to allocate in the ring buffer
400 * Allocate @ndw dwords in the ring buffer (all asics).
401 * Returns 0 on success, error on failure.
403 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
407 /* make sure we aren't trying to allocate more space than there is on the ring */
408 if (ndw > (ring->ring_size / 4))
410 /* Align requested size with padding so unlock_commit can
412 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
413 while (ndw > (ring->ring_free_dw - 1)) {
414 radeon_ring_free_size(rdev, ring);
415 if (ndw < ring->ring_free_dw) {
418 r = radeon_fence_wait_next_locked(rdev, ring->idx);
422 ring->count_dw = ndw;
423 ring->wptr_old = ring->wptr;
428 * radeon_ring_lock - lock the ring and allocate space on it
430 * @rdev: radeon_device pointer
431 * @ring: radeon_ring structure holding ring information
432 * @ndw: number of dwords to allocate in the ring buffer
434 * Lock the ring and allocate @ndw dwords in the ring buffer
436 * Returns 0 on success, error on failure.
438 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
442 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
443 r = radeon_ring_alloc(rdev, ring, ndw);
445 lockmgr(&rdev->ring_lock, LK_RELEASE);
452 * radeon_ring_commit - tell the GPU to execute the new
453 * commands on the ring buffer
455 * @rdev: radeon_device pointer
456 * @ring: radeon_ring structure holding ring information
458 * Update the wptr (write pointer) to tell the GPU to
459 * execute new commands on the ring buffer (all asics).
461 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
463 /* We pad to match fetch size */
464 while (ring->wptr & ring->align_mask) {
465 radeon_ring_write(ring, ring->nop);
468 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
469 (void)RREG32(ring->wptr_reg);
473 * radeon_ring_unlock_commit - tell the GPU to execute the new
474 * commands on the ring buffer and unlock it
476 * @rdev: radeon_device pointer
477 * @ring: radeon_ring structure holding ring information
479 * Call radeon_ring_commit() then unlock the ring (all asics).
481 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
483 radeon_ring_commit(rdev, ring);
484 lockmgr(&rdev->ring_lock, LK_RELEASE);
488 * radeon_ring_undo - reset the wptr
490 * @ring: radeon_ring structure holding ring information
492 * Reset the driver's copy of the wptr (all asics).
494 void radeon_ring_undo(struct radeon_ring *ring)
496 ring->wptr = ring->wptr_old;
500 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
502 * @ring: radeon_ring structure holding ring information
504 * Call radeon_ring_undo() then unlock the ring (all asics).
506 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
508 radeon_ring_undo(ring);
509 lockmgr(&rdev->ring_lock, LK_RELEASE);
513 * radeon_ring_force_activity - add some nop packets to the ring
515 * @rdev: radeon_device pointer
516 * @ring: radeon_ring structure holding ring information
518 * Add some nop packets to the ring to force activity (all asics).
519 * Used for lockup detection to see if the rptr is advancing.
521 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
525 radeon_ring_free_size(rdev, ring);
526 if (ring->rptr == ring->wptr) {
527 r = radeon_ring_alloc(rdev, ring, 1);
529 radeon_ring_write(ring, ring->nop);
530 radeon_ring_commit(rdev, ring);
536 * radeon_ring_lockup_update - update lockup variables
538 * @ring: radeon_ring structure holding ring information
540 * Update the last rptr value and timestamp (all asics).
542 void radeon_ring_lockup_update(struct radeon_ring *ring)
544 ring->last_rptr = ring->rptr;
545 ring->last_activity = jiffies;
549 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
550 * @rdev: radeon device structure
551 * @ring: radeon_ring structure holding ring information
553 * We don't need to initialize the lockup tracking information as we will either
554 * have CP rptr to a different value of jiffies wrap around which will force
555 * initialization of the lockup tracking informations.
557 * A possible false positivie is if we get call after while and last_cp_rptr ==
558 * the current CP rptr, even if it's unlikely it might happen. To avoid this
559 * if the elapsed time since last call is bigger than 2 second than we return
560 * false and update the tracking information. Due to this the caller must call
561 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
562 * the fencing code should be cautious about that.
564 * Caller should write to the ring to force CP to do something so we don't get
565 * false positive when CP is just gived nothing to do.
568 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
570 unsigned long cjiffies, elapsed;
574 if (!time_after(cjiffies, ring->last_activity)) {
575 /* likely a wrap around */
576 radeon_ring_lockup_update(ring);
579 rptr = RREG32(ring->rptr_reg);
580 ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
581 if (ring->rptr != ring->last_rptr) {
582 /* CP is still working no lockup */
583 radeon_ring_lockup_update(ring);
586 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
587 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
588 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
591 /* give a chance to the GPU ... */
596 * radeon_ring_backup - Back up the content of a ring
598 * @rdev: radeon_device pointer
599 * @ring: the ring we want to back up
601 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
603 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
606 unsigned size, ptr, i;
608 /* just in case lock the ring */
609 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
612 if (ring->ring_obj == NULL) {
613 lockmgr(&rdev->ring_lock, LK_RELEASE);
617 /* it doesn't make sense to save anything if all fences are signaled */
618 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
619 lockmgr(&rdev->ring_lock, LK_RELEASE);
623 /* calculate the number of dw on the ring */
624 if (ring->rptr_save_reg)
625 ptr = RREG32(ring->rptr_save_reg);
626 else if (rdev->wb.enabled)
627 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
629 /* no way to read back the next rptr */
630 lockmgr(&rdev->ring_lock, LK_RELEASE);
634 size = ring->wptr + (ring->ring_size / 4);
636 size &= ring->ptr_mask;
638 lockmgr(&rdev->ring_lock, LK_RELEASE);
642 /* and then save the content of the ring */
643 *data = kmalloc(size * sizeof(uint32_t), M_DRM, M_WAITOK);
645 lockmgr(&rdev->ring_lock, LK_RELEASE);
648 for (i = 0; i < size; ++i) {
649 (*data)[i] = ring->ring[ptr++];
650 ptr &= ring->ptr_mask;
653 lockmgr(&rdev->ring_lock, LK_RELEASE);
658 * radeon_ring_restore - append saved commands to the ring again
660 * @rdev: radeon_device pointer
661 * @ring: ring to append commands to
662 * @size: number of dwords we want to write
663 * @data: saved commands
665 * Allocates space on the ring and restore the previously saved commands.
667 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
668 unsigned size, uint32_t *data)
675 /* restore the saved ring content */
676 r = radeon_ring_lock(rdev, ring, size);
680 for (i = 0; i < size; ++i) {
681 radeon_ring_write(ring, data[i]);
684 radeon_ring_unlock_commit(rdev, ring);
685 drm_free(data, M_DRM);
690 * radeon_ring_init - init driver ring struct.
692 * @rdev: radeon_device pointer
693 * @ring: radeon_ring structure holding ring information
694 * @ring_size: size of the ring
695 * @rptr_offs: offset of the rptr writeback location in the WB buffer
696 * @rptr_reg: MMIO offset of the rptr register
697 * @wptr_reg: MMIO offset of the wptr register
698 * @ptr_reg_shift: bit offset of the rptr/wptr values
699 * @ptr_reg_mask: bit mask of the rptr/wptr values
700 * @nop: nop packet for this ring
702 * Initialize the driver information for the selected ring (all asics).
703 * Returns 0 on success, error on failure.
705 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
706 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
707 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
712 ring->ring_size = ring_size;
713 ring->rptr_offs = rptr_offs;
714 ring->rptr_reg = rptr_reg;
715 ring->wptr_reg = wptr_reg;
716 ring->ptr_reg_shift = ptr_reg_shift;
717 ring->ptr_reg_mask = ptr_reg_mask;
719 /* Allocate ring buffer */
720 if (ring->ring_obj == NULL) {
721 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
722 RADEON_GEM_DOMAIN_GTT,
723 NULL, &ring->ring_obj);
725 dev_err(rdev->dev, "(%d) ring create failed\n", r);
728 r = radeon_bo_reserve(ring->ring_obj, false);
729 if (unlikely(r != 0)) {
730 radeon_bo_unref(&ring->ring_obj);
733 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
736 radeon_bo_unreserve(ring->ring_obj);
737 radeon_bo_unref(&ring->ring_obj);
738 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
741 ring_ptr = &ring->ring;
742 r = radeon_bo_kmap(ring->ring_obj,
744 radeon_bo_unreserve(ring->ring_obj);
746 dev_err(rdev->dev, "(%d) ring map failed\n", r);
747 radeon_bo_unref(&ring->ring_obj);
751 ring->ptr_mask = (ring->ring_size / 4) - 1;
752 ring->ring_free_dw = ring->ring_size / 4;
753 if (rdev->wb.enabled) {
754 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
755 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
756 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
759 if (radeon_debugfs_ring_init(rdev, ring)) {
760 DRM_ERROR("Failed to register debugfs file for rings !\n");
762 #endif /* DUMBBELL_WIP */
763 radeon_ring_lockup_update(ring);
768 * radeon_ring_fini - tear down the driver ring struct.
770 * @rdev: radeon_device pointer
771 * @ring: radeon_ring structure holding ring information
773 * Tear down the driver information for the selected ring (all asics).
775 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
778 struct radeon_bo *ring_obj;
780 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
781 ring_obj = ring->ring_obj;
784 ring->ring_obj = NULL;
785 lockmgr(&rdev->ring_lock, LK_RELEASE);
788 r = radeon_bo_reserve(ring_obj, false);
789 if (likely(r == 0)) {
790 radeon_bo_kunmap(ring_obj);
791 radeon_bo_unpin(ring_obj);
792 radeon_bo_unreserve(ring_obj);
794 radeon_bo_unref(&ring_obj);
801 #if defined(CONFIG_DEBUG_FS)
803 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
805 struct drm_info_node *node = (struct drm_info_node *) m->private;
806 struct drm_device *dev = node->minor->dev;
807 struct radeon_device *rdev = dev->dev_private;
808 int ridx = *(int*)node->info_ent->data;
809 struct radeon_ring *ring = &rdev->ring[ridx];
810 unsigned count, i, j;
813 radeon_ring_free_size(rdev, ring);
814 count = (ring->ring_size / 4) - ring->ring_free_dw;
815 tmp = RREG32(ring->wptr_reg) >> ring->ptr_reg_shift;
816 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
817 tmp = RREG32(ring->rptr_reg) >> ring->ptr_reg_shift;
818 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
819 if (ring->rptr_save_reg) {
820 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
821 RREG32(ring->rptr_save_reg));
823 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
824 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
825 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
826 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr);
827 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
828 seq_printf(m, "%u dwords in ring\n", count);
829 /* print 8 dw before current rptr as often it's the last executed
830 * packet that is the root issue
832 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
833 for (j = 0; j <= (count + 32); j++) {
834 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
835 i = (i + 1) & ring->ptr_mask;
840 static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
841 static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
842 static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
843 static int radeon_ring_type_dma1_index = R600_RING_TYPE_DMA_INDEX;
844 static int radeon_ring_type_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
846 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
847 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
848 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
849 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
850 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma1_index},
851 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_ring_type_dma2_index},
854 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
856 struct drm_info_node *node = (struct drm_info_node *) m->private;
857 struct drm_device *dev = node->minor->dev;
858 struct radeon_device *rdev = dev->dev_private;
860 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
866 static struct drm_info_list radeon_debugfs_sa_list[] = {
867 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
873 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
875 #if defined(CONFIG_DEBUG_FS)
877 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
878 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
879 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
882 if (&rdev->ring[ridx] != ring)
885 r = radeon_debugfs_add_files(rdev, info, 1);
893 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
895 #if defined(CONFIG_DEBUG_FS)
896 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
901 #endif /* DUMBBELL_WIP */