2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/apic/ioapic_abi.h>
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 u_int32_t oem_table_pointer;
115 u_short oem_table_size;
117 u_int32_t apic_address;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_int32_t cpu_signature;
130 u_int32_t feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
146 u_int32_t apic_address;
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
268 #ifdef SMP /* APIC-IO */
269 static int mp_nbusses; /* # of busses */
270 int mp_napics; /* # of IO APICs */
271 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
272 u_int32_t *io_apic_versions;
276 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
278 extern int64_t tsc_offsets[];
280 extern u_long ebda_addr;
282 #ifdef SMP /* APIC-IO */
283 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
287 * APIC ID logical/physical mapping structures.
288 * We oversize these to simplify boot-time config.
290 int cpu_num_to_apic_id[NAPICID];
291 #ifdef SMP /* APIC-IO */
292 int io_num_to_apic_id[NAPICID];
294 int apic_id_to_logical[NAPICID];
296 /* AP uses this during bootstrap. Do not staticize. */
300 struct pcb stoppcbs[MAXCPU];
302 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
304 static basetable_entry basetable_entry_types[] =
306 {0, 20, "Processor"},
314 * Local data and functions.
317 static u_int boot_address;
318 static u_int base_memory;
319 static int mp_finish;
321 static void mp_enable(u_int boot_addr);
323 static int mptable_iterate_entries(const mpcth_t,
324 mptable_iter_func, void *);
325 static int mptable_search(void);
326 static long mptable_search_sig(u_int32_t target, int count);
327 static int mptable_hyperthread_fixup(cpumask_t, int);
328 #ifdef SMP /* APIC-IO */
329 static void mptable_pass1(struct mptable_pos *);
330 static void mptable_pass2(struct mptable_pos *);
331 static void mptable_default(int type);
332 static void mptable_fix(void);
334 static int mptable_map(struct mptable_pos *);
335 static void mptable_unmap(struct mptable_pos *);
336 static void mptable_bus_info_alloc(const mpcth_t,
337 struct mptable_bus_info *);
338 static void mptable_bus_info_free(struct mptable_bus_info *);
340 static int mptable_lapic_probe(struct lapic_enumerator *);
341 static void mptable_lapic_enumerate(struct lapic_enumerator *);
342 static void mptable_lapic_default(void);
344 static int mptable_ioapic_probe(struct ioapic_enumerator *);
345 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
347 #ifdef SMP /* APIC-IO */
348 static void setup_apic_irq_mapping(void);
349 static int apic_int_is_bus_type(int intr, int bus_type);
351 static int start_all_aps(u_int boot_addr);
353 static void install_ap_tramp(u_int boot_addr);
355 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
356 static int smitest(void);
358 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
359 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
360 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
361 static u_int bootMP_size;
365 static vm_paddr_t mptable_fps_phyaddr;
366 static int mptable_use_default;
367 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
368 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
369 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
370 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
373 * Calculate usable address in base memory for AP trampoline code.
376 mp_bootaddress(u_int basemem)
378 POSTCODE(MP_BOOTADDRESS_POST);
380 base_memory = basemem;
382 bootMP_size = mptramp_end - mptramp_start;
383 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
384 if (((basemem * 1024) - boot_address) < bootMP_size)
385 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
386 /* 3 levels of page table pages */
387 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
389 return mptramp_pagetables;
396 struct mptable_pos mpt;
399 KKASSERT(mptable_fps_phyaddr == 0);
401 mptable_fps_phyaddr = mptable_search();
402 if (mptable_fps_phyaddr == 0)
405 error = mptable_map(&mpt);
407 mptable_fps_phyaddr = 0;
411 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
412 kprintf("MPTABLE: use default configuration\n");
413 mptable_use_default = 1;
415 if (mpt.mp_fps->mpfb2 & 0x80)
420 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
423 * Look for an Intel MP spec table (ie, SMP capable hardware).
431 POSTCODE(MP_PROBE_POST);
433 /* see if EBDA exists */
434 if (ebda_addr != 0) {
435 /* search first 1K of EBDA */
436 target = (u_int32_t)ebda_addr;
437 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
440 /* last 1K of base memory, effective 'top of base' passed in */
441 target = (u_int32_t)(base_memory - 0x400);
442 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
446 /* search the BIOS */
447 target = (u_int32_t)BIOS_BASE;
448 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
451 /* search the extended BIOS */
452 target = (u_int32_t)BIOS_BASE2;
453 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
461 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
463 int count, total_size;
464 const void *position;
466 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
467 total_size = cth->base_table_length - sizeof(struct MPCTH);
468 position = (const uint8_t *)cth + sizeof(struct MPCTH);
469 count = cth->entry_count;
474 KKASSERT(total_size >= 0);
475 if (total_size == 0) {
476 kprintf("invalid base MP table, "
477 "entry count and length mismatch\n");
481 type = *(const uint8_t *)position;
483 case 0: /* processor_entry */
484 case 1: /* bus_entry */
485 case 2: /* io_apic_entry */
486 case 3: /* int_entry */
487 case 4: /* int_entry */
490 kprintf("unknown base MP table entry type %d\n", type);
494 if (total_size < basetable_entry_types[type].length) {
495 kprintf("invalid base MP table length, "
496 "does not contain all entries\n");
499 total_size -= basetable_entry_types[type].length;
501 error = func(arg, position, type);
505 position = (const uint8_t *)position +
506 basetable_entry_types[type].length;
513 * Startup the SMP processors.
518 POSTCODE(MP_START_POST);
519 mp_enable(boot_address);
524 * Print various information about the SMP system hardware and setup.
531 POSTCODE(MP_ANNOUNCE_POST);
533 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
534 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
535 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
536 for (x = 1; x <= mp_naps; ++x) {
537 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
538 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
541 if (apic_io_enable) {
542 if (ioapic_use_old) {
543 for (x = 0; x < mp_napics; ++x) {
544 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
545 kprintf(", version: 0x%08x", io_apic_versions[x]);
546 kprintf(", at 0x%08lx\n", io_apic_address[x]);
550 kprintf(" Warning: APIC I/O disabled\n");
555 * AP cpu's call this to sync up protected mode.
557 * WARNING! %gs is not set up on entry. This routine sets up %gs.
563 int x, myid = bootAP;
565 struct mdglobaldata *md;
566 struct privatespace *ps;
568 ps = &CPU_prvspace[myid];
570 gdt_segs[GPROC0_SEL].ssd_base =
571 (long) &ps->mdglobaldata.gd_common_tss;
572 ps->mdglobaldata.mi.gd_prvspace = ps;
574 /* We fill the 32-bit segment descriptors */
575 for (x = 0; x < NGDT; x++) {
576 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
577 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
579 /* And now a 64-bit one */
580 ssdtosyssd(&gdt_segs[GPROC0_SEL],
581 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
583 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
584 r_gdt.rd_base = (long) &gdt[myid * NGDT];
585 lgdt(&r_gdt); /* does magic intra-segment return */
587 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
588 wrmsr(MSR_FSBASE, 0); /* User value */
589 wrmsr(MSR_GSBASE, (u_int64_t)ps);
590 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
596 mdcpu->gd_currentldt = _default_ldt;
599 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
600 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
602 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
604 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
606 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
608 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
609 md->gd_common_tssd = *md->gd_tss_gdt;
611 /* double fault stack */
612 md->gd_common_tss.tss_ist1 =
613 (long)&md->mi.gd_prvspace->idlestack[
614 sizeof(md->mi.gd_prvspace->idlestack)];
619 * Set to a known state:
620 * Set by mpboot.s: CR0_PG, CR0_PE
621 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
624 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
627 /* Set up the fast syscall stuff */
628 msr = rdmsr(MSR_EFER) | EFER_SCE;
629 wrmsr(MSR_EFER, msr);
630 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
631 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
632 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
633 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
634 wrmsr(MSR_STAR, msr);
635 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
637 pmap_set_opt(); /* PSE/4MB pages, etc */
639 /* Initialize the PAT MSR. */
643 /* set up CPU registers and state */
646 /* set up SSE/NX registers */
649 /* set up FPU state on the AP */
650 npxinit(__INITIAL_NPXCW__);
652 /* disable the APIC, just to be SURE */
653 lapic->svr &= ~APIC_SVR_ENABLE;
655 /* data returned to BSP */
656 cpu_apic_versions[0] = lapic->version;
659 /*******************************************************************
660 * local functions and data
664 * start the SMP system
667 mp_enable(u_int boot_addr)
671 struct mptable_pos mpt;
673 POSTCODE(MP_ENABLE_POST);
677 /* Initialize BSP's local APIC */
683 if (apic_io_enable && ioapic_use_old) {
686 if (!mptable_fps_phyaddr)
687 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
695 * Switch to I/O APIC MachIntrABI and reconfigure
696 * the default IDT entries.
698 MachIntrABI = MachIntrABI_IOAPIC;
699 MachIntrABI.setdefault();
704 * Examine the MP table for needed info
711 /* Post scan cleanup */
714 setup_apic_irq_mapping();
716 /* fill the LOGICAL io_apic_versions table */
717 for (apic = 0; apic < mp_napics; ++apic) {
718 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
719 io_apic_versions[apic] = ux;
720 io_apic_set_id(apic, IO_TO_ID(apic));
723 /* program each IO APIC in the system */
724 for (apic = 0; apic < mp_napics; ++apic)
725 if (io_apic_setup(apic) < 0)
726 panic("IO APIC setup failure");
730 MachIntrABI.cleanup();
736 MachIntrABI.finalize();
738 /* start each Application Processor */
739 start_all_aps(boot_addr);
744 * look for the MP spec signature
747 /* string defined by the Intel MP Spec as identifying the MP table */
748 #define MP_SIG 0x5f504d5f /* _MP_ */
749 #define NEXT(X) ((X) += 4)
751 mptable_search_sig(u_int32_t target, int count)
757 KKASSERT(target != 0);
759 map_size = count * sizeof(u_int32_t);
760 addr = pmap_mapdev((vm_paddr_t)target, map_size);
763 for (x = 0; x < count; NEXT(x)) {
764 if (addr[x] == MP_SIG) {
765 /* make array index a byte index */
766 ret = target + (x * sizeof(u_int32_t));
771 pmap_unmapdev((vm_offset_t)addr, map_size);
776 typedef struct BUSDATA {
778 enum busTypes bus_type;
781 typedef struct INTDATA {
791 typedef struct BUSTYPENAME {
796 static bus_type_name bus_type_table[] =
802 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
808 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"},
811 {UNKNOWN_BUSTYPE, "---"},
812 {UNKNOWN_BUSTYPE, "---"},
813 {UNKNOWN_BUSTYPE, "---"},
814 {UNKNOWN_BUSTYPE, "---"},
816 {UNKNOWN_BUSTYPE, "---"}
819 /* from MP spec v1.4, table 5-1 */
820 static int default_data[7][5] =
822 /* nbus, id0, type0, id1, type1 */
823 {1, 0, ISA, 255, 255},
824 {1, 0, EISA, 255, 255},
825 {1, 0, EISA, 255, 255},
826 {1, 0, MCA, 255, 255},
828 {2, 0, EISA, 1, PCI},
833 static bus_datum *bus_data;
835 /* the IO INT data, one entry per possible APIC INTerrupt */
836 static io_int *io_apic_ints;
839 static int processor_entry (const struct PROCENTRY *entry, int cpu);
840 static int bus_entry (const struct BUSENTRY *entry, int bus);
841 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
842 static int int_entry (const struct INTENTRY *entry, int intr);
843 static int lookup_bus_type (char *name);
846 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
848 const struct IOAPICENTRY *ioapic_ent;
851 case 1: /* bus_entry */
855 case 2: /* io_apic_entry */
857 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
858 io_apic_address[mp_napics++] =
859 (vm_offset_t)ioapic_ent->apic_address;
863 case 3: /* int_entry */
871 * 1st pass on motherboard's Intel MP specification table.
880 mptable_pass1(struct mptable_pos *mpt)
885 POSTCODE(MPTABLE_PASS1_POST);
888 KKASSERT(fps != NULL);
890 /* clear various tables */
891 for (x = 0; x < NAPICID; ++x)
892 io_apic_address[x] = ~0; /* IO APIC address table */
898 /* check for use of 'default' configuration */
899 if (fps->mpfb1 != 0) {
900 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
901 mp_nbusses = default_data[fps->mpfb1 - 1][0];
907 error = mptable_iterate_entries(mpt->mp_cth,
908 mptable_ioapic_pass1_callback, NULL);
910 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
914 struct mptable_ioapic2_cbarg {
921 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
923 struct mptable_ioapic2_cbarg *arg = xarg;
927 if (bus_entry(pos, arg->bus))
932 if (io_apic_entry(pos, arg->apic))
937 if (int_entry(pos, arg->intr))
945 * 2nd pass on motherboard's Intel MP specification table.
948 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
949 * IO_TO_ID(N), logical IO to APIC ID table
954 mptable_pass2(struct mptable_pos *mpt)
956 struct mptable_ioapic2_cbarg arg;
960 POSTCODE(MPTABLE_PASS2_POST);
963 KKASSERT(fps != NULL);
965 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
967 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
968 M_DEVBUF, M_WAITOK | M_ZERO);
969 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
971 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
974 for (x = 0; x < mp_napics; x++)
975 ioapic[x] = ioapic_map(io_apic_address[x]);
977 /* clear various tables */
978 for (x = 0; x < NAPICID; ++x) {
979 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
980 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
983 /* clear bus data table */
984 for (x = 0; x < mp_nbusses; ++x)
985 bus_data[x].bus_id = 0xff;
987 /* clear IO APIC INT table */
988 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
989 io_apic_ints[x].int_type = 0xff;
990 io_apic_ints[x].int_vector = 0xff;
993 /* check for use of 'default' configuration */
994 if (fps->mpfb1 != 0) {
995 mptable_default(fps->mpfb1);
999 bzero(&arg, sizeof(arg));
1000 error = mptable_iterate_entries(mpt->mp_cth,
1001 mptable_ioapic_pass2_callback, &arg);
1003 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1007 * Check if we should perform a hyperthreading "fix-up" to
1008 * enumerate any logical CPU's that aren't already listed
1011 * XXX: We assume that all of the physical CPUs in the
1012 * system have the same number of logical CPUs.
1014 * XXX: We assume that APIC ID's are allocated such that
1015 * the APIC ID's for a physical processor are aligned
1016 * with the number of logical CPU's in the processor.
1019 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1021 int i, id, lcpus_max, logical_cpus;
1023 if ((cpu_feature & CPUID_HTT) == 0)
1026 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1030 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1032 * INSTRUCTION SET REFERENCE, A-M (#253666)
1033 * Page 3-181, Table 3-20
1034 * "The nearest power-of-2 integer that is not smaller
1035 * than EBX[23:16] is the number of unique initial APIC
1036 * IDs reserved for addressing different logical
1037 * processors in a physical package."
1039 for (i = 0; ; ++i) {
1040 if ((1 << i) >= lcpus_max) {
1047 KKASSERT(cpu_count != 0);
1048 if (cpu_count == lcpus_max) {
1049 /* We have nothing to fix */
1051 } else if (cpu_count == 1) {
1052 /* XXX this may be incorrect */
1053 logical_cpus = lcpus_max;
1055 int cur, prev, dist;
1058 * Calculate the distances between two nearest
1059 * APIC IDs. If all such distances are same,
1060 * then it is the number of missing cpus that
1061 * we are going to fill later.
1063 dist = cur = prev = -1;
1064 for (id = 0; id < MAXCPU; ++id) {
1065 if ((id_mask & CPUMASK(id)) == 0)
1070 int new_dist = cur - prev;
1076 * Make sure that all distances
1077 * between two nearest APIC IDs
1080 if (dist != new_dist)
1088 /* Must be power of 2 */
1089 if (dist & (dist - 1))
1092 /* Can't exceed CPU package capacity */
1093 if (dist > lcpus_max)
1094 logical_cpus = lcpus_max;
1096 logical_cpus = dist;
1100 * For each APIC ID of a CPU that is set in the mask,
1101 * scan the other candidate APIC ID's for this
1102 * physical processor. If any of those ID's are
1103 * already in the table, then kill the fixup.
1105 for (id = 0; id < MAXCPU; id++) {
1106 if ((id_mask & CPUMASK(id)) == 0)
1108 /* First, make sure we are on a logical_cpus boundary. */
1109 if (id % logical_cpus != 0)
1111 for (i = id + 1; i < id + logical_cpus; i++)
1112 if ((id_mask & CPUMASK(i)) != 0)
1115 return logical_cpus;
1119 mptable_map(struct mptable_pos *mpt)
1123 vm_size_t cth_mapsz = 0;
1125 KKASSERT(mptable_fps_phyaddr != 0);
1127 bzero(mpt, sizeof(*mpt));
1129 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1130 if (fps->pap != 0) {
1132 * Map configuration table header to get
1133 * the base table size
1135 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1136 cth_mapsz = cth->base_table_length;
1137 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1139 if (cth_mapsz < sizeof(*cth)) {
1140 kprintf("invalid base MP table length %d\n",
1142 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1147 * Map the base table
1149 cth = pmap_mapdev(fps->pap, cth_mapsz);
1154 mpt->mp_cth_mapsz = cth_mapsz;
1160 mptable_unmap(struct mptable_pos *mpt)
1162 if (mpt->mp_cth != NULL) {
1163 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1165 mpt->mp_cth_mapsz = 0;
1167 if (mpt->mp_fps != NULL) {
1168 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1174 assign_apic_irq(int apic, int intpin, int irq)
1178 if (int_to_apicintpin[irq].ioapic != -1)
1179 panic("assign_apic_irq: inconsistent table");
1181 int_to_apicintpin[irq].ioapic = apic;
1182 int_to_apicintpin[irq].int_pin = intpin;
1183 int_to_apicintpin[irq].apic_address = ioapic[apic];
1184 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1186 for (x = 0; x < nintrs; x++) {
1187 if ((io_apic_ints[x].int_type == 0 ||
1188 io_apic_ints[x].int_type == 3) &&
1189 io_apic_ints[x].int_vector == 0xff &&
1190 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1191 io_apic_ints[x].dst_apic_int == intpin)
1192 io_apic_ints[x].int_vector = irq;
1197 revoke_apic_irq(int irq)
1203 if (int_to_apicintpin[irq].ioapic == -1)
1204 panic("revoke_apic_irq: inconsistent table");
1206 oldapic = int_to_apicintpin[irq].ioapic;
1207 oldintpin = int_to_apicintpin[irq].int_pin;
1209 int_to_apicintpin[irq].ioapic = -1;
1210 int_to_apicintpin[irq].int_pin = 0;
1211 int_to_apicintpin[irq].apic_address = NULL;
1212 int_to_apicintpin[irq].redirindex = 0;
1214 for (x = 0; x < nintrs; x++) {
1215 if ((io_apic_ints[x].int_type == 0 ||
1216 io_apic_ints[x].int_type == 3) &&
1217 io_apic_ints[x].int_vector != 0xff &&
1218 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1219 io_apic_ints[x].dst_apic_int == oldintpin)
1220 io_apic_ints[x].int_vector = 0xff;
1228 allocate_apic_irq(int intr)
1234 if (io_apic_ints[intr].int_vector != 0xff)
1235 return; /* Interrupt handler already assigned */
1237 if (io_apic_ints[intr].int_type != 0 &&
1238 (io_apic_ints[intr].int_type != 3 ||
1239 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1240 io_apic_ints[intr].dst_apic_int == 0)))
1241 return; /* Not INT or ExtInt on != (0, 0) */
1244 while (irq < APIC_INTMAPSIZE &&
1245 int_to_apicintpin[irq].ioapic != -1)
1248 if (irq >= APIC_INTMAPSIZE)
1249 return; /* No free interrupt handlers */
1251 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1252 intpin = io_apic_ints[intr].dst_apic_int;
1254 assign_apic_irq(apic, intpin, irq);
1259 swap_apic_id(int apic, int oldid, int newid)
1266 return; /* Nothing to do */
1268 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1269 apic, oldid, newid);
1271 /* Swap physical APIC IDs in interrupt entries */
1272 for (x = 0; x < nintrs; x++) {
1273 if (io_apic_ints[x].dst_apic_id == oldid)
1274 io_apic_ints[x].dst_apic_id = newid;
1275 else if (io_apic_ints[x].dst_apic_id == newid)
1276 io_apic_ints[x].dst_apic_id = oldid;
1279 /* Swap physical APIC IDs in IO_TO_ID mappings */
1280 for (oapic = 0; oapic < mp_napics; oapic++)
1281 if (IO_TO_ID(oapic) == newid)
1284 if (oapic < mp_napics) {
1285 kprintf("Changing APIC ID for IO APIC #%d from "
1286 "%d to %d in MP table\n",
1287 oapic, newid, oldid);
1288 IO_TO_ID(oapic) = oldid;
1290 IO_TO_ID(apic) = newid;
1295 fix_id_to_io_mapping(void)
1299 for (x = 0; x < NAPICID; x++)
1302 for (x = 0; x <= mp_naps; x++) {
1303 if ((u_int)CPU_TO_ID(x) < NAPICID)
1304 ID_TO_IO(CPU_TO_ID(x)) = x;
1307 for (x = 0; x < mp_napics; x++) {
1308 if ((u_int)IO_TO_ID(x) < NAPICID)
1309 ID_TO_IO(IO_TO_ID(x)) = x;
1315 first_free_apic_id(void)
1319 for (freeid = 0; freeid < NAPICID; freeid++) {
1320 for (x = 0; x <= mp_naps; x++)
1321 if (CPU_TO_ID(x) == freeid)
1325 for (x = 0; x < mp_napics; x++)
1326 if (IO_TO_ID(x) == freeid)
1337 io_apic_id_acceptable(int apic, int id)
1339 int cpu; /* Logical CPU number */
1340 int oapic; /* Logical IO APIC number for other IO APIC */
1342 if ((u_int)id >= NAPICID)
1343 return 0; /* Out of range */
1345 for (cpu = 0; cpu <= mp_naps; cpu++) {
1346 if (CPU_TO_ID(cpu) == id)
1347 return 0; /* Conflict with CPU */
1350 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1351 if (IO_TO_ID(oapic) == id)
1352 return 0; /* Conflict with other APIC */
1355 return 1; /* ID is acceptable for IO APIC */
1360 io_apic_find_int_entry(int apic, int pin)
1364 /* search each of the possible INTerrupt sources */
1365 for (x = 0; x < nintrs; ++x) {
1366 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1367 (pin == io_apic_ints[x].dst_apic_int))
1368 return (&io_apic_ints[x]);
1374 * parse an Intel MP specification table
1381 int apic; /* IO APIC unit number */
1382 int freeid; /* Free physical APIC ID */
1383 int physid; /* Current physical IO APIC ID */
1385 int bus_0 = 0; /* Stop GCC warning */
1386 int bus_pci = 0; /* Stop GCC warning */
1390 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1391 * did it wrong. The MP spec says that when more than 1 PCI bus
1392 * exists the BIOS must begin with bus entries for the PCI bus and use
1393 * actual PCI bus numbering. This implies that when only 1 PCI bus
1394 * exists the BIOS can choose to ignore this ordering, and indeed many
1395 * MP motherboards do ignore it. This causes a problem when the PCI
1396 * sub-system makes requests of the MP sub-system based on PCI bus
1397 * numbers. So here we look for the situation and renumber the
1398 * busses and associated INTs in an effort to "make it right".
1401 /* find bus 0, PCI bus, count the number of PCI busses */
1402 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1403 if (bus_data[x].bus_id == 0) {
1406 if (bus_data[x].bus_type == PCI) {
1412 * bus_0 == slot of bus with ID of 0
1413 * bus_pci == slot of last PCI bus encountered
1416 /* check the 1 PCI bus case for sanity */
1417 /* if it is number 0 all is well */
1418 if (num_pci_bus == 1 &&
1419 bus_data[bus_pci].bus_id != 0) {
1421 /* mis-numbered, swap with whichever bus uses slot 0 */
1423 /* swap the bus entry types */
1424 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1425 bus_data[bus_0].bus_type = PCI;
1427 /* swap each relevant INTerrupt entry */
1428 id = bus_data[bus_pci].bus_id;
1429 for (x = 0; x < nintrs; ++x) {
1430 if (io_apic_ints[x].src_bus_id == id) {
1431 io_apic_ints[x].src_bus_id = 0;
1433 else if (io_apic_ints[x].src_bus_id == 0) {
1434 io_apic_ints[x].src_bus_id = id;
1439 /* Assign IO APIC IDs.
1441 * First try the existing ID. If a conflict is detected, try
1442 * the ID in the MP table. If a conflict is still detected, find
1445 * We cannot use the ID_TO_IO table before all conflicts has been
1446 * resolved and the table has been corrected.
1448 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1450 /* First try to use the value set by the BIOS */
1451 physid = io_apic_get_id(apic);
1452 if (io_apic_id_acceptable(apic, physid)) {
1453 if (IO_TO_ID(apic) != physid)
1454 swap_apic_id(apic, IO_TO_ID(apic), physid);
1458 /* Then check if the value in the MP table is acceptable */
1459 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1462 /* Last resort, find a free APIC ID and use it */
1463 freeid = first_free_apic_id();
1464 if (freeid >= NAPICID)
1465 panic("No free physical APIC IDs found");
1467 if (io_apic_id_acceptable(apic, freeid)) {
1468 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1471 panic("Free physical APIC ID not usable");
1473 fix_id_to_io_mapping();
1475 /* detect and fix broken Compaq MP table */
1476 if (apic_int_type(0, 0) == -1) {
1477 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1478 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1479 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1480 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1481 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1482 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1484 } else if (apic_int_type(0, 0) == 0) {
1485 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1486 for (x = 0; x < nintrs; ++x)
1487 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1488 (io_apic_ints[x].dst_apic_int) == 0) {
1489 io_apic_ints[x].int_type = 3;
1490 io_apic_ints[x].int_vector = 0xff;
1496 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1497 * controllers universally come in pairs. If IRQ 14 is specified
1498 * as an ISA interrupt, then IRQ 15 had better be too.
1500 * [ Shuttle XPC / AMD Athlon X2 ]
1501 * The MPTable is missing an entry for IRQ 15. Note that the
1502 * ACPI table has an entry for both 14 and 15.
1504 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1505 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1506 io14 = io_apic_find_int_entry(0, 14);
1507 io_apic_ints[nintrs] = *io14;
1508 io_apic_ints[nintrs].src_bus_irq = 15;
1509 io_apic_ints[nintrs].dst_apic_int = 15;
1514 /* Assign low level interrupt handlers */
1516 setup_apic_irq_mapping(void)
1522 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1523 int_to_apicintpin[x].ioapic = -1;
1524 int_to_apicintpin[x].int_pin = 0;
1525 int_to_apicintpin[x].apic_address = NULL;
1526 int_to_apicintpin[x].redirindex = 0;
1528 /* Default to masked */
1529 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1532 /* First assign ISA/EISA interrupts */
1533 for (x = 0; x < nintrs; x++) {
1534 int_vector = io_apic_ints[x].src_bus_irq;
1535 if (int_vector < APIC_INTMAPSIZE &&
1536 io_apic_ints[x].int_vector == 0xff &&
1537 int_to_apicintpin[int_vector].ioapic == -1 &&
1538 (apic_int_is_bus_type(x, ISA) ||
1539 apic_int_is_bus_type(x, EISA)) &&
1540 io_apic_ints[x].int_type == 0) {
1541 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1542 io_apic_ints[x].dst_apic_int,
1547 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1548 for (x = 0; x < nintrs; x++) {
1549 if (io_apic_ints[x].dst_apic_int == 0 &&
1550 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1551 io_apic_ints[x].int_vector == 0xff &&
1552 int_to_apicintpin[0].ioapic == -1 &&
1553 io_apic_ints[x].int_type == 3) {
1554 assign_apic_irq(0, 0, 0);
1559 /* Assign PCI interrupts */
1560 for (x = 0; x < nintrs; ++x) {
1561 if (io_apic_ints[x].int_type == 0 &&
1562 io_apic_ints[x].int_vector == 0xff &&
1563 apic_int_is_bus_type(x, PCI))
1564 allocate_apic_irq(x);
1569 mp_set_cpuids(int cpu_id, int apic_id)
1571 CPU_TO_ID(cpu_id) = apic_id;
1572 ID_TO_CPU(apic_id) = cpu_id;
1574 if (apic_id > lapic_id_max)
1575 lapic_id_max = apic_id;
1579 processor_entry(const struct PROCENTRY *entry, int cpu)
1583 /* check for usability */
1584 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1587 /* check for BSP flag */
1588 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1589 mp_set_cpuids(0, entry->apic_id);
1590 return 0; /* its already been counted */
1593 /* add another AP to list, if less than max number of CPUs */
1594 else if (cpu < MAXCPU) {
1595 mp_set_cpuids(cpu, entry->apic_id);
1603 bus_entry(const struct BUSENTRY *entry, int bus)
1608 /* encode the name into an index */
1609 for (x = 0; x < 6; ++x) {
1610 if ((c = entry->bus_type[x]) == ' ')
1616 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1617 panic("unknown bus type: '%s'", name);
1619 bus_data[bus].bus_id = entry->bus_id;
1620 bus_data[bus].bus_type = x;
1626 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1628 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1631 IO_TO_ID(apic) = entry->apic_id;
1632 ID_TO_IO(entry->apic_id) = apic;
1638 lookup_bus_type(char *name)
1642 for (x = 0; x < MAX_BUSTYPE; ++x)
1643 if (strcmp(bus_type_table[x].name, name) == 0)
1644 return bus_type_table[x].type;
1646 return UNKNOWN_BUSTYPE;
1650 int_entry(const struct INTENTRY *entry, int intr)
1654 io_apic_ints[intr].int_type = entry->int_type;
1655 io_apic_ints[intr].int_flags = entry->int_flags;
1656 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1657 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1658 if (entry->dst_apic_id == 255) {
1659 /* This signal goes to all IO APICS. Select an IO APIC
1660 with sufficient number of interrupt pins */
1661 for (apic = 0; apic < mp_napics; apic++)
1662 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1663 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1664 entry->dst_apic_int)
1666 if (apic < mp_napics)
1667 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1669 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1671 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1672 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1678 apic_int_is_bus_type(int intr, int bus_type)
1682 for (bus = 0; bus < mp_nbusses; ++bus)
1683 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1684 && ((int) bus_data[bus].bus_type == bus_type))
1691 * Given a traditional ISA INT mask, return an APIC mask.
1694 isa_apic_mask(u_int isa_mask)
1699 #if defined(SKIP_IRQ15_REDIRECT)
1700 if (isa_mask == (1 << 15)) {
1701 kprintf("skipping ISA IRQ15 redirect\n");
1704 #endif /* SKIP_IRQ15_REDIRECT */
1706 isa_irq = ffs(isa_mask); /* find its bit position */
1707 if (isa_irq == 0) /* doesn't exist */
1709 --isa_irq; /* make it zero based */
1711 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1715 return (1 << apic_pin); /* convert pin# to a mask */
1719 * Determine which APIC pin an ISA/EISA INT is attached to.
1721 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1722 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1723 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1724 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1726 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1728 isa_apic_irq(int isa_irq)
1732 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1733 if (INTTYPE(intr) == 0) { /* standard INT */
1734 if (SRCBUSIRQ(intr) == isa_irq) {
1735 if (apic_int_is_bus_type(intr, ISA) ||
1736 apic_int_is_bus_type(intr, EISA)) {
1737 if (INTIRQ(intr) == 0xff)
1738 return -1; /* unassigned */
1739 return INTIRQ(intr); /* found */
1744 return -1; /* NOT found */
1749 * Determine which APIC pin a PCI INT is attached to.
1751 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1752 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1753 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1755 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1759 --pciInt; /* zero based */
1761 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1762 if ((INTTYPE(intr) == 0) /* standard INT */
1763 && (SRCBUSID(intr) == pciBus)
1764 && (SRCBUSDEVICE(intr) == pciDevice)
1765 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1766 if (apic_int_is_bus_type(intr, PCI)) {
1767 if (INTIRQ(intr) == 0xff) {
1768 kprintf("IOAPIC: pci_apic_irq() "
1770 return -1; /* unassigned */
1772 return INTIRQ(intr); /* exact match */
1777 return -1; /* NOT found */
1781 next_apic_irq(int irq)
1788 for (intr = 0; intr < nintrs; intr++) {
1789 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1791 bus = SRCBUSID(intr);
1792 bustype = apic_bus_type(bus);
1793 if (bustype != ISA &&
1799 if (intr >= nintrs) {
1802 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1803 if (INTTYPE(ointr) != 0)
1805 if (bus != SRCBUSID(ointr))
1807 if (bustype == PCI) {
1808 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1810 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1813 if (bustype == ISA || bustype == EISA) {
1814 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1817 if (INTPIN(intr) == INTPIN(ointr))
1821 if (ointr >= nintrs) {
1824 return INTIRQ(ointr);
1837 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1840 * Exactly what this means is unclear at this point. It is a solution
1841 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1842 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1843 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1847 undirect_isa_irq(int rirq)
1851 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1852 /** FIXME: tickle the MB redirector chip */
1856 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1863 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1866 undirect_pci_irq(int rirq)
1870 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1872 /** FIXME: tickle the MB redirector chip */
1876 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1884 * given a bus ID, return:
1885 * the bus type if found
1889 apic_bus_type(int id)
1893 for (x = 0; x < mp_nbusses; ++x)
1894 if (bus_data[x].bus_id == id)
1895 return bus_data[x].bus_type;
1901 * given a LOGICAL APIC# and pin#, return:
1902 * the associated src bus ID if found
1906 apic_src_bus_id(int apic, int pin)
1910 /* search each of the possible INTerrupt sources */
1911 for (x = 0; x < nintrs; ++x)
1912 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1913 (pin == io_apic_ints[x].dst_apic_int))
1914 return (io_apic_ints[x].src_bus_id);
1916 return -1; /* NOT found */
1920 * given a LOGICAL APIC# and pin#, return:
1921 * the associated src bus IRQ if found
1925 apic_src_bus_irq(int apic, int pin)
1929 for (x = 0; x < nintrs; x++)
1930 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1931 (pin == io_apic_ints[x].dst_apic_int))
1932 return (io_apic_ints[x].src_bus_irq);
1934 return -1; /* NOT found */
1939 * given a LOGICAL APIC# and pin#, return:
1940 * the associated INTerrupt type if found
1944 apic_int_type(int apic, int pin)
1948 /* search each of the possible INTerrupt sources */
1949 for (x = 0; x < nintrs; ++x) {
1950 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1951 (pin == io_apic_ints[x].dst_apic_int))
1952 return (io_apic_ints[x].int_type);
1954 return -1; /* NOT found */
1958 * Return the IRQ associated with an APIC pin
1961 apic_irq(int apic, int pin)
1966 for (x = 0; x < nintrs; ++x) {
1967 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1968 (pin == io_apic_ints[x].dst_apic_int)) {
1969 res = io_apic_ints[x].int_vector;
1972 if (apic != int_to_apicintpin[res].ioapic)
1973 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1974 if (pin != int_to_apicintpin[res].int_pin)
1975 panic("apic_irq inconsistent table (2)");
1984 * given a LOGICAL APIC# and pin#, return:
1985 * the associated trigger mode if found
1989 apic_trigger(int apic, int pin)
1993 /* search each of the possible INTerrupt sources */
1994 for (x = 0; x < nintrs; ++x)
1995 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1996 (pin == io_apic_ints[x].dst_apic_int))
1997 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1999 return -1; /* NOT found */
2004 * given a LOGICAL APIC# and pin#, return:
2005 * the associated 'active' level if found
2009 apic_polarity(int apic, int pin)
2013 /* search each of the possible INTerrupt sources */
2014 for (x = 0; x < nintrs; ++x)
2015 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2016 (pin == io_apic_ints[x].dst_apic_int))
2017 return (io_apic_ints[x].int_flags & 0x03);
2019 return -1; /* NOT found */
2023 * set data according to MP defaults
2024 * FIXME: probably not complete yet...
2027 mptable_default(int type)
2033 kprintf(" MP default config type: %d\n", type);
2036 kprintf(" bus: ISA, APIC: 82489DX\n");
2039 kprintf(" bus: EISA, APIC: 82489DX\n");
2042 kprintf(" bus: EISA, APIC: 82489DX\n");
2045 kprintf(" bus: MCA, APIC: 82489DX\n");
2048 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2051 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2054 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2057 kprintf(" future type\n");
2063 /* one and only IO APIC */
2064 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2067 * sanity check, refer to MP spec section 3.6.6, last paragraph
2068 * necessary as some hardware isn't properly setting up the IO APIC
2070 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2071 if (io_apic_id != 2) {
2073 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2074 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2075 io_apic_set_id(0, 2);
2078 IO_TO_ID(0) = io_apic_id;
2079 ID_TO_IO(io_apic_id) = 0;
2081 /* fill out bus entries */
2090 bus_data[0].bus_id = default_data[type - 1][1];
2091 bus_data[0].bus_type = default_data[type - 1][2];
2092 bus_data[1].bus_id = default_data[type - 1][3];
2093 bus_data[1].bus_type = default_data[type - 1][4];
2096 /* case 4: case 7: MCA NOT supported */
2097 default: /* illegal/reserved */
2098 panic("BAD default MP config: %d", type);
2102 /* general cases from MP v1.4, table 5-2 */
2103 for (pin = 0; pin < 16; ++pin) {
2104 io_apic_ints[pin].int_type = 0;
2105 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2106 io_apic_ints[pin].src_bus_id = 0;
2107 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2108 io_apic_ints[pin].dst_apic_id = io_apic_id;
2109 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2112 /* special cases from MP v1.4, table 5-2 */
2114 io_apic_ints[2].int_type = 0xff; /* N/C */
2115 io_apic_ints[13].int_type = 0xff; /* N/C */
2116 #if !defined(APIC_MIXED_MODE)
2118 panic("sorry, can't support type 2 default yet");
2119 #endif /* APIC_MIXED_MODE */
2122 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2125 io_apic_ints[0].int_type = 0xff; /* N/C */
2127 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2131 * Map a physical memory address representing I/O into KVA. The I/O
2132 * block is assumed not to cross a page boundary.
2135 ioapic_map(vm_paddr_t pa)
2137 KKASSERT(pa < 0x100000000LL);
2139 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2143 * start each AP in our list
2146 start_all_aps(u_int boot_addr)
2148 vm_offset_t va = boot_address + KERNBASE;
2149 u_int64_t *pt4, *pt3, *pt2;
2155 u_char mpbiosreason;
2156 u_long mpbioswarmvec;
2157 struct mdglobaldata *gd;
2158 struct privatespace *ps;
2160 POSTCODE(START_ALL_APS_POST);
2162 /* install the AP 1st level boot code */
2163 pmap_kenter(va, boot_address);
2164 cpu_invlpg((void *)va); /* JG XXX */
2165 bcopy(mptramp_start, (void *)va, bootMP_size);
2167 /* Locate the page tables, they'll be below the trampoline */
2168 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2169 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2170 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2172 /* Create the initial 1GB replicated page tables */
2173 for (i = 0; i < 512; i++) {
2174 /* Each slot of the level 4 pages points to the same level 3 page */
2175 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2176 pt4[i] |= PG_V | PG_RW | PG_U;
2178 /* Each slot of the level 3 pages points to the same level 2 page */
2179 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2180 pt3[i] |= PG_V | PG_RW | PG_U;
2182 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2183 pt2[i] = i * (2 * 1024 * 1024);
2184 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2187 /* save the current value of the warm-start vector */
2188 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2189 outb(CMOS_REG, BIOS_RESET);
2190 mpbiosreason = inb(CMOS_DATA);
2192 /* setup a vector to our boot code */
2193 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2194 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2195 outb(CMOS_REG, BIOS_RESET);
2196 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2199 * If we have a TSC we can figure out the SMI interrupt rate.
2200 * The SMI does not necessarily use a constant rate. Spend
2201 * up to 250ms trying to figure it out.
2204 if (cpu_feature & CPUID_TSC) {
2205 set_apic_timer(275000);
2206 smilast = read_apic_timer();
2207 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2208 smicount = smitest();
2209 if (smibest == 0 || smilast - smicount < smibest)
2210 smibest = smilast - smicount;
2213 if (smibest > 250000)
2216 smibest = smibest * (int64_t)1000000 /
2217 get_apic_timer_frequency();
2221 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2222 1000000 / smibest, smibest);
2224 kprintf("SMP: Starting %d APs: ", mp_naps);
2226 for (x = 1; x <= mp_naps; ++x) {
2228 /* This is a bit verbose, it will go away soon. */
2230 /* first page of AP's private space */
2231 pg = x * x86_64_btop(sizeof(struct privatespace));
2233 /* allocate new private data page(s) */
2234 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2235 MDGLOBALDATA_BASEALLOC_SIZE);
2237 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2238 bzero(gd, sizeof(*gd));
2239 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2241 /* prime data page for it to use */
2242 mi_gdinit(&gd->mi, x);
2244 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2245 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2247 /* setup a vector to our boot code */
2248 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2249 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2250 outb(CMOS_REG, BIOS_RESET);
2251 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2254 * Setup the AP boot stack
2256 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2259 /* attempt to start the Application Processor */
2260 CHECK_INIT(99); /* setup checkpoints */
2261 if (!start_ap(gd, boot_addr, smibest)) {
2262 kprintf("\nAP #%d (PHY# %d) failed!\n",
2264 CHECK_PRINT("trace"); /* show checkpoints */
2265 /* better panic as the AP may be running loose */
2266 kprintf("panic y/n? [y] ");
2267 if (cngetc() != 'n')
2270 CHECK_PRINT("trace"); /* show checkpoints */
2272 /* record its version info */
2273 cpu_apic_versions[x] = cpu_apic_versions[0];
2276 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2279 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2280 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2283 ncpus2_shift = shift;
2284 ncpus2 = 1 << shift;
2285 ncpus2_mask = ncpus2 - 1;
2287 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2288 if ((1 << shift) < ncpus)
2290 ncpus_fit = 1 << shift;
2291 ncpus_fit_mask = ncpus_fit - 1;
2293 /* build our map of 'other' CPUs */
2294 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2295 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2296 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2298 /* fill in our (BSP) APIC version */
2299 cpu_apic_versions[0] = lapic->version;
2301 /* restore the warmstart vector */
2302 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2303 outb(CMOS_REG, BIOS_RESET);
2304 outb(CMOS_DATA, mpbiosreason);
2307 * NOTE! The idlestack for the BSP was setup by locore. Finish
2308 * up, clean out the P==V mapping we did earlier.
2312 /* number of APs actually started */
2318 * load the 1st level AP boot code into base memory.
2321 /* targets for relocation */
2322 extern void bigJump(void);
2323 extern void bootCodeSeg(void);
2324 extern void bootDataSeg(void);
2325 extern void MPentry(void);
2326 extern u_int MP_GDT;
2327 extern u_int mp_gdtbase;
2332 install_ap_tramp(u_int boot_addr)
2335 int size = *(int *) ((u_long) & bootMP_size);
2336 u_char *src = (u_char *) ((u_long) bootMP);
2337 u_char *dst = (u_char *) boot_addr + KERNBASE;
2338 u_int boot_base = (u_int) bootMP;
2343 POSTCODE(INSTALL_AP_TRAMP_POST);
2345 for (x = 0; x < size; ++x)
2349 * modify addresses in code we just moved to basemem. unfortunately we
2350 * need fairly detailed info about mpboot.s for this to work. changes
2351 * to mpboot.s might require changes here.
2354 /* boot code is located in KERNEL space */
2355 dst = (u_char *) boot_addr + KERNBASE;
2357 /* modify the lgdt arg */
2358 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2359 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2361 /* modify the ljmp target for MPentry() */
2362 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2363 *dst32 = ((u_int) MPentry - KERNBASE);
2365 /* modify the target for boot code segment */
2366 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2367 dst8 = (u_int8_t *) (dst16 + 1);
2368 *dst16 = (u_int) boot_addr & 0xffff;
2369 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2371 /* modify the target for boot data segment */
2372 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2373 dst8 = (u_int8_t *) (dst16 + 1);
2374 *dst16 = (u_int) boot_addr & 0xffff;
2375 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2381 * This function starts the AP (application processor) identified
2382 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2383 * to accomplish this. This is necessary because of the nuances
2384 * of the different hardware we might encounter. It ain't pretty,
2385 * but it seems to work.
2387 * NOTE: eventually an AP gets to ap_init(), which is called just
2388 * before the AP goes into the LWKT scheduler's idle loop.
2391 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2395 u_long icr_lo, icr_hi;
2397 POSTCODE(START_AP_POST);
2399 /* get the PHYSICAL APIC ID# */
2400 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2402 /* calculate the vector */
2403 vector = (boot_addr >> 12) & 0xff;
2405 /* We don't want anything interfering */
2408 /* Make sure the target cpu sees everything */
2412 * Try to detect when a SMI has occurred, wait up to 200ms.
2414 * If a SMI occurs during an AP reset but before we issue
2415 * the STARTUP command, the AP may brick. To work around
2416 * this problem we hold off doing the AP startup until
2417 * after we have detected the SMI. Hopefully another SMI
2418 * will not occur before we finish the AP startup.
2420 * Retries don't seem to help. SMIs have a window of opportunity
2421 * and if USB->legacy keyboard emulation is enabled in the BIOS
2422 * the interrupt rate can be quite high.
2424 * NOTE: Don't worry about the L1 cache load, it might bloat
2425 * ldelta a little but ndelta will be so huge when the SMI
2426 * occurs the detection logic will still work fine.
2429 set_apic_timer(200000);
2434 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2435 * and running the target CPU. OR this INIT IPI might be latched (P5
2436 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2439 * see apic/apicreg.h for icr bit definitions.
2441 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2445 * Setup the address for the target AP. We can setup
2446 * icr_hi once and then just trigger operations with
2449 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2450 icr_hi |= (physical_cpu << 24);
2451 icr_lo = lapic->icr_lo & 0xfff00000;
2452 lapic->icr_hi = icr_hi;
2455 * Do an INIT IPI: assert RESET
2457 * Use edge triggered mode to assert INIT
2459 lapic->icr_lo = icr_lo | 0x00004500;
2460 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2464 * The spec calls for a 10ms delay but we may have to use a
2465 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2466 * interrupt. We have other loops here too and dividing by 2
2467 * doesn't seem to be enough even after subtracting 350us,
2468 * so we divide by 4.
2470 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2471 * interrupt was detected we use the full 10ms.
2475 else if (smibest < 150 * 4 + 350)
2477 else if ((smibest - 350) / 4 < 10000)
2478 u_sleep((smibest - 350) / 4);
2483 * Do an INIT IPI: deassert RESET
2485 * Use level triggered mode to deassert. It is unclear
2486 * why we need to do this.
2488 lapic->icr_lo = icr_lo | 0x00008500;
2489 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2491 u_sleep(150); /* wait 150us */
2494 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2495 * latched, (P5 bug) this 1st STARTUP would then terminate
2496 * immediately, and the previously started INIT IPI would continue. OR
2497 * the previous INIT IPI has already run. and this STARTUP IPI will
2498 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2501 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2502 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2504 u_sleep(200); /* wait ~200uS */
2507 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2508 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2509 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2510 * recognized after hardware RESET or INIT IPI.
2512 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2513 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2516 /* Resume normal operation */
2519 /* wait for it to start, see ap_init() */
2520 set_apic_timer(5000000);/* == 5 seconds */
2521 while (read_apic_timer()) {
2522 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2523 return 1; /* return SUCCESS */
2526 return 0; /* return FAILURE */
2541 while (read_apic_timer()) {
2543 for (count = 0; count < 100; ++count)
2544 ntsc = rdtsc(); /* force loop to occur */
2546 ndelta = ntsc - ltsc;
2547 if (ldelta > ndelta)
2549 if (ndelta > ldelta * 2)
2552 ldelta = ntsc - ltsc;
2555 return(read_apic_timer());
2559 * Synchronously flush the TLB on all other CPU's. The current cpu's
2560 * TLB is not flushed. If the caller wishes to flush the current cpu's
2561 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2563 * NOTE: If for some reason we were unable to start all cpus we cannot
2564 * safely use broadcast IPIs.
2567 static cpumask_t smp_invltlb_req;
2569 #define SMP_INVLTLB_DEBUG
2575 struct mdglobaldata *md = mdcpu;
2576 #ifdef SMP_INVLTLB_DEBUG
2581 crit_enter_gd(&md->mi);
2582 md->gd_invltlb_ret = 0;
2583 ++md->mi.gd_cnt.v_smpinvltlb;
2584 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2585 #ifdef SMP_INVLTLB_DEBUG
2588 if (smp_startup_mask == smp_active_mask) {
2589 all_but_self_ipi(XINVLTLB_OFFSET);
2591 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2592 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2595 #ifdef SMP_INVLTLB_DEBUG
2597 kprintf("smp_invltlb: ipi sent\n");
2599 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2600 (smp_active_mask & ~md->mi.gd_cpumask)) {
2603 #ifdef SMP_INVLTLB_DEBUG
2605 if (++count == 400000000) {
2606 print_backtrace(-1);
2607 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2608 "rflags %016jx retry",
2609 (long)md->gd_invltlb_ret,
2610 (long)smp_invltlb_req,
2611 (intmax_t)read_rflags());
2612 __asm __volatile ("sti");
2615 lwkt_process_ipiq();
2617 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2618 ~md->mi.gd_cpumask &
2622 kprintf("bcpu %d\n", bcpu);
2623 xgd = globaldata_find(bcpu);
2624 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2627 Debugger("giving up");
2633 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2634 crit_exit_gd(&md->mi);
2641 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2642 * bother to bump the critical section count or nested interrupt count
2643 * so only do very low level operations here.
2646 smp_invltlb_intr(void)
2648 struct mdglobaldata *md = mdcpu;
2649 struct mdglobaldata *omd;
2654 mask = smp_invltlb_req;
2657 cpu = BSFCPUMASK(mask);
2658 mask &= ~CPUMASK(cpu);
2659 omd = (struct mdglobaldata *)globaldata_find(cpu);
2660 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2667 * When called the executing CPU will send an IPI to all other CPUs
2668 * requesting that they halt execution.
2670 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2672 * - Signals all CPUs in map to stop.
2673 * - Waits for each to stop.
2680 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2681 * from executing at same time.
2684 stop_cpus(cpumask_t map)
2686 map &= smp_active_mask;
2688 /* send the Xcpustop IPI to all CPUs in map */
2689 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2691 while ((stopped_cpus & map) != map)
2699 * Called by a CPU to restart stopped CPUs.
2701 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2703 * - Signals all CPUs in map to restart.
2704 * - Waits for each to restart.
2712 restart_cpus(cpumask_t map)
2714 /* signal other cpus to restart */
2715 started_cpus = map & smp_active_mask;
2717 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2724 * This is called once the mpboot code has gotten us properly relocated
2725 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2726 * and when it returns the scheduler will call the real cpu_idle() main
2727 * loop for the idlethread. Interrupts are disabled on entry and should
2728 * remain disabled at return.
2736 * Adjust smp_startup_mask to signal the BSP that we have started
2737 * up successfully. Note that we do not yet hold the BGL. The BSP
2738 * is waiting for our signal.
2740 * We can't set our bit in smp_active_mask yet because we are holding
2741 * interrupts physically disabled and remote cpus could deadlock
2742 * trying to send us an IPI.
2744 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2748 * Interlock for finalization. Wait until mp_finish is non-zero,
2749 * then get the MP lock.
2751 * Note: We are in a critical section.
2753 * Note: we are the idle thread, we can only spin.
2755 * Note: The load fence is memory volatile and prevents the compiler
2756 * from improperly caching mp_finish, and the cpu from improperly
2759 while (mp_finish == 0)
2761 while (try_mplock() == 0)
2764 if (cpu_feature & CPUID_TSC) {
2766 * The BSP is constantly updating tsc0_offset, figure out
2767 * the relative difference to synchronize ktrdump.
2769 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2772 /* BSP may have changed PTD while we're waiting for the lock */
2775 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2779 /* Build our map of 'other' CPUs. */
2780 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2782 kprintf(" %d", mycpu->gd_cpuid);
2784 /* A quick check from sanity claus */
2785 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2786 if (mycpu->gd_cpuid != apic_id) {
2787 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2788 kprintf("SMP: apic_id = %d lapicid %d\n",
2789 apic_id, (lapic->id & 0xff000000) >> 24);
2791 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2793 panic("cpuid mismatch! boom!!");
2796 /* Initialize AP's local APIC for irq's */
2799 /* Set memory range attributes for this CPU to match the BSP */
2800 mem_range_AP_init();
2803 * Once we go active we must process any IPIQ messages that may
2804 * have been queued, because no actual IPI will occur until we
2805 * set our bit in the smp_active_mask. If we don't the IPI
2806 * message interlock could be left set which would also prevent
2809 * The idle loop doesn't expect the BGL to be held and while
2810 * lwkt_switch() normally cleans things up this is a special case
2811 * because we returning almost directly into the idle loop.
2813 * The idle thread is never placed on the runq, make sure
2814 * nothing we've done put it there.
2816 KKASSERT(get_mplock_count(curthread) == 1);
2817 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2820 * Enable interrupts here. idle_restore will also do it, but
2821 * doing it here lets us clean up any strays that got posted to
2822 * the CPU during the AP boot while we are still in a critical
2825 __asm __volatile("sti; pause; pause"::);
2826 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2828 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2829 lwkt_process_ipiq();
2832 * Releasing the mp lock lets the BSP finish up the SMP init
2835 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2839 * Get SMP fully working before we start initializing devices.
2847 kprintf("Finish MP startup\n");
2848 if (cpu_feature & CPUID_TSC)
2849 tsc0_offset = rdtsc();
2852 while (smp_active_mask != smp_startup_mask) {
2854 if (cpu_feature & CPUID_TSC)
2855 tsc0_offset = rdtsc();
2857 while (try_mplock() == 0)
2861 kprintf("Active CPU Mask: %016jx\n",
2862 (uintmax_t)smp_active_mask);
2866 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2869 cpu_send_ipiq(int dcpu)
2871 if (CPUMASK(dcpu) & smp_active_mask)
2872 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2875 #if 0 /* single_apic_ipi_passive() not working yet */
2877 * Returns 0 on failure, 1 on success
2880 cpu_send_ipiq_passive(int dcpu)
2883 if (CPUMASK(dcpu) & smp_active_mask) {
2884 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2885 APIC_DELMODE_FIXED);
2892 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2894 struct mptable_bus_info *bus_info = xarg;
2895 const struct BUSENTRY *ent;
2896 struct mptable_bus *bus;
2902 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2903 if (bus->mb_id == ent->bus_id) {
2904 kprintf("mptable_bus_info_alloc: duplicated bus id "
2905 "(%d)\n", bus->mb_id);
2911 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2912 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2913 bus->mb_type = MPTABLE_BUS_PCI;
2914 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2915 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2916 bus->mb_type = MPTABLE_BUS_ISA;
2920 bus->mb_id = ent->bus_id;
2921 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2927 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2931 bzero(bus_info, sizeof(*bus_info));
2932 TAILQ_INIT(&bus_info->mbi_list);
2934 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2936 mptable_bus_info_free(bus_info);
2940 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2942 struct mptable_bus *bus;
2944 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2945 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2950 struct mptable_lapic_cbarg1 {
2953 u_int ht_apicid_mask;
2957 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2959 const struct PROCENTRY *ent;
2960 struct mptable_lapic_cbarg1 *arg = xarg;
2966 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2970 if (ent->apic_id < 32) {
2971 arg->ht_apicid_mask |= 1 << ent->apic_id;
2972 } else if (arg->ht_fixup) {
2973 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2979 struct mptable_lapic_cbarg2 {
2986 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2988 const struct PROCENTRY *ent;
2989 struct mptable_lapic_cbarg2 *arg = xarg;
2995 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2996 KKASSERT(!arg->found_bsp);
3000 if (processor_entry(ent, arg->cpu))
3003 if (arg->logical_cpus) {
3004 struct PROCENTRY proc;
3008 * Create fake mptable processor entries
3009 * and feed them to processor_entry() to
3010 * enumerate the logical CPUs.
3012 bzero(&proc, sizeof(proc));
3014 proc.cpu_flags = PROCENTRY_FLAG_EN;
3015 proc.apic_id = ent->apic_id;
3017 for (i = 1; i < arg->logical_cpus; i++) {
3019 processor_entry(&proc, arg->cpu);
3027 mptable_lapic_default(void)
3029 int ap_apicid, bsp_apicid;
3031 mp_naps = 1; /* exclude BSP */
3033 /* Map local apic before the id field is accessed */
3034 lapic_map(DEFAULT_APIC_BASE);
3036 bsp_apicid = APIC_ID(lapic->id);
3037 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3040 mp_set_cpuids(0, bsp_apicid);
3041 /* one and only AP */
3042 mp_set_cpuids(1, ap_apicid);
3048 * ID_TO_CPU(N), APIC ID to logical CPU table
3049 * CPU_TO_ID(N), logical CPU to APIC ID table
3052 mptable_lapic_enumerate(struct lapic_enumerator *e)
3054 struct mptable_pos mpt;
3055 struct mptable_lapic_cbarg1 arg1;
3056 struct mptable_lapic_cbarg2 arg2;
3058 int error, logical_cpus = 0;
3059 vm_offset_t lapic_addr;
3061 if (mptable_use_default) {
3062 mptable_lapic_default();
3066 error = mptable_map(&mpt);
3068 panic("mptable_lapic_enumerate mptable_map failed\n");
3069 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3073 /* Save local apic address */
3074 lapic_addr = (vm_offset_t)cth->apic_address;
3075 KKASSERT(lapic_addr != 0);
3078 * Find out how many CPUs do we have
3080 bzero(&arg1, sizeof(arg1));
3081 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3083 error = mptable_iterate_entries(cth,
3084 mptable_lapic_pass1_callback, &arg1);
3086 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3087 KKASSERT(arg1.cpu_count != 0);
3089 /* See if we need to fixup HT logical CPUs. */
3090 if (arg1.ht_fixup) {
3091 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3093 if (logical_cpus != 0)
3094 arg1.cpu_count *= logical_cpus;
3096 mp_naps = arg1.cpu_count;
3098 /* Qualify the numbers again, after possible HT fixup */
3099 if (mp_naps > MAXCPU) {
3100 kprintf("Warning: only using %d of %d available CPUs!\n",
3106 --mp_naps; /* subtract the BSP */
3109 * Link logical CPU id to local apic id
3111 bzero(&arg2, sizeof(arg2));
3113 arg2.logical_cpus = logical_cpus;
3115 error = mptable_iterate_entries(cth,
3116 mptable_lapic_pass2_callback, &arg2);
3118 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3119 KKASSERT(arg2.found_bsp);
3121 /* Map local apic */
3122 lapic_map(lapic_addr);
3124 mptable_unmap(&mpt);
3127 struct mptable_lapic_probe_cbarg {
3133 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3135 const struct PROCENTRY *ent;
3136 struct mptable_lapic_probe_cbarg *arg = xarg;
3142 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3146 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3147 if (arg->found_bsp) {
3148 kprintf("more than one BSP in base MP table\n");
3157 mptable_lapic_probe(struct lapic_enumerator *e)
3159 struct mptable_pos mpt;
3160 struct mptable_lapic_probe_cbarg arg;
3164 if (mptable_fps_phyaddr == 0)
3167 if (mptable_use_default)
3170 error = mptable_map(&mpt);
3173 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3178 if (cth->apic_address == 0)
3181 bzero(&arg, sizeof(arg));
3182 error = mptable_iterate_entries(cth,
3183 mptable_lapic_probe_callback, &arg);
3185 if (arg.cpu_count == 0) {
3186 kprintf("MP table contains no processor entries\n");
3188 } else if (!arg.found_bsp) {
3189 kprintf("MP table does not contains BSP entry\n");
3194 mptable_unmap(&mpt);
3198 static struct lapic_enumerator mptable_lapic_enumerator = {
3199 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3200 .lapic_probe = mptable_lapic_probe,
3201 .lapic_enumerate = mptable_lapic_enumerate
3205 mptable_lapic_enum_register(void)
3207 lapic_enumerator_register(&mptable_lapic_enumerator);
3209 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3210 mptable_lapic_enum_register, 0);
3213 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3215 const struct IOAPICENTRY *ent;
3216 struct mptable_ioapic *nioapic, *ioapic;
3222 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3225 if (ent->apic_address == 0) {
3226 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3230 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3231 if (ioapic->mio_apic_id == ent->apic_id) {
3232 kprintf("mptable_ioapic_create_list: duplicated "
3233 "apic id %d\n", ioapic->mio_apic_id);
3236 if (ioapic->mio_addr == ent->apic_address) {
3237 kprintf("mptable_ioapic_create_list: overlapped "
3238 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3243 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3244 nioapic->mio_apic_id = ent->apic_id;
3245 nioapic->mio_addr = ent->apic_address;
3248 * Create IOAPIC list in ascending order of APIC ID
3250 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3251 mptable_ioapic_list, mio_link) {
3252 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3253 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3254 ioapic, nioapic, mio_link);
3259 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3265 mptable_ioapic_create_list(void)
3267 struct mptable_ioapic *ioapic;
3268 struct mptable_pos mpt;
3271 if (mptable_fps_phyaddr == 0)
3274 if (mptable_use_default) {
3275 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3276 ioapic->mio_idx = 0;
3277 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3278 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3280 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3284 error = mptable_map(&mpt);
3286 panic("mptable_ioapic_create_list: mptable_map failed\n");
3287 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3289 error = mptable_iterate_entries(mpt.mp_cth,
3290 mptable_ioapic_list_callback, NULL);
3292 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3293 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3294 kfree(ioapic, M_DEVBUF);
3300 * Assign index number for each IOAPIC
3303 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3304 ioapic->mio_idx = idx;
3308 mptable_unmap(&mpt);
3310 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3311 mptable_ioapic_create_list, 0);
3314 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3316 const struct mptable_bus_info *bus_info = xarg;
3317 const struct mptable_ioapic *ioapic;
3318 const struct mptable_bus *bus;
3319 struct mptable_pci_int *pci_int;
3320 const struct INTENTRY *ent;
3321 int pci_pin, pci_dev;
3327 if (ent->int_type != 0)
3330 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3331 if (bus->mb_type == MPTABLE_BUS_PCI &&
3332 bus->mb_id == ent->src_bus_id)
3338 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3339 if (ioapic->mio_apic_id == ent->dst_apic_id)
3342 if (ioapic == NULL) {
3343 kprintf("MPTABLE: warning PCI int dst apic id %d "
3344 "does not exist\n", ent->dst_apic_id);
3348 pci_pin = ent->src_bus_irq & 0x3;
3349 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3351 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3352 if (pci_int->mpci_bus == ent->src_bus_id &&
3353 pci_int->mpci_dev == pci_dev &&
3354 pci_int->mpci_pin == pci_pin) {
3355 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3356 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3357 kprintf("MPTABLE: warning duplicated "
3358 "PCI int entry for "
3359 "bus %d, dev %d, pin %d\n",
3365 kprintf("mptable_pci_int_register: "
3366 "conflict PCI int entry for "
3367 "bus %d, dev %d, pin %d, "
3368 "IOAPIC %d.%d -> %d.%d\n",
3372 pci_int->mpci_ioapic_idx,
3373 pci_int->mpci_ioapic_pin,
3381 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3383 pci_int->mpci_bus = ent->src_bus_id;
3384 pci_int->mpci_dev = pci_dev;
3385 pci_int->mpci_pin = pci_pin;
3386 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3387 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3389 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3395 mptable_pci_int_register(void)
3397 struct mptable_bus_info bus_info;
3398 const struct mptable_bus *bus;
3399 struct mptable_pci_int *pci_int;
3400 struct mptable_pos mpt;
3401 int error, force_pci0, npcibus;
3404 if (mptable_fps_phyaddr == 0)
3407 if (mptable_use_default)
3410 if (TAILQ_EMPTY(&mptable_ioapic_list))
3413 error = mptable_map(&mpt);
3415 panic("mptable_pci_int_register: mptable_map failed\n");
3416 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3420 mptable_bus_info_alloc(cth, &bus_info);
3421 if (TAILQ_EMPTY(&bus_info.mbi_list))
3425 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3426 if (bus->mb_type == MPTABLE_BUS_PCI)
3430 mptable_bus_info_free(&bus_info);
3432 } else if (npcibus == 1) {
3436 error = mptable_iterate_entries(cth,
3437 mptable_pci_int_callback, &bus_info);
3439 mptable_bus_info_free(&bus_info);
3442 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3443 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3444 kfree(pci_int, M_DEVBUF);
3450 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3451 pci_int->mpci_bus = 0;
3454 mptable_unmap(&mpt);
3456 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3457 mptable_pci_int_register, 0);
3459 struct mptable_ioapic_probe_cbarg {
3460 const struct mptable_bus_info *bus_info;
3464 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3466 struct mptable_ioapic_probe_cbarg *arg = xarg;
3467 const struct mptable_ioapic *ioapic;
3468 const struct mptable_bus *bus;
3469 const struct INTENTRY *ent;
3475 if (ent->int_type != 0)
3478 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3479 if (bus->mb_type == MPTABLE_BUS_ISA &&
3480 bus->mb_id == ent->src_bus_id)
3486 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3487 if (ioapic->mio_apic_id == ent->dst_apic_id)
3490 if (ioapic == NULL) {
3491 kprintf("MPTABLE: warning ISA int dst apic id %d "
3492 "does not exist\n", ent->dst_apic_id);
3496 /* XXX magic number */
3497 if (ent->src_bus_irq >= 16) {
3498 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3506 mptable_ioapic_probe(struct ioapic_enumerator *e)
3508 struct mptable_ioapic_probe_cbarg arg;
3509 struct mptable_bus_info bus_info;
3510 struct mptable_pos mpt;
3514 if (mptable_fps_phyaddr == 0)
3517 if (mptable_use_default)
3520 if (TAILQ_EMPTY(&mptable_ioapic_list))
3523 error = mptable_map(&mpt);
3525 panic("mptable_ioapic_probe: mptable_map failed\n");
3526 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3530 mptable_bus_info_alloc(cth, &bus_info);
3532 bzero(&arg, sizeof(arg));
3533 arg.bus_info = &bus_info;
3535 error = mptable_iterate_entries(cth,
3536 mptable_ioapic_probe_callback, &arg);
3538 mptable_bus_info_free(&bus_info);
3539 mptable_unmap(&mpt);
3544 struct mptable_ioapic_int_cbarg {
3545 const struct mptable_bus_info *bus_info;
3550 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3552 struct mptable_ioapic_int_cbarg *arg = xarg;
3553 const struct mptable_ioapic *ioapic;
3554 const struct mptable_bus *bus;
3555 const struct INTENTRY *ent;
3563 if (ent->int_type != 0)
3566 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3567 if (bus->mb_type == MPTABLE_BUS_ISA &&
3568 bus->mb_id == ent->src_bus_id)
3574 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3575 if (ioapic->mio_apic_id == ent->dst_apic_id)
3578 if (ioapic == NULL) {
3579 kprintf("MPTABLE: warning ISA int dst apic id %d "
3580 "does not exist\n", ent->dst_apic_id);
3584 if (!ioapic_use_old) {
3587 if (ent->dst_apic_int >= ioapic->mio_npin) {
3588 panic("mptable_ioapic_enumerate: invalid I/O APIC "
3589 "pin %d, should be < %d",
3590 ent->dst_apic_int, ioapic->mio_npin);
3592 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
3594 if (ent->src_bus_irq != gsi) {
3596 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3597 ent->src_bus_irq, gsi);
3599 ioapic_intsrc(ent->src_bus_irq, gsi);
3602 /* XXX rough estimation */
3603 if (ent->src_bus_irq != ent->dst_apic_int) {
3605 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3606 ent->src_bus_irq, ent->dst_apic_int);
3614 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3616 struct mptable_bus_info bus_info;
3617 struct mptable_ioapic *ioapic;
3618 struct mptable_pos mpt;
3622 KKASSERT(mptable_fps_phyaddr != 0);
3623 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3625 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3626 if (!ioapic_use_old) {
3627 const struct mptable_ioapic *prev_ioapic;
3631 addr = ioapic_map(ioapic->mio_addr);
3633 ver = ioapic_read(addr, IOAPIC_VER);
3634 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3635 >> MAXREDIRSHIFT) + 1;
3637 prev_ioapic = TAILQ_PREV(ioapic,
3638 mptable_ioapic_list, mio_link);
3639 if (prev_ioapic == NULL) {
3640 ioapic->mio_gsi_base = 0;
3642 ioapic->mio_gsi_base =
3643 prev_ioapic->mio_gsi_base +
3644 prev_ioapic->mio_npin;
3646 ioapic_add(addr, ioapic->mio_gsi_base,
3650 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3651 "apic id %d, idx %d, gsi base %d, npin %d\n",
3653 ioapic->mio_apic_id,
3655 ioapic->mio_gsi_base,
3660 if (mptable_use_default) {
3662 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3663 ioapic_intsrc(0, 2);
3667 error = mptable_map(&mpt);
3669 panic("mptable_ioapic_probe: mptable_map failed\n");
3670 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3674 mptable_bus_info_alloc(cth, &bus_info);
3676 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3678 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3679 ioapic_intsrc(0, 2);
3681 struct mptable_ioapic_int_cbarg arg;
3683 bzero(&arg, sizeof(arg));
3684 arg.bus_info = &bus_info;
3686 error = mptable_iterate_entries(cth,
3687 mptable_ioapic_int_callback, &arg);
3689 panic("mptable_ioapic_int failed\n");
3691 if (arg.ioapic_nint == 0) {
3693 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3696 ioapic_intsrc(0, 2);
3700 mptable_bus_info_free(&bus_info);
3702 mptable_unmap(&mpt);
3705 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3706 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3707 .ioapic_probe = mptable_ioapic_probe,
3708 .ioapic_enumerate = mptable_ioapic_enumerate
3712 mptable_ioapic_enum_register(void)
3714 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3716 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3717 mptable_ioapic_enum_register, 0);