sys/dev/drm/radeon/atombios.h

   1 /*
   2  * Copyright 2006-2007 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * $FreeBSD: head/sys/dev/drm2/radeon/atombios.h 254885 2013-08-25 19:37:15Z dumbbell $
  23  */
  24
  25
  26 /****************************************************************************/
  27 /*Portion I: Definitions  shared between VBIOS and Driver                   */
  28 /****************************************************************************/
  29
  30
  31 #ifndef _ATOMBIOS_H
  32 #define _ATOMBIOS_H
  33
  34 #define ATOM_VERSION_MAJOR                   0x00020000
  35 #define ATOM_VERSION_MINOR                   0x00000002
  36
  37 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  38
  39 /* Endianness should be specified before inclusion,
  40  * default to little endian
  41  */
  42 #ifndef ATOM_BIG_ENDIAN
  43 #error Endian not specified
  44 #endif
  45
  46 #ifdef _H2INC
  47   #ifndef ULONG
  48     typedef unsigned long ULONG;
  49   #endif
  50
  51   #ifndef UCHAR
  52     typedef unsigned char UCHAR;
  53   #endif
  54
  55   #ifndef USHORT
  56     typedef unsigned short USHORT;
  57   #endif
  58 #endif
  59
  60 #define ATOM_DAC_A            0
  61 #define ATOM_DAC_B            1
  62 #define ATOM_EXT_DAC          2
  63
  64 #define ATOM_CRTC1            0
  65 #define ATOM_CRTC2            1
  66 #define ATOM_CRTC3            2
  67 #define ATOM_CRTC4            3
  68 #define ATOM_CRTC5            4
  69 #define ATOM_CRTC6            5
  70 #define ATOM_CRTC_INVALID     0xFF
  71
  72 #define ATOM_DIGA             0
  73 #define ATOM_DIGB             1
  74
  75 #define ATOM_PPLL1            0
  76 #define ATOM_PPLL2            1
  77 #define ATOM_DCPLL            2
  78 #define ATOM_PPLL0            2
  79 #define ATOM_EXT_PLL1         8
  80 #define ATOM_EXT_PLL2         9
  81 #define ATOM_EXT_CLOCK        10
  82 #define ATOM_PPLL_INVALID     0xFF
  83
  84 #define ENCODER_REFCLK_SRC_P1PLL       0
  85 #define ENCODER_REFCLK_SRC_P2PLL       1
  86 #define ENCODER_REFCLK_SRC_DCPLL       2
  87 #define ENCODER_REFCLK_SRC_EXTCLK      3
  88 #define ENCODER_REFCLK_SRC_INVALID     0xFF
  89
  90 #define ATOM_SCALER1          0
  91 #define ATOM_SCALER2          1
  92
  93 #define ATOM_SCALER_DISABLE   0
  94 #define ATOM_SCALER_CENTER    1
  95 #define ATOM_SCALER_EXPANSION 2
  96 #define ATOM_SCALER_MULTI_EX  3
  97
  98 #define ATOM_DISABLE          0
  99 #define ATOM_ENABLE           1
 100 #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
 101 #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
 102 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
 103 #define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
 104 #define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
 105 #define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
 106 #define ATOM_INIT                                                 (ATOM_DISABLE+7)
 107 #define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
 108
 109 #define ATOM_BLANKING         1
 110 #define ATOM_BLANKING_OFF     0
 111
 112 #define ATOM_CURSOR1          0
 113 #define ATOM_CURSOR2          1
 114
 115 #define ATOM_ICON1            0
 116 #define ATOM_ICON2            1
 117
 118 #define ATOM_CRT1             0
 119 #define ATOM_CRT2             1
 120
 121 #define ATOM_TV_NTSC          1
 122 #define ATOM_TV_NTSCJ         2
 123 #define ATOM_TV_PAL           3
 124 #define ATOM_TV_PALM          4
 125 #define ATOM_TV_PALCN         5
 126 #define ATOM_TV_PALN          6
 127 #define ATOM_TV_PAL60         7
 128 #define ATOM_TV_SECAM         8
 129 #define ATOM_TV_CV            16
 130
 131 #define ATOM_DAC1_PS2         1
 132 #define ATOM_DAC1_CV          2
 133 #define ATOM_DAC1_NTSC        3
 134 #define ATOM_DAC1_PAL         4
 135
 136 #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
 137 #define ATOM_DAC2_CV          ATOM_DAC1_CV
 138 #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
 139 #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
 140
 141 #define ATOM_PM_ON            0
 142 #define ATOM_PM_STANDBY       1
 143 #define ATOM_PM_SUSPEND       2
 144 #define ATOM_PM_OFF           3
 145
 146 /* Bit0:{=0:single, =1:dual},
 147    Bit1 {=0:666RGB, =1:888RGB},
 148    Bit2:3:{Grey level}
 149    Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
 150
 151 #define ATOM_PANEL_MISC_DUAL               0x00000001
 152 #define ATOM_PANEL_MISC_888RGB             0x00000002
 153 #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
 154 #define ATOM_PANEL_MISC_FPDI               0x00000010
 155 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
 156 #define ATOM_PANEL_MISC_SPATIAL            0x00000020
 157 #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
 158 #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
 159
 160
 161 #define MEMTYPE_DDR1              "DDR1"
 162 #define MEMTYPE_DDR2              "DDR2"
 163 #define MEMTYPE_DDR3              "DDR3"
 164 #define MEMTYPE_DDR4              "DDR4"
 165
 166 #define ASIC_BUS_TYPE_PCI         "PCI"
 167 #define ASIC_BUS_TYPE_AGP         "AGP"
 168 #define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
 169
 170 /* Maximum size of that FireGL flag string */
 171
 172 #define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
 173 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
 174
 175 #define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
 176 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
 177
 178 #define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
 179 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
 180
 181 #define HW_ASSISTED_I2C_STATUS_FAILURE          2
 182 #define HW_ASSISTED_I2C_STATUS_SUCCESS          1
 183
 184 #pragma pack(1)                                       /* BIOS data must use byte aligment */
 185
 186 /*  Define offset to location of ROM header. */
 187
 188 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
 189 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
 190
 191 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
 192 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20    /* including the terminator 0x0! */
 193 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
 194 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
 195
 196 /* Common header for all ROM Data tables.
 197   Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
 198   And the pointer actually points to this header. */
 199
 200 typedef struct _ATOM_COMMON_TABLE_HEADER
 201 {
 202   USHORT usStructureSize;
 203   UCHAR  ucTableFormatRevision;   /*Change it when the Parser is not backward compatible */
 204   UCHAR  ucTableContentRevision;  /*Change it only when the table needs to change but the firmware */
 205                                   /*Image can't be updated, while Driver needs to carry the new table! */
 206 }ATOM_COMMON_TABLE_HEADER;
 207
 208 /****************************************************************************/
 209 // Structure stores the ROM header.
 210 /****************************************************************************/
 211 typedef struct _ATOM_ROM_HEADER
 212 {
 213   ATOM_COMMON_TABLE_HEADER              sHeader;
 214   UCHAR  uaFirmWareSignature[4];    /*Signature to distinguish between Atombios and non-atombios,
 215                                       atombios should init it as "ATOM", don't change the position */
 216   USHORT usBiosRuntimeSegmentAddress;
 217   USHORT usProtectedModeInfoOffset;
 218   USHORT usConfigFilenameOffset;
 219   USHORT usCRC_BlockOffset;
 220   USHORT usBIOS_BootupMessageOffset;
 221   USHORT usInt10Offset;
 222   USHORT usPciBusDevInitCode;
 223   USHORT usIoBaseAddress;
 224   USHORT usSubsystemVendorID;
 225   USHORT usSubsystemID;
 226   USHORT usPCI_InfoOffset;
 227   USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */
 228   USHORT usMasterDataTableOffset;   /*Offset for SW to get all data table offsets, Don't change the position */
 229   UCHAR  ucExtendedFunctionCode;
 230   UCHAR  ucReserved;
 231 }ATOM_ROM_HEADER;
 232
 233 /*==============================Command Table Portion==================================== */
 234
 235 #ifdef  UEFI_BUILD
 236         #define UTEMP   USHORT
 237         #define USHORT  void*
 238 #endif
 239
 240 /****************************************************************************/
 241 // Structures used in Command.mtb
 242 /****************************************************************************/
 243 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
 244   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
 245   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
 246   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 247   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
 248   USHORT DIGxEncoderControl;                                                                             //Only used by Bios
 249   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 250   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
 251   USHORT MemoryParamAdjust;                                                                              //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
 252   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
 253   USHORT GPIOPinControl;                                                                                                 //Atomic Table,  only used by Bios
 254   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
 255   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
 256   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2
 257   USHORT EnableDispPowerGating;                  //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 258   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 259   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 260   USHORT MemoryPLLInit;                          //Atomic Table,  used only by Bios
 261   USHORT AdjustDisplayPll;                                                                                       //Atomic Table,  used by various SW componentes.
 262   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 263   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
 264   USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios
 265   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2
 266   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
 267   USHORT HW_Misc_Operation;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 268   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 269   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 270   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
 271   USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
 272   USHORT GetConditionalGoldenSetting;            //Only used by Bios
 273   USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
 274   USHORT PatchMCSetting;                         //only used by BIOS
 275   USHORT MC_SEQ_Control;                         //only used by BIOS
 276   USHORT TV1OutputControl;                       //Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
 277   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
 278   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
 279   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
 280   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
 281   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
 282   USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
 283   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 284   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
 285   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
 286   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 287   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
 288   USHORT UpdateCRTC_DoubleBufferRegisters;                       //Atomic Table,  used only by Bios
 289   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
 290   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
 291   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 292   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 293   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
 294   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
 295   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 296   USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
 297   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios
 298   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
 299   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
 300   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
 301   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
 302   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
 303   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 304   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
 305   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
 306   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
 307   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 308   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
 309   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
 310   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 311   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
 312   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 313   USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 314   USHORT ComputeMemoryClockParam;                //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
 315   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 316   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 317   USHORT GetDispObjectInfo;                      //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
 318   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 319   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 320   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
 321   USHORT DIG2TransmitterControl;                       //Atomic Table,directly used by various SW components,latest version 1.1
 322   USHORT ProcessAuxChannelTransaction;                                   //Function Table,only used by Bios
 323   USHORT DPEncoderService;                                                                                       //Function Table,only used by Bios
 324   USHORT GetVoltageInfo;                         //Function Table,only used by Bios since SI
 325 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
 326
 327 // For backward compatible
 328 #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
 329 #define DPTranslatorControl                      DIG2EncoderControl
 330 #define UNIPHYTransmitterControl                             DIG1TransmitterControl
 331 #define LVTMATransmitterControl                              DIG2TransmitterControl
 332 #define SetCRTC_DPM_State                        GetConditionalGoldenSetting
 333 #define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
 334 #define HPDInterruptService                      ReadHWAssistedI2CStatus
 335 #define EnableVGA_Access                         GetSCLKOverMCLKRatio
 336 #define EnableYUV                                GetDispObjectInfo
 337 #define DynamicClockGating                       EnableDispPowerGating
 338 #define SetupHWAssistedI2CStatus                 ComputeMemoryClockParam
 339
 340 #define TMDSAEncoderControl                      PatchMCSetting
 341 #define LVDSEncoderControl                       MC_SEQ_Control
 342 #define LCD1OutputControl                        HW_Misc_Operation
 343
 344
 345 typedef struct _ATOM_MASTER_COMMAND_TABLE
 346 {
 347   ATOM_COMMON_TABLE_HEADER           sHeader;
 348   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
 349 }ATOM_MASTER_COMMAND_TABLE;
 350
 351 /****************************************************************************/
 352 // Structures used in every command table
 353 /****************************************************************************/
 354 typedef struct _ATOM_TABLE_ATTRIBUTE
 355 {
 356 #if ATOM_BIG_ENDIAN
 357   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 358   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 359   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 360 #else
 361   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 362   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 363   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 364 #endif
 365 }ATOM_TABLE_ATTRIBUTE;
 366
 367 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
 368 {
 369   ATOM_TABLE_ATTRIBUTE sbfAccess;
 370   USHORT               susAccess;
 371 }ATOM_TABLE_ATTRIBUTE_ACCESS;
 372
 373 /****************************************************************************/
 374 // Common header for all command tables.
 375 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
 376 // And the pointer actually points to this header.
 377 /****************************************************************************/
 378 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 379 {
 380   ATOM_COMMON_TABLE_HEADER CommonHeader;
 381   ATOM_TABLE_ATTRIBUTE     TableAttribute;
 382 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
 383
 384 /****************************************************************************/
 385 // Structures used by ComputeMemoryEnginePLLTable
 386 /****************************************************************************/
 387 #define COMPUTE_MEMORY_PLL_PARAM        1
 388 #define COMPUTE_ENGINE_PLL_PARAM        2
 389 #define ADJUST_MC_SETTING_PARAM         3
 390
 391 /****************************************************************************/
 392 // Structures used by AdjustMemoryControllerTable
 393 /****************************************************************************/
 394 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
 395 {
 396 #if ATOM_BIG_ENDIAN
 397   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
 398   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 399   ULONG ulClockFreq:24;
 400 #else
 401   ULONG ulClockFreq:24;
 402   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 403   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
 404 #endif
 405 }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
 406 #define POINTER_RETURN_FLAG             0x80
 407
 408 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 409 {
 410   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
 411   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine
 412   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
 413   UCHAR   ucFbDiv;        //return value
 414   UCHAR   ucPostDiv;      //return value
 415 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
 416
 417 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 418 {
 419   ULONG   ulClock;        //When return, [23:0] return real clock
 420   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
 421   USHORT  usFbDiv;                  //return Feedback value to be written to register
 422   UCHAR   ucPostDiv;      //return post div to be written to register
 423 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
 424 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 425
 426
 427 #define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
 428 #define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 429 #define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 430 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 431 #define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 432 #define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 433 #define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
 434
 435 #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 436 #define b3USE_MEMORY_SELF_REFRESH                 0x02       //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 437 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 438 #define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 439 #define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 440
 441 typedef struct _ATOM_COMPUTE_CLOCK_FREQ
 442 {
 443 #if ATOM_BIG_ENDIAN
 444   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 445   ULONG ulClockFreq:24;                       // in unit of 10kHz
 446 #else
 447   ULONG ulClockFreq:24;                       // in unit of 10kHz
 448   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 449 #endif
 450 }ATOM_COMPUTE_CLOCK_FREQ;
 451
 452 typedef struct _ATOM_S_MPLL_FB_DIVIDER
 453 {
 454   USHORT usFbDivFrac;
 455   USHORT usFbDiv;
 456 }ATOM_S_MPLL_FB_DIVIDER;
 457
 458 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
 459 {
 460   union
 461   {
 462     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 463     ULONG ulClockParams;                      //ULONG access for BE
 464     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 465   };
 466   UCHAR   ucRefDiv;                           //Output Parameter
 467   UCHAR   ucPostDiv;                          //Output Parameter
 468   UCHAR   ucCntlFlag;                         //Output Parameter
 469   UCHAR   ucReserved;
 470 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
 471
 472 // ucCntlFlag
 473 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
 474 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
 475 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
 476 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                                                8
 477
 478
 479 // V4 are only used for APU which PLL outside GPU
 480 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
 481 {
 482 #if ATOM_BIG_ENDIAN
 483   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
 484   ULONG  ulClock:24;         //Input= target clock, output = actual clock
 485 #else
 486   ULONG  ulClock:24;         //Input= target clock, output = actual clock
 487   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
 488 #endif
 489 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
 490
 491 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
 492 {
 493   union
 494   {
 495     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 496     ULONG ulClockParams;                      //ULONG access for BE
 497     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 498   };
 499   UCHAR   ucRefDiv;                           //Output Parameter
 500   UCHAR   ucPostDiv;                          //Output Parameter
 501   union
 502   {
 503     UCHAR   ucCntlFlag;                       //Output Flags
 504     UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
 505   };
 506   UCHAR   ucReserved;
 507 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
 508
 509 // ucInputFlag
 510 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
 511
 512 // use for ComputeMemoryClockParamTable
 513 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
 514 {
 515   union
 516   {
 517     ULONG  ulClock;
 518     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output:UPPER_WORD=FB_DIV_INTEGER,  LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
 519   };
 520   UCHAR   ucDllSpeed;                         //Output
 521   UCHAR   ucPostDiv;                          //Output
 522   union{
 523     UCHAR   ucInputFlag;                      //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
 524     UCHAR   ucPllCntlFlag;                    //Output:
 525   };
 526   UCHAR   ucBWCntl;
 527 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
 528
 529 // definition of ucInputFlag
 530 #define MPLL_INPUT_FLAG_STROBE_MODE_EN          0x01
 531 // definition of ucPllCntlFlag
 532 #define MPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
 533 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL            0x04
 534 #define MPLL_CNTL_FLAG_QDR_ENABLE               0x08
 535 #define MPLL_CNTL_FLAG_AD_HALF_RATE             0x10
 536
 537 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
 538 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
 539
 540 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
 541 {
 542   ATOM_COMPUTE_CLOCK_FREQ ulClock;
 543   ULONG ulReserved[2];
 544 }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
 545
 546 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
 547 {
 548   ATOM_COMPUTE_CLOCK_FREQ ulClock;
 549   ULONG ulMemoryClock;
 550   ULONG ulReserved;
 551 }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
 552
 553 /****************************************************************************/
 554 // Structures used by SetEngineClockTable
 555 /****************************************************************************/
 556 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
 557 {
 558   ULONG ulTargetEngineClock;          //In 10Khz unit
 559 }SET_ENGINE_CLOCK_PARAMETERS;
 560
 561 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
 562 {
 563   ULONG ulTargetEngineClock;          //In 10Khz unit
 564   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 565 }SET_ENGINE_CLOCK_PS_ALLOCATION;
 566
 567 /****************************************************************************/
 568 // Structures used by SetMemoryClockTable
 569 /****************************************************************************/
 570 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
 571 {
 572   ULONG ulTargetMemoryClock;          //In 10Khz unit
 573 }SET_MEMORY_CLOCK_PARAMETERS;
 574
 575 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
 576 {
 577   ULONG ulTargetMemoryClock;          //In 10Khz unit
 578   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 579 }SET_MEMORY_CLOCK_PS_ALLOCATION;
 580
 581 /****************************************************************************/
 582 // Structures used by ASIC_Init.ctb
 583 /****************************************************************************/
 584 typedef struct _ASIC_INIT_PARAMETERS
 585 {
 586   ULONG ulDefaultEngineClock;         //In 10Khz unit
 587   ULONG ulDefaultMemoryClock;         //In 10Khz unit
 588 }ASIC_INIT_PARAMETERS;
 589
 590 typedef struct _ASIC_INIT_PS_ALLOCATION
 591 {
 592   ASIC_INIT_PARAMETERS sASICInitClocks;
 593   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
 594 }ASIC_INIT_PS_ALLOCATION;
 595
 596 /****************************************************************************/
 597 // Structure used by DynamicClockGatingTable.ctb
 598 /****************************************************************************/
 599 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
 600 {
 601   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 602   UCHAR ucPadding[3];
 603 }DYNAMIC_CLOCK_GATING_PARAMETERS;
 604 #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
 605
 606 /****************************************************************************/
 607 // Structure used by EnableDispPowerGatingTable.ctb
 608 /****************************************************************************/
 609 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
 610 {
 611   UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
 612   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 613   UCHAR ucPadding[2];
 614 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
 615
 616 /****************************************************************************/
 617 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
 618 /****************************************************************************/
 619 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 620 {
 621   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 622   UCHAR ucPadding[3];
 623 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
 624 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 625
 626 /****************************************************************************/
 627 // Structures used by DAC_LoadDetectionTable.ctb
 628 /****************************************************************************/
 629 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
 630 {
 631   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
 632   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
 633   UCHAR  ucMisc;                                                                                        //Valid only when table revision =1.3 and above
 634 }DAC_LOAD_DETECTION_PARAMETERS;
 635
 636 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
 637 #define DAC_LOAD_MISC_YPrPb                                             0x01
 638
 639 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
 640 {
 641   DAC_LOAD_DETECTION_PARAMETERS            sDacload;
 642   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
 643 }DAC_LOAD_DETECTION_PS_ALLOCATION;
 644
 645 /****************************************************************************/
 646 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
 647 /****************************************************************************/
 648 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
 649 {
 650   USHORT usPixelClock;                // in 10KHz; for bios convenient
 651   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
 652   UCHAR  ucAction;                    // 0: turn off encoder
 653                                       // 1: setup and turn on encoder
 654                                       // 7: ATOM_ENCODER_INIT Initialize DAC
 655 }DAC_ENCODER_CONTROL_PARAMETERS;
 656
 657 #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
 658
 659 /****************************************************************************/
 660 // Structures used by DIG1EncoderControlTable
 661 //                    DIG2EncoderControlTable
 662 //                    ExternalEncoderControlTable
 663 /****************************************************************************/
 664 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
 665 {
 666   USHORT usPixelClock;          // in 10KHz; for bios convenient
 667   UCHAR  ucConfig;
 668                             // [2] Link Select:
 669                             // =0: PHY linkA if bfLane<3
 670                             // =1: PHY linkB if bfLanes<3
 671                             // =0: PHY linkA+B if bfLanes=3
 672                             // [3] Transmitter Sel
 673                             // =0: UNIPHY or PCIEPHY
 674                             // =1: LVTMA
 675   UCHAR ucAction;           // =0: turn off encoder
 676                             // =1: turn on encoder
 677   UCHAR ucEncoderMode;
 678                             // =0: DP   encoder
 679                             // =1: LVDS encoder
 680                             // =2: DVI  encoder
 681                             // =3: HDMI encoder
 682                             // =4: SDVO encoder
 683   UCHAR ucLaneNum;          // how many lanes to enable
 684   UCHAR ucReserved[2];
 685 }DIG_ENCODER_CONTROL_PARAMETERS;
 686 #define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
 687 #define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
 688
 689 //ucConfig
 690 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
 691 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
 692 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
 693 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ          0x02
 694 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
 695 #define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
 696 #define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
 697 #define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
 698 #define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
 699 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
 700 #define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
 701 #define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
 702 #define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
 703 #define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
 704 #define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80                  // VBIOS Internal use, outside SW should set this bit=0
 705 // ucAction
 706 // ATOM_ENABLE:  Enable Encoder
 707 // ATOM_DISABLE: Disable Encoder
 708
 709 //ucEncoderMode
 710 #define ATOM_ENCODER_MODE_DP                                                                                    0
 711 #define ATOM_ENCODER_MODE_LVDS                                                                          1
 712 #define ATOM_ENCODER_MODE_DVI                                                                                   2
 713 #define ATOM_ENCODER_MODE_HDMI                                                                          3
 714 #define ATOM_ENCODER_MODE_SDVO                                                                          4
 715 #define ATOM_ENCODER_MODE_DP_AUDIO                5
 716 #define ATOM_ENCODER_MODE_TV                                                                                    13
 717 #define ATOM_ENCODER_MODE_CV                                                                                    14
 718 #define ATOM_ENCODER_MODE_CRT                                                                                   15
 719 #define ATOM_ENCODER_MODE_DVO                                                                                   16
 720 #define ATOM_ENCODER_MODE_DP_SST                  ATOM_ENCODER_MODE_DP    // For DP1.2
 721 #define ATOM_ENCODER_MODE_DP_MST                  5                       // For DP1.2
 722
 723 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
 724 {
 725 #if ATOM_BIG_ENDIAN
 726     UCHAR ucReserved1:2;
 727     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 728     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 729     UCHAR ucReserved:1;
 730     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 731 #else
 732     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 733     UCHAR ucReserved:1;
 734     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 735     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 736     UCHAR ucReserved1:2;
 737 #endif
 738 }ATOM_DIG_ENCODER_CONFIG_V2;
 739
 740
 741 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
 742 {
 743   USHORT usPixelClock;      // in 10KHz; for bios convenient
 744   ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
 745   UCHAR ucAction;
 746   UCHAR ucEncoderMode;
 747                             // =0: DP   encoder
 748                             // =1: LVDS encoder
 749                             // =2: DVI  encoder
 750                             // =3: HDMI encoder
 751                             // =4: SDVO encoder
 752   UCHAR ucLaneNum;          // how many lanes to enable
 753   UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
 754   UCHAR ucReserved;
 755 }DIG_ENCODER_CONTROL_PARAMETERS_V2;
 756
 757 //ucConfig
 758 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                          0x01
 759 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                 0x00
 760 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                 0x01
 761 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                              0x04
 762 #define ATOM_ENCODER_CONFIG_V2_LINKA                                                              0x00
 763 #define ATOM_ENCODER_CONFIG_V2_LINKB                                                              0x04
 764 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK       0x18
 765 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                 0x00
 766 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                 0x08
 767 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                 0x10
 768
 769 // ucAction:
 770 // ATOM_DISABLE
 771 // ATOM_ENABLE
 772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
 773 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
 774 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
 775 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
 776 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
 777 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
 778 #define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
 779 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
 780 #define ATOM_ENCODER_CMD_SETUP                        0x0f
 781 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10
 782
 783 // ucStatus
 784 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
 785 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
 786
 787 //ucTableFormatRevision=1
 788 //ucTableContentRevision=3
 789 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 790 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
 791 {
 792 #if ATOM_BIG_ENDIAN
 793     UCHAR ucReserved1:1;
 794     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 795     UCHAR ucReserved:3;
 796     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 797 #else
 798     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 799     UCHAR ucReserved:3;
 800     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 801     UCHAR ucReserved1:1;
 802 #endif
 803 }ATOM_DIG_ENCODER_CONFIG_V3;
 804
 805 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK                          0x03
 806 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ                 0x00
 807 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ                 0x01
 808 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                                        0x70
 809 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER                                       0x00
 810 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER                                       0x10
 811 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER                                       0x20
 812 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER                                       0x30
 813 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER                                       0x40
 814 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER                                       0x50
 815
 816 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
 817 {
 818   USHORT usPixelClock;      // in 10KHz; for bios convenient
 819   ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
 820   UCHAR ucAction;
 821   union {
 822     UCHAR ucEncoderMode;
 823                             // =0: DP   encoder
 824                             // =1: LVDS encoder
 825                             // =2: DVI  encoder
 826                             // =3: HDMI encoder
 827                             // =4: SDVO encoder
 828                             // =5: DP audio
 829     UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 830                             // =0:     external DP
 831                             // =1:     internal DP2
 832                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
 833   };
 834   UCHAR ucLaneNum;          // how many lanes to enable
 835   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 836   UCHAR ucReserved;
 837 }DIG_ENCODER_CONTROL_PARAMETERS_V3;
 838
 839 //ucTableFormatRevision=1
 840 //ucTableContentRevision=4
 841 // start from NI
 842 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 843 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
 844 {
 845 #if ATOM_BIG_ENDIAN
 846     UCHAR ucReserved1:1;
 847     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 848     UCHAR ucReserved:2;
 849     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 850 #else
 851     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 852     UCHAR ucReserved:2;
 853     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 854     UCHAR ucReserved1:1;
 855 #endif
 856 }ATOM_DIG_ENCODER_CONFIG_V4;
 857
 858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK                          0x03
 859 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ                 0x00
 860 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ                 0x01
 861 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ                 0x02
 862 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ                 0x03
 863 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL                                        0x70
 864 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER                                       0x00
 865 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER                                       0x10
 866 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER                                       0x20
 867 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER                                       0x30
 868 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER                                       0x40
 869 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER                                       0x50
 870 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER                                       0x60
 871
 872 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
 873 {
 874   USHORT usPixelClock;      // in 10KHz; for bios convenient
 875   union{
 876   ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
 877   UCHAR ucConfig;
 878   };
 879   UCHAR ucAction;
 880   union {
 881     UCHAR ucEncoderMode;
 882                             // =0: DP   encoder
 883                             // =1: LVDS encoder
 884                             // =2: DVI  encoder
 885                             // =3: HDMI encoder
 886                             // =4: SDVO encoder
 887                             // =5: DP audio
 888     UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 889                             // =0:     external DP
 890                             // =1:     internal DP2
 891                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
 892   };
 893   UCHAR ucLaneNum;          // how many lanes to enable
 894   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 895   UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
 896 }DIG_ENCODER_CONTROL_PARAMETERS_V4;
 897
 898 // define ucBitPerColor:
 899 #define PANEL_BPC_UNDEFINE                               0x00
 900 #define PANEL_6BIT_PER_COLOR                             0x01
 901 #define PANEL_8BIT_PER_COLOR                             0x02
 902 #define PANEL_10BIT_PER_COLOR                            0x03
 903 #define PANEL_12BIT_PER_COLOR                            0x04
 904 #define PANEL_16BIT_PER_COLOR                            0x05
 905
 906 //define ucPanelMode
 907 #define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
 908 #define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
 909 #define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
 910
 911 /****************************************************************************/
 912 // Structures used by UNIPHYTransmitterControlTable
 913 //                    LVTMATransmitterControlTable
 914 //                    DVOOutputControlTable
 915 /****************************************************************************/
 916 typedef struct _ATOM_DP_VS_MODE
 917 {
 918   UCHAR ucLaneSel;
 919   UCHAR ucLaneSet;
 920 }ATOM_DP_VS_MODE;
 921
 922 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
 923 {
 924         union
 925         {
 926   USHORT usPixelClock;          // in 10KHz; for bios convenient
 927         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
 928   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
 929         };
 930   UCHAR ucConfig;
 931                                                                                                         // [0]=0: 4 lane Link,
 932                                                                                                         //    =1: 8 lane Link ( Dual Links TMDS )
 933                           // [1]=0: InCoherent mode
 934                                                                                                         //    =1: Coherent Mode
 935                                                                                                         // [2] Link Select:
 936                                                                                                 // =0: PHY linkA   if bfLane<3
 937                                                                                                         // =1: PHY linkB   if bfLanes<3
 938                                                                                                 // =0: PHY linkA+B if bfLanes=3
 939                           // [5:4]PCIE lane Sel
 940                           // =0: lane 0~3 or 0~7
 941                           // =1: lane 4~7
 942                           // =2: lane 8~11 or 8~15
 943                           // =3: lane 12~15
 944         UCHAR ucAction;                           // =0: turn off encoder
 945                                 // =1: turn on encoder
 946   UCHAR ucReserved[4];
 947 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
 948
 949 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS
 950
 951 //ucInitInfo
 952 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff
 953
 954 //ucConfig
 955 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
 956 #define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
 957 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
 958 #define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
 959 #define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
 960 #define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00
 961 #define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
 962
 963 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 964 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 965 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
 966
 967 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
 968 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
 969 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
 970 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
 971 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
 972 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
 973 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
 974 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
 975 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
 976 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
 977 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
 978
 979 //ucAction
 980 #define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
 981 #define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
 982 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
 983 #define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
 984 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
 985 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
 986 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
 987 #define ATOM_TRANSMITTER_ACTION_INIT                                                   7
 988 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
 989 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
 990 #define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
 991 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
 992 #define ATOM_TRANSMITTER_ACTION_POWER_ON               12
 993 #define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
 994
 995 // Following are used for DigTransmitterControlTable ver1.2
 996 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
 997 {
 998 #if ATOM_BIG_ENDIAN
 999   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1000                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1001                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1002   UCHAR ucReserved:1;
1003   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
1004   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1005   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1006                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1007
1008   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1009   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1010 #else
1011   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1012   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1013   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1014                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1015   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1016   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
1017   UCHAR ucReserved:1;
1018   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1019                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1020                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1021 #endif
1022 }ATOM_DIG_TRANSMITTER_CONFIG_V2;
1023
1024 //ucConfig
1025 //Bit0
1026 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                  0x01
1027
1028 //Bit1
1029 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                       0x02
1030
1031 //Bit2
1032 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                        0x04
1033 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                    0x00
1034 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                            0x04
1035
1036 // Bit3
1037 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK             0x08
1038 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                   0x00                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1039 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                   0x08                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1040
1041 // Bit4
1042 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                          0x10
1043
1044 // Bit7:6
1045 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
1046 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                 0x00    //AB
1047 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                 0x40    //CD
1048 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                 0x80    //EF
1049
1050 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1051 {
1052         union
1053         {
1054   USHORT usPixelClock;          // in 10KHz; for bios convenient
1055         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1056   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1057         };
1058   ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1059         UCHAR ucAction;                           // define as ATOM_TRANSMITER_ACTION_XXX
1060   UCHAR ucReserved[4];
1061 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1062
1063 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1064 {
1065 #if ATOM_BIG_ENDIAN
1066   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1067                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1068                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1069   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1070   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1071   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1072                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1073   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1074   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1075 #else
1076   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1077   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1078   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1079                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1080   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1081   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1082   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1083                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1084                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1085 #endif
1086 }ATOM_DIG_TRANSMITTER_CONFIG_V3;
1087
1088
1089 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1090 {
1091         union
1092         {
1093     USHORT usPixelClock;                // in 10KHz; for bios convenient
1094           USHORT usInitInfo;                    // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1095     ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1096         };
1097   ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1098         UCHAR ucAction;                             // define as ATOM_TRANSMITER_ACTION_XXX
1099   UCHAR ucLaneNum;
1100   UCHAR ucReserved[3];
1101 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1102
1103 //ucConfig
1104 //Bit0
1105 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR                  0x01
1106
1107 //Bit1
1108 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                                       0x02
1109
1110 //Bit2
1111 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK                        0x04
1112 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA                                    0x00
1113 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB                                            0x04
1114
1115 // Bit3
1116 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK             0x08
1117 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                   0x00
1118 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                   0x08
1119
1120 // Bit5:4
1121 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK               0x30
1122 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL                                 0x00
1123 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL                           0x10
1124 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
1125
1126 // Bit7:6
1127 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
1128 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1                 0x00    //AB
1129 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2                 0x40    //CD
1130 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3                 0x80    //EF
1131
1132
1133 /****************************************************************************/
1134 // Structures used by UNIPHYTransmitterControlTable V1.4
1135 // ASIC Families: NI
1136 // ucTableFormatRevision=1
1137 // ucTableContentRevision=4
1138 /****************************************************************************/
1139 typedef struct _ATOM_DP_VS_MODE_V4
1140 {
1141   UCHAR ucLaneSel;
1142         union
1143         {
1144           UCHAR ucLaneSet;
1145           struct {
1146 #if ATOM_BIG_ENDIAN
1147                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
1148                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
1149                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
1150 #else
1151                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
1152                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
1153                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
1154 #endif
1155                 };
1156         };
1157 }ATOM_DP_VS_MODE_V4;
1158
1159 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1160 {
1161 #if ATOM_BIG_ENDIAN
1162   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1163                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1164                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1165   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
1166   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1167   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1168                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1169   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1170   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1171 #else
1172   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1173   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1174   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1175                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1176   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1177   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
1178   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1179                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1180                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1181 #endif
1182 }ATOM_DIG_TRANSMITTER_CONFIG_V4;
1183
1184 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1185 {
1186   union
1187   {
1188     USHORT usPixelClock;                // in 10KHz; for bios convenient
1189     USHORT usInitInfo;                  // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1190     ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
1191   };
1192   union
1193   {
1194   ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1195   UCHAR ucConfig;
1196   };
1197   UCHAR ucAction;                                   // define as ATOM_TRANSMITER_ACTION_XXX
1198   UCHAR ucLaneNum;
1199   UCHAR ucReserved[3];
1200 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1201
1202 //ucConfig
1203 //Bit0
1204 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR                  0x01
1205 //Bit1
1206 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT                                       0x02
1207 //Bit2
1208 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK                        0x04
1209 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA                                    0x00
1210 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB                                            0x04
1211 // Bit3
1212 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK             0x08
1213 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER                   0x00
1214 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER                   0x08
1215 // Bit5:4
1216 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK              0x30
1217 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL                                0x00
1218 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL                                0x10
1219 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL                                0x20   // New in _V4
1220 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
1221 // Bit7:6
1222 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
1223 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1                 0x00    //AB
1224 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2                 0x40    //CD
1225 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3                 0x80    //EF
1226
1227
1228 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1229 {
1230 #if ATOM_BIG_ENDIAN
1231   UCHAR ucReservd1:1;
1232   UCHAR ucHPDSel:3;
1233   UCHAR ucPhyClkSrcId:2;
1234   UCHAR ucCoherentMode:1;
1235   UCHAR ucReserved:1;
1236 #else
1237   UCHAR ucReserved:1;
1238   UCHAR ucCoherentMode:1;
1239   UCHAR ucPhyClkSrcId:2;
1240   UCHAR ucHPDSel:3;
1241   UCHAR ucReservd1:1;
1242 #endif
1243 }ATOM_DIG_TRANSMITTER_CONFIG_V5;
1244
1245 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1246 {
1247   USHORT usSymClock;                    // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock,  (HDMI deep color), =pixel clock * deep_color_ratio
1248   UCHAR  ucPhyId;                   // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1249   UCHAR  ucAction;                                  // define as ATOM_TRANSMITER_ACTION_xxx
1250   UCHAR  ucLaneNum;                 // indicate lane number 1-8
1251   UCHAR  ucConnObjId;               // Connector Object Id defined in ObjectId.h
1252   UCHAR  ucDigMode;                 // indicate DIG mode
1253   union{
1254   ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1255   UCHAR ucConfig;
1256   };
1257   UCHAR  ucDigEncoderSel;           // indicate DIG front end encoder
1258   UCHAR  ucDPLaneSet;
1259   UCHAR  ucReserved;
1260   UCHAR  ucReserved1;
1261 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1262
1263 //ucPhyId
1264 #define ATOM_PHY_ID_UNIPHYA                                 0
1265 #define ATOM_PHY_ID_UNIPHYB                                 1
1266 #define ATOM_PHY_ID_UNIPHYC                                 2
1267 #define ATOM_PHY_ID_UNIPHYD                                 3
1268 #define ATOM_PHY_ID_UNIPHYE                                 4
1269 #define ATOM_PHY_ID_UNIPHYF                                 5
1270 #define ATOM_PHY_ID_UNIPHYG                                 6
1271
1272 // ucDigEncoderSel
1273 #define ATOM_TRANMSITTER_V5__DIGA_SEL                       0x01
1274 #define ATOM_TRANMSITTER_V5__DIGB_SEL                       0x02
1275 #define ATOM_TRANMSITTER_V5__DIGC_SEL                       0x04
1276 #define ATOM_TRANMSITTER_V5__DIGD_SEL                       0x08
1277 #define ATOM_TRANMSITTER_V5__DIGE_SEL                       0x10
1278 #define ATOM_TRANMSITTER_V5__DIGF_SEL                       0x20
1279 #define ATOM_TRANMSITTER_V5__DIGG_SEL                       0x40
1280
1281 // ucDigMode
1282 #define ATOM_TRANSMITTER_DIGMODE_V5_DP                      0
1283 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS                    1
1284 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI                     2
1285 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI                    3
1286 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO                    4
1287 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST                  5
1288
1289 // ucDPLaneSet
1290 #define DP_LANE_SET__0DB_0_4V                               0x00
1291 #define DP_LANE_SET__0DB_0_6V                               0x01
1292 #define DP_LANE_SET__0DB_0_8V                               0x02
1293 #define DP_LANE_SET__0DB_1_2V                               0x03
1294 #define DP_LANE_SET__3_5DB_0_4V                             0x08
1295 #define DP_LANE_SET__3_5DB_0_6V                             0x09
1296 #define DP_LANE_SET__3_5DB_0_8V                             0x0a
1297 #define DP_LANE_SET__6DB_0_4V                               0x10
1298 #define DP_LANE_SET__6DB_0_6V                               0x11
1299 #define DP_LANE_SET__9_5DB_0_4V                             0x18
1300
1301 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1302 // Bit1
1303 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT                                       0x02
1304
1305 // Bit3:2
1306 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK              0x0c
1307 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT                 0x02
1308
1309 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL                                0x00
1310 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL                                0x04
1311 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL                                0x08
1312 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT           0x0c
1313 // Bit6:4
1314 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK                   0x70
1315 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT                      0x04
1316
1317 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL                                   0x00
1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL                                       0x10
1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL                                       0x20
1320 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL                                       0x30
1321 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL                                       0x40
1322 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL                                       0x50
1323 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL                                       0x60
1324
1325 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1326
1327
1328 /****************************************************************************/
1329 // Structures used by ExternalEncoderControlTable V1.3
1330 // ASIC Families: Evergreen, Llano, NI
1331 // ucTableFormatRevision=1
1332 // ucTableContentRevision=3
1333 /****************************************************************************/
1334
1335 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1336 {
1337   union{
1338   USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1339   USHORT usConnectorId;     // connector id, valid when ucAction = INIT
1340   };
1341   UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1342   UCHAR  ucAction;          //
1343   UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1344   UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1345   UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1346   UCHAR  ucReserved;
1347 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1348
1349 // ucAction
1350 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
1351 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
1352 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
1353 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
1354 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
1355 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
1356 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
1357 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
1358
1359 // ucConfig
1360 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK                              0x03
1361 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ             0x00
1362 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ             0x01
1363 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ             0x02
1364 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK                 0x70
1365 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                         0x00
1366 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                         0x10
1367 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                         0x20
1368
1369 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1370 {
1371   EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1372   ULONG ulReserved[2];
1373 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1374
1375
1376 /****************************************************************************/
1377 // Structures used by DAC1OuputControlTable
1378 //                    DAC2OuputControlTable
1379 //                    LVTMAOutputControlTable  (Before DEC30)
1380 //                    TMDSAOutputControlTable  (Before DEC30)
1381 /****************************************************************************/
1382 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1383 {
1384   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
1385                                       // When the display is LCD, in addition to above:
1386                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1387                                       // ATOM_LCD_SELFTEST_STOP
1388
1389   UCHAR  aucPadding[3];               // padding to DWORD aligned
1390 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1391
1392 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1393
1394
1395 #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1396 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1397
1398 #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1399 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1400
1401 #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1402 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1403
1404 #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1405 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1406
1407 #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1408 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1409
1410 #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1411 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1412
1413 #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1414 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1415
1416 #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1417 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1418 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
1419
1420 /****************************************************************************/
1421 // Structures used by BlankCRTCTable
1422 /****************************************************************************/
1423 typedef struct _BLANK_CRTC_PARAMETERS
1424 {
1425   UCHAR  ucCRTC;                        // ATOM_CRTC1 or ATOM_CRTC2
1426   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
1427   USHORT usBlackColorRCr;
1428   USHORT usBlackColorGY;
1429   USHORT usBlackColorBCb;
1430 }BLANK_CRTC_PARAMETERS;
1431 #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
1432
1433 /****************************************************************************/
1434 // Structures used by EnableCRTCTable
1435 //                    EnableCRTCMemReqTable
1436 //                    UpdateCRTC_DoubleBufferRegistersTable
1437 /****************************************************************************/
1438 typedef struct _ENABLE_CRTC_PARAMETERS
1439 {
1440   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1441   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
1442   UCHAR ucPadding[2];
1443 }ENABLE_CRTC_PARAMETERS;
1444 #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
1445
1446 /****************************************************************************/
1447 // Structures used by SetCRTC_OverScanTable
1448 /****************************************************************************/
1449 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1450 {
1451   USHORT usOverscanRight;             // right
1452   USHORT usOverscanLeft;              // left
1453   USHORT usOverscanBottom;            // bottom
1454   USHORT usOverscanTop;               // top
1455   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
1456   UCHAR  ucPadding[3];
1457 }SET_CRTC_OVERSCAN_PARAMETERS;
1458 #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
1459
1460 /****************************************************************************/
1461 // Structures used by SetCRTC_ReplicationTable
1462 /****************************************************************************/
1463 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1464 {
1465   UCHAR ucH_Replication;              // horizontal replication
1466   UCHAR ucV_Replication;              // vertical replication
1467   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
1468   UCHAR ucPadding;
1469 }SET_CRTC_REPLICATION_PARAMETERS;
1470 #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
1471
1472 /****************************************************************************/
1473 // Structures used by SelectCRTC_SourceTable
1474 /****************************************************************************/
1475 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1476 {
1477   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1478   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1479   UCHAR ucPadding[2];
1480 }SELECT_CRTC_SOURCE_PARAMETERS;
1481 #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
1482
1483 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1484 {
1485   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
1486   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1487   UCHAR ucEncodeMode;                                                                   // Encoding mode, only valid when using DIG1/DIG2/DVO
1488   UCHAR ucPadding;
1489 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
1490
1491 //ucEncoderID
1492 //#define ASIC_INT_DAC1_ENCODER_ID                                              0x00
1493 //#define ASIC_INT_TV_ENCODER_ID                                                                        0x02
1494 //#define ASIC_INT_DIG1_ENCODER_ID                                                              0x03
1495 //#define ASIC_INT_DAC2_ENCODER_ID                                                              0x04
1496 //#define ASIC_EXT_TV_ENCODER_ID                                                                        0x06
1497 //#define ASIC_INT_DVO_ENCODER_ID                                                                       0x07
1498 //#define ASIC_INT_DIG2_ENCODER_ID                                                              0x09
1499 //#define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05
1500
1501 //ucEncodeMode
1502 //#define ATOM_ENCODER_MODE_DP                                                                          0
1503 //#define ATOM_ENCODER_MODE_LVDS                                                                        1
1504 //#define ATOM_ENCODER_MODE_DVI                                                                         2
1505 //#define ATOM_ENCODER_MODE_HDMI                                                                        3
1506 //#define ATOM_ENCODER_MODE_SDVO                                                                        4
1507 //#define ATOM_ENCODER_MODE_TV                                                                          13
1508 //#define ATOM_ENCODER_MODE_CV                                                                          14
1509 //#define ATOM_ENCODER_MODE_CRT                                                                         15
1510
1511 /****************************************************************************/
1512 // Structures used by SetPixelClockTable
1513 //                    GetPixelClockTable
1514 /****************************************************************************/
1515 //Major revision=1., Minor revision=1
1516 typedef struct _PIXEL_CLOCK_PARAMETERS
1517 {
1518   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1519                                       // 0 means disable PPLL
1520   USHORT usRefDiv;                    // Reference divider
1521   USHORT usFbDiv;                     // feedback divider
1522   UCHAR  ucPostDiv;                   // post divider
1523   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1524   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1525   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1526   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1527   UCHAR  ucPadding;
1528 }PIXEL_CLOCK_PARAMETERS;
1529
1530 //Major revision=1., Minor revision=2, add ucMiscIfno
1531 //ucMiscInfo:
1532 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1533 #define MISC_DEVICE_INDEX_MASK        0xF0
1534 #define MISC_DEVICE_INDEX_SHIFT       4
1535
1536 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1537 {
1538   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1539                                       // 0 means disable PPLL
1540   USHORT usRefDiv;                    // Reference divider
1541   USHORT usFbDiv;                     // feedback divider
1542   UCHAR  ucPostDiv;                   // post divider
1543   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1544   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1545   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1546   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1547   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1548 }PIXEL_CLOCK_PARAMETERS_V2;
1549
1550 //Major revision=1., Minor revision=3, structure/definition change
1551 //ucEncoderMode:
1552 //ATOM_ENCODER_MODE_DP
1553 //ATOM_ENOCDER_MODE_LVDS
1554 //ATOM_ENOCDER_MODE_DVI
1555 //ATOM_ENOCDER_MODE_HDMI
1556 //ATOM_ENOCDER_MODE_SDVO
1557 //ATOM_ENCODER_MODE_TV                                                                          13
1558 //ATOM_ENCODER_MODE_CV                                                                          14
1559 //ATOM_ENCODER_MODE_CRT                                                                         15
1560
1561 //ucDVOConfig
1562 //#define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01
1563 //#define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00
1564 //#define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01
1565 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c
1566 //#define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00
1567 //#define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04
1568 //#define DVO_ENCODER_CONFIG_24BIT                                                              0x08
1569
1570 //ucMiscInfo: also changed, see below
1571 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
1572 #define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
1573 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
1574 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
1575 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
1576 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
1577 #define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
1578 // V1.4 for RoadRunner
1579 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
1580 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
1581
1582
1583 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1584 {
1585   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1586                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1587   USHORT usRefDiv;                    // Reference divider
1588   USHORT usFbDiv;                     // feedback divider
1589   UCHAR  ucPostDiv;                   // post divider
1590   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1591   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1592   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
1593         union
1594         {
1595   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1596         UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
1597         };
1598   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1599                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1600                                       // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1601 }PIXEL_CLOCK_PARAMETERS_V3;
1602
1603 #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
1604 #define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
1605
1606 typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1607 {
1608   UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to
1609                              // drive the pixel clock. not used for DCPLL case.
1610   union{
1611   UCHAR  ucReserved;
1612   UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
1613   };
1614   USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
1615                              // 0 means disable PPLL/DCPLL.
1616   USHORT usFbDiv;            // feedback divider integer part.
1617   UCHAR  ucPostDiv;          // post divider.
1618   UCHAR  ucRefDiv;           // Reference divider
1619   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1620   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
1621                              // indicate which graphic encoder will be used.
1622   UCHAR  ucEncoderMode;      // Encoder mode:
1623   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
1624                              // bit[1]= when VGA timing is used.
1625                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1626                              // bit[4]= RefClock source for PPLL.
1627                              // =0: XTLAIN( default mode )
1628                                    // =1: other external clock source, which is pre-defined
1629                              //     by VBIOS depend on the feature required.
1630                              // bit[7:5]: reserved.
1631   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1632
1633 }PIXEL_CLOCK_PARAMETERS_V5;
1634
1635 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL                                     0x01
1636 #define PIXEL_CLOCK_V5_MISC_VGA_MODE                                                            0x02
1637 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
1638 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
1639 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
1640 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
1641 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
1642
1643 typedef struct _CRTC_PIXEL_CLOCK_FREQ
1644 {
1645 #if ATOM_BIG_ENDIAN
1646   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
1647                               // drive the pixel clock. not used for DCPLL case.
1648   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
1649                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1650 #else
1651   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
1652                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1653   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
1654                               // drive the pixel clock. not used for DCPLL case.
1655 #endif
1656 }CRTC_PIXEL_CLOCK_FREQ;
1657
1658 typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1659 {
1660   union{
1661     CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency
1662     ULONG ulDispEngClkFreq;                  // dispclk frequency
1663   };
1664   USHORT usFbDiv;            // feedback divider integer part.
1665   UCHAR  ucPostDiv;          // post divider.
1666   UCHAR  ucRefDiv;           // Reference divider
1667   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1668   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
1669                              // indicate which graphic encoder will be used.
1670   UCHAR  ucEncoderMode;      // Encoder mode:
1671   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
1672                              // bit[1]= when VGA timing is used.
1673                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1674                              // bit[4]= RefClock source for PPLL.
1675                              // =0: XTLAIN( default mode )
1676                                    // =1: other external clock source, which is pre-defined
1677                              //     by VBIOS depend on the feature required.
1678                              // bit[7:5]: reserved.
1679   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1680
1681 }PIXEL_CLOCK_PARAMETERS_V6;
1682
1683 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL                                     0x01
1684 #define PIXEL_CLOCK_V6_MISC_VGA_MODE                                                            0x02
1685 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
1686 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
1687 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
1688 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
1689 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
1690 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
1691
1692 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1693 {
1694   PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1695 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1696
1697 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1698 {
1699   UCHAR  ucStatus;
1700   UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1701   UCHAR  ucReserved[2];
1702 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1703
1704 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1705 {
1706   PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1707 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1708
1709 /****************************************************************************/
1710 // Structures used by AdjustDisplayPllTable
1711 /****************************************************************************/
1712 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1713 {
1714         USHORT usPixelClock;
1715         UCHAR ucTransmitterID;
1716         UCHAR ucEncodeMode;
1717         union
1718         {
1719                 UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
1720                 UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
1721         };
1722         UCHAR ucReserved[3];
1723 }ADJUST_DISPLAY_PLL_PARAMETERS;
1724
1725 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
1726 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
1727
1728 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1729 {
1730         USHORT usPixelClock;                    // target pixel clock
1731         UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
1732         UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1733   UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1734   UCHAR ucExtTransmitterID;               // external encoder id.
1735         UCHAR ucReserved[2];
1736 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1737
1738 // usDispPllConfig v1.2 for RoadRunner
1739 #define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
1740 #define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
1741 #define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
1742 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
1743 #define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
1744 #define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
1745 #define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
1746 #define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
1747 #define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
1748 #define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
1749
1750
1751 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1752 {
1753   ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1754   UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1755   UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1756   UCHAR ucReserved[2];
1757 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1758
1759 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1760 {
1761   union
1762   {
1763     ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
1764     ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1765   };
1766 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1767
1768 /****************************************************************************/
1769 // Structures used by EnableYUVTable
1770 /****************************************************************************/
1771 typedef struct _ENABLE_YUV_PARAMETERS
1772 {
1773   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1774   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
1775   UCHAR ucPadding[2];
1776 }ENABLE_YUV_PARAMETERS;
1777 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1778
1779 /****************************************************************************/
1780 // Structures used by GetMemoryClockTable
1781 /****************************************************************************/
1782 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1783 {
1784   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
1785 } GET_MEMORY_CLOCK_PARAMETERS;
1786 #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
1787
1788 /****************************************************************************/
1789 // Structures used by GetEngineClockTable
1790 /****************************************************************************/
1791 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1792 {
1793   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
1794 } GET_ENGINE_CLOCK_PARAMETERS;
1795 #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
1796
1797 /****************************************************************************/
1798 // Following Structures and constant may be obsolete
1799 /****************************************************************************/
1800 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1801 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1802 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1803 {
1804   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1805   USHORT    usVRAMAddress;      //Address in Frame Buffer where to pace raw EDID
1806   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
1807                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
1808   UCHAR     ucSlaveAddr;        //Read from which slave
1809   UCHAR     ucLineNumber;       //Read from which HW assisted line
1810 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1811 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1812
1813
1814 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
1815 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
1816 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
1817 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
1818 #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
1819
1820 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1821 {
1822   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1823   USHORT    usByteOffset;       //Write to which byte
1824                                 //Upper portion of usByteOffset is Format of data
1825                                 //1bytePS+offsetPS
1826                                 //2bytesPS+offsetPS
1827                                 //blockID+offsetPS
1828                                 //blockID+offsetID
1829                                 //blockID+counterID+offsetID
1830   UCHAR     ucData;             //PS data1
1831   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
1832   UCHAR     ucSlaveAddr;        //Write to which slave
1833   UCHAR     ucLineNumber;       //Write from which HW assisted line
1834 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1835
1836 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1837
1838 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1839 {
1840   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1841   UCHAR     ucSlaveAddr;        //Write to which slave
1842   UCHAR     ucLineNumber;       //Write from which HW assisted line
1843 }SET_UP_HW_I2C_DATA_PARAMETERS;
1844
1845
1846 /**************************************************************************/
1847 #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1848
1849
1850 /****************************************************************************/
1851 // Structures used by PowerConnectorDetectionTable
1852 /****************************************************************************/
1853 typedef struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
1854 {
1855   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1856         UCHAR   ucPwrBehaviorId;
1857         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
1858 }POWER_CONNECTOR_DETECTION_PARAMETERS;
1859
1860 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1861 {
1862   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1863         UCHAR   ucReserved;
1864         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
1865   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
1866 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1867
1868 /****************************LVDS SS Command Table Definitions**********************/
1869
1870 /****************************************************************************/
1871 // Structures used by EnableSpreadSpectrumOnPPLLTable
1872 /****************************************************************************/
1873 typedef struct  _ENABLE_LVDS_SS_PARAMETERS
1874 {
1875   USHORT  usSpreadSpectrumPercentage;
1876   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1877   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1878   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1879   UCHAR   ucPadding[3];
1880 }ENABLE_LVDS_SS_PARAMETERS;
1881
1882 //ucTableFormatRevision=1,ucTableContentRevision=2
1883 typedef struct  _ENABLE_LVDS_SS_PARAMETERS_V2
1884 {
1885   USHORT  usSpreadSpectrumPercentage;
1886   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1887   UCHAR   ucSpreadSpectrumStep;           //
1888   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1889   UCHAR   ucSpreadSpectrumDelay;
1890   UCHAR   ucSpreadSpectrumRange;
1891   UCHAR   ucPadding;
1892 }ENABLE_LVDS_SS_PARAMETERS_V2;
1893
1894 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1895 typedef struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1896 {
1897   USHORT  usSpreadSpectrumPercentage;
1898   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1899   UCHAR   ucSpreadSpectrumStep;           //
1900   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
1901   UCHAR   ucSpreadSpectrumDelay;
1902   UCHAR   ucSpreadSpectrumRange;
1903   UCHAR   ucPpll;                                                                                                 // ATOM_PPLL1/ATOM_PPLL2
1904 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1905
1906 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1907 {
1908   USHORT  usSpreadSpectrumPercentage;
1909   UCHAR   ucSpreadSpectrumType;         // Bit[0]: 0-Down Spread,1-Center Spread.
1910                                         // Bit[1]: 1-Ext. 0-Int.
1911                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1912                                         // Bits[7:4] reserved
1913   UCHAR   ucEnable;                         // ATOM_ENABLE or ATOM_DISABLE
1914   USHORT  usSpreadSpectrumAmount;       // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1915   USHORT  usSpreadSpectrumStep;         // SS_STEP_SIZE_DSFRAC
1916 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1917
1918 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
1919 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
1920 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
1921 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
1922 #define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
1923 #define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
1924 #define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
1925 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
1926 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
1927 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
1928 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
1929
1930 // Used by DCE5.0
1931  typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
1932 {
1933   USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
1934   UCHAR   ucSpreadSpectrumType;         // Bit[0]: 0-Down Spread,1-Center Spread.
1935                                         // Bit[1]: 1-Ext. 0-Int.
1936                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1937                                         // Bits[7:4] reserved
1938   UCHAR   ucEnable;                         // ATOM_ENABLE or ATOM_DISABLE
1939   USHORT  usSpreadSpectrumAmount;       // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1940   USHORT  usSpreadSpectrumStep;         // SS_STEP_SIZE_DSFRAC
1941 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
1942
1943 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
1944 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
1945 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
1946 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
1947 #define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
1948 #define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
1949 #define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
1950 #define ATOM_PPLL_SS_TYPE_V3_P0PLL            ATOM_PPLL_SS_TYPE_V3_DCPLL
1951 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
1952 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
1953 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
1954 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
1955
1956 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
1957
1958 /**************************************************************************/
1959
1960 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
1961 {
1962   PIXEL_CLOCK_PARAMETERS sPCLKInput;
1963   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
1964 }SET_PIXEL_CLOCK_PS_ALLOCATION;
1965
1966 #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
1967
1968 /****************************************************************************/
1969 // Structures used by ###
1970 /****************************************************************************/
1971 typedef struct  _MEMORY_TRAINING_PARAMETERS
1972 {
1973   ULONG ulTargetMemoryClock;          //In 10Khz unit
1974 }MEMORY_TRAINING_PARAMETERS;
1975 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
1976
1977
1978 /****************************LVDS and other encoder command table definitions **********************/
1979
1980
1981 /****************************************************************************/
1982 // Structures used by LVDSEncoderControlTable   (Before DCE30)
1983 //                    LVTMAEncoderControlTable  (Before DCE30)
1984 //                    TMDSAEncoderControlTable  (Before DCE30)
1985 /****************************************************************************/
1986 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
1987 {
1988   USHORT usPixelClock;  // in 10KHz; for bios convenient
1989   UCHAR  ucMisc;        // bit0=0: Enable single link
1990                         //     =1: Enable dual link
1991                         // Bit1=0: 666RGB
1992                         //     =1: 888RGB
1993   UCHAR  ucAction;      // 0: turn off encoder
1994                         // 1: setup and turn on encoder
1995 }LVDS_ENCODER_CONTROL_PARAMETERS;
1996
1997 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
1998
1999 #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
2000 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2001
2002 #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
2003 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2004
2005
2006 //ucTableFormatRevision=1,ucTableContentRevision=2
2007 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2008 {
2009   USHORT usPixelClock;  // in 10KHz; for bios convenient
2010   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
2011   UCHAR  ucAction;      // 0: turn off encoder
2012                         // 1: setup and turn on encoder
2013   UCHAR  ucTruncate;    // bit0=0: Disable truncate
2014                         //     =1: Enable truncate
2015                         // bit4=0: 666RGB
2016                         //     =1: 888RGB
2017   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
2018                         //     =1: Enable spatial dithering
2019                         // bit4=0: 666RGB
2020                         //     =1: 888RGB
2021   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
2022                         //     =1: Enable temporal dithering
2023                         // bit4=0: 666RGB
2024                         //     =1: 888RGB
2025                         // bit5=0: Gray level 2
2026                         //     =1: Gray level 4
2027   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
2028                         //     =1: 25FRC_SEL pattern F
2029                         // bit6:5=0: 50FRC_SEL pattern A
2030                         //       =1: 50FRC_SEL pattern B
2031                         //       =2: 50FRC_SEL pattern C
2032                         //       =3: 50FRC_SEL pattern D
2033                         // bit7=0: 75FRC_SEL pattern E
2034                         //     =1: 75FRC_SEL pattern F
2035 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2036
2037 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
2038
2039 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
2040 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2041
2042 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2043 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2044
2045 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
2046 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
2047
2048 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2049 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2050
2051 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2052 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2053
2054 /****************************************************************************/
2055 // Structures used by ###
2056 /****************************************************************************/
2057 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2058 {
2059   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
2060   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2061   UCHAR    ucPadding[2];
2062 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2063
2064 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2065 {
2066   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
2067   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
2068 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2069
2070 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
2071
2072 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2073 {
2074   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
2075   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
2076 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2077
2078 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2079 {
2080   DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
2081   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2082 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2083
2084 /****************************************************************************/
2085 // Structures used by DVOEncoderControlTable
2086 /****************************************************************************/
2087 //ucTableFormatRevision=1,ucTableContentRevision=3
2088
2089 //ucDVOConfig:
2090 #define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
2091 #define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
2092 #define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
2093 #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
2094 #define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
2095 #define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
2096 #define DVO_ENCODER_CONFIG_24BIT                                                                0x08
2097
2098 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2099 {
2100   USHORT usPixelClock;
2101   UCHAR  ucDVOConfig;
2102   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2103   UCHAR  ucReseved[4];
2104 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
2105 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
2106
2107 //ucTableFormatRevision=1
2108 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2109 // bit1=0: non-coherent mode
2110 //     =1: coherent mode
2111
2112 //==========================================================================================
2113 //Only change is here next time when changing encoder parameter definitions again!
2114 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
2115 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2116
2117 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2118 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2119
2120 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2121 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2122
2123 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
2124 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
2125
2126 //==========================================================================================
2127 #define PANEL_ENCODER_MISC_DUAL                0x01
2128 #define PANEL_ENCODER_MISC_COHERENT            0x02
2129 #define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
2130 #define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
2131
2132 #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
2133 #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
2134 #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
2135
2136 #define PANEL_ENCODER_TRUNCATE_EN              0x01
2137 #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
2138 #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
2139 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
2140 #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
2141 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
2142 #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
2143 #define PANEL_ENCODER_25FRC_MASK               0x10
2144 #define PANEL_ENCODER_25FRC_E                  0x00
2145 #define PANEL_ENCODER_25FRC_F                  0x10
2146 #define PANEL_ENCODER_50FRC_MASK               0x60
2147 #define PANEL_ENCODER_50FRC_A                  0x00
2148 #define PANEL_ENCODER_50FRC_B                  0x20
2149 #define PANEL_ENCODER_50FRC_C                  0x40
2150 #define PANEL_ENCODER_50FRC_D                  0x60
2151 #define PANEL_ENCODER_75FRC_MASK               0x80
2152 #define PANEL_ENCODER_75FRC_E                  0x00
2153 #define PANEL_ENCODER_75FRC_F                  0x80
2154
2155 /****************************************************************************/
2156 // Structures used by SetVoltageTable
2157 /****************************************************************************/
2158 #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
2159 #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
2160 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
2161 #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
2162 #define SET_VOLTAGE_INIT_MODE                  5
2163 #define SET_VOLTAGE_GET_MAX_VOLTAGE            6                                        //Gets the Max. voltage for the soldered Asic
2164
2165 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
2166 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
2167 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
2168
2169 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
2170 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
2171 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
2172
2173 typedef struct  _SET_VOLTAGE_PARAMETERS
2174 {
2175   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2176   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
2177   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
2178   UCHAR    ucReserved;
2179 }SET_VOLTAGE_PARAMETERS;
2180
2181 typedef struct  _SET_VOLTAGE_PARAMETERS_V2
2182 {
2183   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2184   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
2185   USHORT   usVoltageLevel;              // real voltage level
2186 }SET_VOLTAGE_PARAMETERS_V2;
2187
2188
2189 typedef struct  _SET_VOLTAGE_PARAMETERS_V1_3
2190 {
2191   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2192   UCHAR    ucVoltageMode;               // Indicate action: Set voltage level
2193   USHORT   usVoltageLevel;              // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2194 }SET_VOLTAGE_PARAMETERS_V1_3;
2195
2196 //ucVoltageType
2197 #define VOLTAGE_TYPE_VDDC                    1
2198 #define VOLTAGE_TYPE_MVDDC                   2
2199 #define VOLTAGE_TYPE_MVDDQ                   3
2200 #define VOLTAGE_TYPE_VDDCI                   4
2201
2202 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2203 #define ATOM_SET_VOLTAGE                     0        //Set voltage Level
2204 #define ATOM_INIT_VOLTAGE_REGULATOR          3        //Init Regulator
2205 #define ATOM_SET_VOLTAGE_PHASE               4        //Set Vregulator Phase
2206 #define ATOM_GET_MAX_VOLTAGE                 6        //Get Max Voltage, not used in SetVoltageTable v1.3
2207 #define ATOM_GET_VOLTAGE_LEVEL               6        //Get Voltage level from vitual voltage ID
2208
2209 // define vitual voltage id in usVoltageLevel
2210 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
2211 #define ATOM_VIRTUAL_VOLTAGE_ID1             0xff02
2212 #define ATOM_VIRTUAL_VOLTAGE_ID2             0xff03
2213 #define ATOM_VIRTUAL_VOLTAGE_ID3             0xff04
2214
2215 typedef struct _SET_VOLTAGE_PS_ALLOCATION
2216 {
2217   SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2218   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2219 }SET_VOLTAGE_PS_ALLOCATION;
2220
2221 // New Added from SI for GetVoltageInfoTable, input parameter structure
2222 typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2223 {
2224   UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2225   UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
2226   USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2227   ULONG    ulReserved;
2228 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2229
2230 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2231 typedef struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2232 {
2233   ULONG    ulVotlageGpioState;
2234   ULONG    ulVoltageGPioMask;
2235 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2236
2237 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2238 typedef struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2239 {
2240   USHORT   usVoltageLevel;
2241   USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
2242   ULONG    ulReseved;
2243 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2244
2245
2246 // GetVoltageInfo v1.1 ucVoltageMode
2247 #define ATOM_GET_VOLTAGE_VID                0x00
2248 #define ATOM_GET_VOTLAGE_INIT_SEQ           0x03
2249 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
2250 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2251 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2252
2253 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2254 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2255 // undefined power state
2256 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2257 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2258
2259 /****************************************************************************/
2260 // Structures used by TVEncoderControlTable
2261 /****************************************************************************/
2262 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2263 {
2264   USHORT usPixelClock;                // in 10KHz; for bios convenient
2265   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
2266   UCHAR  ucAction;                    // 0: turn off encoder
2267                                       // 1: setup and turn on encoder
2268 }TV_ENCODER_CONTROL_PARAMETERS;
2269
2270 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2271 {
2272   TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2273   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
2274 }TV_ENCODER_CONTROL_PS_ALLOCATION;
2275
2276 //==============================Data Table Portion====================================
2277
2278 /****************************************************************************/
2279 // Structure used in Data.mtb
2280 /****************************************************************************/
2281 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2282 {
2283   USHORT        UtilityPipeLine;                // Offest for the utility to get parser info,Don't change this position!
2284   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2285   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2286   USHORT        StandardVESA_Timing;      // Only used by Bios
2287   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
2288   USHORT        PaletteData;              // Only used by BIOS
2289   USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info
2290   USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
2291   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
2292   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
2293   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600
2294   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
2295   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
2296   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
2297   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
2298   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
2299   USHORT        CompassionateData;        // Will be obsolete from R600
2300   USHORT        SaveRestoreInfo;          // Only used by Bios
2301   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2302   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
2303   USHORT        XTMDS_Info;               // Will be obsolete from R600
2304   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2305   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
2306   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
2307   USHORT        MC_InitParameter;         // Only used by command table
2308   USHORT        ASIC_VDDC_Info;                                         // Will be obsolete from R600
2309   USHORT        ASIC_InternalSS_Info;                   // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2310   USHORT        TV_VideoMode;                                                   // Only used by command table
2311   USHORT        VRAM_Info;                                                              // Only used by command table, latest version 1.3
2312   USHORT        MemoryTrainingInfo;                             // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2313   USHORT        IntegratedSystemInfo;                   // Shared by various SW components
2314   USHORT        ASIC_ProfilingInfo;                             // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2315   USHORT        VoltageObjectInfo;                              // Shared by various SW components, latest version 1.1
2316         USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
2317 }ATOM_MASTER_LIST_OF_DATA_TABLES;
2318
2319 typedef struct _ATOM_MASTER_DATA_TABLE
2320 {
2321   ATOM_COMMON_TABLE_HEADER sHeader;
2322   ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
2323 }ATOM_MASTER_DATA_TABLE;
2324
2325 // For backward compatible
2326 #define LVDS_Info                LCD_Info
2327 #define DAC_Info                 PaletteData
2328 #define TMDS_Info                DIGTransmitterInfo
2329
2330 /****************************************************************************/
2331 // Structure used in MultimediaCapabilityInfoTable
2332 /****************************************************************************/
2333 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2334 {
2335   ATOM_COMMON_TABLE_HEADER sHeader;
2336   ULONG                    ulSignature;      // HW info table signature string "$ATI"
2337   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2338   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2339   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
2340   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
2341 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
2342
2343 /****************************************************************************/
2344 // Structure used in MultimediaConfigInfoTable
2345 /****************************************************************************/
2346 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2347 {
2348   ATOM_COMMON_TABLE_HEADER sHeader;
2349   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
2350   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2351   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2352   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
2353   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2354   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2355   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2356   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
2357   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2358   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2359   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2360   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2361   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2362 }ATOM_MULTIMEDIA_CONFIG_INFO;
2363
2364
2365 /****************************************************************************/
2366 // Structures used in FirmwareInfoTable
2367 /****************************************************************************/
2368
2369 // usBIOSCapability Definition:
2370 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2371 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2372 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2373 // Others: Reserved
2374 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
2375 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
2376 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
2377 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008              // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2378 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010              // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2379 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
2380 #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
2381 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
2382 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
2383 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
2384 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2385 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
2386 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008              // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2387 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010              // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2388
2389 #ifndef _H2INC
2390
2391 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2392 typedef struct _ATOM_FIRMWARE_CAPABILITY
2393 {
2394 #if ATOM_BIG_ENDIAN
2395   USHORT Reserved:1;
2396   USHORT SCL2Redefined:1;
2397   USHORT PostWithoutModeSet:1;
2398   USHORT HyperMemory_Size:4;
2399   USHORT HyperMemory_Support:1;
2400   USHORT PPMode_Assigned:1;
2401   USHORT WMI_SUPPORT:1;
2402   USHORT GPUControlsBL:1;
2403   USHORT EngineClockSS_Support:1;
2404   USHORT MemoryClockSS_Support:1;
2405   USHORT ExtendedDesktopSupport:1;
2406   USHORT DualCRTC_Support:1;
2407   USHORT FirmwarePosted:1;
2408 #else
2409   USHORT FirmwarePosted:1;
2410   USHORT DualCRTC_Support:1;
2411   USHORT ExtendedDesktopSupport:1;
2412   USHORT MemoryClockSS_Support:1;
2413   USHORT EngineClockSS_Support:1;
2414   USHORT GPUControlsBL:1;
2415   USHORT WMI_SUPPORT:1;
2416   USHORT PPMode_Assigned:1;
2417   USHORT HyperMemory_Support:1;
2418   USHORT HyperMemory_Size:4;
2419   USHORT PostWithoutModeSet:1;
2420   USHORT SCL2Redefined:1;
2421   USHORT Reserved:1;
2422 #endif
2423 }ATOM_FIRMWARE_CAPABILITY;
2424
2425 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2426 {
2427   ATOM_FIRMWARE_CAPABILITY sbfAccess;
2428   USHORT                   susAccess;
2429 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2430
2431 #else
2432
2433 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2434 {
2435   USHORT                   susAccess;
2436 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2437
2438 #endif
2439
2440 typedef struct _ATOM_FIRMWARE_INFO
2441 {
2442   ATOM_COMMON_TABLE_HEADER        sHeader;
2443   ULONG                           ulFirmwareRevision;
2444   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2445   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2446   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2447   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2448   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2449   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2450   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2451   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2452   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2453   UCHAR                           ucASICMaxTemperature;
2454   UCHAR                           ucPadding[3];               //Don't use them
2455   ULONG                           aulReservedForBIOS[3];      //Don't use them
2456   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2457   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2458   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2459   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2460   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2461   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2462   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2463   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2464   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2465   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
2466   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2467   USHORT                          usReferenceClock;           //In 10Khz unit
2468   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2469   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2470   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2471   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2472 }ATOM_FIRMWARE_INFO;
2473
2474 typedef struct _ATOM_FIRMWARE_INFO_V1_2
2475 {
2476   ATOM_COMMON_TABLE_HEADER        sHeader;
2477   ULONG                           ulFirmwareRevision;
2478   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2479   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2480   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2481   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2482   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2483   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2484   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2485   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2486   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2487   UCHAR                           ucASICMaxTemperature;
2488   UCHAR                           ucMinAllowedBL_Level;
2489   UCHAR                           ucPadding[2];               //Don't use them
2490   ULONG                           aulReservedForBIOS[2];      //Don't use them
2491   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2492   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2493   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2494   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2495   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2496   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2497   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2498   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2499   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2500   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2501   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2502   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2503   USHORT                          usReferenceClock;           //In 10Khz unit
2504   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2505   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2506   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2507   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2508 }ATOM_FIRMWARE_INFO_V1_2;
2509
2510 typedef struct _ATOM_FIRMWARE_INFO_V1_3
2511 {
2512   ATOM_COMMON_TABLE_HEADER        sHeader;
2513   ULONG                           ulFirmwareRevision;
2514   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2515   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2516   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2517   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2518   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2519   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2520   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2521   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2522   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2523   UCHAR                           ucASICMaxTemperature;
2524   UCHAR                           ucMinAllowedBL_Level;
2525   UCHAR                           ucPadding[2];               //Don't use them
2526   ULONG                           aulReservedForBIOS;         //Don't use them
2527   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
2528   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2529   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2530   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2531   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2532   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2533   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2534   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2535   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2536   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2537   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2538   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2539   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2540   USHORT                          usReferenceClock;           //In 10Khz unit
2541   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2542   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2543   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2544   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2545 }ATOM_FIRMWARE_INFO_V1_3;
2546
2547 typedef struct _ATOM_FIRMWARE_INFO_V1_4
2548 {
2549   ATOM_COMMON_TABLE_HEADER        sHeader;
2550   ULONG                           ulFirmwareRevision;
2551   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2552   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2553   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2554   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2555   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2556   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2557   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2558   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2559   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2560   UCHAR                           ucASICMaxTemperature;
2561   UCHAR                           ucMinAllowedBL_Level;
2562   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2563   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2564   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2565   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
2566   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2567   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2568   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2569   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2570   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2571   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2572   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2573   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2574   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2575   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2576   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2577   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2578   USHORT                          usReferenceClock;           //In 10Khz unit
2579   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2580   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2581   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2582   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2583 }ATOM_FIRMWARE_INFO_V1_4;
2584
2585 //the structure below to be used from Cypress
2586 typedef struct _ATOM_FIRMWARE_INFO_V2_1
2587 {
2588   ATOM_COMMON_TABLE_HEADER        sHeader;
2589   ULONG                           ulFirmwareRevision;
2590   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2591   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2592   ULONG                           ulReserved1;
2593   ULONG                           ulReserved2;
2594   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2595   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2596   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2597   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
2598   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
2599   UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
2600   UCHAR                           ucMinAllowedBL_Level;
2601   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2602   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2603   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2604   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
2605   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2606   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2607   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2608   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2609   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2610   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2611   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2612   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2613   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2614   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2615   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2616   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2617   USHORT                          usCoreReferenceClock;       //In 10Khz unit
2618   USHORT                          usMemoryReferenceClock;     //In 10Khz unit
2619   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2620   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2621   UCHAR                           ucReserved4[3];
2622 }ATOM_FIRMWARE_INFO_V2_1;
2623
2624 //the structure below to be used from NI
2625 //ucTableFormatRevision=2
2626 //ucTableContentRevision=2
2627 typedef struct _ATOM_FIRMWARE_INFO_V2_2
2628 {
2629   ATOM_COMMON_TABLE_HEADER        sHeader;
2630   ULONG                           ulFirmwareRevision;
2631   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2632   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2633   ULONG                           ulReserved[2];
2634   ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2635   ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2636   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2637   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
2638   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2639   UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
2640   UCHAR                           ucMinAllowedBL_Level;
2641   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2642   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2643   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2644   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
2645   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2646   UCHAR                           ucRemoteDisplayConfig;
2647   UCHAR                           ucReserved5[3];             //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2648   ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2649   ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2650   USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
2651   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2652   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2653   USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
2654   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2655   USHORT                          usCoreReferenceClock;       //In 10Khz unit
2656   USHORT                          usMemoryReferenceClock;     //In 10Khz unit
2657   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2658   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2659   UCHAR                           ucReserved9[3];
2660   USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
2661   USHORT                          usReserved12;
2662   ULONG                           ulReserved10[3];            // New added comparing to previous version
2663 }ATOM_FIRMWARE_INFO_V2_2;
2664
2665 #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
2666
2667
2668 // definition of ucRemoteDisplayConfig
2669 #define REMOTE_DISPLAY_DISABLE                   0x00
2670 #define REMOTE_DISPLAY_ENABLE                    0x01
2671
2672 /****************************************************************************/
2673 // Structures used in IntegratedSystemInfoTable
2674 /****************************************************************************/
2675 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
2676 #define IGP_CAP_FLAG_AC_CARD               0x4
2677 #define IGP_CAP_FLAG_SDVO_CARD             0x8
2678 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
2679
2680 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2681 {
2682   ATOM_COMMON_TABLE_HEADER        sHeader;
2683   ULONG                           ulBootUpEngineClock;              //in 10kHz unit
2684   ULONG                           ulBootUpMemoryClock;              //in 10kHz unit
2685   ULONG                           ulMaxSystemMemoryClock;           //in 10kHz unit
2686   ULONG                           ulMinSystemMemoryClock;           //in 10kHz unit
2687   UCHAR                           ucNumberOfCyclesInPeriodHi;
2688   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2689   USHORT                          usReserved1;
2690   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
2691   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
2692   ULONG                           ulReserved[2];
2693
2694   USHORT                                usFSBClock;                                 //In MHz unit
2695   USHORT                          usCapabilityFlag;                     //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2696                                                                                                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2697                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
2698   USHORT                                usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2699   USHORT                                usK8MemoryClock;            //in MHz unit
2700   USHORT                                usK8SyncStartDelay;         //in 0.01 us unit
2701   USHORT                                usK8DataReturnTime;         //in 0.01 us unit
2702   UCHAR                           ucMaxNBVoltage;
2703   UCHAR                           ucMinNBVoltage;
2704   UCHAR                           ucMemoryType;                                       //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2705   UCHAR                           ucNumberOfCyclesInPeriod;             //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2706   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2707   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
2708   UCHAR                           ucMaxNBVoltageHigh;
2709   UCHAR                           ucMinNBVoltageHigh;
2710 }ATOM_INTEGRATED_SYSTEM_INFO;
2711
2712 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2713 ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
2714                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2715 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2716                         For AMD IGP,for now this can be 0
2717 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2718                         For AMD IGP,for now this can be 0
2719
2720 usFSBClock:             For Intel IGP,it's FSB Freq
2721                         For AMD IGP,it's HT Link Speed
2722
2723 usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
2724 usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2725 usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2726
2727 VC:Voltage Control
2728 ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2729 ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2730
2731 ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2732 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2733
2734 ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2735 ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2736
2737
2738 usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2739 usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2740 */
2741
2742
2743 /*
2744 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2745 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2746 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2747
2748 SW components can access the IGP system infor structure in the same way as before
2749 */
2750
2751
2752 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2753 {
2754   ATOM_COMMON_TABLE_HEADER   sHeader;
2755   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
2756   ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
2757   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
2758   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
2759   ULONG                      ulMinSidePortClock;        //in 10kHz unit
2760   ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
2761   ULONG                      ulSystemConfig;            //see explanation below
2762   ULONG                      ulBootUpReqDisplayVector;
2763   ULONG                      ulOtherDisplayMisc;
2764   ULONG                      ulDDISlot1Config;
2765   ULONG                      ulDDISlot2Config;
2766   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2767   UCHAR                      ucUMAChannelNumber;
2768   UCHAR                      ucDockingPinBit;
2769   UCHAR                      ucDockingPinPolarity;
2770   ULONG                      ulDockingPinCFGInfo;
2771   ULONG                      ulCPUCapInfo;
2772   USHORT                     usNumberOfCyclesInPeriod;
2773   USHORT                     usMaxNBVoltage;
2774   USHORT                     usMinNBVoltage;
2775   USHORT                     usBootUpNBVoltage;
2776   ULONG                      ulHTLinkFreq;              //in 10Khz
2777   USHORT                     usMinHTLinkWidth;
2778   USHORT                     usMaxHTLinkWidth;
2779   USHORT                     usUMASyncStartDelay;
2780   USHORT                     usUMADataReturnTime;
2781   USHORT                     usLinkStatusZeroTime;
2782   USHORT                     usDACEfuse;                                //for storing badgap value (for RS880 only)
2783   ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
2784   ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
2785   USHORT                     usMaxUpStreamHTLinkWidth;
2786   USHORT                     usMaxDownStreamHTLinkWidth;
2787   USHORT                     usMinUpStreamHTLinkWidth;
2788   USHORT                     usMinDownStreamHTLinkWidth;
2789   USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2790   USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2791   ULONG                      ulReserved3[96];          //must be 0x0
2792 }ATOM_INTEGRATED_SYSTEM_INFO_V2;
2793
2794 /*
2795 ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
2796 ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2797 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2798
2799 ulSystemConfig:
2800 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2801 Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2802       =0: system boots up at driver control state. Power state depends on PowerPlay table.
2803 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2804 Bit[3]=1: Only one power state(Performance) will be supported.
2805       =0: Multiple power states supported from PowerPlay table.
2806 Bit[4]=1: CLMC is supported and enabled on current system.
2807       =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2808 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2809       =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2810 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2811       =0: Voltage settings is determined by powerplay table.
2812 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2813       =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2814 Bit[8]=1: CDLF is supported and enabled on current system.
2815       =0: CDLF is not supported or enabled on current system.
2816 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2817       =0: DLL Shut Down feature is not enabled or supported on current system.
2818
2819 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2820
2821 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2822                                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
2823
2824 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2825       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2826                         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2827       When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2828       in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2829       one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2830
2831                         [15:8] - Lane configuration attribute;
2832       [23:16]- Connector type, possible value:
2833                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2834                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2835                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2836                CONNECTOR_OBJECT_ID_DISPLAYPORT
2837                CONNECTOR_OBJECT_ID_eDP
2838                         [31:24]- Reserved
2839
2840 ulDDISlot2Config: Same as Slot1.
2841 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2842 For IGP, Hypermemory is the only memory type showed in CCC.
2843
2844 ucUMAChannelNumber:  how many channels for the UMA;
2845
2846 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2847 ucDockingPinBit:     which bit in this register to read the pin status;
2848 ucDockingPinPolarity:Polarity of the pin when docked;
2849
2850 ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
2851
2852 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
2853
2854 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
2855 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
2856                     GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
2857                     PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
2858                     GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
2859
2860 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2861
2862 ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
2863 usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
2864                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
2865 usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
2866                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
2867
2868 usUMASyncStartDelay: Memory access latency, required for watermark calculation
2869 usUMADataReturnTime: Memory access latency, required for watermark calculation
2870 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
2871 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
2872                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
2873                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
2874                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
2875                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
2876
2877 ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
2878                              This must be less than or equal to ulHTLinkFreq(bootup frequency).
2879 ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
2880                              This must be less than or equal to ulHighVoltageHTLinkFreq.
2881
2882 usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
2883 usMaxDownStreamHTLinkWidth:  same as above.
2884 usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
2885 usMinDownStreamHTLinkWidth:  same as above.
2886 */
2887
2888 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo  - CPU type definition
2889 #define    INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU             0
2890 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN        1
2891 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND      2
2892 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__K8             3
2893 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH        4
2894 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI         5
2895
2896 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE       INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI    // this deff reflects max defined CPU code
2897
2898 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
2899 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
2900 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
2901 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
2902 #define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
2903 #define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
2904 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
2905 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
2906 #define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
2907 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
2908
2909 #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
2910
2911 #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
2912 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
2913 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
2914 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
2915 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
2916 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
2917
2918 #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
2919 #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
2920 #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
2921
2922 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
2923
2924 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
2925 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
2926 {
2927   ATOM_COMMON_TABLE_HEADER   sHeader;
2928   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
2929   ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
2930   ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
2931   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
2932   ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
2933   ULONG                      ulBootUpReqDisplayVector;
2934   ULONG                      ulOtherDisplayMisc;
2935   ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
2936   ULONG                      ulSystemConfig;            //TBD
2937   ULONG                      ulCPUCapInfo;              //TBD
2938   USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2939   USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
2940   USHORT                     usBootUpNBVoltage;         //boot up NB voltage
2941   UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
2942   UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
2943   ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
2944   ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
2945   ULONG                      ulDDISlot2Config;
2946   ULONG                      ulDDISlot3Config;
2947   ULONG                      ulDDISlot4Config;
2948   ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
2949   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2950   UCHAR                      ucUMAChannelNumber;
2951   USHORT                     usReserved;
2952   ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
2953   ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
2954   ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
2955   ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
2956   ULONG                      ulReserved6[61];           //must be 0x0
2957 }ATOM_INTEGRATED_SYSTEM_INFO_V5;
2958
2959 #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
2960 #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
2961 #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
2962 #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
2963 #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
2964 #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
2965 #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
2966 #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
2967 #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
2968 #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
2969 #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
2970 #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
2971 #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
2972 #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
2973
2974 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
2975 #define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00
2976 #define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
2977 #define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
2978 #define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
2979 #define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
2980 #define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
2981 #define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
2982 #define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
2983 #define ASIC_EXT_DIG2_ENCODER_ID                                                                                                        0x08
2984 #define ASIC_INT_DIG3_ENCODER_ID                                                                                                        0x0a
2985 #define ASIC_INT_DIG4_ENCODER_ID                                                                                                        0x0b
2986 #define ASIC_INT_DIG5_ENCODER_ID                                                                                                        0x0c
2987 #define ASIC_INT_DIG6_ENCODER_ID                                                                                                        0x0d
2988 #define ASIC_INT_DIG7_ENCODER_ID                                                                                                        0x0e
2989
2990 //define Encoder attribute
2991 #define ATOM_ANALOG_ENCODER                                                                                                                             0
2992 #define ATOM_DIGITAL_ENCODER                                                                                                                    1
2993 #define ATOM_DP_ENCODER                                                                                                                       2
2994
2995 #define ATOM_ENCODER_ENUM_MASK                            0x70
2996 #define ATOM_ENCODER_ENUM_ID1                             0x00
2997 #define ATOM_ENCODER_ENUM_ID2                             0x10
2998 #define ATOM_ENCODER_ENUM_ID3                             0x20
2999 #define ATOM_ENCODER_ENUM_ID4                             0x30
3000 #define ATOM_ENCODER_ENUM_ID5                             0x40
3001 #define ATOM_ENCODER_ENUM_ID6                             0x50
3002
3003 #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
3004 #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
3005 #define ATOM_DEVICE_TV1_INDEX                             0x00000002
3006 #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
3007 #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
3008 #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
3009 #define ATOM_DEVICE_DFP6_INDEX                            0x00000006
3010 #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
3011 #define ATOM_DEVICE_CV_INDEX                              0x00000008
3012 #define ATOM_DEVICE_DFP3_INDEX                            0x00000009
3013 #define ATOM_DEVICE_DFP4_INDEX                            0x0000000A
3014 #define ATOM_DEVICE_DFP5_INDEX                            0x0000000B
3015
3016 #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
3017 #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
3018 #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
3019 #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
3020 #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
3021 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
3022 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
3023
3024 #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
3025
3026 #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
3027 #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
3028 #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
3029 #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
3030 #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
3031 #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
3032 #define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
3033 #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
3034 #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
3035 #define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
3036 #define ATOM_DEVICE_DFP4_SUPPORT                          (0x1L << ATOM_DEVICE_DFP4_INDEX )
3037 #define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
3038
3039 #define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3040 #define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3041 #define ATOM_DEVICE_TV_SUPPORT                            (ATOM_DEVICE_TV1_SUPPORT)
3042 #define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3043
3044 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
3045 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
3046 #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
3047 #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
3048 #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
3049 #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
3050 #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
3051 #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
3052 #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
3053 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
3054 #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
3055 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
3056 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
3057 #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
3058 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
3059
3060
3061 #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
3062 #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
3063 #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
3064 #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
3065 #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
3066 #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
3067
3068 #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
3069
3070 #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
3071 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
3072
3073 #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
3074 #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
3075 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
3076 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
3077 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
3078 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
3079
3080 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
3081 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
3082 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
3083 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
3084
3085 //  usDeviceSupport:
3086 //  Bits0       = 0 - no CRT1 support= 1- CRT1 is supported
3087 //  Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported
3088 //  Bit 2       = 0 - no TV1  support= 1- TV1  is supported
3089 //  Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported
3090 //  Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported
3091 //  Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported
3092 //  Bit 6       = 0 - no DFP6 support= 1- DFP6 is supported
3093 //  Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported
3094 //  Bit 8       = 0 - no CV   support= 1- CV   is supported
3095 //  Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported
3096 //  Bit 10      = 0 - no DFP4 support= 1- DFP4 is supported
3097 //  Bit 11      = 0 - no DFP5 support= 1- DFP5 is supported
3098 //
3099 //
3100
3101 /****************************************************************************/
3102 /* Structure used in MclkSS_InfoTable                                       */
3103 /****************************************************************************/
3104 //              ucI2C_ConfigID
3105 //    [7:0] - I2C LINE Associate ID
3106 //          = 0   - no I2C
3107 //    [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection)
3108 //                          =   0,  [6:0]=SW assisted I2C ID
3109 //    [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use
3110 //                          =   2,      HW engine for Multimedia use
3111 //                          =   3-7     Reserved for future I2C engines
3112 //              [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3113
3114 typedef struct _ATOM_I2C_ID_CONFIG
3115 {
3116 #if ATOM_BIG_ENDIAN
3117   UCHAR   bfHW_Capable:1;
3118   UCHAR   bfHW_EngineID:3;
3119   UCHAR   bfI2C_LineMux:4;
3120 #else
3121   UCHAR   bfI2C_LineMux:4;
3122   UCHAR   bfHW_EngineID:3;
3123   UCHAR   bfHW_Capable:1;
3124 #endif
3125 }ATOM_I2C_ID_CONFIG;
3126
3127 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3128 {
3129   ATOM_I2C_ID_CONFIG sbfAccess;
3130   UCHAR              ucAccess;
3131 }ATOM_I2C_ID_CONFIG_ACCESS;
3132
3133
3134 /****************************************************************************/
3135 // Structure used in GPIO_I2C_InfoTable
3136 /****************************************************************************/
3137 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3138 {
3139   USHORT                    usClkMaskRegisterIndex;
3140   USHORT                    usClkEnRegisterIndex;
3141   USHORT                    usClkY_RegisterIndex;
3142   USHORT                    usClkA_RegisterIndex;
3143   USHORT                    usDataMaskRegisterIndex;
3144   USHORT                    usDataEnRegisterIndex;
3145   USHORT                    usDataY_RegisterIndex;
3146   USHORT                    usDataA_RegisterIndex;
3147   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3148   UCHAR                     ucClkMaskShift;
3149   UCHAR                     ucClkEnShift;
3150   UCHAR                     ucClkY_Shift;
3151   UCHAR                     ucClkA_Shift;
3152   UCHAR                     ucDataMaskShift;
3153   UCHAR                     ucDataEnShift;
3154   UCHAR                     ucDataY_Shift;
3155   UCHAR                     ucDataA_Shift;
3156   UCHAR                     ucReserved1;
3157   UCHAR                     ucReserved2;
3158 }ATOM_GPIO_I2C_ASSIGMENT;
3159
3160 typedef struct _ATOM_GPIO_I2C_INFO
3161 {
3162   ATOM_COMMON_TABLE_HEADER      sHeader;
3163   ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3164 }ATOM_GPIO_I2C_INFO;
3165
3166 /****************************************************************************/
3167 // Common Structure used in other structures
3168 /****************************************************************************/
3169
3170 #ifndef _H2INC
3171
3172 //Please don't add or expand this bitfield structure below, this one will retire soon.!
3173 typedef struct _ATOM_MODE_MISC_INFO
3174 {
3175 #if ATOM_BIG_ENDIAN
3176   USHORT Reserved:6;
3177   USHORT RGB888:1;
3178   USHORT DoubleClock:1;
3179   USHORT Interlace:1;
3180   USHORT CompositeSync:1;
3181   USHORT V_ReplicationBy2:1;
3182   USHORT H_ReplicationBy2:1;
3183   USHORT VerticalCutOff:1;
3184   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
3185   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
3186   USHORT HorizontalCutOff:1;
3187 #else
3188   USHORT HorizontalCutOff:1;
3189   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
3190   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
3191   USHORT VerticalCutOff:1;
3192   USHORT H_ReplicationBy2:1;
3193   USHORT V_ReplicationBy2:1;
3194   USHORT CompositeSync:1;
3195   USHORT Interlace:1;
3196   USHORT DoubleClock:1;
3197   USHORT RGB888:1;
3198   USHORT Reserved:6;
3199 #endif
3200 }ATOM_MODE_MISC_INFO;
3201
3202 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3203 {
3204   ATOM_MODE_MISC_INFO sbfAccess;
3205   USHORT              usAccess;
3206 }ATOM_MODE_MISC_INFO_ACCESS;
3207
3208 #else
3209
3210 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3211 {
3212   USHORT              usAccess;
3213 }ATOM_MODE_MISC_INFO_ACCESS;
3214
3215 #endif
3216
3217 // usModeMiscInfo-
3218 #define ATOM_H_CUTOFF           0x01
3219 #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
3220 #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
3221 #define ATOM_V_CUTOFF           0x08
3222 #define ATOM_H_REPLICATIONBY2   0x10
3223 #define ATOM_V_REPLICATIONBY2   0x20
3224 #define ATOM_COMPOSITESYNC      0x40
3225 #define ATOM_INTERLACE          0x80
3226 #define ATOM_DOUBLE_CLOCK_MODE  0x100
3227 #define ATOM_RGB888_MODE        0x200
3228
3229 //usRefreshRate-
3230 #define ATOM_REFRESH_43         43
3231 #define ATOM_REFRESH_47         47
3232 #define ATOM_REFRESH_56         56
3233 #define ATOM_REFRESH_60         60
3234 #define ATOM_REFRESH_65         65
3235 #define ATOM_REFRESH_70         70
3236 #define ATOM_REFRESH_72         72
3237 #define ATOM_REFRESH_75         75
3238 #define ATOM_REFRESH_85         85
3239
3240 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3241 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3242 //
3243 //      VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3244 //                                              =       EDID_HA + EDID_HBL
3245 //      VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA
3246 //      VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3247 //                                              =       EDID_HA + EDID_HSO
3248 //      VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW
3249 //      VESA_BORDER                     =       EDID_BORDER
3250
3251 /****************************************************************************/
3252 // Structure used in SetCRTC_UsingDTDTimingTable
3253 /****************************************************************************/
3254 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3255 {
3256   USHORT  usH_Size;
3257   USHORT  usH_Blanking_Time;
3258   USHORT  usV_Size;
3259   USHORT  usV_Blanking_Time;
3260   USHORT  usH_SyncOffset;
3261   USHORT  usH_SyncWidth;
3262   USHORT  usV_SyncOffset;
3263   USHORT  usV_SyncWidth;
3264   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3265   UCHAR   ucH_Border;         // From DFP EDID
3266   UCHAR   ucV_Border;
3267   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2
3268   UCHAR   ucPadding[3];
3269 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3270
3271 /****************************************************************************/
3272 // Structure used in SetCRTC_TimingTable
3273 /****************************************************************************/
3274 typedef struct _SET_CRTC_TIMING_PARAMETERS
3275 {
3276   USHORT                      usH_Total;        // horizontal total
3277   USHORT                      usH_Disp;         // horizontal display
3278   USHORT                      usH_SyncStart;    // horozontal Sync start
3279   USHORT                      usH_SyncWidth;    // horizontal Sync width
3280   USHORT                      usV_Total;        // vertical total
3281   USHORT                      usV_Disp;         // vertical display
3282   USHORT                      usV_SyncStart;    // vertical Sync start
3283   USHORT                      usV_SyncWidth;    // vertical Sync width
3284   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3285   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
3286   UCHAR                       ucOverscanRight;  // right
3287   UCHAR                       ucOverscanLeft;   // left
3288   UCHAR                       ucOverscanBottom; // bottom
3289   UCHAR                       ucOverscanTop;    // top
3290   UCHAR                       ucReserved;
3291 }SET_CRTC_TIMING_PARAMETERS;
3292 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3293
3294 /****************************************************************************/
3295 // Structure used in StandardVESA_TimingTable
3296 //                   AnalogTV_InfoTable
3297 //                   ComponentVideoInfoTable
3298 /****************************************************************************/
3299 typedef struct _ATOM_MODE_TIMING
3300 {
3301   USHORT  usCRTC_H_Total;
3302   USHORT  usCRTC_H_Disp;
3303   USHORT  usCRTC_H_SyncStart;
3304   USHORT  usCRTC_H_SyncWidth;
3305   USHORT  usCRTC_V_Total;
3306   USHORT  usCRTC_V_Disp;
3307   USHORT  usCRTC_V_SyncStart;
3308   USHORT  usCRTC_V_SyncWidth;
3309   USHORT  usPixelClock;                                                  //in 10Khz unit
3310   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3311   USHORT  usCRTC_OverscanRight;
3312   USHORT  usCRTC_OverscanLeft;
3313   USHORT  usCRTC_OverscanBottom;
3314   USHORT  usCRTC_OverscanTop;
3315   USHORT  usReserve;
3316   UCHAR   ucInternalModeNumber;
3317   UCHAR   ucRefreshRate;
3318 }ATOM_MODE_TIMING;
3319
3320 typedef struct _ATOM_DTD_FORMAT
3321 {
3322   USHORT  usPixClk;
3323   USHORT  usHActive;
3324   USHORT  usHBlanking_Time;
3325   USHORT  usVActive;
3326   USHORT  usVBlanking_Time;
3327   USHORT  usHSyncOffset;
3328   USHORT  usHSyncWidth;
3329   USHORT  usVSyncOffset;
3330   USHORT  usVSyncWidth;
3331   USHORT  usImageHSize;
3332   USHORT  usImageVSize;
3333   UCHAR   ucHBorder;
3334   UCHAR   ucVBorder;
3335   ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3336   UCHAR   ucInternalModeNumber;
3337   UCHAR   ucRefreshRate;
3338 }ATOM_DTD_FORMAT;
3339
3340 /****************************************************************************/
3341 // Structure used in LVDS_InfoTable
3342 //  * Need a document to describe this table
3343 /****************************************************************************/
3344 #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
3345 #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
3346 #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
3347 #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
3348
3349 //ucTableFormatRevision=1
3350 //ucTableContentRevision=1
3351 typedef struct _ATOM_LVDS_INFO
3352 {
3353   ATOM_COMMON_TABLE_HEADER sHeader;
3354   ATOM_DTD_FORMAT     sLCDTiming;
3355   USHORT              usModePatchTableOffset;
3356   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
3357   USHORT              usOffDelayInMs;
3358   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
3359   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
3360   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3361                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3362                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3363                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3364   UCHAR               ucPanelDefaultRefreshRate;
3365   UCHAR               ucPanelIdentification;
3366   UCHAR               ucSS_Id;
3367 }ATOM_LVDS_INFO;
3368
3369 //ucTableFormatRevision=1
3370 //ucTableContentRevision=2
3371 typedef struct _ATOM_LVDS_INFO_V12
3372 {
3373   ATOM_COMMON_TABLE_HEADER sHeader;
3374   ATOM_DTD_FORMAT     sLCDTiming;
3375   USHORT              usExtInfoTableOffset;
3376   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
3377   USHORT              usOffDelayInMs;
3378   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
3379   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
3380   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3381                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3382                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3383                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3384   UCHAR               ucPanelDefaultRefreshRate;
3385   UCHAR               ucPanelIdentification;
3386   UCHAR               ucSS_Id;
3387   USHORT              usLCDVenderID;
3388   USHORT              usLCDProductID;
3389   UCHAR               ucLCDPanel_SpecialHandlingCap;
3390         UCHAR                                                           ucPanelInfoSize;                                        //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3391   UCHAR               ucReserved[2];
3392 }ATOM_LVDS_INFO_V12;
3393
3394 //Definitions for ucLCDPanel_SpecialHandlingCap:
3395
3396 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3397 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3398 #define LCDPANEL_CAP_READ_EDID                  0x1
3399
3400 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3401 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3402 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3403 #define LCDPANEL_CAP_DRR_SUPPORTED              0x2
3404
3405 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3406 #define LCDPANEL_CAP_eDP                        0x4
3407
3408
3409 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3410 //Bit 6  5  4
3411                               //      0  0  0  -  Color bit depth is undefined
3412                               //      0  0  1  -  6 Bits per Primary Color
3413                               //      0  1  0  -  8 Bits per Primary Color
3414                               //      0  1  1  - 10 Bits per Primary Color
3415                               //      1  0  0  - 12 Bits per Primary Color
3416                               //      1  0  1  - 14 Bits per Primary Color
3417                               //      1  1  0  - 16 Bits per Primary Color
3418                               //      1  1  1  - Reserved
3419
3420 #define PANEL_COLOR_BIT_DEPTH_MASK    0x70
3421
3422 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3423 #define PANEL_RANDOM_DITHER   0x80
3424 #define PANEL_RANDOM_DITHER_MASK   0x80
3425
3426 #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12   // no need to change this
3427
3428 /****************************************************************************/
3429 // Structures used by LCD_InfoTable V1.3    Note: previous version was called ATOM_LVDS_INFO_V12
3430 // ASIC Families:  NI
3431 // ucTableFormatRevision=1
3432 // ucTableContentRevision=3
3433 /****************************************************************************/
3434 typedef struct _ATOM_LCD_INFO_V13
3435 {
3436   ATOM_COMMON_TABLE_HEADER sHeader;
3437   ATOM_DTD_FORMAT     sLCDTiming;
3438   USHORT              usExtInfoTableOffset;
3439   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
3440   ULONG               ulReserved0;
3441   UCHAR               ucLCD_Misc;                // Reorganized in V13
3442                                                  // Bit0: {=0:single, =1:dual},
3443                                                  // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888}  // was {=0:666RGB, =1:888RGB},
3444                                                  // Bit3:2: {Grey level}
3445                                                  // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3446                                                  // Bit7   Reserved.  was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3447   UCHAR               ucPanelDefaultRefreshRate;
3448   UCHAR               ucPanelIdentification;
3449   UCHAR               ucSS_Id;
3450   USHORT              usLCDVenderID;
3451   USHORT              usLCDProductID;
3452   UCHAR               ucLCDPanel_SpecialHandlingCap;  // Reorganized in V13
3453                                                  // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3454                                                  // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3455                                                  // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3456                                                  // Bit7-3: Reserved
3457   UCHAR               ucPanelInfoSize;                                   //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3458   USHORT              usBacklightPWM;            //  Backlight PWM in Hz. New in _V13
3459
3460   UCHAR               ucPowerSequenceDIGONtoDE_in4Ms;
3461   UCHAR               ucPowerSequenceDEtoVARY_BL_in4Ms;
3462   UCHAR               ucPowerSequenceVARY_BLtoDE_in4Ms;
3463   UCHAR               ucPowerSequenceDEtoDIGON_in4Ms;
3464
3465   UCHAR               ucOffDelay_in4Ms;
3466   UCHAR               ucPowerSequenceVARY_BLtoBLON_in4Ms;
3467   UCHAR               ucPowerSequenceBLONtoVARY_BL_in4Ms;
3468   UCHAR               ucReserved1;
3469
3470   UCHAR               ucDPCD_eDP_CONFIGURATION_CAP;     // dpcd 0dh
3471   UCHAR               ucDPCD_MAX_LINK_RATE;             // dpcd 01h
3472   UCHAR               ucDPCD_MAX_LANE_COUNT;            // dpcd 02h
3473   UCHAR               ucDPCD_MAX_DOWNSPREAD;            // dpcd 03h
3474
3475   USHORT              usMaxPclkFreqInSingleLink;        // Max PixelClock frequency in single link mode.
3476   UCHAR               uceDPToLVDSRxId;
3477   UCHAR               ucLcdReservd;
3478   ULONG               ulReserved[2];
3479 }ATOM_LCD_INFO_V13;
3480
3481 #define ATOM_LCD_INFO_LAST  ATOM_LCD_INFO_V13
3482
3483 //Definitions for ucLCD_Misc
3484 #define ATOM_PANEL_MISC_V13_DUAL                   0x00000001
3485 #define ATOM_PANEL_MISC_V13_FPDI                   0x00000002
3486 #define ATOM_PANEL_MISC_V13_GREY_LEVEL             0x0000000C
3487 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT       2
3488 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
3489 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR         0x10
3490 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR         0x20
3491
3492 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3493 //Bit 6  5  4
3494                               //      0  0  0  -  Color bit depth is undefined
3495                               //      0  0  1  -  6 Bits per Primary Color
3496                               //      0  1  0  -  8 Bits per Primary Color
3497                               //      0  1  1  - 10 Bits per Primary Color
3498                               //      1  0  0  - 12 Bits per Primary Color
3499                               //      1  0  1  - 14 Bits per Primary Color
3500                               //      1  1  0  - 16 Bits per Primary Color
3501                               //      1  1  1  - Reserved
3502
3503 //Definitions for ucLCDPanel_SpecialHandlingCap:
3504
3505 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3506 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3507 #define LCDPANEL_CAP_V13_READ_EDID              0x1        // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3508
3509 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3510 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3511 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3512 #define LCDPANEL_CAP_V13_DRR_SUPPORTED          0x2        // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
3513
3514 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3515 #define LCDPANEL_CAP_V13_eDP                    0x4        // = LCDPANEL_CAP_eDP no change comparing to previous version
3516
3517 //uceDPToLVDSRxId
3518 #define eDP_TO_LVDS_RX_DISABLE                  0x00       // no eDP->LVDS translator chip
3519 #define eDP_TO_LVDS_COMMON_ID                   0x01       // common eDP->LVDS translator chip without AMD SW init
3520 #define eDP_TO_LVDS_RT_ID                       0x02       // RT tanslator which require AMD SW init
3521
3522 typedef struct  _ATOM_PATCH_RECORD_MODE
3523 {
3524   UCHAR     ucRecordType;
3525   USHORT    usHDisp;
3526   USHORT    usVDisp;
3527 }ATOM_PATCH_RECORD_MODE;
3528
3529 typedef struct  _ATOM_LCD_RTS_RECORD
3530 {
3531   UCHAR     ucRecordType;
3532   UCHAR     ucRTSValue;
3533 }ATOM_LCD_RTS_RECORD;
3534
3535 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
3536 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
3537 typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
3538 {
3539   UCHAR     ucRecordType;
3540   USHORT    usLCDCap;
3541 }ATOM_LCD_MODE_CONTROL_CAP;
3542
3543 #define LCD_MODE_CAP_BL_OFF                   1
3544 #define LCD_MODE_CAP_CRTC_OFF                 2
3545 #define LCD_MODE_CAP_PANEL_OFF                4
3546
3547 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
3548 {
3549   UCHAR ucRecordType;
3550   UCHAR ucFakeEDIDLength;
3551   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
3552 } ATOM_FAKE_EDID_PATCH_RECORD;
3553
3554 typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
3555 {
3556    UCHAR    ucRecordType;
3557    USHORT               usHSize;
3558    USHORT               usVSize;
3559 }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
3560
3561 #define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
3562 #define LCD_RTS_RECORD_TYPE                   2
3563 #define LCD_CAP_RECORD_TYPE                   3
3564 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
3565 #define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
3566 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE     6
3567 #define ATOM_RECORD_END_TYPE                  0xFF
3568
3569 /****************************Spread Spectrum Info Table Definitions **********************/
3570
3571 //ucTableFormatRevision=1
3572 //ucTableContentRevision=2
3573 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
3574 {
3575   USHORT              usSpreadSpectrumPercentage;
3576   UCHAR               ucSpreadSpectrumType;         //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS  Others:TBD
3577   UCHAR               ucSS_Step;
3578   UCHAR               ucSS_Delay;
3579   UCHAR               ucSS_Id;
3580   UCHAR               ucRecommendedRef_Div;
3581   UCHAR               ucSS_Range;               //it was reserved for V11
3582 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
3583
3584 #define ATOM_MAX_SS_ENTRY                      16
3585 #define ATOM_DP_SS_ID1                                                                                           0x0f1                  // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3586 #define ATOM_DP_SS_ID2                                                                                           0x0f2                  // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3587 #define ATOM_LVLINK_2700MHz_SS_ID              0x0f3      // SS ID for LV link translator chip at 2.7Ghz
3588 #define ATOM_LVLINK_1620MHz_SS_ID              0x0f4      // SS ID for LV link translator chip at 1.62Ghz
3589
3590
3591 #define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
3592 #define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
3593 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
3594 #define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
3595 #define ATOM_INTERNAL_SS_MASK                  0x00000000
3596 #define ATOM_EXTERNAL_SS_MASK                  0x00000002
3597 #define EXEC_SS_STEP_SIZE_SHIFT                2
3598 #define EXEC_SS_DELAY_SHIFT                    4
3599 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
3600
3601 typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3602 {
3603   ATOM_COMMON_TABLE_HEADER      sHeader;
3604   ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
3605 }ATOM_SPREAD_SPECTRUM_INFO;
3606
3607 /****************************************************************************/
3608 // Structure used in AnalogTV_InfoTable (Top level)
3609 /****************************************************************************/
3610 //ucTVBootUpDefaultStd definition:
3611
3612 //ATOM_TV_NTSC                1
3613 //ATOM_TV_NTSCJ               2
3614 //ATOM_TV_PAL                 3
3615 //ATOM_TV_PALM                4
3616 //ATOM_TV_PALCN               5
3617 //ATOM_TV_PALN                6
3618 //ATOM_TV_PAL60               7
3619 //ATOM_TV_SECAM               8
3620
3621 //ucTVSupportedStd definition:
3622 #define NTSC_SUPPORT          0x1
3623 #define NTSCJ_SUPPORT         0x2
3624
3625 #define PAL_SUPPORT           0x4
3626 #define PALM_SUPPORT          0x8
3627 #define PALCN_SUPPORT         0x10
3628 #define PALN_SUPPORT          0x20
3629 #define PAL60_SUPPORT         0x40
3630 #define SECAM_SUPPORT         0x80
3631
3632 #define MAX_SUPPORTED_TV_TIMING    2
3633
3634 typedef struct _ATOM_ANALOG_TV_INFO
3635 {
3636   ATOM_COMMON_TABLE_HEADER sHeader;
3637   UCHAR                    ucTV_SupportedStandard;
3638   UCHAR                    ucTV_BootUpDefaultStandard;
3639   UCHAR                    ucExt_TV_ASIC_ID;
3640   UCHAR                    ucExt_TV_ASIC_SlaveAddr;
3641   /*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
3642   ATOM_MODE_TIMING         aModeTimings[MAX_SUPPORTED_TV_TIMING];
3643 }ATOM_ANALOG_TV_INFO;
3644
3645 #define MAX_SUPPORTED_TV_TIMING_V1_2    3
3646
3647 typedef struct _ATOM_ANALOG_TV_INFO_V1_2
3648 {
3649   ATOM_COMMON_TABLE_HEADER sHeader;
3650   UCHAR                    ucTV_SupportedStandard;
3651   UCHAR                    ucTV_BootUpDefaultStandard;
3652   UCHAR                    ucExt_TV_ASIC_ID;
3653   UCHAR                    ucExt_TV_ASIC_SlaveAddr;
3654   ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
3655 }ATOM_ANALOG_TV_INFO_V1_2;
3656
3657 typedef struct _ATOM_DPCD_INFO
3658 {
3659   UCHAR   ucRevisionNumber;        //10h : Revision 1.0; 11h : Revision 1.1
3660   UCHAR   ucMaxLinkRate;           //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3661   UCHAR   ucMaxLane;               //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3662   UCHAR   ucMaxDownSpread;         //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3663 }ATOM_DPCD_INFO;
3664
3665 #define ATOM_DPCD_MAX_LANE_MASK    0x1F
3666
3667 /**************************************************************************/
3668 // VRAM usage and their defintions
3669
3670 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
3671 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
3672 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
3673 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
3674 // To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3675
3676 #ifndef VESA_MEMORY_IN_64K_BLOCK
3677 #define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
3678 #endif
3679
3680 #define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
3681 #define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
3682 #define ATOM_HWICON_INFOTABLE_SIZE      32
3683 #define MAX_DTD_MODE_IN_VRAM            6
3684 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
3685 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
3686 //20 bytes for Encoder Type and DPCD in STD EDID area
3687 #define DFP_ENCODER_TYPE_OFFSET         (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3688 #define ATOM_DP_DPCD_OFFSET             (DFP_ENCODER_TYPE_OFFSET + 4 )
3689
3690 #define ATOM_HWICON1_SURFACE_ADDR       0
3691 #define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3692 #define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3693 #define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
3694 #define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3695 #define ATOM_CRT1_STD_MODE_TBL_ADDR         (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3696
3697 #define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3698 #define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3699 #define ATOM_LCD1_STD_MODE_TBL_ADDR     (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3700
3701 #define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3702
3703 #define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3704 #define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3705 #define ATOM_DFP1_STD_MODE_TBL_ADDR         (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3706
3707 #define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3708 #define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3709 #define ATOM_CRT2_STD_MODE_TBL_ADDR         (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3710
3711 #define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3712 #define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3713 #define ATOM_LCD2_STD_MODE_TBL_ADDR     (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3714
3715 #define ATOM_DFP6_EDID_ADDR             (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3716 #define ATOM_DFP6_DTD_MODE_TBL_ADDR     (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3717 #define ATOM_DFP6_STD_MODE_TBL_ADDR     (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3718
3719 #define ATOM_DFP2_EDID_ADDR             (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3720 #define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3721 #define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3722
3723 #define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3724 #define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3725 #define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3726
3727 #define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3728 #define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3729 #define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3730
3731 #define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3732 #define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3733 #define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3734
3735 #define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3736 #define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3737 #define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3738
3739 #define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3740
3741 #define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3742 #define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START + 512
3743
3744 //The size below is in Kb!
3745 #define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3746
3747 #define ATOM_VRAM_RESERVE_V2_SIZE      32
3748
3749 #define ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
3750 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
3751 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
3752 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
3753
3754 /***********************************************************************************/
3755 // Structure used in VRAM_UsageByFirmwareTable
3756 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
3757 //        at running time.
3758 // note2: From RV770, the memory is more than 32bit addressable, so we will change
3759 //        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
3760 //        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
3761 //        (in offset to start of memory address) is KB aligned instead of byte aligend.
3762 /***********************************************************************************/
3763 // Note3:
3764 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
3765 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can  have:
3766
3767 If (ulStartAddrUsedByFirmware!=0)
3768 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3769 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
3770 else    //Non VGA case
3771  if (FB_Size<=2Gb)
3772     FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3773  else
3774           FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3775
3776 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
3777
3778 /***********************************************************************************/
3779 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO                       1
3780
3781 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
3782 {
3783   ULONG   ulStartAddrUsedByFirmware;
3784   USHORT  usFirmwareUseInKb;
3785   USHORT  usReserved;
3786 }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
3787
3788 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
3789 {
3790   ATOM_COMMON_TABLE_HEADER sHeader;
3791   ATOM_FIRMWARE_VRAM_RESERVE_INFO       asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3792 }ATOM_VRAM_USAGE_BY_FIRMWARE;
3793
3794 // change verion to 1.5, when allow driver to allocate the vram area for command table access.
3795 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
3796 {
3797   ULONG   ulStartAddrUsedByFirmware;
3798   USHORT  usFirmwareUseInKb;
3799   USHORT  usFBUsedByDrvInKb;
3800 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
3801
3802 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
3803 {
3804   ATOM_COMMON_TABLE_HEADER sHeader;
3805   ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5  asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3806 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
3807
3808 /****************************************************************************/
3809 // Structure used in GPIO_Pin_LUTTable
3810 /****************************************************************************/
3811 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3812 {
3813   USHORT                   usGpioPin_AIndex;
3814   UCHAR                    ucGpioPinBitShift;
3815   UCHAR                    ucGPIO_ID;
3816 }ATOM_GPIO_PIN_ASSIGNMENT;
3817
3818 typedef struct _ATOM_GPIO_PIN_LUT
3819 {
3820   ATOM_COMMON_TABLE_HEADER  sHeader;
3821   ATOM_GPIO_PIN_ASSIGNMENT      asGPIO_Pin[1];
3822 }ATOM_GPIO_PIN_LUT;
3823
3824 /****************************************************************************/
3825 // Structure used in ComponentVideoInfoTable
3826 /****************************************************************************/
3827 #define GPIO_PIN_ACTIVE_HIGH          0x1
3828
3829 #define MAX_SUPPORTED_CV_STANDARDS    5
3830
3831 // definitions for ATOM_D_INFO.ucSettings
3832 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
3833 #define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
3834 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
3835
3836 typedef struct _ATOM_GPIO_INFO
3837 {
3838   USHORT  usAOffset;
3839   UCHAR   ucSettings;
3840   UCHAR   ucReserved;
3841 }ATOM_GPIO_INFO;
3842
3843 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
3844 #define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
3845
3846 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
3847 #define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
3848 #define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
3849
3850 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
3851 //Line 3 out put 5V.
3852 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
3853 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
3854 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
3855
3856 //Line 3 out put 2.2V
3857 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
3858 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
3859 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
3860
3861 //Line 3 out put 0V
3862 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
3863 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
3864 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
3865
3866 #define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
3867
3868 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
3869
3870 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
3871 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3872 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
3873
3874
3875 typedef struct _ATOM_COMPONENT_VIDEO_INFO
3876 {
3877   ATOM_COMMON_TABLE_HEADER sHeader;
3878   USHORT             usMask_PinRegisterIndex;
3879   USHORT             usEN_PinRegisterIndex;
3880   USHORT             usY_PinRegisterIndex;
3881   USHORT             usA_PinRegisterIndex;
3882   UCHAR              ucBitShift;
3883   UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
3884   ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
3885   UCHAR              ucMiscInfo;
3886   UCHAR              uc480i;
3887   UCHAR              uc480p;
3888   UCHAR              uc720p;
3889   UCHAR              uc1080i;
3890   UCHAR              ucLetterBoxMode;
3891   UCHAR              ucReserved[3];
3892   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3893   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3894   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3895 }ATOM_COMPONENT_VIDEO_INFO;
3896
3897 //ucTableFormatRevision=2
3898 //ucTableContentRevision=1
3899 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
3900 {
3901   ATOM_COMMON_TABLE_HEADER sHeader;
3902   UCHAR              ucMiscInfo;
3903   UCHAR              uc480i;
3904   UCHAR              uc480p;
3905   UCHAR              uc720p;
3906   UCHAR              uc1080i;
3907   UCHAR              ucReserved;
3908   UCHAR              ucLetterBoxMode;
3909   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
3910   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
3911   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
3912 }ATOM_COMPONENT_VIDEO_INFO_V21;
3913
3914 #define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
3915
3916 /****************************************************************************/
3917 // Structure used in object_InfoTable
3918 /****************************************************************************/
3919 typedef struct _ATOM_OBJECT_HEADER
3920 {
3921   ATOM_COMMON_TABLE_HEADER      sHeader;
3922   USHORT                    usDeviceSupport;
3923   USHORT                    usConnectorObjectTableOffset;
3924   USHORT                    usRouterObjectTableOffset;
3925   USHORT                    usEncoderObjectTableOffset;
3926   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
3927   USHORT                    usDisplayPathTableOffset;
3928 }ATOM_OBJECT_HEADER;
3929
3930 typedef struct _ATOM_OBJECT_HEADER_V3
3931 {
3932   ATOM_COMMON_TABLE_HEADER      sHeader;
3933   USHORT                    usDeviceSupport;
3934   USHORT                    usConnectorObjectTableOffset;
3935   USHORT                    usRouterObjectTableOffset;
3936   USHORT                    usEncoderObjectTableOffset;
3937   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
3938   USHORT                    usDisplayPathTableOffset;
3939   USHORT                    usMiscObjectTableOffset;
3940 }ATOM_OBJECT_HEADER_V3;
3941
3942 typedef struct  _ATOM_DISPLAY_OBJECT_PATH
3943 {
3944   USHORT    usDeviceTag;                                   //supported device
3945   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
3946   USHORT    usConnObjectId;                                //Connector Object ID
3947   USHORT    usGPUObjectId;                                 //GPU ID
3948   USHORT    usGraphicObjIds[1];                             //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
3949 }ATOM_DISPLAY_OBJECT_PATH;
3950
3951 typedef struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
3952 {
3953   USHORT    usDeviceTag;                                   //supported device
3954   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
3955   USHORT    usConnObjectId;                                //Connector Object ID
3956   USHORT    usGPUObjectId;                                 //GPU ID
3957   USHORT    usGraphicObjIds[2];                            //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
3958 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
3959
3960 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
3961 {
3962   UCHAR                           ucNumOfDispPath;
3963   UCHAR                           ucVersion;
3964   UCHAR                           ucPadding[2];
3965   ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
3966 }ATOM_DISPLAY_OBJECT_PATH_TABLE;
3967
3968
3969 typedef struct _ATOM_OBJECT                                //each object has this structure
3970 {
3971   USHORT              usObjectID;
3972   USHORT              usSrcDstTableOffset;
3973   USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
3974   USHORT              usReserved;
3975 }ATOM_OBJECT;
3976
3977 typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure
3978 {
3979   UCHAR               ucNumberOfObjects;
3980   UCHAR               ucPadding[3];
3981   ATOM_OBJECT         asObjects[1];
3982 }ATOM_OBJECT_TABLE;
3983
3984 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
3985 {
3986   UCHAR               ucNumberOfSrc;
3987   USHORT              usSrcObjectID[1];
3988   UCHAR               ucNumberOfDst;
3989   USHORT              usDstObjectID[1];
3990 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
3991
3992
3993 //Two definitions below are for OPM on MXM module designs
3994
3995 #define EXT_HPDPIN_LUTINDEX_0                   0
3996 #define EXT_HPDPIN_LUTINDEX_1                   1
3997 #define EXT_HPDPIN_LUTINDEX_2                   2
3998 #define EXT_HPDPIN_LUTINDEX_3                   3
3999 #define EXT_HPDPIN_LUTINDEX_4                   4
4000 #define EXT_HPDPIN_LUTINDEX_5                   5
4001 #define EXT_HPDPIN_LUTINDEX_6                   6
4002 #define EXT_HPDPIN_LUTINDEX_7                   7
4003 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
4004
4005 #define EXT_AUXDDC_LUTINDEX_0                   0
4006 #define EXT_AUXDDC_LUTINDEX_1                   1
4007 #define EXT_AUXDDC_LUTINDEX_2                   2
4008 #define EXT_AUXDDC_LUTINDEX_3                   3
4009 #define EXT_AUXDDC_LUTINDEX_4                   4
4010 #define EXT_AUXDDC_LUTINDEX_5                   5
4011 #define EXT_AUXDDC_LUTINDEX_6                   6
4012 #define EXT_AUXDDC_LUTINDEX_7                   7
4013 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
4014
4015 //ucChannelMapping are defined as following
4016 //for DP connector, eDP, DP to VGA/LVDS
4017 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4018 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4019 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4020 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4021 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4022 {
4023 #if ATOM_BIG_ENDIAN
4024   UCHAR ucDP_Lane3_Source:2;
4025   UCHAR ucDP_Lane2_Source:2;
4026   UCHAR ucDP_Lane1_Source:2;
4027   UCHAR ucDP_Lane0_Source:2;
4028 #else
4029   UCHAR ucDP_Lane0_Source:2;
4030   UCHAR ucDP_Lane1_Source:2;
4031   UCHAR ucDP_Lane2_Source:2;
4032   UCHAR ucDP_Lane3_Source:2;
4033 #endif
4034 }ATOM_DP_CONN_CHANNEL_MAPPING;
4035
4036 //for DVI/HDMI, in dual link case, both links have to have same mapping.
4037 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4038 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4039 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4040 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4041 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4042 {
4043 #if ATOM_BIG_ENDIAN
4044   UCHAR ucDVI_CLK_Source:2;
4045   UCHAR ucDVI_DATA0_Source:2;
4046   UCHAR ucDVI_DATA1_Source:2;
4047   UCHAR ucDVI_DATA2_Source:2;
4048 #else
4049   UCHAR ucDVI_DATA2_Source:2;
4050   UCHAR ucDVI_DATA1_Source:2;
4051   UCHAR ucDVI_DATA0_Source:2;
4052   UCHAR ucDVI_CLK_Source:2;
4053 #endif
4054 }ATOM_DVI_CONN_CHANNEL_MAPPING;
4055
4056 typedef struct _EXT_DISPLAY_PATH
4057 {
4058   USHORT  usDeviceTag;                    //A bit vector to show what devices are supported
4059   USHORT  usDeviceACPIEnum;               //16bit device ACPI id.
4060   USHORT  usDeviceConnector;              //A physical connector for displays to plug in, using object connector definitions
4061   UCHAR   ucExtAUXDDCLutIndex;            //An index into external AUX/DDC channel LUT
4062   UCHAR   ucExtHPDPINLutIndex;            //An index into external HPD pin LUT
4063   USHORT  usExtEncoderObjId;              //external encoder object id
4064   union{
4065     UCHAR   ucChannelMapping;                  // if ucChannelMapping=0, using default one to one mapping
4066     ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4067     ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4068   };
4069   UCHAR   ucChPNInvert;                   // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4070   USHORT  usCaps;
4071   USHORT  usReserved;
4072 }EXT_DISPLAY_PATH;
4073
4074 #define NUMBER_OF_UCHAR_FOR_GUID          16
4075 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
4076
4077 //usCaps
4078 #define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE          0x01
4079
4080 typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4081 {
4082   ATOM_COMMON_TABLE_HEADER sHeader;
4083   UCHAR                    ucGuid [NUMBER_OF_UCHAR_FOR_GUID];     // a GUID is a 16 byte long string
4084   EXT_DISPLAY_PATH         sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4085   UCHAR                    ucChecksum;                            // a  simple Checksum of the sum of whole structure equal to 0x0.
4086   UCHAR                    uc3DStereoPinId;                       // use for eDP panel
4087   UCHAR                    ucRemoteDisplayConfig;
4088   UCHAR                    uceDPToLVDSRxId;
4089   UCHAR                    Reserved[4];                           // for potential expansion
4090 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4091
4092 //Related definitions, all records are different but they have a commond header
4093 typedef struct _ATOM_COMMON_RECORD_HEADER
4094 {
4095   UCHAR               ucRecordType;                      //An emun to indicate the record type
4096   UCHAR               ucRecordSize;                      //The size of the whole record in byte
4097 }ATOM_COMMON_RECORD_HEADER;
4098
4099
4100 #define ATOM_I2C_RECORD_TYPE                           1
4101 #define ATOM_HPD_INT_RECORD_TYPE                       2
4102 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
4103 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
4104 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE             5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4105 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4106 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
4107 #define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4108 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
4109 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
4110 #define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
4111 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE       12
4112 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
4113 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE       14
4114 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE  15
4115 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE          16 //This is for the case when connectors are not known to object table
4116 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE          17 //This is for the case when connectors are not known to object table
4117 #define ATOM_OBJECT_LINK_RECORD_TYPE                   18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4118 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
4119 #define ATOM_ENCODER_CAP_RECORD_TYPE                   20
4120
4121
4122 //Must be updated when new record type is added,equal to that record definition!
4123 #define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_ENCODER_CAP_RECORD_TYPE
4124
4125 typedef struct  _ATOM_I2C_RECORD
4126 {
4127   ATOM_COMMON_RECORD_HEADER   sheader;
4128   ATOM_I2C_ID_CONFIG          sucI2cId;
4129   UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
4130 }ATOM_I2C_RECORD;
4131
4132 typedef struct  _ATOM_HPD_INT_RECORD
4133 {
4134   ATOM_COMMON_RECORD_HEADER   sheader;
4135   UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info
4136   UCHAR                       ucPlugged_PinState;
4137 }ATOM_HPD_INT_RECORD;
4138
4139
4140 typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
4141 {
4142   ATOM_COMMON_RECORD_HEADER   sheader;
4143   UCHAR                       ucProtectionFlag;
4144   UCHAR                       ucReserved;
4145 }ATOM_OUTPUT_PROTECTION_RECORD;
4146
4147 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
4148 {
4149   ULONG                       ulACPIDeviceEnum;       //Reserved for now
4150   USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4151   USHORT                      usPadding;
4152 }ATOM_CONNECTOR_DEVICE_TAG;
4153
4154 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4155 {
4156   ATOM_COMMON_RECORD_HEADER   sheader;
4157   UCHAR                       ucNumberOfDevice;
4158   UCHAR                       ucReserved;
4159   ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4160 }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4161
4162
4163 typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4164 {
4165   ATOM_COMMON_RECORD_HEADER   sheader;
4166   UCHAR                                                     ucConfigGPIOID;
4167   UCHAR                                                     ucConfigGPIOState;      //Set to 1 when it's active high to enable external flow in
4168   UCHAR                       ucFlowinGPIPID;
4169   UCHAR                       ucExtInGPIPID;
4170 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4171
4172 typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
4173 {
4174   ATOM_COMMON_RECORD_HEADER   sheader;
4175   UCHAR                       ucCTL1GPIO_ID;
4176   UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
4177   UCHAR                       ucCTL2GPIO_ID;
4178   UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
4179   UCHAR                       ucCTL3GPIO_ID;
4180   UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
4181   UCHAR                       ucCTLFPGA_IN_ID;
4182   UCHAR                       ucPadding[3];
4183 }ATOM_ENCODER_FPGA_CONTROL_RECORD;
4184
4185 typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4186 {
4187   ATOM_COMMON_RECORD_HEADER   sheader;
4188   UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
4189   UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
4190 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4191
4192 typedef struct  _ATOM_JTAG_RECORD
4193 {
4194   ATOM_COMMON_RECORD_HEADER   sheader;
4195   UCHAR                       ucTMSGPIO_ID;
4196   UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
4197   UCHAR                       ucTCKGPIO_ID;
4198   UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
4199   UCHAR                       ucTDOGPIO_ID;
4200   UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
4201   UCHAR                       ucTDIGPIO_ID;
4202   UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
4203   UCHAR                       ucPadding[2];
4204 }ATOM_JTAG_RECORD;
4205
4206
4207 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4208 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4209 {
4210   UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
4211   UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
4212 }ATOM_GPIO_PIN_CONTROL_PAIR;
4213
4214 typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
4215 {
4216   ATOM_COMMON_RECORD_HEADER   sheader;
4217   UCHAR                       ucFlags;                // Future expnadibility
4218   UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
4219   ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
4220 }ATOM_OBJECT_GPIO_CNTL_RECORD;
4221
4222 //Definitions for GPIO pin state
4223 #define GPIO_PIN_TYPE_INPUT             0x00
4224 #define GPIO_PIN_TYPE_OUTPUT            0x10
4225 #define GPIO_PIN_TYPE_HW_CONTROL        0x20
4226
4227 //For GPIO_PIN_TYPE_OUTPUT the following is defined
4228 #define GPIO_PIN_OUTPUT_STATE_MASK      0x01
4229 #define GPIO_PIN_OUTPUT_STATE_SHIFT     0
4230 #define GPIO_PIN_STATE_ACTIVE_LOW       0x0
4231 #define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
4232
4233 // Indexes to GPIO array in GLSync record
4234 // GLSync record is for Frame Lock/Gen Lock feature.
4235 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK    0
4236 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC     1
4237 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC     2
4238 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  3
4239 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  4
4240 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4241 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
4242 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4243 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  8
4244 #define ATOM_GPIO_INDEX_GLSYNC_MAX       9
4245
4246 typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
4247 {
4248   ATOM_COMMON_RECORD_HEADER   sheader;
4249   ULONG                       ulStrengthControl;      // DVOA strength control for CF
4250   UCHAR                       ucPadding[2];
4251 }ATOM_ENCODER_DVO_CF_RECORD;
4252
4253 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
4254 #define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder
4255 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN               0x02         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4256
4257 typedef struct  _ATOM_ENCODER_CAP_RECORD
4258 {
4259   ATOM_COMMON_RECORD_HEADER   sheader;
4260   union {
4261     USHORT                    usEncoderCap;
4262     struct {
4263 #if ATOM_BIG_ENDIAN
4264       USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
4265       USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
4266       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
4267 #else
4268       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
4269       USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
4270       USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
4271 #endif
4272     };
4273   };
4274 }ATOM_ENCODER_CAP_RECORD;
4275
4276 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4277 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
4278 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
4279
4280 typedef struct  _ATOM_CONNECTOR_CF_RECORD
4281 {
4282   ATOM_COMMON_RECORD_HEADER   sheader;
4283   USHORT                      usMaxPixClk;
4284   UCHAR                       ucFlowCntlGpioId;
4285   UCHAR                       ucSwapCntlGpioId;
4286   UCHAR                       ucConnectedDvoBundle;
4287   UCHAR                       ucPadding;
4288 }ATOM_CONNECTOR_CF_RECORD;
4289
4290 typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4291 {
4292   ATOM_COMMON_RECORD_HEADER   sheader;
4293         ATOM_DTD_FORMAT                                                 asTiming;
4294 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4295
4296 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4297 {
4298   ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4299   UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4300   UCHAR                       ucReserved;
4301 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4302
4303
4304 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4305 {
4306         ATOM_COMMON_RECORD_HEADER   sheader;
4307         UCHAR                                                                                           ucMuxType;                                                      //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4308         UCHAR                                                                                           ucMuxControlPin;
4309         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
4310 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4311
4312 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4313 {
4314         ATOM_COMMON_RECORD_HEADER   sheader;
4315         UCHAR                                                                                           ucMuxType;
4316         UCHAR                                                                                           ucMuxControlPin;
4317         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
4318 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4319
4320 // define ucMuxType
4321 #define ATOM_ROUTER_MUX_PIN_STATE_MASK                                                          0x0f
4322 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT             0x01
4323
4324 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4325 {
4326   ATOM_COMMON_RECORD_HEADER   sheader;
4327   UCHAR                       ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES];  //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4328 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4329
4330 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD  //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4331 {
4332   ATOM_COMMON_RECORD_HEADER   sheader;
4333   ATOM_I2C_ID_CONFIG          ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES];  //An fixed size array which maps external pins to internal DDC ID
4334 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4335
4336 typedef struct _ATOM_OBJECT_LINK_RECORD
4337 {
4338   ATOM_COMMON_RECORD_HEADER   sheader;
4339   USHORT                      usObjectID;         //could be connector, encorder or other object in object.h
4340 }ATOM_OBJECT_LINK_RECORD;
4341
4342 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4343 {
4344   ATOM_COMMON_RECORD_HEADER   sheader;
4345   USHORT                      usReserved;
4346 }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4347
4348 /****************************************************************************/
4349 // ASIC voltage data table
4350 /****************************************************************************/
4351 typedef struct  _ATOM_VOLTAGE_INFO_HEADER
4352 {
4353    USHORT   usVDDCBaseLevel;                //In number of 50mv unit
4354    USHORT   usReserved;                     //For possible extension table offset
4355    UCHAR    ucNumOfVoltageEntries;
4356    UCHAR    ucBytesPerVoltageEntry;
4357    UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
4358    UCHAR    ucDefaultVoltageEntry;
4359    UCHAR    ucVoltageControlI2cLine;
4360    UCHAR    ucVoltageControlAddress;
4361    UCHAR    ucVoltageControlOffset;
4362 }ATOM_VOLTAGE_INFO_HEADER;
4363
4364 typedef struct  _ATOM_VOLTAGE_INFO
4365 {
4366    ATOM_COMMON_TABLE_HEADER     sHeader;
4367    ATOM_VOLTAGE_INFO_HEADER viHeader;
4368    UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
4369 }ATOM_VOLTAGE_INFO;
4370
4371
4372 typedef struct  _ATOM_VOLTAGE_FORMULA
4373 {
4374    USHORT   usVoltageBaseLevel;             // In number of 1mv unit
4375    USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
4376          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
4377          UCHAR          ucFlag;                                                                                                 // bit0=0 :step is 1mv =1 0.5mv
4378          UCHAR          ucBaseVID;                                                                                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
4379          UCHAR          ucReserved;
4380          UCHAR          ucVIDAdjustEntries[32];                                 // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
4381 }ATOM_VOLTAGE_FORMULA;
4382
4383 typedef struct  _VOLTAGE_LUT_ENTRY
4384 {
4385          USHORT         usVoltageCode;                                                                  // The Voltage ID, either GPIO or I2C code
4386          USHORT         usVoltageValue;                                                                 // The corresponding Voltage Value, in mV
4387 }VOLTAGE_LUT_ENTRY;
4388
4389 typedef struct  _ATOM_VOLTAGE_FORMULA_V2
4390 {
4391          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
4392          UCHAR          ucReserved[3];
4393          VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
4394 }ATOM_VOLTAGE_FORMULA_V2;
4395
4396 typedef struct _ATOM_VOLTAGE_CONTROL
4397 {
4398         UCHAR            ucVoltageControlId;                                                    //Indicate it is controlled by I2C or GPIO or HW state machine
4399   UCHAR    ucVoltageControlI2cLine;
4400   UCHAR    ucVoltageControlAddress;
4401   UCHAR    ucVoltageControlOffset;
4402   USHORT   usGpioPin_AIndex;                                                            //GPIO_PAD register index
4403   UCHAR    ucGpioPinBitShift[9];                                                //at most 8 pin support 255 VIDs, termintate with 0xff
4404         UCHAR            ucReserved;
4405 }ATOM_VOLTAGE_CONTROL;
4406
4407 // Define ucVoltageControlId
4408 #define VOLTAGE_CONTROLLED_BY_HW                                                        0x00
4409 #define VOLTAGE_CONTROLLED_BY_I2C_MASK                          0x7F
4410 #define VOLTAGE_CONTROLLED_BY_GPIO                                              0x80
4411 #define VOLTAGE_CONTROL_ID_LM64                                                         0x01                                                                    //I2C control, used for R5xx Core Voltage
4412 #define VOLTAGE_CONTROL_ID_DAC                                                          0x02                                                                    //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
4413 #define VOLTAGE_CONTROL_ID_VT116xM                                              0x03                                                                    //I2C control, used for R6xx Core Voltage
4414 #define VOLTAGE_CONTROL_ID_DS4402                                                       0x04
4415 #define VOLTAGE_CONTROL_ID_UP6266                                               0x05
4416 #define VOLTAGE_CONTROL_ID_SCORPIO                                              0x06
4417 #define VOLTAGE_CONTROL_ID_VT1556M                                              0x07
4418 #define VOLTAGE_CONTROL_ID_CHL822x                                              0x08
4419 #define VOLTAGE_CONTROL_ID_VT1586M                                              0x09
4420 #define VOLTAGE_CONTROL_ID_UP1637                                               0x0A
4421
4422 typedef struct  _ATOM_VOLTAGE_OBJECT
4423 {
4424          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4425          UCHAR          ucSize;                                                                                                 //Size of Object
4426          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control
4427          ATOM_VOLTAGE_FORMULA                   asFormula;                      //Indicate How to convert real Voltage to VID
4428 }ATOM_VOLTAGE_OBJECT;
4429
4430 typedef struct  _ATOM_VOLTAGE_OBJECT_V2
4431 {
4432          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4433          UCHAR          ucSize;                                                                                                 //Size of Object
4434          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control
4435          ATOM_VOLTAGE_FORMULA_V2        asFormula;                      //Indicate How to convert real Voltage to VID
4436 }ATOM_VOLTAGE_OBJECT_V2;
4437
4438 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
4439 {
4440    ATOM_COMMON_TABLE_HEADER     sHeader;
4441          ATOM_VOLTAGE_OBJECT                    asVoltageObj[3];        //Info for Voltage control
4442 }ATOM_VOLTAGE_OBJECT_INFO;
4443
4444 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
4445 {
4446    ATOM_COMMON_TABLE_HEADER     sHeader;
4447          ATOM_VOLTAGE_OBJECT_V2                 asVoltageObj[3];        //Info for Voltage control
4448 }ATOM_VOLTAGE_OBJECT_INFO_V2;
4449
4450 typedef struct  _ATOM_LEAKID_VOLTAGE
4451 {
4452         UCHAR           ucLeakageId;
4453         UCHAR           ucReserved;
4454         USHORT  usVoltage;
4455 }ATOM_LEAKID_VOLTAGE;
4456
4457 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
4458          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4459    UCHAR                ucVoltageMode;                                                      //Indicate voltage control mode: Init/Set/Leakage/Set phase
4460          USHORT         usSize;                                                                                                 //Size of Object
4461 }ATOM_VOLTAGE_OBJECT_HEADER_V3;
4462
4463 typedef struct  _VOLTAGE_LUT_ENTRY_V2
4464 {
4465          ULONG          ulVoltageId;                                                                      // The Voltage ID which is used to program GPIO register
4466          USHORT         usVoltageValue;                                                                 // The corresponding Voltage Value, in mV
4467 }VOLTAGE_LUT_ENTRY_V2;
4468
4469 typedef struct  _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
4470 {
4471   USHORT        usVoltageLevel;                                                           // The Voltage ID which is used to program GPIO register
4472   USHORT  usVoltageId;
4473         USHORT  usLeakageId;                                                                      // The corresponding Voltage Value, in mV
4474 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
4475
4476 typedef struct  _ATOM_I2C_VOLTAGE_OBJECT_V3
4477 {
4478    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4479    UCHAR        ucVoltageRegulatorId;                                     //Indicate Voltage Regulator Id
4480    UCHAR    ucVoltageControlI2cLine;
4481    UCHAR    ucVoltageControlAddress;
4482    UCHAR    ucVoltageControlOffset;
4483    ULONG    ulReserved;
4484    VOLTAGE_LUT_ENTRY asVolI2cLut[1];        // end with 0xff
4485 }ATOM_I2C_VOLTAGE_OBJECT_V3;
4486
4487 typedef struct  _ATOM_GPIO_VOLTAGE_OBJECT_V3
4488 {
4489    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4490    UCHAR    ucVoltageGpioCntlId;         // default is 0 which indicate control through CG VID mode
4491    UCHAR    ucGpioEntryNum;              // indiate the entry numbers of Votlage/Gpio value Look up table
4492    UCHAR    ucPhaseDelay;                // phase delay in unit of micro second
4493    UCHAR    ucReserved;
4494    ULONG    ulGpioMaskVal;               // GPIO Mask value
4495    VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
4496 }ATOM_GPIO_VOLTAGE_OBJECT_V3;
4497
4498 typedef struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4499 {
4500    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;
4501    UCHAR    ucLeakageCntlId;             // default is 0
4502    UCHAR    ucLeakageEntryNum;           // indicate the entry number of LeakageId/Voltage Lut table
4503    UCHAR    ucReserved[2];
4504    ULONG    ulMaxVoltageLevel;
4505    LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
4506 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
4507
4508 typedef union _ATOM_VOLTAGE_OBJECT_V3{
4509   ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
4510   ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
4511   ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
4512 }ATOM_VOLTAGE_OBJECT_V3;
4513
4514 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
4515 {
4516    ATOM_COMMON_TABLE_HEADER     sHeader;
4517          ATOM_VOLTAGE_OBJECT_V3                 asVoltageObj[3];        //Info for Voltage control
4518 }ATOM_VOLTAGE_OBJECT_INFO_V3_1;
4519
4520 typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
4521 {
4522         UCHAR           ucProfileId;
4523         UCHAR           ucReserved;
4524         USHORT  usSize;
4525         USHORT  usEfuseSpareStartAddr;
4526         USHORT  usFuseIndex[8];                                                                                         //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
4527         ATOM_LEAKID_VOLTAGE                                     asLeakVol[2];                   //Leakid and relatd voltage
4528 }ATOM_ASIC_PROFILE_VOLTAGE;
4529
4530 //ucProfileId
4531 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                      1
4532 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE                  1
4533 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE                                      2
4534
4535 typedef struct  _ATOM_ASIC_PROFILING_INFO
4536 {
4537   ATOM_COMMON_TABLE_HEADER                      asHeader;
4538         ATOM_ASIC_PROFILE_VOLTAGE                       asVoltage;
4539 }ATOM_ASIC_PROFILING_INFO;
4540
4541 typedef struct _ATOM_POWER_SOURCE_OBJECT
4542 {
4543         UCHAR   ucPwrSrcId;                                                                                                     // Power source
4544         UCHAR   ucPwrSensorType;                                                                                // GPIO, I2C or none
4545         UCHAR   ucPwrSensId;                                                                                      // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
4546         UCHAR   ucPwrSensSlaveAddr;                                                                     // Slave address if I2C detect
4547         UCHAR ucPwrSensRegIndex;                                                                        // I2C register Index if I2C detect
4548         UCHAR ucPwrSensRegBitMask;                                                              // detect which bit is used if I2C detect
4549         UCHAR   ucPwrSensActiveState;                                                           // high active or low active
4550         UCHAR   ucReserve[3];                                                                                           // reserve
4551         USHORT usSensPwr;                                                                                                       // in unit of watt
4552 }ATOM_POWER_SOURCE_OBJECT;
4553
4554 typedef struct _ATOM_POWER_SOURCE_INFO
4555 {
4556                 ATOM_COMMON_TABLE_HEADER                asHeader;
4557                 UCHAR                                                                                           asPwrbehave[16];
4558                 ATOM_POWER_SOURCE_OBJECT                asPwrObj[1];
4559 }ATOM_POWER_SOURCE_INFO;
4560
4561
4562 //Define ucPwrSrcId
4563 #define POWERSOURCE_PCIE_ID1                                            0x00
4564 #define POWERSOURCE_6PIN_CONNECTOR_ID1  0x01
4565 #define POWERSOURCE_8PIN_CONNECTOR_ID1  0x02
4566 #define POWERSOURCE_6PIN_CONNECTOR_ID2  0x04
4567 #define POWERSOURCE_8PIN_CONNECTOR_ID2  0x08
4568
4569 //define ucPwrSensorId
4570 #define POWER_SENSOR_ALWAYS                                                     0x00
4571 #define POWER_SENSOR_GPIO                                                               0x01
4572 #define POWER_SENSOR_I2C                                                                0x02
4573
4574 typedef struct _ATOM_CLK_VOLT_CAPABILITY
4575 {
4576   ULONG      ulVoltageIndex;                      // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
4577   ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
4578 }ATOM_CLK_VOLT_CAPABILITY;
4579
4580 typedef struct _ATOM_AVAILABLE_SCLK_LIST
4581 {
4582   ULONG      ulSupportedSCLK;               // Maximum clock supported with specified voltage index,  unit in 10kHz
4583   USHORT     usVoltageIndex;                // The Voltage Index indicated by FUSE for specified SCLK
4584   USHORT     usVoltageID;                   // The Voltage ID indicated by FUSE for specified SCLK
4585 }ATOM_AVAILABLE_SCLK_LIST;
4586
4587 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
4588 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE             1       // refer to ulSystemConfig bit[0]
4589
4590 // this IntegrateSystemInfoTable is used for Liano/Ontario APU
4591 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
4592 {
4593   ATOM_COMMON_TABLE_HEADER   sHeader;
4594   ULONG  ulBootUpEngineClock;
4595   ULONG  ulDentistVCOFreq;
4596   ULONG  ulBootUpUMAClock;
4597   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
4598   ULONG  ulBootUpReqDisplayVector;
4599   ULONG  ulOtherDisplayMisc;
4600   ULONG  ulGPUCapInfo;
4601   ULONG  ulSB_MMIO_Base_Addr;
4602   USHORT usRequestedPWMFreqInHz;
4603   UCHAR  ucHtcTmpLmt;
4604   UCHAR  ucHtcHystLmt;
4605   ULONG  ulMinEngineClock;
4606   ULONG  ulSystemConfig;
4607   ULONG  ulCPUCapInfo;
4608   USHORT usNBP0Voltage;
4609   USHORT usNBP1Voltage;
4610   USHORT usBootUpNBVoltage;
4611   USHORT usExtDispConnInfoOffset;
4612   USHORT usPanelRefreshRateRange;
4613   UCHAR  ucMemoryType;
4614   UCHAR  ucUMAChannelNumber;
4615   ULONG  ulCSR_M3_ARB_CNTL_DEFAULT[10];
4616   ULONG  ulCSR_M3_ARB_CNTL_UVD[10];
4617   ULONG  ulCSR_M3_ARB_CNTL_FS3D[10];
4618   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
4619   ULONG  ulGMCRestoreResetTime;
4620   ULONG  ulMinimumNClk;
4621   ULONG  ulIdleNClk;
4622   ULONG  ulDDR_DLL_PowerUpTime;
4623   ULONG  ulDDR_PLL_PowerUpTime;
4624   USHORT usPCIEClkSSPercentage;
4625   USHORT usPCIEClkSSType;
4626   USHORT usLvdsSSPercentage;
4627   USHORT usLvdsSSpreadRateIn10Hz;
4628   USHORT usHDMISSPercentage;
4629   USHORT usHDMISSpreadRateIn10Hz;
4630   USHORT usDVISSPercentage;
4631   USHORT usDVISSpreadRateIn10Hz;
4632   ULONG  SclkDpmBoostMargin;
4633   ULONG  SclkDpmThrottleMargin;
4634   USHORT SclkDpmTdpLimitPG;
4635   USHORT SclkDpmTdpLimitBoost;
4636   ULONG  ulBoostEngineCLock;
4637   UCHAR  ulBoostVid_2bit;
4638   UCHAR  EnableBoost;
4639   USHORT GnbTdpLimit;
4640   USHORT usMaxLVDSPclkFreqInSingleLink;
4641   UCHAR  ucLvdsMisc;
4642   UCHAR  ucLVDSReserved;
4643   ULONG  ulReserved3[15];
4644   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4645 }ATOM_INTEGRATED_SYSTEM_INFO_V6;
4646
4647 // ulGPUCapInfo
4648 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE       0x01
4649 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION          0x08
4650
4651 //ucLVDSMisc:
4652 #define SYS_INFO_LVDSMISC__888_FPDI_MODE                                             0x01
4653 #define SYS_INFO_LVDSMISC__DL_CH_SWAP                                                0x02
4654 #define SYS_INFO_LVDSMISC__888_BPC                                                   0x04
4655 #define SYS_INFO_LVDSMISC__OVERRIDE_EN                                               0x08
4656 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW                                           0x10
4657
4658 // not used any more
4659 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW                                          0x04
4660 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW                                          0x08
4661
4662 /**********************************************************************************************************************
4663   ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
4664 ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4665 ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
4666 ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
4667 sDISPCLK_Voltage:                 Report Display clock voltage requirement.
4668
4669 ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
4670                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
4671                                   ATOM_DEVICE_CRT2_SUPPORT                  0x0010
4672                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
4673                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
4674                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080
4675                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200
4676                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400
4677                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
4678                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
4679 ulOtherDisplayMisc:                     Other display related flags, not defined yet.
4680 ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4681                                         =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4682                                   bit[3]=0: Enable HW AUX mode detection logic
4683                                         =1: Disable HW AUX mode dettion logic
4684 ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4685
4686 usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4687                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4688
4689                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4690                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4691                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4692                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4693                                   and enabling VariBri under the driver environment from PP table is optional.
4694
4695                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4696                                   that BL control from GPU is expected.
4697                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4698                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4699                                   it's per platform
4700                                   and enabling VariBri under the driver environment from PP table is optional.
4701
4702 ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4703                                   Threshold on value to enter HTC_active state.
4704 ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
4705                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4706 ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4707 ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
4708                                         =1: PCIE Power Gating Enabled
4709                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
4710                                          1: DDR-DLL shut-down feature enabled.
4711                                   Bit[2]=0: DDR-PLL Power down feature disabled.
4712                                          1: DDR-PLL Power down feature enabled.
4713 ulCPUCapInfo:                     TBD
4714 usNBP0Voltage:                    VID for voltage on NB P0 State
4715 usNBP1Voltage:                    VID for voltage on NB P1 State
4716 usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4717 usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
4718 usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4719                                   to indicate a range.
4720                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
4721                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
4722                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
4723                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
4724 ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4725 ucUMAChannelNumber:                     System memory channel numbers.
4726 ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
4727 ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
4728 ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4729 sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
4730 ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4731 ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4732 ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4733 ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
4734 ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
4735 usPCIEClkSSPercentage:            PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
4736 usPCIEClkSSType:                  PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4737 usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4738 usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4739 usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
4740 usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
4741 usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
4742 usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
4743 usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4744 ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4745                                   [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4746                                   [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
4747                                   [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4748                                   [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4749 **********************************************************************************************************************/
4750
4751 // this Table is used for Liano/Ontario APU
4752 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
4753 {
4754   ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;
4755   ULONG  ulPowerplayTable[128];
4756 }ATOM_FUSION_SYSTEM_INFO_V1;
4757 /**********************************************************************************************************************
4758   ATOM_FUSION_SYSTEM_INFO_V1 Description
4759 sIntegratedSysInfo:               refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
4760 ulPowerplayTable[128]:            This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
4761 **********************************************************************************************************************/
4762
4763 // this IntegrateSystemInfoTable is used for Trinity APU
4764 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
4765 {
4766   ATOM_COMMON_TABLE_HEADER   sHeader;
4767   ULONG  ulBootUpEngineClock;
4768   ULONG  ulDentistVCOFreq;
4769   ULONG  ulBootUpUMAClock;
4770   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
4771   ULONG  ulBootUpReqDisplayVector;
4772   ULONG  ulOtherDisplayMisc;
4773   ULONG  ulGPUCapInfo;
4774   ULONG  ulSB_MMIO_Base_Addr;
4775   USHORT usRequestedPWMFreqInHz;
4776   UCHAR  ucHtcTmpLmt;
4777   UCHAR  ucHtcHystLmt;
4778   ULONG  ulMinEngineClock;
4779   ULONG  ulSystemConfig;
4780   ULONG  ulCPUCapInfo;
4781   USHORT usNBP0Voltage;
4782   USHORT usNBP1Voltage;
4783   USHORT usBootUpNBVoltage;
4784   USHORT usExtDispConnInfoOffset;
4785   USHORT usPanelRefreshRateRange;
4786   UCHAR  ucMemoryType;
4787   UCHAR  ucUMAChannelNumber;
4788   UCHAR  strVBIOSMsg[40];
4789   ULONG  ulReserved[20];
4790   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
4791   ULONG  ulGMCRestoreResetTime;
4792   ULONG  ulMinimumNClk;
4793   ULONG  ulIdleNClk;
4794   ULONG  ulDDR_DLL_PowerUpTime;
4795   ULONG  ulDDR_PLL_PowerUpTime;
4796   USHORT usPCIEClkSSPercentage;
4797   USHORT usPCIEClkSSType;
4798   USHORT usLvdsSSPercentage;
4799   USHORT usLvdsSSpreadRateIn10Hz;
4800   USHORT usHDMISSPercentage;
4801   USHORT usHDMISSpreadRateIn10Hz;
4802   USHORT usDVISSPercentage;
4803   USHORT usDVISSpreadRateIn10Hz;
4804   ULONG  SclkDpmBoostMargin;
4805   ULONG  SclkDpmThrottleMargin;
4806   USHORT SclkDpmTdpLimitPG;
4807   USHORT SclkDpmTdpLimitBoost;
4808   ULONG  ulBoostEngineCLock;
4809   UCHAR  ulBoostVid_2bit;
4810   UCHAR  EnableBoost;
4811   USHORT GnbTdpLimit;
4812   USHORT usMaxLVDSPclkFreqInSingleLink;
4813   UCHAR  ucLvdsMisc;
4814   UCHAR  ucLVDSReserved;
4815   UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
4816   UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
4817   UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
4818   UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
4819   UCHAR  ucLVDSOffToOnDelay_in4Ms;
4820   UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
4821   UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
4822   UCHAR  ucLVDSReserved1;
4823   ULONG  ulLCDBitDepthControlVal;
4824   ULONG  ulNbpStateMemclkFreq[4];
4825   USHORT usNBP2Voltage;
4826   USHORT usNBP3Voltage;
4827   ULONG  ulNbpStateNClkFreq[4];
4828   UCHAR  ucNBDPMEnable;
4829   UCHAR  ucReserved[3];
4830   UCHAR  ucDPMState0VclkFid;
4831   UCHAR  ucDPMState0DclkFid;
4832   UCHAR  ucDPMState1VclkFid;
4833   UCHAR  ucDPMState1DclkFid;
4834   UCHAR  ucDPMState2VclkFid;
4835   UCHAR  ucDPMState2DclkFid;
4836   UCHAR  ucDPMState3VclkFid;
4837   UCHAR  ucDPMState3DclkFid;
4838   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
4839 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
4840
4841 // ulOtherDisplayMisc
4842 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT            0x01
4843 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT  0x02
4844 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT       0x04
4845 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT                         0x08
4846
4847 // ulGPUCapInfo
4848 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
4849 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
4850 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
4851
4852 /**********************************************************************************************************************
4853   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
4854 ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
4855 ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
4856 ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
4857 sDISPCLK_Voltage:                 Report Display clock voltage requirement.
4858
4859 ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
4860                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
4861                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
4862                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
4863                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080
4864                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200
4865                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400
4866                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
4867                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
4868 ulOtherDisplayMisc:                     bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
4869                                         =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
4870                                   bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
4871                                         =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
4872                                   bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
4873                                         =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
4874                                   bit[3]=0: VBIOS fast boot is disable
4875                                         =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
4876 ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
4877                                         =1: TMDS/HDMI Coherent Mode use signel PLL mode.
4878                                   bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
4879                                         =1: DP mode use single PLL mode
4880                                   bit[3]=0: Enable AUX HW mode detection logic
4881                                         =1: Disable AUX HW mode detection logic
4882
4883 ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
4884
4885 usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
4886                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
4887
4888                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
4889                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
4890                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
4891                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4892                                   and enabling VariBri under the driver environment from PP table is optional.
4893
4894                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
4895                                   that BL control from GPU is expected.
4896                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
4897                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
4898                                   it's per platform
4899                                   and enabling VariBri under the driver environment from PP table is optional.
4900
4901 ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
4902                                   Threshold on value to enter HTC_active state.
4903 ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
4904                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
4905 ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
4906 ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
4907                                         =1: PCIE Power Gating Enabled
4908                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
4909                                          1: DDR-DLL shut-down feature enabled.
4910                                   Bit[2]=0: DDR-PLL Power down feature disabled.
4911                                          1: DDR-PLL Power down feature enabled.
4912 ulCPUCapInfo:                     TBD
4913 usNBP0Voltage:                    VID for voltage on NB P0 State
4914 usNBP1Voltage:                    VID for voltage on NB P1 State
4915 usNBP2Voltage:                    VID for voltage on NB P2 State
4916 usNBP3Voltage:                    VID for voltage on NB P3 State
4917 usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
4918 usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
4919 usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
4920                                   to indicate a range.
4921                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
4922                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
4923                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
4924                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
4925 ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4926 ucUMAChannelNumber:                     System memory channel numbers.
4927 ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
4928 ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
4929 ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
4930 sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
4931 ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
4932 ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4933 ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4934 ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
4935 ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
4936 usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
4937 usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
4938 usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
4939 usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
4940 usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
4941 usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
4942 usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
4943 usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
4944 usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
4945 ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
4946                                   [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
4947                                   [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
4948                                   [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
4949                                   [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
4950 ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
4951                                   =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4952                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4953 ucLVDSPwrOnDEtoVARY_BL_in4Ms:     LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
4954                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
4955                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4956
4957 ucLVDSPwrOffVARY_BLtoDE_in4Ms:    LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
4958                                   =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4959                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4960
4961 ucLVDSPwrOffDEtoDIGON_in4Ms:      LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
4962                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
4963                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4964
4965 ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
4966                                   =0 means to use VBIOS default delay which is 125 ( 500ms ).
4967                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4968
4969 ucLVDSPwrOnVARY_BLtoBLON_in4Ms:   LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
4970                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
4971                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4972
4973 ucLVDSPwrOffBLONtoVARY_BL_in4Ms:  LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
4974                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
4975                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
4976
4977 ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB pstate.
4978
4979 **********************************************************************************************************************/
4980
4981 /**************************************************************************/
4982 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
4983 //Memory SS Info Table
4984 //Define Memory Clock SS chip ID
4985 #define ICS91719  1
4986 #define ICS91720  2
4987
4988 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
4989 typedef struct _ATOM_I2C_DATA_RECORD
4990 {
4991   UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
4992   UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
4993 }ATOM_I2C_DATA_RECORD;
4994
4995
4996 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
4997 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
4998 {
4999   ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
5000   UCHAR                                 ucSSChipID;             //SS chip being used
5001   UCHAR                                 ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
5002   UCHAR                           ucNumOfI2CDataRecords;  //number of data block
5003   ATOM_I2C_DATA_RECORD            asI2CData[1];
5004 }ATOM_I2C_DEVICE_SETUP_INFO;
5005
5006 //==========================================================================================
5007 typedef struct  _ATOM_ASIC_MVDD_INFO
5008 {
5009   ATOM_COMMON_TABLE_HEADER            sHeader;
5010   ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
5011 }ATOM_ASIC_MVDD_INFO;
5012
5013 //==========================================================================================
5014 #define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
5015
5016 //==========================================================================================
5017 /**************************************************************************/
5018
5019 typedef struct _ATOM_ASIC_SS_ASSIGNMENT
5020 {
5021         ULONG                                                           ulTargetClockRange;                                             //Clock Out frequence (VCO ), in unit of 10Khz
5022   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
5023         USHORT                                                  usSpreadRateInKhz;                                              //in unit of kHz, modulation freq
5024   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
5025         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit1=0 Down Spread,=1 Center Spread.
5026         UCHAR                                                           ucReserved[2];
5027 }ATOM_ASIC_SS_ASSIGNMENT;
5028
5029 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
5030 //SS is not required or enabled if a match is not found.
5031 #define ASIC_INTERNAL_MEMORY_SS                 1
5032 #define ASIC_INTERNAL_ENGINE_SS                 2
5033 #define ASIC_INTERNAL_UVD_SS        3
5034 #define ASIC_INTERNAL_SS_ON_TMDS    4
5035 #define ASIC_INTERNAL_SS_ON_HDMI    5
5036 #define ASIC_INTERNAL_SS_ON_LVDS    6
5037 #define ASIC_INTERNAL_SS_ON_DP      7
5038 #define ASIC_INTERNAL_SS_ON_DCPLL   8
5039 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
5040 #define ASIC_INTERNAL_VCE_SS        10
5041
5042 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
5043 {
5044         ULONG                                                           ulTargetClockRange;                                             //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5045                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5046   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
5047         USHORT                                                  usSpreadRateIn10Hz;                                             //in unit of 10Hz, modulation freq
5048   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
5049         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5050         UCHAR                                                           ucReserved[2];
5051 }ATOM_ASIC_SS_ASSIGNMENT_V2;
5052
5053 //ucSpreadSpectrumMode
5054 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
5055 //#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
5056 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
5057 //#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
5058 //#define ATOM_INTERNAL_SS_MASK                  0x00000000
5059 //#define ATOM_EXTERNAL_SS_MASK                  0x00000002
5060
5061 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
5062 {
5063   ATOM_COMMON_TABLE_HEADER            sHeader;
5064   ATOM_ASIC_SS_ASSIGNMENT                     asSpreadSpectrum[4];
5065 }ATOM_ASIC_INTERNAL_SS_INFO;
5066
5067 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
5068 {
5069   ATOM_COMMON_TABLE_HEADER            sHeader;
5070   ATOM_ASIC_SS_ASSIGNMENT_V2              asSpreadSpectrum[1];      //this is point only.
5071 }ATOM_ASIC_INTERNAL_SS_INFO_V2;
5072
5073 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
5074 {
5075         ULONG                                                           ulTargetClockRange;                                             //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5076                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5077   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
5078         USHORT                                                  usSpreadRateIn10Hz;                                             //in unit of 10Hz, modulation freq
5079   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
5080         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5081         UCHAR                                                           ucReserved[2];
5082 }ATOM_ASIC_SS_ASSIGNMENT_V3;
5083
5084 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
5085 {
5086   ATOM_COMMON_TABLE_HEADER            sHeader;
5087   ATOM_ASIC_SS_ASSIGNMENT_V3              asSpreadSpectrum[1];      //this is pointer only.
5088 }ATOM_ASIC_INTERNAL_SS_INFO_V3;
5089
5090
5091 //==============================Scratch Pad Definition Portion===============================
5092 #define ATOM_DEVICE_CONNECT_INFO_DEF  0
5093 #define ATOM_ROM_LOCATION_DEF         1
5094 #define ATOM_TV_STANDARD_DEF          2
5095 #define ATOM_ACTIVE_INFO_DEF          3
5096 #define ATOM_LCD_INFO_DEF             4
5097 #define ATOM_DOS_REQ_INFO_DEF         5
5098 #define ATOM_ACC_CHANGE_INFO_DEF      6
5099 #define ATOM_DOS_MODE_INFO_DEF        7
5100 #define ATOM_I2C_CHANNEL_STATUS_DEF   8
5101 #define ATOM_I2C_CHANNEL_STATUS1_DEF  9
5102 #define ATOM_INTERNAL_TIMER_DEF       10
5103
5104 // BIOS_0_SCRATCH Definition
5105 #define ATOM_S0_CRT1_MONO               0x00000001L
5106 #define ATOM_S0_CRT1_COLOR              0x00000002L
5107 #define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
5108
5109 #define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
5110 #define ATOM_S0_TV1_SVIDEO_A            0x00000008L
5111 #define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
5112
5113 #define ATOM_S0_CV_A                    0x00000010L
5114 #define ATOM_S0_CV_DIN_A                0x00000020L
5115 #define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
5116
5117
5118 #define ATOM_S0_CRT2_MONO               0x00000100L
5119 #define ATOM_S0_CRT2_COLOR              0x00000200L
5120 #define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
5121
5122 #define ATOM_S0_TV1_COMPOSITE           0x00000400L
5123 #define ATOM_S0_TV1_SVIDEO              0x00000800L
5124 #define ATOM_S0_TV1_SCART               0x00004000L
5125 #define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
5126
5127 #define ATOM_S0_CV                      0x00001000L
5128 #define ATOM_S0_CV_DIN                  0x00002000L
5129 #define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
5130
5131 #define ATOM_S0_DFP1                    0x00010000L
5132 #define ATOM_S0_DFP2                    0x00020000L
5133 #define ATOM_S0_LCD1                    0x00040000L
5134 #define ATOM_S0_LCD2                    0x00080000L
5135 #define ATOM_S0_DFP6                    0x00100000L
5136 #define ATOM_S0_DFP3                    0x00200000L
5137 #define ATOM_S0_DFP4                    0x00400000L
5138 #define ATOM_S0_DFP5                    0x00800000L
5139
5140 #define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
5141
5142 #define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
5143                                                     // the FAD/HDP reg access bug.  Bit is read by DAL, this is obsolete from RV5xx
5144
5145 #define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
5146 #define ATOM_S0_THERMAL_STATE_SHIFT     26
5147
5148 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
5149 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
5150
5151 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
5152 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
5153 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
5154 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
5155
5156 //Byte aligned definition for BIOS usage
5157 #define ATOM_S0_CRT1_MONOb0             0x01
5158 #define ATOM_S0_CRT1_COLORb0            0x02
5159 #define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
5160
5161 #define ATOM_S0_TV1_COMPOSITEb0         0x04
5162 #define ATOM_S0_TV1_SVIDEOb0            0x08
5163 #define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
5164
5165 #define ATOM_S0_CVb0                    0x10
5166 #define ATOM_S0_CV_DINb0                0x20
5167 #define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
5168
5169 #define ATOM_S0_CRT2_MONOb1             0x01
5170 #define ATOM_S0_CRT2_COLORb1            0x02
5171 #define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
5172
5173 #define ATOM_S0_TV1_COMPOSITEb1         0x04
5174 #define ATOM_S0_TV1_SVIDEOb1            0x08
5175 #define ATOM_S0_TV1_SCARTb1             0x40
5176 #define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
5177
5178 #define ATOM_S0_CVb1                    0x10
5179 #define ATOM_S0_CV_DINb1                0x20
5180 #define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
5181
5182 #define ATOM_S0_DFP1b2                  0x01
5183 #define ATOM_S0_DFP2b2                  0x02
5184 #define ATOM_S0_LCD1b2                  0x04
5185 #define ATOM_S0_LCD2b2                  0x08
5186 #define ATOM_S0_DFP6b2                  0x10
5187 #define ATOM_S0_DFP3b2                  0x20
5188 #define ATOM_S0_DFP4b2                  0x40
5189 #define ATOM_S0_DFP5b2                  0x80
5190
5191
5192 #define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
5193 #define ATOM_S0_THERMAL_STATE_SHIFTb3   2
5194
5195 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
5196 #define ATOM_S0_LCD1_SHIFT              18
5197
5198 // BIOS_1_SCRATCH Definition
5199 #define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
5200 #define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
5201
5202 //      BIOS_2_SCRATCH Definition
5203 #define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
5204 #define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
5205 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
5206
5207 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
5208 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
5209 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
5210
5211 #define ATOM_S2_DEVICE_DPMS_STATE       0x00010000L
5212 #define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
5213
5214 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
5215 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
5216 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
5217 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
5218 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
5219 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
5220
5221
5222 //Byte aligned definition for BIOS usage
5223 #define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
5224 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
5225 #define ATOM_S2_DEVICE_DPMS_STATEb2     0x01
5226
5227 #define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
5228 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
5229 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
5230 #define ATOM_S2_TMDS_COHERENT_MODEb3    0x10          // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
5231 #define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
5232 #define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
5233
5234
5235 // BIOS_3_SCRATCH Definition
5236 #define ATOM_S3_CRT1_ACTIVE             0x00000001L
5237 #define ATOM_S3_LCD1_ACTIVE             0x00000002L
5238 #define ATOM_S3_TV1_ACTIVE              0x00000004L
5239 #define ATOM_S3_DFP1_ACTIVE             0x00000008L
5240 #define ATOM_S3_CRT2_ACTIVE             0x00000010L
5241 #define ATOM_S3_LCD2_ACTIVE             0x00000020L
5242 #define ATOM_S3_DFP6_ACTIVE             0x00000040L
5243 #define ATOM_S3_DFP2_ACTIVE             0x00000080L
5244 #define ATOM_S3_CV_ACTIVE               0x00000100L
5245 #define ATOM_S3_DFP3_ACTIVE                                                     0x00000200L
5246 #define ATOM_S3_DFP4_ACTIVE                                                     0x00000400L
5247 #define ATOM_S3_DFP5_ACTIVE                                                     0x00000800L
5248
5249 #define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
5250
5251 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
5252 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
5253
5254 #define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
5255 #define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
5256 #define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
5257 #define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
5258 #define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
5259 #define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
5260 #define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
5261 #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
5262 #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
5263 #define ATOM_S3_DFP3_CRTC_ACTIVE                                0x02000000L
5264 #define ATOM_S3_DFP4_CRTC_ACTIVE                                0x04000000L
5265 #define ATOM_S3_DFP5_CRTC_ACTIVE                                0x08000000L
5266
5267 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
5268 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
5269 //Below two definitions are not supported in pplib, but in the old powerplay in DAL
5270 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
5271 #define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
5272
5273 //Byte aligned definition for BIOS usage
5274 #define ATOM_S3_CRT1_ACTIVEb0           0x01
5275 #define ATOM_S3_LCD1_ACTIVEb0           0x02
5276 #define ATOM_S3_TV1_ACTIVEb0            0x04
5277 #define ATOM_S3_DFP1_ACTIVEb0           0x08
5278 #define ATOM_S3_CRT2_ACTIVEb0           0x10
5279 #define ATOM_S3_LCD2_ACTIVEb0           0x20
5280 #define ATOM_S3_DFP6_ACTIVEb0           0x40
5281 #define ATOM_S3_DFP2_ACTIVEb0           0x80
5282 #define ATOM_S3_CV_ACTIVEb1             0x01
5283 #define ATOM_S3_DFP3_ACTIVEb1                                           0x02
5284 #define ATOM_S3_DFP4_ACTIVEb1                                           0x04
5285 #define ATOM_S3_DFP5_ACTIVEb1                                           0x08
5286
5287 #define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
5288
5289 #define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
5290 #define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
5291 #define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
5292 #define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
5293 #define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
5294 #define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
5295 #define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
5296 #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
5297 #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
5298 #define ATOM_S3_DFP3_CRTC_ACTIVEb3                      0x02
5299 #define ATOM_S3_DFP4_CRTC_ACTIVEb3                      0x04
5300 #define ATOM_S3_DFP5_CRTC_ACTIVEb3                      0x08
5301
5302 #define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
5303
5304 // BIOS_4_SCRATCH Definition
5305 #define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
5306 #define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
5307 #define ATOM_S4_LCD1_REFRESH_SHIFT      8
5308
5309 //Byte aligned definition for BIOS usage
5310 #define ATOM_S4_LCD1_PANEL_ID_MASKb0      0x0FF
5311 #define ATOM_S4_LCD1_REFRESH_MASKb1               ATOM_S4_LCD1_PANEL_ID_MASKb0
5312 #define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
5313
5314 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
5315 #define ATOM_S5_DOS_REQ_CRT1b0          0x01
5316 #define ATOM_S5_DOS_REQ_LCD1b0          0x02
5317 #define ATOM_S5_DOS_REQ_TV1b0           0x04
5318 #define ATOM_S5_DOS_REQ_DFP1b0          0x08
5319 #define ATOM_S5_DOS_REQ_CRT2b0          0x10
5320 #define ATOM_S5_DOS_REQ_LCD2b0          0x20
5321 #define ATOM_S5_DOS_REQ_DFP6b0          0x40
5322 #define ATOM_S5_DOS_REQ_DFP2b0          0x80
5323 #define ATOM_S5_DOS_REQ_CVb1            0x01
5324 #define ATOM_S5_DOS_REQ_DFP3b1                                  0x02
5325 #define ATOM_S5_DOS_REQ_DFP4b1                                  0x04
5326 #define ATOM_S5_DOS_REQ_DFP5b1                                  0x08
5327
5328 #define ATOM_S5_DOS_REQ_DEVICEw0        0x0FFF
5329
5330 #define ATOM_S5_DOS_REQ_CRT1            0x0001
5331 #define ATOM_S5_DOS_REQ_LCD1            0x0002
5332 #define ATOM_S5_DOS_REQ_TV1             0x0004
5333 #define ATOM_S5_DOS_REQ_DFP1            0x0008
5334 #define ATOM_S5_DOS_REQ_CRT2            0x0010
5335 #define ATOM_S5_DOS_REQ_LCD2            0x0020
5336 #define ATOM_S5_DOS_REQ_DFP6            0x0040
5337 #define ATOM_S5_DOS_REQ_DFP2            0x0080
5338 #define ATOM_S5_DOS_REQ_CV              0x0100
5339 #define ATOM_S5_DOS_REQ_DFP3            0x0200
5340 #define ATOM_S5_DOS_REQ_DFP4            0x0400
5341 #define ATOM_S5_DOS_REQ_DFP5            0x0800
5342
5343 #define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
5344 #define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
5345 #define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
5346 #define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
5347 #define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
5348                                         (ATOM_S5_DOS_FORCE_CVb3<<8))
5349
5350 // BIOS_6_SCRATCH Definition
5351 #define ATOM_S6_DEVICE_CHANGE           0x00000001L
5352 #define ATOM_S6_SCALER_CHANGE           0x00000002L
5353 #define ATOM_S6_LID_CHANGE              0x00000004L
5354 #define ATOM_S6_DOCKING_CHANGE          0x00000008L
5355 #define ATOM_S6_ACC_MODE                0x00000010L
5356 #define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
5357 #define ATOM_S6_LID_STATE               0x00000040L
5358 #define ATOM_S6_DOCK_STATE              0x00000080L
5359 #define ATOM_S6_CRITICAL_STATE          0x00000100L
5360 #define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
5361 #define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
5362 #define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
5363 #define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
5364 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
5365
5366 #define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
5367 #define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
5368
5369 #define ATOM_S6_ACC_REQ_CRT1            0x00010000L
5370 #define ATOM_S6_ACC_REQ_LCD1            0x00020000L
5371 #define ATOM_S6_ACC_REQ_TV1             0x00040000L
5372 #define ATOM_S6_ACC_REQ_DFP1            0x00080000L
5373 #define ATOM_S6_ACC_REQ_CRT2            0x00100000L
5374 #define ATOM_S6_ACC_REQ_LCD2            0x00200000L
5375 #define ATOM_S6_ACC_REQ_DFP6            0x00400000L
5376 #define ATOM_S6_ACC_REQ_DFP2            0x00800000L
5377 #define ATOM_S6_ACC_REQ_CV              0x01000000L
5378 #define ATOM_S6_ACC_REQ_DFP3                                            0x02000000L
5379 #define ATOM_S6_ACC_REQ_DFP4                                            0x04000000L
5380 #define ATOM_S6_ACC_REQ_DFP5                                            0x08000000L
5381
5382 #define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
5383 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
5384 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
5385 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
5386 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
5387
5388 //Byte aligned definition for BIOS usage
5389 #define ATOM_S6_DEVICE_CHANGEb0         0x01
5390 #define ATOM_S6_SCALER_CHANGEb0         0x02
5391 #define ATOM_S6_LID_CHANGEb0            0x04
5392 #define ATOM_S6_DOCKING_CHANGEb0        0x08
5393 #define ATOM_S6_ACC_MODEb0              0x10
5394 #define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
5395 #define ATOM_S6_LID_STATEb0             0x40
5396 #define ATOM_S6_DOCK_STATEb0            0x80
5397 #define ATOM_S6_CRITICAL_STATEb1        0x01
5398 #define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
5399 #define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
5400 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
5401 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
5402 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
5403
5404 #define ATOM_S6_ACC_REQ_CRT1b2          0x01
5405 #define ATOM_S6_ACC_REQ_LCD1b2          0x02
5406 #define ATOM_S6_ACC_REQ_TV1b2           0x04
5407 #define ATOM_S6_ACC_REQ_DFP1b2          0x08
5408 #define ATOM_S6_ACC_REQ_CRT2b2          0x10
5409 #define ATOM_S6_ACC_REQ_LCD2b2          0x20
5410 #define ATOM_S6_ACC_REQ_DFP6b2          0x40
5411 #define ATOM_S6_ACC_REQ_DFP2b2          0x80
5412 #define ATOM_S6_ACC_REQ_CVb3            0x01
5413 #define ATOM_S6_ACC_REQ_DFP3b3          0x02
5414 #define ATOM_S6_ACC_REQ_DFP4b3          0x04
5415 #define ATOM_S6_ACC_REQ_DFP5b3          0x08
5416
5417 #define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
5418 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
5419 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
5420 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
5421 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
5422
5423 #define ATOM_S6_DEVICE_CHANGE_SHIFT             0
5424 #define ATOM_S6_SCALER_CHANGE_SHIFT             1
5425 #define ATOM_S6_LID_CHANGE_SHIFT                2
5426 #define ATOM_S6_DOCKING_CHANGE_SHIFT            3
5427 #define ATOM_S6_ACC_MODE_SHIFT                  4
5428 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
5429 #define ATOM_S6_LID_STATE_SHIFT                 6
5430 #define ATOM_S6_DOCK_STATE_SHIFT                7
5431 #define ATOM_S6_CRITICAL_STATE_SHIFT            8
5432 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
5433 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
5434 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
5435 #define ATOM_S6_REQ_SCALER_SHIFT                12
5436 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
5437 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
5438 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
5439 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
5440 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
5441 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
5442 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
5443
5444 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
5445 #define ATOM_S7_DOS_MODE_TYPEb0             0x03
5446 #define ATOM_S7_DOS_MODE_VGAb0              0x00
5447 #define ATOM_S7_DOS_MODE_VESAb0             0x01
5448 #define ATOM_S7_DOS_MODE_EXTb0              0x02
5449 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
5450 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
5451 #define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
5452 #define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
5453
5454 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
5455
5456 // BIOS_8_SCRATCH Definition
5457 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
5458 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
5459
5460 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
5461 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
5462
5463 // BIOS_9_SCRATCH Definition
5464 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
5465 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
5466 #endif
5467 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
5468 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
5469 #endif
5470 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
5471 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
5472 #endif
5473 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
5474 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
5475 #endif
5476
5477
5478 #define ATOM_FLAG_SET                         0x20
5479 #define ATOM_FLAG_CLEAR                       0
5480 #define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
5481 #define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
5482 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
5483 #define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
5484 #define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
5485
5486 #define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
5487 #define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
5488
5489 #define SET_ATOM_S6_DOCK_CHANGE                           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
5490 #define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
5491 #define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
5492
5493 #define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
5494 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
5495 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
5496
5497 #define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
5498 #define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
5499
5500 #define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
5501 #define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
5502
5503 #define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
5504 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
5505
5506 #define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5507
5508 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
5509
5510 #define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
5511 #define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
5512 #define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
5513 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
5514
5515 /****************************************************************************/
5516 //Portion II: Definitinos only used in Driver
5517 /****************************************************************************/
5518
5519 // Macros used by driver
5520 #ifdef __cplusplus
5521 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
5522
5523 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
5524 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
5525 #else // not __cplusplus
5526 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
5527
5528 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
5529 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
5530 #endif // __cplusplus
5531
5532 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
5533 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
5534
5535 /****************************************************************************/
5536 //Portion III: Definitinos only used in VBIOS
5537 /****************************************************************************/
5538 #define ATOM_DAC_SRC                                    0x80
5539 #define ATOM_SRC_DAC1                                   0
5540 #define ATOM_SRC_DAC2                                   0x80
5541
5542 typedef struct _MEMORY_PLLINIT_PARAMETERS
5543 {
5544   ULONG ulTargetMemoryClock; //In 10Khz unit
5545   UCHAR   ucAction;                                      //not define yet
5546   UCHAR   ucFbDiv_Hi;                            //Fbdiv Hi byte
5547   UCHAR   ucFbDiv;                                       //FB value
5548   UCHAR   ucPostDiv;                             //Post div
5549 }MEMORY_PLLINIT_PARAMETERS;
5550
5551 #define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
5552
5553
5554 #define GPIO_PIN_WRITE                                                                                                  0x01
5555 #define GPIO_PIN_READ                                                                                                           0x00
5556
5557 typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
5558 {
5559   UCHAR ucGPIO_ID;           //return value, read from GPIO pins
5560   UCHAR ucGPIOBitShift;      //define which bit in uGPIOBitVal need to be update
5561         UCHAR ucGPIOBitVal;                  //Set/Reset corresponding bit defined in ucGPIOBitMask
5562   UCHAR ucAction;                                    //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
5563 }GPIO_PIN_CONTROL_PARAMETERS;
5564
5565 typedef struct _ENABLE_SCALER_PARAMETERS
5566 {
5567   UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
5568   UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
5569   UCHAR ucTVStandard;        //
5570   UCHAR ucPadding[1];
5571 }ENABLE_SCALER_PARAMETERS;
5572 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
5573
5574 //ucEnable:
5575 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
5576 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
5577 #define SCALER_ENABLE_2TAP_ALPHA_MODE               2
5578 #define SCALER_ENABLE_MULTITAP_MODE                 3
5579
5580 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
5581 {
5582   ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
5583   UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
5584   UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
5585   UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
5586   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
5587 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
5588
5589 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
5590 {
5591   ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
5592   ENABLE_CRTC_PARAMETERS                  sReserved;
5593 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
5594
5595 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
5596 {
5597   USHORT usHight;                     // Image Hight
5598   USHORT usWidth;                     // Image Width
5599   UCHAR  ucSurface;                   // Surface 1 or 2
5600   UCHAR  ucPadding[3];
5601 }ENABLE_GRAPH_SURFACE_PARAMETERS;
5602
5603 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
5604 {
5605   USHORT usHight;                     // Image Hight
5606   USHORT usWidth;                     // Image Width
5607   UCHAR  ucSurface;                   // Surface 1 or 2
5608   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
5609   UCHAR  ucPadding[2];
5610 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
5611
5612 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
5613 {
5614   USHORT usHight;                     // Image Hight
5615   USHORT usWidth;                     // Image Width
5616   UCHAR  ucSurface;                   // Surface 1 or 2
5617   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
5618   USHORT usDeviceId;                  // Active Device Id for this surface. If no device, set to 0.
5619 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
5620
5621 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
5622 {
5623   USHORT usHight;                     // Image Hight
5624   USHORT usWidth;                     // Image Width
5625   USHORT usGraphPitch;
5626   UCHAR  ucColorDepth;
5627   UCHAR  ucPixelFormat;
5628   UCHAR  ucSurface;                   // Surface 1 or 2
5629   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
5630   UCHAR  ucModeType;
5631   UCHAR  ucReserved;
5632 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
5633
5634 // ucEnable
5635 #define ATOM_GRAPH_CONTROL_SET_PITCH             0x0f
5636 #define ATOM_GRAPH_CONTROL_SET_DISP_START        0x10
5637
5638 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
5639 {
5640   ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
5641   ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
5642 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
5643
5644 typedef struct _MEMORY_CLEAN_UP_PARAMETERS
5645 {
5646   USHORT  usMemoryStart;                //in 8Kb boundary, offset from memory base address
5647   USHORT  usMemorySize;                 //8Kb blocks aligned
5648 }MEMORY_CLEAN_UP_PARAMETERS;
5649 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
5650
5651 typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
5652 {
5653   USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
5654   USHORT  usY_Size;
5655 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
5656
5657 typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
5658 {
5659   union{
5660     USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
5661     USHORT  usSurface;
5662   };
5663   USHORT usY_Size;
5664   USHORT usDispXStart;
5665   USHORT usDispYStart;
5666 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
5667
5668
5669 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
5670 {
5671   UCHAR  ucLutId;
5672   UCHAR  ucAction;
5673   USHORT usLutStartIndex;
5674   USHORT usLutLength;
5675   USHORT usLutOffsetInVram;
5676 }PALETTE_DATA_CONTROL_PARAMETERS_V3;
5677
5678 // ucAction:
5679 #define PALETTE_DATA_AUTO_FILL            1
5680 #define PALETTE_DATA_READ                 2
5681 #define PALETTE_DATA_WRITE                3
5682
5683
5684 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
5685 {
5686   UCHAR  ucInterruptId;
5687   UCHAR  ucServiceId;
5688   UCHAR  ucStatus;
5689   UCHAR  ucReserved;
5690 }INTERRUPT_SERVICE_PARAMETER_V2;
5691
5692 // ucInterruptId
5693 #define HDP1_INTERRUPT_ID                 1
5694 #define HDP2_INTERRUPT_ID                 2
5695 #define HDP3_INTERRUPT_ID                 3
5696 #define HDP4_INTERRUPT_ID                 4
5697 #define HDP5_INTERRUPT_ID                 5
5698 #define HDP6_INTERRUPT_ID                 6
5699 #define SW_INTERRUPT_ID                   11
5700
5701 // ucAction
5702 #define INTERRUPT_SERVICE_GEN_SW_INT      1
5703 #define INTERRUPT_SERVICE_GET_STATUS      2
5704
5705  // ucStatus
5706 #define INTERRUPT_STATUS__INT_TRIGGER     1
5707 #define INTERRUPT_STATUS__HPD_HIGH        2
5708
5709 typedef struct _INDIRECT_IO_ACCESS
5710 {
5711   ATOM_COMMON_TABLE_HEADER sHeader;
5712   UCHAR                    IOAccessSequence[256];
5713 } INDIRECT_IO_ACCESS;
5714
5715 #define INDIRECT_READ              0x00
5716 #define INDIRECT_WRITE             0x80
5717
5718 #define INDIRECT_IO_MM             0
5719 #define INDIRECT_IO_PLL            1
5720 #define INDIRECT_IO_MC             2
5721 #define INDIRECT_IO_PCIE           3
5722 #define INDIRECT_IO_PCIEP          4
5723 #define INDIRECT_IO_NBMISC         5
5724
5725 #define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
5726 #define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
5727 #define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
5728 #define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
5729 #define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
5730 #define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
5731 #define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
5732 #define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
5733 #define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
5734 #define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
5735
5736 typedef struct _ATOM_OEM_INFO
5737 {
5738   ATOM_COMMON_TABLE_HEADER      sHeader;
5739   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
5740 }ATOM_OEM_INFO;
5741
5742 typedef struct _ATOM_TV_MODE
5743 {
5744    UCHAR        ucVMode_Num;                      //Video mode number
5745    UCHAR        ucTV_Mode_Num;                  //Internal TV mode number
5746 }ATOM_TV_MODE;
5747
5748 typedef struct _ATOM_BIOS_INT_TVSTD_MODE
5749 {
5750   ATOM_COMMON_TABLE_HEADER sHeader;
5751    USHORT       usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
5752    USHORT       usTV_FIFO_Offset;                 // Pointer to FIFO entry table
5753    USHORT       usNTSC_Tbl_Offset;              // Pointer to SDTV_Mode_NTSC table
5754    USHORT       usPAL_Tbl_Offset;                 // Pointer to SDTV_Mode_PAL table
5755    USHORT       usCV_Tbl_Offset;                  // Pointer to SDTV_Mode_PAL table
5756 }ATOM_BIOS_INT_TVSTD_MODE;
5757
5758
5759 typedef struct _ATOM_TV_MODE_SCALER_PTR
5760 {
5761    USHORT       ucFilter0_Offset;               //Pointer to filter format 0 coefficients
5762    USHORT       usFilter1_Offset;               //Pointer to filter format 0 coefficients
5763    UCHAR        ucTV_Mode_Num;
5764 }ATOM_TV_MODE_SCALER_PTR;
5765
5766 typedef struct _ATOM_STANDARD_VESA_TIMING
5767 {
5768   ATOM_COMMON_TABLE_HEADER sHeader;
5769   ATOM_DTD_FORMAT                                aModeTimings[16];      // 16 is not the real array number, just for initial allocation
5770 }ATOM_STANDARD_VESA_TIMING;
5771
5772
5773 typedef struct _ATOM_STD_FORMAT
5774 {
5775   USHORT    usSTD_HDisp;
5776   USHORT    usSTD_VDisp;
5777   USHORT    usSTD_RefreshRate;
5778   USHORT    usReserved;
5779 }ATOM_STD_FORMAT;
5780
5781 typedef struct _ATOM_VESA_TO_EXTENDED_MODE
5782 {
5783   USHORT  usVESA_ModeNumber;
5784   USHORT  usExtendedModeNumber;
5785 }ATOM_VESA_TO_EXTENDED_MODE;
5786
5787 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
5788 {
5789   ATOM_COMMON_TABLE_HEADER   sHeader;
5790   ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
5791 }ATOM_VESA_TO_INTENAL_MODE_LUT;
5792
5793 /*************** ATOM Memory Related Data Structure ***********************/
5794 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
5795         UCHAR                                                                                           ucMemoryType;
5796         UCHAR                                                                                           ucMemoryVendor;
5797         UCHAR                                                                                           ucAdjMCId;
5798         UCHAR                                                                                           ucDynClkId;
5799         ULONG                                                                                           ulDllResetClkRange;
5800 }ATOM_MEMORY_VENDOR_BLOCK;
5801
5802
5803 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
5804 #if ATOM_BIG_ENDIAN
5805         ULONG                                                                                           ucMemBlkId:8;
5806         ULONG                                                                                           ulMemClockRange:24;
5807 #else
5808         ULONG                                                                                           ulMemClockRange:24;
5809         ULONG                                                                                           ucMemBlkId:8;
5810 #endif
5811 }ATOM_MEMORY_SETTING_ID_CONFIG;
5812
5813 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
5814 {
5815   ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
5816   ULONG                         ulAccess;
5817 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
5818
5819
5820 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
5821         ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS                    ulMemoryID;
5822         ULONG                                                                                                                           aulMemData[1];
5823 }ATOM_MEMORY_SETTING_DATA_BLOCK;
5824
5825
5826 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
5827          USHORT                                                                                 usRegIndex;                                     // MC register index
5828          UCHAR                                                                                  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
5829 }ATOM_INIT_REG_INDEX_FORMAT;
5830
5831
5832 typedef struct _ATOM_INIT_REG_BLOCK{
5833         USHORT                                                                                                  usRegIndexTblSize;                                                                                                      //size of asRegIndexBuf
5834         USHORT                                                                                                  usRegDataBlkSize;                                                                                                               //size of ATOM_MEMORY_SETTING_DATA_BLOCK
5835         ATOM_INIT_REG_INDEX_FORMAT                      asRegIndexBuf[1];
5836         ATOM_MEMORY_SETTING_DATA_BLOCK  asRegDataBuf[1];
5837 }ATOM_INIT_REG_BLOCK;
5838
5839 #define END_OF_REG_INDEX_BLOCK  0x0ffff
5840 #define END_OF_REG_DATA_BLOCK   0x00000000
5841 #define ATOM_INIT_REG_MASK_FLAG 0x80               //Not used in BIOS
5842 #define CLOCK_RANGE_HIGHEST                     0x00ffffff
5843
5844 #define VALUE_DWORD             SIZEOF ULONG
5845 #define VALUE_SAME_AS_ABOVE     0
5846 #define VALUE_MASK_DWORD        0x84
5847
5848 #define INDEX_ACCESS_RANGE_BEGIN            (VALUE_DWORD + 1)
5849 #define INDEX_ACCESS_RANGE_END              (INDEX_ACCESS_RANGE_BEGIN + 1)
5850 #define VALUE_INDEX_ACCESS_SINGLE           (INDEX_ACCESS_RANGE_END + 1)
5851 //#define ACCESS_MCIODEBUGIND            0x40       //defined in BIOS code
5852 #define ACCESS_PLACEHOLDER             0x80
5853
5854 typedef struct _ATOM_MC_INIT_PARAM_TABLE
5855 {
5856   ATOM_COMMON_TABLE_HEADER              sHeader;
5857   USHORT                                                                                        usAdjustARB_SEQDataOffset;
5858   USHORT                                                                                        usMCInitMemTypeTblOffset;
5859   USHORT                                                                                        usMCInitCommonTblOffset;
5860   USHORT                                                                                        usMCInitPowerDownTblOffset;
5861         ULONG                                                                                           ulARB_SEQDataBuf[32];
5862         ATOM_INIT_REG_BLOCK                                     asMCInitMemType;
5863         ATOM_INIT_REG_BLOCK                                     asMCInitCommon;
5864 }ATOM_MC_INIT_PARAM_TABLE;
5865
5866
5867 #define _4Mx16              0x2
5868 #define _4Mx32              0x3
5869 #define _8Mx16              0x12
5870 #define _8Mx32              0x13
5871 #define _16Mx16             0x22
5872 #define _16Mx32             0x23
5873 #define _32Mx16             0x32
5874 #define _32Mx32             0x33
5875 #define _64Mx8              0x41
5876 #define _64Mx16             0x42
5877 #define _64Mx32             0x43
5878 #define _128Mx8             0x51
5879 #define _128Mx16            0x52
5880 #define _256Mx8             0x61
5881 #define _256Mx16            0x62
5882
5883 #define SAMSUNG             0x1
5884 #define INFINEON            0x2
5885 #define ELPIDA              0x3
5886 #define ETRON               0x4
5887 #define NANYA               0x5
5888 #define HYNIX               0x6
5889 #define MOSEL               0x7
5890 #define WINBOND             0x8
5891 #define ESMT                0x9
5892 #define MICRON              0xF
5893
5894 #define QIMONDA             INFINEON
5895 #define PROMOS              MOSEL
5896 #define KRETON              INFINEON
5897 #define ELIXIR              NANYA
5898
5899 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
5900
5901 #define UCODE_ROM_START_ADDRESS         0x1b800
5902 #define UCODE_SIGNATURE                 0x4375434d // 'MCuC' - MC uCode
5903
5904 //uCode block header for reference
5905
5906 typedef struct _MCuCodeHeader
5907 {
5908   ULONG  ulSignature;
5909   UCHAR  ucRevision;
5910   UCHAR  ucChecksum;
5911   UCHAR  ucReserved1;
5912   UCHAR  ucReserved2;
5913   USHORT usParametersLength;
5914   USHORT usUCodeLength;
5915   USHORT usReserved1;
5916   USHORT usReserved2;
5917 } MCuCodeHeader;
5918
5919 //////////////////////////////////////////////////////////////////////////////////
5920
5921 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE  16
5922
5923 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK  0xF
5924 typedef struct _ATOM_VRAM_MODULE_V1
5925 {
5926   ULONG                      ulReserved;
5927   USHORT                     usEMRSValue;
5928   USHORT                     usMRSValue;
5929   USHORT                     usReserved;
5930   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5931   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
5932   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
5933   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5934   UCHAR                      ucRow;             // Number of Row,in power of 2;
5935   UCHAR                      ucColumn;          // Number of Column,in power of 2;
5936   UCHAR                      ucBank;            // Nunber of Bank;
5937   UCHAR                      ucRank;            // Number of Rank, in power of 2
5938   UCHAR                      ucChannelNum;      // Number of channel;
5939   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5940   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5941   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5942   UCHAR                      ucReserved[2];
5943 }ATOM_VRAM_MODULE_V1;
5944
5945
5946 typedef struct _ATOM_VRAM_MODULE_V2
5947 {
5948   ULONG                      ulReserved;
5949   ULONG                      ulFlags;                           // To enable/disable functionalities based on memory type
5950   ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
5951   ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
5952   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
5953   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
5954   USHORT                     usEMRSValue;
5955   USHORT                     usMRSValue;
5956   USHORT                     usReserved;
5957   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
5958   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
5959   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
5960   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
5961   UCHAR                      ucRow;             // Number of Row,in power of 2;
5962   UCHAR                      ucColumn;          // Number of Column,in power of 2;
5963   UCHAR                      ucBank;            // Nunber of Bank;
5964   UCHAR                      ucRank;            // Number of Rank, in power of 2
5965   UCHAR                      ucChannelNum;      // Number of channel;
5966   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
5967   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
5968   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
5969   UCHAR                      ucRefreshRateFactor;
5970   UCHAR                      ucReserved[3];
5971 }ATOM_VRAM_MODULE_V2;
5972
5973
5974 typedef struct _ATOM_MEMORY_TIMING_FORMAT
5975 {
5976         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
5977   union{
5978           USHORT                                                                                 usMRS;                                                 // mode register
5979     USHORT                     usDDR3_MR0;
5980   };
5981   union{
5982           USHORT                                                                                 usEMRS;                                                // extended mode register
5983     USHORT                     usDDR3_MR1;
5984   };
5985         UCHAR                                                                                    ucCL;                                                  // CAS latency
5986         UCHAR                                                                                    ucWL;                                                  // WRITE Latency
5987         UCHAR                                                                                    uctRAS;                                                // tRAS
5988         UCHAR                                                                                    uctRC;                                                 // tRC
5989         UCHAR                                                                                    uctRFC;                                                // tRFC
5990         UCHAR                                                                                    uctRCDR;                                               // tRCDR
5991         UCHAR                                                                                    uctRCDW;                                               // tRCDW
5992         UCHAR                                                                                    uctRP;                                                 // tRP
5993         UCHAR                                                                                    uctRRD;                                                // tRRD
5994         UCHAR                                                                                    uctWR;                                                 // tWR
5995         UCHAR                                                                                    uctWTR;                                                // tWTR
5996         UCHAR                                                                                    uctPDIX;                                               // tPDIX
5997         UCHAR                                                                                    uctFAW;                                                // tFAW
5998         UCHAR                                                                                    uctAOND;                                               // tAOND
5999   union
6000   {
6001     struct {
6002             UCHAR                                                                                        ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6003             UCHAR                                                                                        ucReserved;
6004     };
6005     USHORT                   usDDR3_MR2;
6006   };
6007 }ATOM_MEMORY_TIMING_FORMAT;
6008
6009
6010 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
6011 {
6012         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6013         USHORT                                                                           usMRS;                                                 // mode register
6014         USHORT                                                                           usEMRS;                                                // extended mode register
6015         UCHAR                                                                                    ucCL;                                                  // CAS latency
6016         UCHAR                                                                                    ucWL;                                                  // WRITE Latency
6017         UCHAR                                                                                    uctRAS;                                                // tRAS
6018         UCHAR                                                                                    uctRC;                                                 // tRC
6019         UCHAR                                                                                    uctRFC;                                                // tRFC
6020         UCHAR                                                                                    uctRCDR;                                               // tRCDR
6021         UCHAR                                                                                    uctRCDW;                                               // tRCDW
6022         UCHAR                                                                                    uctRP;                                                 // tRP
6023         UCHAR                                                                                    uctRRD;                                                // tRRD
6024         UCHAR                                                                                    uctWR;                                                 // tWR
6025         UCHAR                                                                                    uctWTR;                                                // tWTR
6026         UCHAR                                                                                    uctPDIX;                                               // tPDIX
6027         UCHAR                                                                                    uctFAW;                                                // tFAW
6028         UCHAR                                                                                    uctAOND;                                               // tAOND
6029         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6030 ////////////////////////////////////GDDR parameters///////////////////////////////////
6031         UCHAR                                                                                    uctCCDL;                                               //
6032         UCHAR                                                                                    uctCRCRL;                                              //
6033         UCHAR                                                                                    uctCRCWL;                                              //
6034         UCHAR                                                                                    uctCKE;                                                //
6035         UCHAR                                                                                    uctCKRSE;                                              //
6036         UCHAR                                                                                    uctCKRSX;                                              //
6037         UCHAR                                                                                    uctFAW32;                                              //
6038         UCHAR                                                                                    ucMR5lo;                                       //
6039         UCHAR                                                                                    ucMR5hi;                                       //
6040         UCHAR                                                                                    ucTerminator;
6041 }ATOM_MEMORY_TIMING_FORMAT_V1;
6042
6043 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
6044 {
6045         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6046         USHORT                                                                           usMRS;                                                 // mode register
6047         USHORT                                                                           usEMRS;                                                // extended mode register
6048         UCHAR                                                                                    ucCL;                                                  // CAS latency
6049         UCHAR                                                                                    ucWL;                                                  // WRITE Latency
6050         UCHAR                                                                                    uctRAS;                                                // tRAS
6051         UCHAR                                                                                    uctRC;                                                 // tRC
6052         UCHAR                                                                                    uctRFC;                                                // tRFC
6053         UCHAR                                                                                    uctRCDR;                                               // tRCDR
6054         UCHAR                                                                                    uctRCDW;                                               // tRCDW
6055         UCHAR                                                                                    uctRP;                                                 // tRP
6056         UCHAR                                                                                    uctRRD;                                                // tRRD
6057         UCHAR                                                                                    uctWR;                                                 // tWR
6058         UCHAR                                                                                    uctWTR;                                                // tWTR
6059         UCHAR                                                                                    uctPDIX;                                               // tPDIX
6060         UCHAR                                                                                    uctFAW;                                                // tFAW
6061         UCHAR                                                                                    uctAOND;                                               // tAOND
6062         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6063 ////////////////////////////////////GDDR parameters///////////////////////////////////
6064         UCHAR                                                                                    uctCCDL;                                               //
6065         UCHAR                                                                                    uctCRCRL;                                              //
6066         UCHAR                                                                                    uctCRCWL;                                              //
6067         UCHAR                                                                                    uctCKE;                                                //
6068         UCHAR                                                                                    uctCKRSE;                                              //
6069         UCHAR                                                                                    uctCKRSX;                                              //
6070         UCHAR                                                                                    uctFAW32;                                              //
6071         UCHAR                                                                                    ucMR4lo;                                       //
6072         UCHAR                                                                                    ucMR4hi;                                       //
6073         UCHAR                                                                                    ucMR5lo;                                       //
6074         UCHAR                                                                                    ucMR5hi;                                       //
6075         UCHAR                                                                                    ucTerminator;
6076         UCHAR                                                                                    ucReserved;
6077 }ATOM_MEMORY_TIMING_FORMAT_V2;
6078
6079 typedef struct _ATOM_MEMORY_FORMAT
6080 {
6081         ULONG                                                                                    ulDllDisClock;                 // memory DLL will be disable when target memory clock is below this clock
6082   union{
6083     USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6084     USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
6085   };
6086   union{
6087     USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6088     USHORT                     usDDR3_MR3;        // Used for DDR3 memory
6089   };
6090   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
6091   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
6092   UCHAR                      ucRow;             // Number of Row,in power of 2;
6093   UCHAR                      ucColumn;          // Number of Column,in power of 2;
6094   UCHAR                      ucBank;            // Nunber of Bank;
6095   UCHAR                      ucRank;            // Number of Rank, in power of 2
6096         UCHAR                                                                                    ucBurstSize;                           // burst size, 0= burst size=4  1= burst size=8
6097   UCHAR                      ucDllDisBit;                               // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
6098   UCHAR                      ucRefreshRateFactor;       // memory refresh rate in unit of ms
6099         UCHAR                                                                                    ucDensity;                                     // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6100         UCHAR                                                                                    ucPreamble;                            //[7:4] Write Preamble, [3:0] Read Preamble
6101   UCHAR                                                                                  ucMemAttrib;                           // Memory Device Addribute, like RDBI/WDBI etc
6102         ATOM_MEMORY_TIMING_FORMAT        asMemTiming[5];                //Memory Timing block sort from lower clock to higher clock
6103 }ATOM_MEMORY_FORMAT;
6104
6105
6106 typedef struct _ATOM_VRAM_MODULE_V3
6107 {
6108         ULONG                                                                                    ulChannelMapCfg;               // board dependent paramenter:Channel combination
6109         USHORT                                                                           usSize;                                                // size of ATOM_VRAM_MODULE_V3
6110   USHORT                     usDefaultMVDDQ;            // board dependent parameter:Default Memory Core Voltage
6111   USHORT                     usDefaultMVDDC;            // board dependent parameter:Default Memory IO Voltage
6112         UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6113   UCHAR                      ucChannelNum;      // board dependent parameter:Number of channel;
6114         UCHAR                                                                                    ucChannelSize;                 // board dependent parameter:32bit or 64bit
6115         UCHAR                                                                                    ucVREFI;                                               // board dependnt parameter: EXT or INT +160mv to -140mv
6116         UCHAR                                                                                    ucNPL_RT;                                      // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6117         UCHAR                                                                                    ucFlag;                                                // To enable/disable functionalities based on memory type
6118         ATOM_MEMORY_FORMAT                               asMemory;                                      // describ all of video memory parameters from memory spec
6119 }ATOM_VRAM_MODULE_V3;
6120
6121
6122 //ATOM_VRAM_MODULE_V3.ucNPL_RT
6123 #define NPL_RT_MASK                                                                                                                     0x0f
6124 #define BATTERY_ODT_MASK                                                                                                0xc0
6125
6126 #define ATOM_VRAM_MODULE                 ATOM_VRAM_MODULE_V3
6127
6128 typedef struct _ATOM_VRAM_MODULE_V4
6129 {
6130   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
6131   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6132   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6133                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6134   USHORT  usReserved;
6135   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6136   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6137   UCHAR   ucChannelNum;                     // Number of channels present in this module config
6138   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
6139         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6140         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
6141         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
6142   UCHAR         ucVREFI;                          // board dependent parameter
6143   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6144   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
6145   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6146                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6147   UCHAR   ucReserved[3];
6148
6149 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6150   union{
6151     USHORT      usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6152     USHORT  usDDR3_Reserved;
6153   };
6154   union{
6155     USHORT      usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6156     USHORT  usDDR3_MR3;                     // Used for DDR3 memory
6157   };
6158   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
6159   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6160   UCHAR   ucReserved2[2];
6161   ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6162 }ATOM_VRAM_MODULE_V4;
6163
6164 #define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
6165 #define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
6166 #define VRAM_MODULE_V4_MISC_BL_MASK         0x4
6167 #define VRAM_MODULE_V4_MISC_BL8             0x4
6168 #define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
6169
6170 typedef struct _ATOM_VRAM_MODULE_V5
6171 {
6172   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
6173   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6174   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6175                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6176   USHORT  usReserved;
6177   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6178   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6179   UCHAR   ucChannelNum;                     // Number of channels present in this module config
6180   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
6181         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6182         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
6183         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
6184   UCHAR         ucVREFI;                          // board dependent parameter
6185   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6186   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
6187   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6188                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6189   UCHAR   ucReserved[3];
6190
6191 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6192   USHORT        usEMRS2Value;                               // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6193   USHORT        usEMRS3Value;                               // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6194   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
6195   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6196   UCHAR   ucFIFODepth;                                  // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6197   UCHAR   ucCDR_Bandwidth;                 // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6198   ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6199 }ATOM_VRAM_MODULE_V5;
6200
6201 typedef struct _ATOM_VRAM_MODULE_V6
6202 {
6203   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
6204   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
6205   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6206                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6207   USHORT  usReserved;
6208   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6209   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
6210   UCHAR   ucChannelNum;                     // Number of channels present in this module config
6211   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
6212         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6213         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
6214         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
6215   UCHAR         ucVREFI;                          // board dependent parameter
6216   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
6217   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
6218   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
6219                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6220   UCHAR   ucReserved[3];
6221
6222 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
6223   USHORT        usEMRS2Value;                               // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6224   USHORT        usEMRS3Value;                               // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6225   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
6226   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6227   UCHAR   ucFIFODepth;                                  // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
6228   UCHAR   ucCDR_Bandwidth;                 // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6229   ATOM_MEMORY_TIMING_FORMAT_V2  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
6230 }ATOM_VRAM_MODULE_V6;
6231
6232 typedef struct _ATOM_VRAM_MODULE_V7
6233 {
6234 // Design Specific Values
6235   ULONG   ulChannelMapCfg;                      // mmMC_SHARED_CHREMAP
6236   USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
6237   USHORT  usPrivateReserved;                // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
6238   USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
6239   UCHAR   ucExtMemoryID;                    // Current memory module ID
6240   UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
6241   UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
6242   UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
6243   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6244   UCHAR   ucReserve;                        // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
6245   UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
6246   UCHAR   ucVREFI;                          // Not used.
6247   UCHAR   ucNPL_RT;                         // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6248   UCHAR   ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
6249   UCHAR   ucMemorySize;                     // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6250   USHORT  usSEQSettingOffset;
6251   UCHAR   ucReserved;
6252 // Memory Module specific values
6253   USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
6254   USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
6255   UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
6256   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6257   UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
6258   UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6259   char    strMemPNString[20];               // part number end with '0'.
6260 }ATOM_VRAM_MODULE_V7;
6261
6262 typedef struct _ATOM_VRAM_INFO_V2
6263 {
6264   ATOM_COMMON_TABLE_HEADER   sHeader;
6265   UCHAR                      ucNumOfVRAMModule;
6266   ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6267 }ATOM_VRAM_INFO_V2;
6268
6269 typedef struct _ATOM_VRAM_INFO_V3
6270 {
6271   ATOM_COMMON_TABLE_HEADER   sHeader;
6272         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6273         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6274         USHORT                                                                           usRerseved;
6275         UCHAR                            aVID_PinsShift[9];                                                                                                                      // 8 bit strap maximum+terminator
6276   UCHAR                      ucNumOfVRAMModule;
6277   ATOM_VRAM_MODULE                     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6278         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
6279                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
6280 }ATOM_VRAM_INFO_V3;
6281
6282 #define ATOM_VRAM_INFO_LAST          ATOM_VRAM_INFO_V3
6283
6284 typedef struct _ATOM_VRAM_INFO_V4
6285 {
6286   ATOM_COMMON_TABLE_HEADER   sHeader;
6287   USHORT                     usMemAdjustTblOffset;                                                                                                       // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6288   USHORT                     usMemClkPatchTblOffset;                                                                                             //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6289   USHORT                                                                                 usRerseved;
6290   UCHAR                          ucMemDQ7_0ByteRemap;                                                                                                      // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
6291   ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
6292   UCHAR                      ucReservde[4];
6293   UCHAR                      ucNumOfVRAMModule;
6294   ATOM_VRAM_MODULE_V4                aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6295         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
6296                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
6297 }ATOM_VRAM_INFO_V4;
6298
6299 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
6300 {
6301   ATOM_COMMON_TABLE_HEADER   sHeader;
6302   USHORT                     usMemAdjustTblOffset;                                                                                                       // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
6303   USHORT                     usMemClkPatchTblOffset;                                                                                             //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
6304   USHORT                     usPerBytePresetOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
6305   USHORT                     usReserved[3];
6306   UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
6307   UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
6308   UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
6309   UCHAR                      ucReserved;
6310   ATOM_VRAM_MODULE_V7                aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
6311 }ATOM_VRAM_INFO_HEADER_V2_1;
6312
6313
6314 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
6315 {
6316   ATOM_COMMON_TABLE_HEADER   sHeader;
6317   UCHAR                          aVID_PinsShift[9];   //8 bit strap maximum+terminator
6318 }ATOM_VRAM_GPIO_DETECTION_INFO;
6319
6320
6321 typedef struct _ATOM_MEMORY_TRAINING_INFO
6322 {
6323         ATOM_COMMON_TABLE_HEADER   sHeader;
6324         UCHAR                                                                                    ucTrainingLoop;
6325         UCHAR                                                                                    ucReserved[3];
6326         ATOM_INIT_REG_BLOCK                              asMemTrainingSetting;
6327 }ATOM_MEMORY_TRAINING_INFO;
6328
6329
6330 typedef struct SW_I2C_CNTL_DATA_PARAMETERS
6331 {
6332   UCHAR    ucControl;
6333   UCHAR    ucData;
6334   UCHAR    ucSatus;
6335   UCHAR    ucTemp;
6336 } SW_I2C_CNTL_DATA_PARAMETERS;
6337
6338 #define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
6339
6340 typedef struct _SW_I2C_IO_DATA_PARAMETERS
6341 {
6342   USHORT   GPIO_Info;
6343   UCHAR    ucAct;
6344   UCHAR    ucData;
6345  } SW_I2C_IO_DATA_PARAMETERS;
6346
6347 #define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
6348
6349 /****************************SW I2C CNTL DEFINITIONS**********************/
6350 #define SW_I2C_IO_RESET       0
6351 #define SW_I2C_IO_GET         1
6352 #define SW_I2C_IO_DRIVE       2
6353 #define SW_I2C_IO_SET         3
6354 #define SW_I2C_IO_START       4
6355
6356 #define SW_I2C_IO_CLOCK       0
6357 #define SW_I2C_IO_DATA        0x80
6358
6359 #define SW_I2C_IO_ZERO        0
6360 #define SW_I2C_IO_ONE         0x100
6361
6362 #define SW_I2C_CNTL_READ      0
6363 #define SW_I2C_CNTL_WRITE     1
6364 #define SW_I2C_CNTL_START     2
6365 #define SW_I2C_CNTL_STOP      3
6366 #define SW_I2C_CNTL_OPEN      4
6367 #define SW_I2C_CNTL_CLOSE     5
6368 #define SW_I2C_CNTL_WRITE1BIT 6
6369
6370 //==============================VESA definition Portion===============================
6371 #define VESA_OEM_PRODUCT_REV                                "01.00"
6372 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT             0xBB       //refer to VBE spec p.32, no TTY support
6373 #define VESA_MODE_WIN_ATTRIBUTE                                              7
6374 #define VESA_WIN_SIZE                                                                                        64
6375
6376 typedef struct _PTR_32_BIT_STRUCTURE
6377 {
6378         USHORT  Offset16;
6379         USHORT  Segment16;
6380 } PTR_32_BIT_STRUCTURE;
6381
6382 typedef union _PTR_32_BIT_UNION
6383 {
6384         PTR_32_BIT_STRUCTURE    SegmentOffset;
6385         ULONG                                           Ptr32_Bit;
6386 } PTR_32_BIT_UNION;
6387
6388 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
6389 {
6390         UCHAR                                 VbeSignature[4];
6391         USHORT                              VbeVersion;
6392         PTR_32_BIT_UNION        OemStringPtr;
6393         UCHAR                                 Capabilities[4];
6394         PTR_32_BIT_UNION        VideoModePtr;
6395         USHORT                              TotalMemory;
6396 } VBE_1_2_INFO_BLOCK_UPDATABLE;
6397
6398
6399 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
6400 {
6401         VBE_1_2_INFO_BLOCK_UPDATABLE    CommonBlock;
6402         USHORT                                                      OemSoftRev;
6403         PTR_32_BIT_UNION                                OemVendorNamePtr;
6404         PTR_32_BIT_UNION                                OemProductNamePtr;
6405         PTR_32_BIT_UNION                                OemProductRevPtr;
6406 } VBE_2_0_INFO_BLOCK_UPDATABLE;
6407
6408 typedef union _VBE_VERSION_UNION
6409 {
6410         VBE_2_0_INFO_BLOCK_UPDATABLE    VBE_2_0_InfoBlock;
6411         VBE_1_2_INFO_BLOCK_UPDATABLE    VBE_1_2_InfoBlock;
6412 } VBE_VERSION_UNION;
6413
6414 typedef struct _VBE_INFO_BLOCK
6415 {
6416         VBE_VERSION_UNION                       UpdatableVBE_Info;
6417         UCHAR                                                 Reserved[222];
6418         UCHAR                                                 OemData[256];
6419 } VBE_INFO_BLOCK;
6420
6421 typedef struct _VBE_FP_INFO
6422 {
6423   USHORT        HSize;
6424         USHORT  VSize;
6425         USHORT  FPType;
6426         UCHAR           RedBPP;
6427         UCHAR           GreenBPP;
6428         UCHAR           BlueBPP;
6429         UCHAR           ReservedBPP;
6430         ULONG           RsvdOffScrnMemSize;
6431         ULONG           RsvdOffScrnMEmPtr;
6432         UCHAR           Reserved[14];
6433 } VBE_FP_INFO;
6434
6435 typedef struct _VESA_MODE_INFO_BLOCK
6436 {
6437 // Mandatory information for all VBE revisions
6438   USHORT    ModeAttributes;  //                 dw      ?       ; mode attributes
6439         UCHAR     WinAAttributes;  //                   db      ?       ; window A attributes
6440         UCHAR     WinBAttributes;  //                   db      ?       ; window B attributes
6441         USHORT    WinGranularity;  //                   dw      ?       ; window granularity
6442         USHORT    WinSize;         //                   dw      ?       ; window size
6443         USHORT    WinASegment;     //                   dw      ?       ; window A start segment
6444         USHORT    WinBSegment;     //                   dw      ?       ; window B start segment
6445         ULONG     WinFuncPtr;      //                   dd      ?       ; real mode pointer to window function
6446         USHORT    BytesPerScanLine;//                   dw      ?       ; bytes per scan line
6447
6448 //; Mandatory information for VBE 1.2 and above
6449   USHORT    XResolution;      //                        dw      ?       ; horizontal resolution in pixels or characters
6450         USHORT    YResolution;      //                  dw      ?       ; vertical resolution in pixels or characters
6451         UCHAR     XCharSize;        //                  db      ?       ; character cell width in pixels
6452         UCHAR     YCharSize;        //                  db      ?       ; character cell height in pixels
6453         UCHAR     NumberOfPlanes;   //                  db      ?       ; number of memory planes
6454         UCHAR     BitsPerPixel;     //                  db      ?       ; bits per pixel
6455         UCHAR     NumberOfBanks;    //                  db      ?       ; number of banks
6456         UCHAR     MemoryModel;      //                  db      ?       ; memory model type
6457         UCHAR     BankSize;         //                  db      ?       ; bank size in KB
6458         UCHAR     NumberOfImagePages;//           db    ?       ; number of images
6459         UCHAR     ReservedForPageFunction;//db  1       ; reserved for page function
6460
6461 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
6462         UCHAR                   RedMaskSize;        //          db      ?       ; size of direct color red mask in bits
6463         UCHAR                   RedFieldPosition;   //          db      ?       ; bit position of lsb of red mask
6464         UCHAR                   GreenMaskSize;      //          db      ?       ; size of direct color green mask in bits
6465         UCHAR                   GreenFieldPosition; //          db      ?       ; bit position of lsb of green mask
6466         UCHAR                   BlueMaskSize;       //          db      ?       ; size of direct color blue mask in bits
6467         UCHAR                   BlueFieldPosition;  //          db      ?       ; bit position of lsb of blue mask
6468         UCHAR                   RsvdMaskSize;       //          db      ?       ; size of direct color reserved mask in bits
6469         UCHAR                   RsvdFieldPosition;  //          db      ?       ; bit position of lsb of reserved mask
6470         UCHAR                   DirectColorModeInfo;//          db      ?       ; direct color mode attributes
6471
6472 //; Mandatory information for VBE 2.0 and above
6473         ULONG                   PhysBasePtr;        //          dd      ?       ; physical address for flat memory frame buffer
6474         ULONG                   Reserved_1;         //          dd      0       ; reserved - always set to 0
6475         USHORT          Reserved_2;         //    dw    0       ; reserved - always set to 0
6476
6477 //; Mandatory information for VBE 3.0 and above
6478         USHORT          LinBytesPerScanLine;  //        dw      ?       ; bytes per scan line for linear modes
6479         UCHAR                   BnkNumberOfImagePages;//        db      ?       ; number of images for banked modes
6480         UCHAR                   LinNumberOfImagPages; //        db      ?       ; number of images for linear modes
6481         UCHAR                   LinRedMaskSize;       //        db      ?       ; size of direct color red mask(linear modes)
6482         UCHAR                   LinRedFieldPosition;  //        db      ?       ; bit position of lsb of red mask(linear modes)
6483         UCHAR                   LinGreenMaskSize;     //        db      ?       ; size of direct color green mask(linear modes)
6484         UCHAR                   LinGreenFieldPosition;//        db      ?       ; bit position of lsb of green mask(linear modes)
6485         UCHAR                   LinBlueMaskSize;      //        db      ?       ; size of direct color blue mask(linear modes)
6486         UCHAR                   LinBlueFieldPosition; //        db      ?       ; bit position of lsb of blue mask(linear modes)
6487         UCHAR                   LinRsvdMaskSize;      //        db      ?       ; size of direct color reserved mask(linear modes)
6488         UCHAR                   LinRsvdFieldPosition; //        db      ?       ; bit position of lsb of reserved mask(linear modes)
6489         ULONG                   MaxPixelClock;        //        dd      ?       ; maximum pixel clock(in Hz) for graphics mode
6490         UCHAR                   Reserved;             //        db      190 dup (0)
6491 } VESA_MODE_INFO_BLOCK;
6492
6493 // BIOS function CALLS
6494 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0            // ATI Extended Function code
6495 #define ATOM_BIOS_FUNCTION_COP_MODE             0x00
6496 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
6497 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
6498 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
6499 #define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
6500 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
6501 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
6502 #define ATOM_BIOS_FUNCTION_STV_STD              0x16
6503 #define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
6504 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
6505
6506 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
6507 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
6508 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
6509 #define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
6510 #define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
6511 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
6512 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
6513
6514 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
6515 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
6516 #define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
6517 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03
6518 #define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
6519 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
6520 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
6521 #define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
6522 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
6523 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
6524
6525
6526 #define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
6527 #define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
6528 #define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
6529 #define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.
6530 #define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY
6531 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
6532 #define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
6533 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
6534
6535 #define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
6536 #define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
6537 #define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
6538
6539 // structure used for VBIOS only
6540
6541 //DispOutInfoTable
6542 typedef struct _ASIC_TRANSMITTER_INFO
6543 {
6544         USHORT usTransmitterObjId;
6545         USHORT usSupportDevice;
6546   UCHAR  ucTransmitterCmdTblId;
6547         UCHAR  ucConfig;
6548         UCHAR  ucEncoderID;                                      //available 1st encoder ( default )
6549         UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
6550         UCHAR  uc2ndEncoderID;
6551         UCHAR  ucReserved;
6552 }ASIC_TRANSMITTER_INFO;
6553
6554 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE          0x01
6555 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE         0x02
6556 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK    0xc4
6557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A             0x00
6558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B             0x04
6559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C             0x40
6560 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D             0x44
6561 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E             0x80
6562 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F             0x84
6563
6564 typedef struct _ASIC_ENCODER_INFO
6565 {
6566         UCHAR ucEncoderID;
6567         UCHAR ucEncoderConfig;
6568   USHORT usEncoderCmdTblId;
6569 }ASIC_ENCODER_INFO;
6570
6571 typedef struct _ATOM_DISP_OUT_INFO
6572 {
6573   ATOM_COMMON_TABLE_HEADER sHeader;
6574         USHORT ptrTransmitterInfo;
6575         USHORT ptrEncoderInfo;
6576         ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
6577         ASIC_ENCODER_INFO      asEncoderInfo[1];
6578 }ATOM_DISP_OUT_INFO;
6579
6580 typedef struct _ATOM_DISP_OUT_INFO_V2
6581 {
6582   ATOM_COMMON_TABLE_HEADER sHeader;
6583         USHORT ptrTransmitterInfo;
6584         USHORT ptrEncoderInfo;
6585   USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
6586         ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
6587         ASIC_ENCODER_INFO      asEncoderInfo[1];
6588 }ATOM_DISP_OUT_INFO_V2;
6589
6590
6591 typedef struct _ATOM_DISP_CLOCK_ID {
6592   UCHAR ucPpllId;
6593   UCHAR ucPpllAttribute;
6594 }ATOM_DISP_CLOCK_ID;
6595
6596 // ucPpllAttribute
6597 #define CLOCK_SOURCE_SHAREABLE            0x01
6598 #define CLOCK_SOURCE_DP_MODE              0x02
6599 #define CLOCK_SOURCE_NONE_DP_MODE         0x04
6600
6601 //DispOutInfoTable
6602 typedef struct _ASIC_TRANSMITTER_INFO_V2
6603 {
6604         USHORT usTransmitterObjId;
6605         USHORT usDispClkIdOffset;    // point to clock source id list supported by Encoder Object
6606   UCHAR  ucTransmitterCmdTblId;
6607         UCHAR  ucConfig;
6608         UCHAR  ucEncoderID;                                      // available 1st encoder ( default )
6609         UCHAR  ucOptionEncoderID;    // available 2nd encoder ( optional )
6610         UCHAR  uc2ndEncoderID;
6611         UCHAR  ucReserved;
6612 }ASIC_TRANSMITTER_INFO_V2;
6613
6614 typedef struct _ATOM_DISP_OUT_INFO_V3
6615 {
6616   ATOM_COMMON_TABLE_HEADER sHeader;
6617         USHORT ptrTransmitterInfo;
6618         USHORT ptrEncoderInfo;
6619   USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
6620   USHORT usReserved;
6621   UCHAR  ucDCERevision;
6622   UCHAR  ucMaxDispEngineNum;
6623   UCHAR  ucMaxActiveDispEngineNum;
6624   UCHAR  ucMaxPPLLNum;
6625   UCHAR  ucCoreRefClkSource;                          // value of CORE_REF_CLK_SOURCE
6626   UCHAR  ucReserved[3];
6627         ASIC_TRANSMITTER_INFO_V2  asTransmitterInfo[1];     // for alligment only
6628 }ATOM_DISP_OUT_INFO_V3;
6629
6630 typedef enum CORE_REF_CLK_SOURCE{
6631   CLOCK_SRC_XTALIN=0,
6632   CLOCK_SRC_XO_IN=1,
6633   CLOCK_SRC_XO_IN2=2,
6634 }CORE_REF_CLK_SOURCE;
6635
6636 // DispDevicePriorityInfo
6637 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
6638 {
6639   ATOM_COMMON_TABLE_HEADER sHeader;
6640         USHORT asDevicePriority[16];
6641 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
6642
6643 //ProcessAuxChannelTransactionTable
6644 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6645 {
6646         USHORT  lpAuxRequest;
6647         USHORT  lpDataOut;
6648         UCHAR           ucChannelID;
6649         union
6650         {
6651   UCHAR   ucReplyStatus;
6652         UCHAR   ucDelay;
6653         };
6654   UCHAR   ucDataOutLen;
6655         UCHAR   ucReserved;
6656 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
6657
6658 //ProcessAuxChannelTransactionTable
6659 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
6660 {
6661         USHORT  lpAuxRequest;
6662         USHORT  lpDataOut;
6663         UCHAR           ucChannelID;
6664         union
6665         {
6666   UCHAR   ucReplyStatus;
6667         UCHAR   ucDelay;
6668         };
6669   UCHAR   ucDataOutLen;
6670         UCHAR   ucHPD_ID;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
6671 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
6672
6673 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION                   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
6674
6675 //GetSinkType
6676
6677 typedef struct _DP_ENCODER_SERVICE_PARAMETERS
6678 {
6679         USHORT ucLinkClock;
6680         union
6681         {
6682         UCHAR ucConfig;                         // for DP training command
6683         UCHAR ucI2cId;                          // use for GET_SINK_TYPE command
6684         };
6685         UCHAR ucAction;
6686         UCHAR ucStatus;
6687         UCHAR ucLaneNum;
6688         UCHAR ucReserved[2];
6689 }DP_ENCODER_SERVICE_PARAMETERS;
6690
6691 // ucAction
6692 #define ATOM_DP_ACTION_GET_SINK_TYPE                                                    0x01
6693 /* obselete */
6694 #define ATOM_DP_ACTION_TRAINING_START                                                   0x02
6695 #define ATOM_DP_ACTION_TRAINING_COMPLETE                                        0x03
6696 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL                             0x04
6697 #define ATOM_DP_ACTION_SET_VSWING_PREEMP                                        0x05
6698 #define ATOM_DP_ACTION_GET_VSWING_PREEMP                                        0x06
6699 #define ATOM_DP_ACTION_BLANKING                   0x07
6700
6701 // ucConfig
6702 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK                                         0x03
6703 #define ATOM_DP_CONFIG_DIG1_ENCODER                                                             0x00
6704 #define ATOM_DP_CONFIG_DIG2_ENCODER                                                             0x01
6705 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER                                         0x02
6706 #define ATOM_DP_CONFIG_LINK_SEL_MASK                                                    0x04
6707 #define ATOM_DP_CONFIG_LINK_A                                                                                   0x00
6708 #define ATOM_DP_CONFIG_LINK_B                                                                                   0x04
6709 /* /obselete */
6710 #define DP_ENCODER_SERVICE_PS_ALLOCATION                                WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
6711
6712
6713 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
6714 {
6715         USHORT usExtEncoderObjId;   // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6716   UCHAR  ucAuxId;
6717   UCHAR  ucAction;
6718   UCHAR  ucSinkType;          // Iput and Output parameters.
6719   UCHAR  ucHPDId;             // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
6720         UCHAR  ucReserved[2];
6721 }DP_ENCODER_SERVICE_PARAMETERS_V2;
6722
6723 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
6724 {
6725   DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
6726   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
6727 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
6728
6729 // ucAction
6730 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE                                                      0x01
6731 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION                     0x02
6732
6733
6734 // DP_TRAINING_TABLE
6735 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR                             ATOM_DP_TRAINING_TBL_ADDR
6736 #define DPCD_SET_SS_CNTL_TBL_ADDR                                                                                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
6737 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 16 )
6738 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 24 )
6739 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 32)
6740 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                                                   (ATOM_DP_TRAINING_TBL_ADDR + 40)
6741 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 48)
6742 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 60)
6743 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                                                                   (ATOM_DP_TRAINING_TBL_ADDR + 64)
6744 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                                                              (ATOM_DP_TRAINING_TBL_ADDR + 72)
6745 #define DP_I2C_AUX_DDC_READ_TBL_ADDR                                                                                    (ATOM_DP_TRAINING_TBL_ADDR + 76)
6746 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR                 (ATOM_DP_TRAINING_TBL_ADDR + 80)
6747 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                                                                        (ATOM_DP_TRAINING_TBL_ADDR + 84)
6748
6749 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6750 {
6751         UCHAR   ucI2CSpeed;
6752         union
6753         {
6754    UCHAR ucRegIndex;
6755    UCHAR ucStatus;
6756         };
6757         USHORT  lpI2CDataOut;
6758   UCHAR   ucFlag;
6759   UCHAR   ucTransBytes;
6760   UCHAR   ucSlaveAddr;
6761   UCHAR   ucLineNumber;
6762 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
6763
6764 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
6765
6766 //ucFlag
6767 #define HW_I2C_WRITE        1
6768 #define HW_I2C_READ         0
6769 #define I2C_2BYTE_ADDR      0x02
6770
6771 /****************************************************************************/
6772 // Structures used by HW_Misc_OperationTable
6773 /****************************************************************************/
6774 typedef struct  _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
6775 {
6776   UCHAR  ucCmd;                //  Input: To tell which action to take
6777   UCHAR  ucReserved[3];
6778   ULONG  ulReserved;
6779 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
6780
6781 typedef struct  _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
6782 {
6783   UCHAR  ucReturnCode;        // Output: Return value base on action was taken
6784   UCHAR  ucReserved[3];
6785   ULONG  ulReserved;
6786 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
6787
6788 // Actions code
6789 #define  ATOM_GET_SDI_SUPPORT              0xF0
6790
6791 // Return code
6792 #define  ATOM_UNKNOWN_CMD                   0
6793 #define  ATOM_FEATURE_NOT_SUPPORTED         1
6794 #define  ATOM_FEATURE_SUPPORTED             2
6795
6796 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
6797 {
6798         ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1        sInput_Output;
6799         PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS         sReserved;
6800 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
6801
6802 /****************************************************************************/
6803
6804 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
6805 {
6806    UCHAR ucHWBlkInst;                // HW block instance, 0, 1, 2, ...
6807    UCHAR ucReserved[3];
6808 }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
6809
6810 #define HWBLKINST_INSTANCE_MASK       0x07
6811 #define HWBLKINST_HWBLK_MASK          0xF0
6812 #define HWBLKINST_HWBLK_SHIFT         0x04
6813
6814 //ucHWBlock
6815 #define SELECT_DISP_ENGINE            0
6816 #define SELECT_DISP_PLL               1
6817 #define SELECT_DCIO_UNIPHY_LINK0      2
6818 #define SELECT_DCIO_UNIPHY_LINK1      3
6819 #define SELECT_DCIO_IMPCAL            4
6820 #define SELECT_DCIO_DIG               6
6821 #define SELECT_CRTC_PIXEL_RATE        7
6822 #define SELECT_VGA_BLK                8
6823
6824 // DIGTransmitterInfoTable structure used to program UNIPHY settings
6825 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
6826   ATOM_COMMON_TABLE_HEADER sHeader;
6827   USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
6828   USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
6829   USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
6830   USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
6831   USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
6832 }DIG_TRANSMITTER_INFO_HEADER_V3_1;
6833
6834 typedef struct _CLOCK_CONDITION_REGESTER_INFO{
6835   USHORT usRegisterIndex;
6836   UCHAR  ucStartBit;
6837   UCHAR  ucEndBit;
6838 }CLOCK_CONDITION_REGESTER_INFO;
6839
6840 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
6841   USHORT usMaxClockFreq;
6842   UCHAR  ucEncodeMode;
6843   UCHAR  ucPhySel;
6844   ULONG  ulAnalogSetting[1];
6845 }CLOCK_CONDITION_SETTING_ENTRY;
6846
6847 typedef struct _CLOCK_CONDITION_SETTING_INFO{
6848   USHORT usEntrySize;
6849   CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
6850 }CLOCK_CONDITION_SETTING_INFO;
6851
6852 typedef struct _PHY_CONDITION_REG_VAL{
6853   ULONG  ulCondition;
6854   ULONG  ulRegVal;
6855 }PHY_CONDITION_REG_VAL;
6856
6857 typedef struct _PHY_CONDITION_REG_INFO{
6858   USHORT usRegIndex;
6859   USHORT usSize;
6860   PHY_CONDITION_REG_VAL asRegVal[1];
6861 }PHY_CONDITION_REG_INFO;
6862
6863 typedef struct _PHY_ANALOG_SETTING_INFO{
6864   UCHAR  ucEncodeMode;
6865   UCHAR  ucPhySel;
6866   USHORT usSize;
6867   PHY_CONDITION_REG_INFO  asAnalogSetting[1];
6868 }PHY_ANALOG_SETTING_INFO;
6869
6870 /****************************************************************************/
6871 //Portion VI: Definitinos for vbios MC scratch registers that driver used
6872 /****************************************************************************/
6873
6874 #define MC_MISC0__MEMORY_TYPE_MASK    0xF0000000
6875 #define MC_MISC0__MEMORY_TYPE__GDDR1  0x10000000
6876 #define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
6877 #define MC_MISC0__MEMORY_TYPE__GDDR3  0x30000000
6878 #define MC_MISC0__MEMORY_TYPE__GDDR4  0x40000000
6879 #define MC_MISC0__MEMORY_TYPE__GDDR5  0x50000000
6880 #define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
6881
6882 /****************************************************************************/
6883 //Portion VI: Definitinos being oboselete
6884 /****************************************************************************/
6885
6886 //==========================================================================================
6887 //Remove the definitions below when driver is ready!
6888 typedef struct _ATOM_DAC_INFO
6889 {
6890   ATOM_COMMON_TABLE_HEADER sHeader;
6891   USHORT                   usMaxFrequency;      // in 10kHz unit
6892   USHORT                   usReserved;
6893 }ATOM_DAC_INFO;
6894
6895
6896 typedef struct  _COMPASSIONATE_DATA
6897 {
6898   ATOM_COMMON_TABLE_HEADER sHeader;
6899
6900   //==============================  DAC1 portion
6901   UCHAR   ucDAC1_BG_Adjustment;
6902   UCHAR   ucDAC1_DAC_Adjustment;
6903   USHORT  usDAC1_FORCE_Data;
6904   //==============================  DAC2 portion
6905   UCHAR   ucDAC2_CRT2_BG_Adjustment;
6906   UCHAR   ucDAC2_CRT2_DAC_Adjustment;
6907   USHORT  usDAC2_CRT2_FORCE_Data;
6908   USHORT  usDAC2_CRT2_MUX_RegisterIndex;
6909   UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6910   UCHAR   ucDAC2_NTSC_BG_Adjustment;
6911   UCHAR   ucDAC2_NTSC_DAC_Adjustment;
6912   USHORT  usDAC2_TV1_FORCE_Data;
6913   USHORT  usDAC2_TV1_MUX_RegisterIndex;
6914   UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6915   UCHAR   ucDAC2_CV_BG_Adjustment;
6916   UCHAR   ucDAC2_CV_DAC_Adjustment;
6917   USHORT  usDAC2_CV_FORCE_Data;
6918   USHORT  usDAC2_CV_MUX_RegisterIndex;
6919   UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
6920   UCHAR   ucDAC2_PAL_BG_Adjustment;
6921   UCHAR   ucDAC2_PAL_DAC_Adjustment;
6922   USHORT  usDAC2_TV2_FORCE_Data;
6923 }COMPASSIONATE_DATA;
6924
6925 /****************************Supported Device Info Table Definitions**********************/
6926 //  ucConnectInfo:
6927 //    [7:4] - connector type
6928 //      = 1   - VGA connector
6929 //      = 2   - DVI-I
6930 //      = 3   - DVI-D
6931 //      = 4   - DVI-A
6932 //      = 5   - SVIDEO
6933 //      = 6   - COMPOSITE
6934 //      = 7   - LVDS
6935 //      = 8   - DIGITAL LINK
6936 //      = 9   - SCART
6937 //      = 0xA - HDMI_type A
6938 //      = 0xB - HDMI_type B
6939 //      = 0xE - Special case1 (DVI+DIN)
6940 //      Others=TBD
6941 //    [3:0] - DAC Associated
6942 //      = 0   - no DAC
6943 //      = 1   - DACA
6944 //      = 2   - DACB
6945 //      = 3   - External DAC
6946 //      Others=TBD
6947 //
6948
6949 typedef struct _ATOM_CONNECTOR_INFO
6950 {
6951 #if ATOM_BIG_ENDIAN
6952   UCHAR   bfConnectorType:4;
6953   UCHAR   bfAssociatedDAC:4;
6954 #else
6955   UCHAR   bfAssociatedDAC:4;
6956   UCHAR   bfConnectorType:4;
6957 #endif
6958 }ATOM_CONNECTOR_INFO;
6959
6960 typedef union _ATOM_CONNECTOR_INFO_ACCESS
6961 {
6962   ATOM_CONNECTOR_INFO sbfAccess;
6963   UCHAR               ucAccess;
6964 }ATOM_CONNECTOR_INFO_ACCESS;
6965
6966 typedef struct _ATOM_CONNECTOR_INFO_I2C
6967 {
6968   ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
6969   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
6970 }ATOM_CONNECTOR_INFO_I2C;
6971
6972
6973 typedef struct _ATOM_SUPPORTED_DEVICES_INFO
6974 {
6975   ATOM_COMMON_TABLE_HEADER      sHeader;
6976   USHORT                    usDeviceSupport;
6977   ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
6978 }ATOM_SUPPORTED_DEVICES_INFO;
6979
6980 #define NO_INT_SRC_MAPPED       0xFF
6981
6982 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
6983 {
6984   UCHAR   ucIntSrcBitmap;
6985 }ATOM_CONNECTOR_INC_SRC_BITMAP;
6986
6987 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
6988 {
6989   ATOM_COMMON_TABLE_HEADER      sHeader;
6990   USHORT                        usDeviceSupport;
6991   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6992   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
6993 }ATOM_SUPPORTED_DEVICES_INFO_2;
6994
6995 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
6996 {
6997   ATOM_COMMON_TABLE_HEADER      sHeader;
6998   USHORT                        usDeviceSupport;
6999   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
7000   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
7001 }ATOM_SUPPORTED_DEVICES_INFO_2d1;
7002
7003 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
7004
7005
7006
7007 typedef struct _ATOM_MISC_CONTROL_INFO
7008 {
7009    USHORT usFrequency;
7010    UCHAR  ucPLL_ChargePump;                                             // PLL charge-pump gain control
7011    UCHAR  ucPLL_DutyCycle;                                              // PLL duty cycle control
7012    UCHAR  ucPLL_VCO_Gain;                                                 // PLL VCO gain control
7013    UCHAR  ucPLL_VoltageSwing;                                   // PLL driver voltage swing control
7014 }ATOM_MISC_CONTROL_INFO;
7015
7016
7017 #define ATOM_MAX_MISC_INFO       4
7018
7019 typedef struct _ATOM_TMDS_INFO
7020 {
7021   ATOM_COMMON_TABLE_HEADER sHeader;
7022   USHORT                                                        usMaxFrequency;             // in 10Khz
7023   ATOM_MISC_CONTROL_INFO                                asMiscInfo[ATOM_MAX_MISC_INFO];
7024 }ATOM_TMDS_INFO;
7025
7026
7027 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
7028 {
7029   UCHAR ucTVStandard;     //Same as TV standards defined above,
7030   UCHAR ucPadding[1];
7031 }ATOM_ENCODER_ANALOG_ATTRIBUTE;
7032
7033 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
7034 {
7035   UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
7036   UCHAR ucPadding[1];
7037 }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
7038
7039 typedef union _ATOM_ENCODER_ATTRIBUTE
7040 {
7041   ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
7042   ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
7043 }ATOM_ENCODER_ATTRIBUTE;
7044
7045
7046 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
7047 {
7048   USHORT usPixelClock;
7049   USHORT usEncoderID;
7050   UCHAR  ucDeviceType;                                                                                          //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
7051   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
7052   ATOM_ENCODER_ATTRIBUTE usDevAttr;
7053 }DVO_ENCODER_CONTROL_PARAMETERS;
7054
7055 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
7056 {
7057   DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
7058   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
7059 }DVO_ENCODER_CONTROL_PS_ALLOCATION;
7060
7061
7062 #define ATOM_XTMDS_ASIC_SI164_ID        1
7063 #define ATOM_XTMDS_ASIC_SI178_ID        2
7064 #define ATOM_XTMDS_ASIC_TFP513_ID       3
7065 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
7066 #define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
7067 #define ATOM_XTMDS_MVPU_FPGA            0x00000004
7068
7069
7070 typedef struct _ATOM_XTMDS_INFO
7071 {
7072   ATOM_COMMON_TABLE_HEADER   sHeader;
7073   USHORT                     usSingleLinkMaxFrequency;
7074   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
7075   UCHAR                      ucXtransimitterID;
7076   UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
7077   UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
7078                                                  // due to design. This ID is used to alert driver that the sequence is not "standard"!
7079   UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
7080   UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
7081 }ATOM_XTMDS_INFO;
7082
7083 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
7084 {
7085   UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
7086   UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
7087   UCHAR ucPadding[2];
7088 }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
7089
7090 /****************************Legacy Power Play Table Definitions **********************/
7091
7092 //Definitions for ulPowerPlayMiscInfo
7093 #define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
7094 #define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
7095 #define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
7096
7097 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
7098 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
7099
7100 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
7101
7102 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
7103 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
7104 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
7105
7106 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
7107 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
7108 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
7109 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
7110 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
7111 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
7112 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
7113
7114 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
7115 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
7116 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
7117 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
7118 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
7119
7120 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
7121 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
7122
7123 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
7124 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
7125 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
7126 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
7127 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
7128 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
7129
7130 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
7131 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
7132 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
7133
7134 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
7135 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
7136 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
7137 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
7138 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
7139 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
7140 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
7141                                                                       //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
7142 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
7143 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
7144 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
7145
7146 //ucTableFormatRevision=1
7147 //ucTableContentRevision=1
7148 typedef struct  _ATOM_POWERMODE_INFO
7149 {
7150   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
7151   ULONG     ulReserved1;                // must set to 0
7152   ULONG     ulReserved2;                // must set to 0
7153   USHORT    usEngineClock;
7154   USHORT    usMemoryClock;
7155   UCHAR     ucVoltageDropIndex;         // index to GPIO table
7156   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
7157   UCHAR     ucMinTemperature;
7158   UCHAR     ucMaxTemperature;
7159   UCHAR     ucNumPciELanes;             // number of PCIE lanes
7160 }ATOM_POWERMODE_INFO;
7161
7162 //ucTableFormatRevision=2
7163 //ucTableContentRevision=1
7164 typedef struct  _ATOM_POWERMODE_INFO_V2
7165 {
7166   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
7167   ULONG     ulMiscInfo2;
7168   ULONG     ulEngineClock;
7169   ULONG     ulMemoryClock;
7170   UCHAR     ucVoltageDropIndex;         // index to GPIO table
7171   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
7172   UCHAR     ucMinTemperature;
7173   UCHAR     ucMaxTemperature;
7174   UCHAR     ucNumPciELanes;             // number of PCIE lanes
7175 }ATOM_POWERMODE_INFO_V2;
7176
7177 //ucTableFormatRevision=2
7178 //ucTableContentRevision=2
7179 typedef struct  _ATOM_POWERMODE_INFO_V3
7180 {
7181   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
7182   ULONG     ulMiscInfo2;
7183   ULONG     ulEngineClock;
7184   ULONG     ulMemoryClock;
7185   UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
7186   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
7187   UCHAR     ucMinTemperature;
7188   UCHAR     ucMaxTemperature;
7189   UCHAR     ucNumPciELanes;             // number of PCIE lanes
7190   UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
7191 }ATOM_POWERMODE_INFO_V3;
7192
7193
7194 #define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
7195
7196 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
7197 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
7198
7199 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
7200 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
7201 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
7202 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
7203 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
7204 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
7205 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07      // Andigilog
7206
7207
7208 typedef struct  _ATOM_POWERPLAY_INFO
7209 {
7210   ATOM_COMMON_TABLE_HEADER      sHeader;
7211   UCHAR    ucOverdriveThermalController;
7212   UCHAR    ucOverdriveI2cLine;
7213   UCHAR    ucOverdriveIntBitmap;
7214   UCHAR    ucOverdriveControllerAddress;
7215   UCHAR    ucSizeOfPowerModeEntry;
7216   UCHAR    ucNumOfPowerModeEntries;
7217   ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7218 }ATOM_POWERPLAY_INFO;
7219
7220 typedef struct  _ATOM_POWERPLAY_INFO_V2
7221 {
7222   ATOM_COMMON_TABLE_HEADER      sHeader;
7223   UCHAR    ucOverdriveThermalController;
7224   UCHAR    ucOverdriveI2cLine;
7225   UCHAR    ucOverdriveIntBitmap;
7226   UCHAR    ucOverdriveControllerAddress;
7227   UCHAR    ucSizeOfPowerModeEntry;
7228   UCHAR    ucNumOfPowerModeEntries;
7229   ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7230 }ATOM_POWERPLAY_INFO_V2;
7231
7232 typedef struct  _ATOM_POWERPLAY_INFO_V3
7233 {
7234   ATOM_COMMON_TABLE_HEADER      sHeader;
7235   UCHAR    ucOverdriveThermalController;
7236   UCHAR    ucOverdriveI2cLine;
7237   UCHAR    ucOverdriveIntBitmap;
7238   UCHAR    ucOverdriveControllerAddress;
7239   UCHAR    ucSizeOfPowerModeEntry;
7240   UCHAR    ucNumOfPowerModeEntries;
7241   ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
7242 }ATOM_POWERPLAY_INFO_V3;
7243
7244 /* New PPlib */
7245 /**************************************************************************/
7246 typedef struct _ATOM_PPLIB_THERMALCONTROLLER
7247
7248 {
7249     UCHAR ucType;           // one of ATOM_PP_THERMALCONTROLLER_*
7250     UCHAR ucI2cLine;        // as interpreted by DAL I2C
7251     UCHAR ucI2cAddress;
7252     UCHAR ucFanParameters;  // Fan Control Parameters.
7253     UCHAR ucFanMinRPM;      // Fan Minimum RPM (hundreds) -- for display purposes only.
7254     UCHAR ucFanMaxRPM;      // Fan Maximum RPM (hundreds) -- for display purposes only.
7255     UCHAR ucReserved;       // ----
7256     UCHAR ucFlags;          // to be defined
7257 } ATOM_PPLIB_THERMALCONTROLLER;
7258
7259 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
7260 #define ATOM_PP_FANPARAMETERS_NOFAN                                 0x80    // No fan is connected to this controller.
7261
7262 #define ATOM_PP_THERMALCONTROLLER_NONE      0
7263 #define ATOM_PP_THERMALCONTROLLER_LM63      1  // Not used by PPLib
7264 #define ATOM_PP_THERMALCONTROLLER_ADM1032   2  // Not used by PPLib
7265 #define ATOM_PP_THERMALCONTROLLER_ADM1030   3  // Not used by PPLib
7266 #define ATOM_PP_THERMALCONTROLLER_MUA6649   4  // Not used by PPLib
7267 #define ATOM_PP_THERMALCONTROLLER_LM64      5
7268 #define ATOM_PP_THERMALCONTROLLER_F75375    6  // Not used by PPLib
7269 #define ATOM_PP_THERMALCONTROLLER_RV6xx     7
7270 #define ATOM_PP_THERMALCONTROLLER_RV770     8
7271 #define ATOM_PP_THERMALCONTROLLER_ADT7473   9
7272 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO     11
7273 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
7274 #define ATOM_PP_THERMALCONTROLLER_EMC2103   13  /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
7275 #define ATOM_PP_THERMALCONTROLLER_SUMO      14  /* 0x0E */ // Sumo type, used internally
7276 #define ATOM_PP_THERMALCONTROLLER_NISLANDS  15
7277 #define ATOM_PP_THERMALCONTROLLER_SISLANDS  16
7278 #define ATOM_PP_THERMALCONTROLLER_LM96163   17
7279
7280 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
7281 // We probably should reserve the bit 0x80 for this use.
7282 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
7283 // The driver can pick the correct internal controller based on the ASIC.
7284
7285 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL   0x89    // ADT7473 Fan Control + Internal Thermal Controller
7286 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL   0x8D    // EMC2103 Fan Control + Internal Thermal Controller
7287
7288 typedef struct _ATOM_PPLIB_STATE
7289 {
7290     UCHAR ucNonClockStateIndex;
7291     UCHAR ucClockStateIndices[1]; // variable-sized
7292 } ATOM_PPLIB_STATE;
7293
7294
7295 typedef struct _ATOM_PPLIB_FANTABLE
7296 {
7297     UCHAR   ucFanTableFormat;                // Change this if the table format changes or version changes so that the other fields are not the same.
7298     UCHAR   ucTHyst;                         // Temperature hysteresis. Integer.
7299     USHORT  usTMin;                          // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
7300     USHORT  usTMed;                          // The middle temperature where we change slopes.
7301     USHORT  usTHigh;                         // The high point above TMed for adjusting the second slope.
7302     USHORT  usPWMMin;                        // The minimum PWM value in percent (0.01% increments).
7303     USHORT  usPWMMed;                        // The PWM value (in percent) at TMed.
7304     USHORT  usPWMHigh;                       // The PWM value at THigh.
7305 } ATOM_PPLIB_FANTABLE;
7306
7307 typedef struct _ATOM_PPLIB_FANTABLE2
7308 {
7309     ATOM_PPLIB_FANTABLE basicTable;
7310     USHORT  usTMax;                          // The max temperature
7311 } ATOM_PPLIB_FANTABLE2;
7312
7313 typedef struct _ATOM_PPLIB_EXTENDEDHEADER
7314 {
7315     USHORT  usSize;
7316     ULONG   ulMaxEngineClock;   // For Overdrive.
7317     ULONG   ulMaxMemoryClock;   // For Overdrive.
7318     // Add extra system parameters here, always adjust size to include all fields.
7319     USHORT  usVCETableOffset; //points to ATOM_PPLIB_VCE_Table
7320     USHORT  usUVDTableOffset;   //points to ATOM_PPLIB_UVD_Table
7321 } ATOM_PPLIB_EXTENDEDHEADER;
7322
7323 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
7324 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
7325 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
7326 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
7327 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
7328 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
7329 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
7330 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
7331 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
7332 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
7333 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
7334 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
7335 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
7336 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
7337 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000              // Go to boot state on alerts, e.g. on an AC->DC transition.
7338 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000   // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
7339 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000                   // Does the driver control VDDCI independently from VDDC.
7340 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000               // Enable the 'regulator hot' feature.
7341 #define ATOM_PP_PLATFORM_CAP_BACO          0x00020000               // Does the driver supports BACO state.
7342
7343
7344 typedef struct _ATOM_PPLIB_POWERPLAYTABLE
7345 {
7346       ATOM_COMMON_TABLE_HEADER sHeader;
7347
7348       UCHAR ucDataRevision;
7349
7350       UCHAR ucNumStates;
7351       UCHAR ucStateEntrySize;
7352       UCHAR ucClockInfoSize;
7353       UCHAR ucNonClockSize;
7354
7355       // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
7356       USHORT usStateArrayOffset;
7357
7358       // offset from start of this table to array of ASIC-specific structures,
7359       // currently ATOM_PPLIB_CLOCK_INFO.
7360       USHORT usClockInfoArrayOffset;
7361
7362       // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
7363       USHORT usNonClockInfoArrayOffset;
7364
7365       USHORT usBackbiasTime;    // in microseconds
7366       USHORT usVoltageTime;     // in microseconds
7367       USHORT usTableSize;       //the size of this structure, or the extended structure
7368
7369       ULONG ulPlatformCaps;            // See ATOM_PPLIB_CAPS_*
7370
7371       ATOM_PPLIB_THERMALCONTROLLER    sThermalController;
7372
7373       USHORT usBootClockInfoOffset;
7374       USHORT usBootNonClockInfoOffset;
7375
7376 } ATOM_PPLIB_POWERPLAYTABLE;
7377
7378 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
7379 {
7380     ATOM_PPLIB_POWERPLAYTABLE basicTable;
7381     UCHAR   ucNumCustomThermalPolicy;
7382     USHORT  usCustomThermalPolicyArrayOffset;
7383 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
7384
7385 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
7386 {
7387     ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
7388     USHORT                     usFormatID;                      // To be used ONLY by PPGen.
7389     USHORT                     usFanTableOffset;
7390     USHORT                     usExtendendedHeaderOffset;
7391 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
7392
7393 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
7394 {
7395     ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
7396     ULONG                      ulGoldenPPID;                    // PPGen use only
7397     ULONG                      ulGoldenRevision;                // PPGen use only
7398     USHORT                     usVddcDependencyOnSCLKOffset;
7399     USHORT                     usVddciDependencyOnMCLKOffset;
7400     USHORT                     usVddcDependencyOnMCLKOffset;
7401     USHORT                     usMaxClockVoltageOnDCOffset;
7402     USHORT                     usVddcPhaseShedLimitsTableOffset;    // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
7403     USHORT                     usReserved;
7404 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
7405
7406 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
7407 {
7408     ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
7409     ULONG                      ulTDPLimit;
7410     ULONG                      ulNearTDPLimit;
7411     ULONG                      ulSQRampingThreshold;
7412     USHORT                     usCACLeakageTableOffset;         // Points to ATOM_PPLIB_CAC_Leakage_Table
7413     ULONG                      ulCACLeakage;                    // The iLeakage for driver calculated CAC leakage table
7414     USHORT                     usTDPODLimit;
7415     USHORT                     usLoadLineSlope;                 // in milliOhms * 100
7416 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
7417
7418 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification
7419 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK          0x0007
7420 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT         0
7421 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE          0
7422 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY       1
7423 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED      3
7424 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE   5
7425 // 2, 4, 6, 7 are reserved
7426
7427 #define ATOM_PPLIB_CLASSIFICATION_BOOT                   0x0008
7428 #define ATOM_PPLIB_CLASSIFICATION_THERMAL                0x0010
7429 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE     0x0020
7430 #define ATOM_PPLIB_CLASSIFICATION_REST                   0x0040
7431 #define ATOM_PPLIB_CLASSIFICATION_FORCED                 0x0080
7432 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE          0x0100
7433 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE      0x0200
7434 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE               0x0400
7435 #define ATOM_PPLIB_CLASSIFICATION_3DLOW                  0x0800
7436 #define ATOM_PPLIB_CLASSIFICATION_ACPI                   0x1000
7437 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE               0x2000
7438 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE                0x4000
7439 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE                0x8000
7440
7441 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
7442 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2     0x0001
7443 #define ATOM_PPLIB_CLASSIFICATION2_ULV                      0x0002
7444 #define ATOM_PPLIB_CLASSIFICATION2_MVC                      0x0004   //Multi-View Codec (BD-3D)
7445
7446 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
7447 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY           0x00000001
7448 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK         0x00000002
7449
7450 // 0 is 2.5Gb/s, 1 is 5Gb/s
7451 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK            0x00000004
7452 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT           2
7453
7454 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
7455 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
7456 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
7457
7458 // lookup into reduced refresh-rate table
7459 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
7460 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
7461
7462 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
7463 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
7464 // 2-15 TBD as needed.
7465
7466 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING        0x00001000
7467 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS  0x00002000
7468
7469 #define ATOM_PPLIB_DISALLOW_ON_DC                       0x00004000
7470
7471 #define ATOM_PPLIB_ENABLE_VARIBRIGHT                     0x00008000
7472
7473 //memory related flags
7474 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF               0x000010000
7475
7476 //M3 Arb    //2bits, current 3 sets of parameters in total
7477 #define ATOM_PPLIB_M3ARB_MASK                       0x00060000
7478 #define ATOM_PPLIB_M3ARB_SHIFT                      17
7479
7480 #define ATOM_PPLIB_ENABLE_DRR                       0x00080000
7481
7482 // remaining 16 bits are reserved
7483 typedef struct _ATOM_PPLIB_THERMAL_STATE
7484 {
7485     UCHAR   ucMinTemperature;
7486     UCHAR   ucMaxTemperature;
7487     UCHAR   ucThermalAction;
7488 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
7489
7490 // Contained in an array starting at the offset
7491 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
7492 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
7493 #define ATOM_PPLIB_NONCLOCKINFO_VER1      12
7494 #define ATOM_PPLIB_NONCLOCKINFO_VER2      24
7495 typedef struct _ATOM_PPLIB_NONCLOCK_INFO
7496 {
7497       USHORT usClassification;
7498       UCHAR  ucMinTemperature;
7499       UCHAR  ucMaxTemperature;
7500       ULONG  ulCapsAndSettings;
7501       UCHAR  ucRequiredPower;
7502       USHORT usClassification2;
7503       ULONG  ulVCLK;
7504       ULONG  ulDCLK;
7505       UCHAR  ucUnused[5];
7506 } ATOM_PPLIB_NONCLOCK_INFO;
7507
7508 // Contained in an array starting at the offset
7509 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
7510 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices
7511 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
7512 {
7513       USHORT usEngineClockLow;
7514       UCHAR ucEngineClockHigh;
7515
7516       USHORT usMemoryClockLow;
7517       UCHAR ucMemoryClockHigh;
7518
7519       USHORT usVDDC;
7520       USHORT usUnused1;
7521       USHORT usUnused2;
7522
7523       ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7524
7525 } ATOM_PPLIB_R600_CLOCK_INFO;
7526
7527 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
7528 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2          1
7529 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE           2
7530 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE    4
7531 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF    8
7532 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF   16
7533 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER         32   // On the RV770 use 'low power' setting (sequencer S0).
7534
7535 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
7536 {
7537       USHORT usEngineClockLow;
7538       UCHAR  ucEngineClockHigh;
7539
7540       USHORT usMemoryClockLow;
7541       UCHAR  ucMemoryClockHigh;
7542
7543       USHORT usVDDC;
7544       USHORT usVDDCI;
7545       USHORT usUnused;
7546
7547       ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
7548
7549 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
7550
7551 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO
7552 {
7553       USHORT usEngineClockLow;
7554       UCHAR  ucEngineClockHigh;
7555
7556       USHORT usMemoryClockLow;
7557       UCHAR  ucMemoryClockHigh;
7558
7559       USHORT usVDDC;
7560       USHORT usVDDCI;
7561       UCHAR  ucPCIEGen;
7562       UCHAR  ucUnused1;
7563
7564       ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now
7565
7566 } ATOM_PPLIB_SI_CLOCK_INFO;
7567
7568
7569 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
7570
7571 {
7572       USHORT usLowEngineClockLow;         // Low Engine clock in MHz (the same way as on the R600).
7573       UCHAR  ucLowEngineClockHigh;
7574       USHORT usHighEngineClockLow;        // High Engine clock in MHz.
7575       UCHAR  ucHighEngineClockHigh;
7576       USHORT usMemoryClockLow;            // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
7577       UCHAR  ucMemoryClockHigh;           // Currentyl unused.
7578       UCHAR  ucPadding;                   // For proper alignment and size.
7579       USHORT usVDDC;                      // For the 780, use: None, Low, High, Variable
7580       UCHAR  ucMaxHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}
7581       UCHAR  ucMinHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement.
7582       USHORT usHTLinkFreq;                // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
7583       ULONG  ulFlags;
7584 } ATOM_PPLIB_RS780_CLOCK_INFO;
7585
7586 #define ATOM_PPLIB_RS780_VOLTAGE_NONE       0
7587 #define ATOM_PPLIB_RS780_VOLTAGE_LOW        1
7588 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH       2
7589 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE   3
7590
7591 #define ATOM_PPLIB_RS780_SPMCLK_NONE        0   // We cannot change the side port memory clock, leave it as it is.
7592 #define ATOM_PPLIB_RS780_SPMCLK_LOW         1
7593 #define ATOM_PPLIB_RS780_SPMCLK_HIGH        2
7594
7595 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE       0
7596 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW        1
7597 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH       2
7598
7599 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
7600       USHORT usEngineClockLow;  //clockfrequency & 0xFFFF. The unit is in 10khz
7601       UCHAR  ucEngineClockHigh; //clockfrequency >> 16.
7602       UCHAR  vddcIndex;         //2-bit vddc index;
7603       USHORT tdpLimit;
7604       //please initalize to 0
7605       USHORT rsv1;
7606       //please initialize to 0s
7607       ULONG rsv2[2];
7608 }ATOM_PPLIB_SUMO_CLOCK_INFO;
7609
7610
7611
7612 typedef struct _ATOM_PPLIB_STATE_V2
7613 {
7614       //number of valid dpm levels in this state; Driver uses it to calculate the whole
7615       //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
7616       UCHAR ucNumDPMLevels;
7617
7618       //a index to the array of nonClockInfos
7619       UCHAR nonClockInfoIndex;
7620       /**
7621       * Driver will read the first ucNumDPMLevels in this array
7622       */
7623       UCHAR clockInfoIndex[1];
7624 } ATOM_PPLIB_STATE_V2;
7625
7626 typedef struct _StateArray{
7627     //how many states we have
7628     UCHAR ucNumEntries;
7629
7630     ATOM_PPLIB_STATE_V2 states[1];
7631 }StateArray;
7632
7633
7634 typedef struct _ClockInfoArray{
7635     //how many clock levels we have
7636     UCHAR ucNumEntries;
7637
7638     //sizeof(ATOM_PPLIB_CLOCK_INFO)
7639     UCHAR ucEntrySize;
7640
7641     UCHAR clockInfo[1];
7642 }ClockInfoArray;
7643
7644 typedef struct _NonClockInfoArray{
7645
7646     //how many non-clock levels we have. normally should be same as number of states
7647     UCHAR ucNumEntries;
7648     //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
7649     UCHAR ucEntrySize;
7650
7651     ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
7652 }NonClockInfoArray;
7653
7654 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
7655 {
7656     USHORT usClockLow;
7657     UCHAR  ucClockHigh;
7658     USHORT usVoltage;
7659 }ATOM_PPLIB_Clock_Voltage_Dependency_Record;
7660
7661 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
7662 {
7663     UCHAR ucNumEntries;                                                // Number of entries.
7664     ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1];             // Dynamically allocate entries.
7665 }ATOM_PPLIB_Clock_Voltage_Dependency_Table;
7666
7667 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
7668 {
7669     USHORT usSclkLow;
7670     UCHAR  ucSclkHigh;
7671     USHORT usMclkLow;
7672     UCHAR  ucMclkHigh;
7673     USHORT usVddc;
7674     USHORT usVddci;
7675 }ATOM_PPLIB_Clock_Voltage_Limit_Record;
7676
7677 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
7678 {
7679     UCHAR ucNumEntries;                                                // Number of entries.
7680     ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1];                  // Dynamically allocate entries.
7681 }ATOM_PPLIB_Clock_Voltage_Limit_Table;
7682
7683 typedef struct _ATOM_PPLIB_CAC_Leakage_Record
7684 {
7685     USHORT usVddc;  // We use this field for the "fake" standardized VDDC for power calculations
7686     ULONG  ulLeakageValue;
7687 }ATOM_PPLIB_CAC_Leakage_Record;
7688
7689 typedef struct _ATOM_PPLIB_CAC_Leakage_Table
7690 {
7691     UCHAR ucNumEntries;                                                 // Number of entries.
7692     ATOM_PPLIB_CAC_Leakage_Record entries[1];                           // Dynamically allocate entries.
7693 }ATOM_PPLIB_CAC_Leakage_Table;
7694
7695 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
7696 {
7697     USHORT usVoltage;
7698     USHORT usSclkLow;
7699     UCHAR  ucSclkHigh;
7700     USHORT usMclkLow;
7701     UCHAR  ucMclkHigh;
7702 }ATOM_PPLIB_PhaseSheddingLimits_Record;
7703
7704 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
7705 {
7706     UCHAR ucNumEntries;                                                 // Number of entries.
7707     ATOM_PPLIB_PhaseSheddingLimits_Record entries[1];                   // Dynamically allocate entries.
7708 }ATOM_PPLIB_PhaseSheddingLimits_Table;
7709
7710 typedef struct _VCEClockInfo{
7711     USHORT usEVClkLow;
7712     UCHAR  ucEVClkHigh;
7713     USHORT usECClkLow;
7714     UCHAR  ucECClkHigh;
7715 }VCEClockInfo;
7716
7717 typedef struct _VCEClockInfoArray{
7718     UCHAR ucNumEntries;
7719     VCEClockInfo entries[1];
7720 }VCEClockInfoArray;
7721
7722 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
7723 {
7724     USHORT usVoltage;
7725     UCHAR  ucVCEClockInfoIndex;
7726 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record;
7727
7728 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
7729 {
7730     UCHAR numEntries;
7731     ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
7732 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
7733
7734 typedef struct _ATOM_PPLIB_VCE_State_Record
7735 {
7736     UCHAR  ucVCEClockInfoIndex;
7737     UCHAR  ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7738 }ATOM_PPLIB_VCE_State_Record;
7739
7740 typedef struct _ATOM_PPLIB_VCE_State_Table
7741 {
7742     UCHAR numEntries;
7743     ATOM_PPLIB_VCE_State_Record entries[1];
7744 }ATOM_PPLIB_VCE_State_Table;
7745
7746
7747 typedef struct _ATOM_PPLIB_VCE_Table
7748 {
7749       UCHAR revid;
7750 //    VCEClockInfoArray array;
7751 //    ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits;
7752 //    ATOM_PPLIB_VCE_State_Table states;
7753 }ATOM_PPLIB_VCE_Table;
7754
7755
7756 typedef struct _UVDClockInfo{
7757     USHORT usVClkLow;
7758     UCHAR  ucVClkHigh;
7759     USHORT usDClkLow;
7760     UCHAR  ucDClkHigh;
7761 }UVDClockInfo;
7762
7763 typedef struct _UVDClockInfoArray{
7764     UCHAR ucNumEntries;
7765     UVDClockInfo entries[1];
7766 }UVDClockInfoArray;
7767
7768 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
7769 {
7770     USHORT usVoltage;
7771     UCHAR  ucUVDClockInfoIndex;
7772 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record;
7773
7774 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
7775 {
7776     UCHAR numEntries;
7777     ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
7778 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
7779
7780 typedef struct _ATOM_PPLIB_UVD_State_Record
7781 {
7782     UCHAR  ucUVDClockInfoIndex;
7783     UCHAR  ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary
7784 }ATOM_PPLIB_UVD_State_Record;
7785
7786 typedef struct _ATOM_PPLIB_UVD_State_Table
7787 {
7788     UCHAR numEntries;
7789     ATOM_PPLIB_UVD_State_Record entries[1];
7790 }ATOM_PPLIB_UVD_State_Table;
7791
7792
7793 typedef struct _ATOM_PPLIB_UVD_Table
7794 {
7795       UCHAR revid;
7796 //    UVDClockInfoArray array;
7797 //    ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits;
7798 //    ATOM_PPLIB_UVD_State_Table states;
7799 }ATOM_PPLIB_UVD_Table;
7800
7801 /**************************************************************************/
7802
7803
7804 // Following definitions are for compatibility issue in different SW components.
7805 #define ATOM_MASTER_DATA_TABLE_REVISION   0x01
7806 #define Object_Info                                                                                             Object_Header
7807 #define AdjustARB_SEQ                                                                                   MC_InitParameter
7808 #define VRAM_GPIO_DetectionInfo                                         VoltageObjectInfo
7809 #define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
7810 #define ASIC_MVDDQ_Info                                                                         MemoryTrainingInfo
7811 #define SS_Info                           PPLL_SS_Info
7812 #define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
7813 #define DispDevicePriorityInfo                                          SaveRestoreInfo
7814 #define DispOutInfo                                                                                             TV_VideoMode
7815
7816
7817 #define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
7818 #define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
7819
7820 //New device naming, remove them when both DAL/VBIOS is ready
7821 #define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
7822 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
7823
7824 #define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
7825 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
7826
7827 #define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
7828 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
7829
7830 #define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
7831 #define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
7832
7833 #define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
7834 #define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
7835
7836 #define ATOM_DEVICE_DFP2I_INDEX            0x00000009
7837 #define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
7838
7839 #define ATOM_S0_DFP1I                      ATOM_S0_DFP1
7840 #define ATOM_S0_DFP1X                      ATOM_S0_DFP2
7841
7842 #define ATOM_S0_DFP2I                      0x00200000L
7843 #define ATOM_S0_DFP2Ib2                    0x20
7844
7845 #define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
7846 #define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
7847
7848 #define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
7849 #define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
7850
7851 #define ATOM_S3_DFP2I_ACTIVEb1             0x02
7852
7853 #define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
7854 #define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
7855
7856 #define ATOM_S3_DFP2I_ACTIVE               0x00000200L
7857
7858 #define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
7859 #define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
7860 #define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
7861
7862 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
7863 #define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
7864
7865 #define ATOM_S5_DOS_REQ_DFP2I              0x0200
7866 #define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
7867 #define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
7868
7869 #define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
7870 #define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
7871
7872 #define TMDS1XEncoderControl               DVOEncoderControl
7873 #define DFP1XOutputControl                 DVOOutputControl
7874
7875 #define ExternalDFPOutputControl           DFP1XOutputControl
7876 #define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
7877
7878 #define DFP1IOutputControl                 TMDSAOutputControl
7879 #define DFP2IOutputControl                 LVTMAOutputControl
7880
7881 #define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
7882 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7883
7884 #define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
7885 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
7886
7887 #define ucDac1Standard  ucDacStandard
7888 #define ucDac2Standard  ucDacStandard
7889
7890 #define TMDS1EncoderControl TMDSAEncoderControl
7891 #define TMDS2EncoderControl LVTMAEncoderControl
7892
7893 #define DFP1OutputControl   TMDSAOutputControl
7894 #define DFP2OutputControl   LVTMAOutputControl
7895 #define CRT1OutputControl   DAC1OutputControl
7896 #define CRT2OutputControl   DAC2OutputControl
7897
7898 //These two lines will be removed for sure in a few days, will follow up with Michael V.
7899 #define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
7900 #define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
7901
7902 //#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
7903 //#define ATOM_S2_LCD1_DPMS_STATE               ATOM_S2_CRT1_DPMS_STATE
7904 //#define ATOM_S2_TV1_DPMS_STATE          ATOM_S2_CRT1_DPMS_STATE
7905 //#define ATOM_S2_DFP1_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
7906 //#define ATOM_S2_CRT2_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
7907
7908 #define ATOM_S6_ACC_REQ_TV2             0x00400000L
7909 #define ATOM_DEVICE_TV2_INDEX           0x00000006
7910 #define ATOM_DEVICE_TV2_SUPPORT         (0x1L << ATOM_DEVICE_TV2_INDEX)
7911 #define ATOM_S0_TV2                     0x00100000L
7912 #define ATOM_S3_TV2_ACTIVE              ATOM_S3_DFP6_ACTIVE
7913 #define ATOM_S3_TV2_CRTC_ACTIVE         ATOM_S3_DFP6_CRTC_ACTIVE
7914
7915 //
7916 #define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
7917 #define ATOM_S2_LCD1_DPMS_STATE         0x00020000L
7918 #define ATOM_S2_TV1_DPMS_STATE          0x00040000L
7919 #define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
7920 #define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
7921 #define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
7922 #define ATOM_S2_TV2_DPMS_STATE          0x00400000L
7923 #define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
7924 #define ATOM_S2_CV_DPMS_STATE           0x01000000L
7925 #define ATOM_S2_DFP3_DPMS_STATE                                 0x02000000L
7926 #define ATOM_S2_DFP4_DPMS_STATE                                 0x04000000L
7927 #define ATOM_S2_DFP5_DPMS_STATE                                 0x08000000L
7928
7929 #define ATOM_S2_CRT1_DPMS_STATEb2       0x01
7930 #define ATOM_S2_LCD1_DPMS_STATEb2       0x02
7931 #define ATOM_S2_TV1_DPMS_STATEb2        0x04
7932 #define ATOM_S2_DFP1_DPMS_STATEb2       0x08
7933 #define ATOM_S2_CRT2_DPMS_STATEb2       0x10
7934 #define ATOM_S2_LCD2_DPMS_STATEb2       0x20
7935 #define ATOM_S2_TV2_DPMS_STATEb2        0x40
7936 #define ATOM_S2_DFP2_DPMS_STATEb2       0x80
7937 #define ATOM_S2_CV_DPMS_STATEb3         0x01
7938 #define ATOM_S2_DFP3_DPMS_STATEb3                               0x02
7939 #define ATOM_S2_DFP4_DPMS_STATEb3                               0x04
7940 #define ATOM_S2_DFP5_DPMS_STATEb3                               0x08
7941
7942 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3  0x20
7943 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
7944 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
7945
7946 /*********************************************************************************/
7947
7948 #pragma pack() // BIOS data must use byte aligment
7949
7950 //
7951 // AMD ACPI Table
7952 //
7953 #pragma pack(1)
7954
7955 typedef struct {
7956   ULONG Signature;
7957   ULONG TableLength;      //Length
7958   UCHAR Revision;
7959   UCHAR Checksum;
7960   UCHAR OemId[6];
7961   UCHAR OemTableId[8];    //UINT64  OemTableId;
7962   ULONG OemRevision;
7963   ULONG CreatorId;
7964   ULONG CreatorRevision;
7965 } AMD_ACPI_DESCRIPTION_HEADER;
7966 /*
7967 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
7968 typedef struct {
7969   UINT32  Signature;       //0x0
7970   UINT32  Length;          //0x4
7971   UINT8   Revision;        //0x8
7972   UINT8   Checksum;        //0x9
7973   UINT8   OemId[6];        //0xA
7974   UINT64  OemTableId;      //0x10
7975   UINT32  OemRevision;     //0x18
7976   UINT32  CreatorId;       //0x1C
7977   UINT32  CreatorRevision; //0x20
7978 }EFI_ACPI_DESCRIPTION_HEADER;
7979 */
7980 typedef struct {
7981   AMD_ACPI_DESCRIPTION_HEADER SHeader;
7982   UCHAR TableUUID[16];    //0x24
7983   ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
7984   ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
7985   ULONG Reserved[4];      //0x3C
7986 }UEFI_ACPI_VFCT;
7987
7988 typedef struct {
7989   ULONG  PCIBus;          //0x4C
7990   ULONG  PCIDevice;       //0x50
7991   ULONG  PCIFunction;     //0x54
7992   USHORT VendorID;        //0x58
7993   USHORT DeviceID;        //0x5A
7994   USHORT SSVID;           //0x5C
7995   USHORT SSID;            //0x5E
7996   ULONG  Revision;        //0x60
7997   ULONG  ImageLength;     //0x64
7998 }VFCT_IMAGE_HEADER;
7999
8000
8001 typedef struct {
8002   VFCT_IMAGE_HEADER     VbiosHeader;
8003   UCHAR VbiosContent[1];
8004 }GOP_VBIOS_CONTENT;
8005
8006 typedef struct {
8007   VFCT_IMAGE_HEADER     Lib1Header;
8008   UCHAR Lib1Content[1];
8009 }GOP_LIB1_CONTENT;
8010
8011 #pragma pack()
8012
8013
8014 #endif /* _ATOMBIOS_H */