2 * Copyright (c) 2003, 2004, 2005
3 * John Wehle <john@feith.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by John Wehle.
16 * 4. The name of the author may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
36 * Header file for the Conexant MPEG-2 Codec driver.
39 #include <sys/selinfo.h>
41 #include <bus/pci/pcidevs.h>
45 #define bswap32(X) ntohl(X)
47 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
50 * For simplicity several large buffers allocate during
51 * driver attachment which normally occurs early on
52 * (when large areas of memory are available) are used
53 * to move data to / from the card. It's not unusual
54 * for the memory allocation to fail due to fragmentation
55 * if the driver is loaded after the system has been
56 * running for a while. One solution is to allocate
57 * several PAGE_SIZE buffers instead, however it doesn't
58 * seem worth the trouble.
60 enum cxm_byte_order { cxm_unknown_byte_order,
61 cxm_device_mpeg_byte_order, cxm_device_yuv12_byte_order,
62 cxm_host_byte_order };
69 enum cxm_byte_order byte_order;
72 #define CXM_SG_BUFFERS 50
74 struct cxm_buffer_pool {
78 volatile unsigned int write;
79 struct cxm_buffer bufs[CXM_SG_BUFFERS];
83 * Audio format encoding
103 * 0 1 1 1 224k / 112k
104 * 1 0 0 0 256k / 128k
105 * 1 0 0 1 288k / 160k
106 * 1 0 1 0 320k / 192k
107 * 1 0 1 1 352k / 224k
108 * 1 1 0 0 384k / 256k
109 * 1 1 0 1 416k / 320k
110 * 1 1 1 0 448k / 384k
112 struct cxm_codec_audio_format {
113 unsigned int sample_rate;
117 struct cxm_codec_profile {
119 uint32_t stream_type;
123 uint32_t source_height;
148 unsigned int audio_sample_rate;
157 #define CXM_MBX_FW_CMD_MAILBOX 0
158 #define CXM_MBX_FW_CMD_MAILBOXES 6
160 #define CXM_MBX_FW_DMA_MAILBOX 9
162 #define CXM_MBX_MAX_PARAMETERS 16
164 /* Mailbox flags bit definitions */
165 #define CXM_MBX_FLAG_DRV_DONE 0x00000002
166 #define CXM_MBX_FLAG_FW_DONE 0x00000004
167 #define CXM_MBX_FLAG_IN_USE 0x00000001
174 uint32_t parameters[CXM_MBX_MAX_PARAMETERS];
175 } __attribute__ ((packed));
177 enum cxm_mailbox_name { cxm_unknown_mailbox,
178 cxm_dec_mailbox, cxm_enc_mailbox };
181 * Scatter / gather is supported with the restriction
182 * that the size of each piece must be a multiple of
183 * 256 and less than 64k.
185 #define CXM_SG_SEGMENT (0xff00 & ~(PAGE_SIZE - 1))
187 struct cxm_sg_entry {
191 } __attribute__ ((packed));
195 struct cxm_sg_entry *vaddr;
201 enum cxm_source { cxm_unknown_source, cxm_fm_source, cxm_tuner_source,
202 cxm_line_in_source_composite, cxm_line_in_source_svideo };
204 enum cxm_source_format { cxm_unknown_source_format,
205 cxm_bw_50hz_source_format,
206 cxm_bw_60hz_source_format,
207 cxm_ntsc_50hz_source_format,
208 cxm_ntsc_60hz_source_format,
209 cxm_pal_50hz_source_format,
210 cxm_pal_60hz_source_format,
211 cxm_secam_50hz_source_format };
213 enum cxm_type { cxm_unknown_type, cxm_iTVC15_type, cxm_iTVC16_type };
216 * Conexant iTVC15 / iTVC16 info structure, one per card installed.
221 struct resource *mem_res; /* Resource descriptor for registers */
222 bus_space_tag_t btag; /* Bus space access functions */
223 bus_space_handle_t bhandle; /* Bus space access functions */
225 struct resource *irq_res; /* Resource descriptor for interrupt */
226 void *ih_cookie; /* Newbus interrupt handler cookie */
230 bus_dma_tag_t parent_dmat;
232 struct cxm_buffer_pool enc_pool;
233 struct cxm_sg_list enc_sg;
235 struct selinfo enc_sel;
237 struct proc *enc_proc;
240 unsigned int dec_mbx;
241 unsigned int enc_mbx;
246 const struct cxm_tuner *tuner;
247 const struct cxm_tuner_channels *tuner_channels;
249 unsigned long tuner_freq;
253 const struct cxm_codec_profile *profile;
255 enum cxm_source source;
257 device_t dev; /* bus attachment */
258 cdev_t cxm_dev_t; /* control device */
269 * Conexant iTVC15 / iTVC16 I2C info structure, one per card installed.
271 struct cxm_iic_softc {
272 bus_space_tag_t btag; /* Bus space access functions */
273 bus_space_handle_t bhandle; /* Bus space access functions */
280 * List of IVARS available to the I2C device driver
282 #define CXM_IVAR_BHANDLE 0
283 #define CXM_IVAR_BTAG 1
284 #define CXM_IVAR_IICBUS 2
289 #define CXM_RID PCIR_MAPS
294 #define CSR_WRITE_4(sc, reg, val) \
295 bus_space_write_4((sc)->btag, (sc)->bhandle, (reg), (val))
296 #define CSR_WRITE_2(sc, reg, val) \
297 bus_space_write_2((sc)->btag, (sc)->bhandle, (reg), val))
298 #define CSR_WRITE_1(sc, reg, val) \
299 bus_space_write_1((sc)->btag, (sc)->bhandle, (reg), val))
300 #define CSR_READ_4(sc, reg) \
301 bus_space_read_4((sc)->btag, (sc)->bhandle, (reg))
302 #define CSR_READ_2(sc, reg) \
303 bus_space_read_2((sc)->btag, (sc)->bhandle, (reg))
304 #define CSR_READ_1(sc, reg) \
305 bus_space_read_1((sc)->btag, (sc)->bhandle, (reg))
308 * Decoder / encoder firmware
310 extern const char cxm_dec_fw[];
311 extern const char cxm_enc_fw[];
313 #define CXM_FW_SIZE (256 * 1024)
316 * Decoder / encoder memory offsets
318 #define CXM_MEM_DEC 0x01000000
319 #define CXM_MEM_ENC 0x00000000
321 #define CXM_MEM_DEC_SIZE 0x01000000
322 #define CXM_MEM_ENC_SIZE 0x01000000
327 #define CXM_REG_AO 0x2002d00
328 #define CXM_REG_APU 0x200a064
329 #define CXM_REG_DEC_SDRAM_PRECHARGE 0x20008fc
330 #define CXM_REG_DEC_SDRAM_REFRESH 0x20008f8
331 #define CXM_REG_DMA_STATUS 0x2000004
332 #define CXM_REG_ENC_SDRAM_PRECHARGE 0x20007fc
333 #define CXM_REG_ENC_SDRAM_REFRESH 0x20007f8
334 #define CXM_REG_HW_BLOCKS 0x2009054
335 #define CXM_REG_I2C_GETSCL 0x2007008
336 #define CXM_REG_I2C_GETSDA 0x200700c
337 #define CXM_REG_I2C_SETSCL 0x2007000
338 #define CXM_REG_I2C_SETSDA 0x2007004
339 #define CXM_REG_IRQ_MASK 0x2000048
340 #define CXM_REG_IRQ_STATUS 0x2000040
341 #define CXM_REG_SPU 0x2009050
342 #define CXM_REG_VDM 0x2002800
343 #define CXM_REG_VPU 0x2009058
348 #define CXM_CMD_AO_STOP 0x00000005
349 #define CXM_CMD_APU_PING 0x00000000
350 #define CXM_CMD_HW_BLOCKS_RST 0xffffffff
351 #define CXM_CMD_SDRAM_PRECHARGE_INIT 0x0000001a
352 #define CXM_CMD_SDRAM_REFRESH_INIT 0x80000640
353 #define CXM_CMD_SPU_STOP 0x00000001
354 #define CXM_CMD_VDM_STOP 0x00000000
355 #define CXM_CMD_VPU_STOP15 0xfffffffe
356 #define CXM_CMD_VPU_STOP16 0xffffffee
358 #define CXM_DMA_ERROR_LIST 0x00000008
359 #define CXM_DMA_ERROR_READ 0x00000002
360 #define CXM_DMA_ERROR_WRITE 0x00000004
361 #define CXM_DMA_SUCCESS 0x00000001
363 #define CXM_IRQ_DEC_DMA_DONE (1 << 20)
364 #define CXM_IRQ_DEC_DMA_REQUEST (1 << 22)
365 #define CXM_IRQ_DEC_VSYNC (1 << 10)
366 #define CXM_IRQ_ENC_DMA_DONE (1 << 27)
367 #define CXM_IRQ_ENC_DMA_REQUEST (1 << 31)
368 #define CXM_IRQ_ENC_EOS (1 << 30)
369 #define CXM_IRQ_ENC_EVENT (1 << 28)
371 #define CXM_IRQ_ENC (CXM_IRQ_ENC_DMA_REQUEST | CXM_IRQ_ENC_DMA_DONE \
372 | CXM_IRQ_ENC_EOS | CXM_IRQ_ENC_EVENT)
377 #define CXM_MASK_SPU_ENABLE 0xfffffffe
378 #define CXM_MASK_VPU_ENABLE15 0xfffffff6
379 #define CXM_MASK_VPU_ENABLE16 0xfffffffb
384 #define CXM_FW_CMD_ASSIGN_3_2_PULLDOWN 0x000000b1
385 #define CXM_FW_CMD_ASSIGN_ASPECT_RATIO 0x00000099
386 #define CXM_FW_CMD_ASSIGN_AUDIO_PROPERTIES 0x000000bd
387 #define CXM_FW_CMD_ASSIGN_BITRATES 0x00000095
388 #define CXM_FW_CMD_ASSIGN_CORING_LEVELS 0x0000009f
389 #define CXM_FW_CMD_ASSIGN_DMA_BLOCKLEN 0x000000c9
390 #define CXM_FW_CMD_ASSIGN_DNR_FILTER_MODE 0x0000009b
391 #define CXM_FW_CMD_ASSIGN_DNR_FILTER_PROPERTIES 0x0000009d
392 #define CXM_FW_CMD_ASSIGN_FRAME_DROP_RATE 0x000000d0
393 #define CXM_FW_CMD_ASSIGN_FRAME_RATE 0x0000008f
394 #define CXM_FW_CMD_ASSIGN_FRAME_SIZE 0x00000091
395 #define CXM_FW_CMD_ASSIGN_GOP_CLOSURE 0x000000c5
396 #define CXM_FW_CMD_ASSIGN_GOP_PROPERTIES 0x00000097
397 #define CXM_FW_CMD_ASSIGN_NUM_VSYNC_LINES 0x000000d6
398 #define CXM_FW_CMD_ASSIGN_OUTPUT_PORT 0x000000bb
399 #define CXM_FW_CMD_ASSIGN_PGM_INDEX_INFO 0x000000c7
400 #define CXM_FW_CMD_ASSIGN_PLACEHOLDER 0x000000d8
401 #define CXM_FW_CMD_ASSIGN_SPATIAL_FILTER_TYPE 0x000000a1
402 #define CXM_FW_CMD_ASSIGN_STREAM_TYPE 0x000000b9
403 #define CXM_FW_CMD_ASSIGN_VBI_LINE 0x000000b7
404 #define CXM_FW_CMD_ASSIGN_VBI_PROPERTIES 0x000000c8
405 #define CXM_FW_CMD_BEGIN_CAPTURE 0x00000081
406 #define CXM_FW_CMD_DEC_EVENT_NOTIFICATION 0x00000017
407 #define CXM_FW_CMD_DEC_GET_FW_VER 0x00000011
408 #define CXM_FW_CMD_DEC_HALT_FW 0x0000000e
409 #define CXM_FW_CMD_ENC_EVENT_NOTIFICATION 0x000000d5
410 #define CXM_FW_CMD_ENC_GET_FW_VER 0x000000c4
411 #define CXM_FW_CMD_ENC_HALT_FW 0x000000c3
412 #define CXM_FW_CMD_END_CAPTURE 0x00000082
413 #define CXM_FW_CMD_INITIALIZE_VIDEO_INPUT 0x000000cd
414 #define CXM_FW_CMD_MUTE_VIDEO_INPUT 0x000000d9
415 #define CXM_FW_CMD_PAUSE_ENCODER 0x000000d2
416 #define CXM_FW_CMD_SCHED_DMA_TO_HOST 0x000000cc
418 #define CXM_FW_STD_TIMEOUT 0x00010000
420 #define CXM_FW_CAPTURE_STREAM_TYPE_MPEG 0x00000000
421 #define CXM_FW_CAPTURE_STREAM_TYPE_RAW 0x00000001
422 #define CXM_FW_CAPTURE_STREAM_TYPE_RAW_PASSTHROUGH 0x00000002
423 #define CXM_FW_CAPTURE_STREAM_TYPE_VBI 0x00000003
425 #define CXM_FW_CAPTURE_STREAM_YUV 0x00000001
426 #define CXM_FW_CAPTURE_STREAM_PCM_AUDIO 0x00000002
427 #define CXM_FW_CAPTURE_STREAM_VBI 0x00000004
429 #define CXM_FW_STREAM_TYPE_DVD 0x0000000a
430 #define CXM_FW_STREAM_TYPE_MPEG1 0x00000002
431 #define CXM_FW_STREAM_TYPE_MPEG2_PROGRAM 0x00000000
432 #define CXM_FW_STREAM_TYPE_SVCD 0x0000000c
433 #define CXM_FW_STREAM_TYPE_VCD 0x0000000b
435 #define CXM_MACROBLOCK_HEIGHT 16
436 #define CXM_MACROBLOCK_WIDTH 16
437 #define CXM_MACROBLOCK_SIZE (CXM_MACROBLOCK_HEIGHT * CXM_MACROBLOCK_WIDTH)
442 #define CXM_I2C_CX2584x 0x88
443 #define CXM_I2C_EEPROM 0xa0
444 #define CXM_I2C_IR 0x30
445 #define CXM_I2C_MSP3400 0x80
446 #define CXM_I2C_SAA7115 0x42
447 #define CXM_I2C_TDA988x_W (0x43 << 1) /* Write address */
448 #define CXM_I2C_TDA988x_R ((0x43 << 1) | 0x01) /* Read address */
449 #define CXM_I2C_TUNER 0xc2
450 #define CXM_I2C_TUNER_IF 0x86
451 #define CXM_I2C_WM8775 0x36
453 #define CXM_I2C_TIMEOUT 1000
458 int cxm_eeprom_init(struct cxm_softc *sc);
459 int cxm_eeprom_tuner_type(struct cxm_softc *sc);
464 int cxm_ir_init(struct cxm_softc *sc);
465 int cxm_ir_key(struct cxm_softc *sc, char *buf, int len);
468 * msp34xxx Audio decoder
470 #define CXM_MSP3400C_DEM 0x10
471 #define CXM_MSP3400C_DFP 0x12
473 struct cxm_msp_setting {
479 struct cxm_msp_command {
480 unsigned int nsettings;
481 struct cxm_msp_setting settings[5];
484 int cxm_msp_init(struct cxm_softc *sc);
485 int cxm_msp_mute(struct cxm_softc *sc);
486 int cxm_msp_unmute(struct cxm_softc *sc);
487 int cxm_msp_is_muted(struct cxm_softc *sc);
488 int cxm_msp_select_source(struct cxm_softc *sc, enum cxm_source source);
489 enum cxm_source cxm_msp_selected_source(struct cxm_softc *sc);
490 int cxm_msp_autodetect_standard(struct cxm_softc *sc);
491 int cxm_msp_is_locked(struct cxm_softc *sc);
492 int cxm_msp_wait_for_lock(struct cxm_softc *sc);
497 struct cxm_wm8775_setting {
502 struct cxm_wm8775_command {
503 unsigned int nsettings;
504 struct cxm_wm8775_setting settings[13];
507 int cxm_wm8775_init(struct cxm_softc *sc);
510 * tda988x Demodulator
512 int cxm_tda988x_init(struct cxm_softc *sc);
513 int cxm_tda988x_diag(struct cxm_softc *sc);
518 struct cxm_cx2584x_setting {
523 struct cxm_cx2584x_command {
524 unsigned int nsettings;
525 struct cxm_cx2584x_setting settings[21];
528 int cxm_cx2584x_init(struct cxm_softc *sc);
529 int cxm_cx2584x_mute(struct cxm_softc *sc);
530 int cxm_cx2584x_unmute(struct cxm_softc *sc);
531 int cxm_cx2584x_select_source(struct cxm_softc *sc, enum cxm_source source);
532 int cxm_cx2584x_set_std(struct cxm_softc *sc);
537 #define CXM_TUNER_PHILIPS_FI1216_MK2 0
538 #define CXM_TUNER_PHILIPS_FM1216 1
539 #define CXM_TUNER_PHILIPS_FQ1216ME 2
540 #define CXM_TUNER_PHILIPS_FQ1216ME_MK3 3
541 #define CXM_TUNER_PHILIPS_FM1216ME_MK3 4
542 #define CXM_TUNER_PHILIPS_FI1236_MK2 5
543 #define CXM_TUNER_PHILIPS_FM1236 6
544 #define CXM_TUNER_PHILIPS_FI1246_MK2 7
545 #define CXM_TUNER_PHILIPS_FM1246 8
546 #define CXM_TUNER_TEMIC_4006_FH5 9
547 #define CXM_TUNER_TEMIC_4009_FR5 10
548 #define CXM_TUNER_TEMIC_4036_FY5 11
549 #define CXM_TUNER_TEMIC_4039_FR5 12
550 #define CXM_TUNER_TEMIC_4066_FY5 13
551 #define CXM_TUNER_LG_TPI8PSB11D 14
552 #define CXM_TUNER_LG_TPI8PSB01N 15
553 #define CXM_TUNER_LG_TAPC_H701F 16
554 #define CXM_TUNER_LG_TAPC_H001F 17
555 #define CXM_TUNER_LG_TAPE_H001F 18
556 #define CXM_TUNER_MICROTUNE_4049_FM5 19
557 #define CXM_TUNER_TCL_2002N_6A 20
558 #define CXM_TUNER_TYPES 21
560 #define CXM_TUNER_AFC_MASK 0x07
562 #define CXM_TUNER_AFC_FREQ_MINUS_125 0x00
563 #define CXM_TUNER_AFC_FREQ_MINUS_62 0x01
564 #define CXM_TUNER_AFC_FREQ_CENTERED 0x02
565 #define CXM_TUNER_AFC_FREQ_PLUS_62 0x03
566 #define CXM_TUNER_AFC_FREQ_PLUS_125 0x04
568 #define CXM_TUNER_PHASE_LOCKED 0x40
570 #define CXM_TUNER_FM_SYSTEM 0x01
571 #define CXM_TUNER_TV_SYSTEM_BG 0x02
572 #define CXM_TUNER_TV_SYSTEM_DK 0x04
573 #define CXM_TUNER_TV_SYSTEM_I 0x08
574 #define CXM_TUNER_TV_SYSTEM_MN 0x10
575 #define CXM_TUNER_TV_SYSTEM_L 0x20
576 #define CXM_TUNER_TV_SYSTEM_L_PRIME 0x40
578 struct cxm_tuner_band_code {
580 unsigned char codes[2];
583 struct cxm_tuner_channel_assignment {
584 unsigned int channel;
589 struct cxm_tuner_channels {
591 unsigned int chnlset;
593 unsigned int min_channel;
594 unsigned int max_channel;
595 unsigned long if_freq;
596 struct cxm_tuner_channel_assignment assignments[17];
599 struct cxm_tuner_system_code {
601 unsigned char codes[4];
604 enum cxm_tuner_system_code_style { cxm_unknown_system_code_style,
605 cxm_none_system_code_style,
606 cxm_port_system_code_style,
607 cxm_if_system_code_style,
608 cxm_if_system_with_aux_code_style };
610 struct cxm_tuner_system {
611 unsigned int supported;
612 enum cxm_tuner_system_code_style code_style;
613 struct cxm_tuner_system_code codes[6];
618 struct cxm_tuner_system systems;
619 unsigned long min_freq;
620 unsigned long max_freq;
621 struct cxm_tuner_band_code band_codes[3];
622 unsigned long fm_min_freq;
623 unsigned long fm_max_freq;
624 struct cxm_tuner_band_code fm_band_code;
625 const struct cxm_tuner_channels *default_channels;
628 enum cxm_tuner_freq_type { cxm_tuner_unknown_freq_type, cxm_tuner_fm_freq_type,
629 cxm_tuner_tv_freq_type };
631 extern const struct cxm_tuner cxm_tuners[];
633 int cxm_tuner_init(struct cxm_softc *sc);
634 int cxm_tuner_select_channel_set(struct cxm_softc *sc,
635 unsigned int channel_set);
636 unsigned int cxm_tuner_selected_channel_set(struct cxm_softc *sc);
637 int cxm_tuner_select_frequency(struct cxm_softc *sc,
638 enum cxm_tuner_freq_type type,
640 int cxm_tuner_select_channel(struct cxm_softc *sc, unsigned int channel);
641 int cxm_tuner_apply_afc(struct cxm_softc *sc);
642 int cxm_tuner_is_locked(struct cxm_softc *sc);
643 int cxm_tuner_wait_for_lock(struct cxm_softc *sc);
644 int cxm_tuner_status(struct cxm_softc *sc);
649 struct cxm_saa7115_setting {
651 unsigned int nvalues;
655 struct cxm_saa7115_command {
656 unsigned int nsettings;
657 struct cxm_saa7115_setting settings[20];
660 struct cxm_saa7115_audio_clock {
661 unsigned int sample_rate;
663 const struct cxm_saa7115_command *clock;
666 struct cxm_saa7115_scaling {
670 const struct cxm_saa7115_command *scaling;
673 int cxm_saa7115_init(struct cxm_softc *sc);
674 int cxm_saa7115_mute(struct cxm_softc *sc);
675 int cxm_saa7115_unmute(struct cxm_softc *sc);
676 int cxm_saa7115_select_source(struct cxm_softc *sc, enum cxm_source source);
677 int cxm_saa7115_configure(struct cxm_softc *sc,
678 unsigned int width, unsigned int height,
679 unsigned int fps, unsigned int audio_sample_rate);
680 enum cxm_source_format cxm_saa7115_detected_format(struct cxm_softc *sc);
681 int cxm_saa7115_detected_fps(struct cxm_softc *sc);
682 int cxm_saa7115_get_brightness(struct cxm_softc *sc);
683 int cxm_saa7115_set_brightness(struct cxm_softc *sc,
684 unsigned char brightness);
685 int cxm_saa7115_get_chroma_saturation(struct cxm_softc *sc);
686 int cxm_saa7115_set_chroma_saturation(struct cxm_softc *sc,
687 unsigned char chroma_saturation);
688 int cxm_saa7115_get_contrast(struct cxm_softc *sc);
689 int cxm_saa7115_set_contrast(struct cxm_softc *sc, unsigned char contrast);
690 int cxm_saa7115_get_hue(struct cxm_softc *sc);
691 int cxm_saa7115_set_hue(struct cxm_softc *sc, unsigned char hue);
692 int cxm_saa7115_is_locked(struct cxm_softc *sc);
693 int cxm_saa7115_wait_for_lock(struct cxm_softc *sc);