2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/mpapic.h>
58 #include <machine/psl.h>
59 #include <machine/segments.h>
60 #include <machine/tss.h>
61 #include <machine/specialreg.h>
62 #include <machine/globaldata.h>
63 #include <machine/pmap_inval.h>
65 #include <machine/md_var.h> /* setidt() */
66 #include <machine_base/icu/icu.h> /* IPIs */
67 #include <machine_base/apic/ioapic_abi.h>
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 #define MPTABLE_POS_USE_DEFAULT(mpt) \
172 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
176 int mb_type; /* MPTABLE_BUS_ */
177 TAILQ_ENTRY(mptable_bus) mb_link;
180 #define MPTABLE_BUS_ISA 0
181 #define MPTABLE_BUS_PCI 1
183 struct mptable_bus_info {
184 TAILQ_HEAD(, mptable_bus) mbi_list;
187 struct mptable_pci_int {
194 TAILQ_ENTRY(mptable_pci_int) mpci_link;
197 struct mptable_ioapic {
203 TAILQ_ENTRY(mptable_ioapic) mio_link;
206 typedef int (*mptable_iter_func)(void *, const void *, int);
209 * this code MUST be enabled here and in mpboot.s.
210 * it follows the very early stages of AP boot by placing values in CMOS ram.
211 * it NORMALLY will never be needed and thus the primitive method for enabling.
214 #if defined(CHECK_POINTS)
215 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
216 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
218 #define CHECK_INIT(D); \
219 CHECK_WRITE(0x34, (D)); \
220 CHECK_WRITE(0x35, (D)); \
221 CHECK_WRITE(0x36, (D)); \
222 CHECK_WRITE(0x37, (D)); \
223 CHECK_WRITE(0x38, (D)); \
224 CHECK_WRITE(0x39, (D));
226 #define CHECK_PRINT(S); \
227 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
236 #else /* CHECK_POINTS */
238 #define CHECK_INIT(D)
239 #define CHECK_PRINT(S)
241 #endif /* CHECK_POINTS */
244 * Values to send to the POST hardware.
246 #define MP_BOOTADDRESS_POST 0x10
247 #define MP_PROBE_POST 0x11
248 #define MPTABLE_PASS1_POST 0x12
250 #define MP_START_POST 0x13
251 #define MP_ENABLE_POST 0x14
252 #define MPTABLE_PASS2_POST 0x15
254 #define START_ALL_APS_POST 0x16
255 #define INSTALL_AP_TRAMP_POST 0x17
256 #define START_AP_POST 0x18
258 #define MP_ANNOUNCE_POST 0x19
260 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
261 int current_postcode;
263 /** XXX FIXME: what system files declare these??? */
264 extern struct region_descriptor r_gdt, r_idt;
266 int mp_naps; /* # of Applications processors */
269 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
271 extern int64_t tsc_offsets[];
273 extern u_long ebda_addr;
275 #ifdef SMP /* APIC-IO */
276 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
280 * APIC ID logical/physical mapping structures.
281 * We oversize these to simplify boot-time config.
283 int cpu_num_to_apic_id[NAPICID];
284 int apic_id_to_logical[NAPICID];
286 /* AP uses this during bootstrap. Do not staticize. */
290 struct pcb stoppcbs[MAXCPU];
292 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
294 static basetable_entry basetable_entry_types[] =
296 {0, 20, "Processor"},
304 * Local data and functions.
307 static u_int boot_address;
308 static u_int base_memory;
309 static int mp_finish;
310 static int mp_finish_lapic;
312 static void mp_enable(u_int boot_addr);
314 static int mptable_iterate_entries(const mpcth_t,
315 mptable_iter_func, void *);
316 static int mptable_search(void);
317 static long mptable_search_sig(u_int32_t target, int count);
318 static int mptable_hyperthread_fixup(cpumask_t, int);
319 static int mptable_map(struct mptable_pos *);
320 static void mptable_unmap(struct mptable_pos *);
321 static void mptable_bus_info_alloc(const mpcth_t,
322 struct mptable_bus_info *);
323 static void mptable_bus_info_free(struct mptable_bus_info *);
325 static int mptable_lapic_probe(struct lapic_enumerator *);
326 static void mptable_lapic_enumerate(struct lapic_enumerator *);
327 static void mptable_lapic_default(void);
329 static int mptable_ioapic_probe(struct ioapic_enumerator *);
330 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
332 static int start_all_aps(u_int boot_addr);
334 static void install_ap_tramp(u_int boot_addr);
336 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
337 static int smitest(void);
339 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
340 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
341 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
342 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
343 static u_int bootMP_size;
347 static vm_paddr_t mptable_fps_phyaddr;
348 static int mptable_use_default;
349 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
350 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
351 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
352 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
355 * Calculate usable address in base memory for AP trampoline code.
358 mp_bootaddress(u_int basemem)
360 POSTCODE(MP_BOOTADDRESS_POST);
362 base_memory = basemem;
364 bootMP_size = mptramp_end - mptramp_start;
365 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
366 if (((basemem * 1024) - boot_address) < bootMP_size)
367 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
368 /* 3 levels of page table pages */
369 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
371 return mptramp_pagetables;
378 struct mptable_pos mpt;
381 KKASSERT(mptable_fps_phyaddr == 0);
383 mptable_fps_phyaddr = mptable_search();
384 if (mptable_fps_phyaddr == 0)
387 error = mptable_map(&mpt);
389 mptable_fps_phyaddr = 0;
393 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
394 kprintf("MPTABLE: use default configuration\n");
395 mptable_use_default = 1;
397 if (mpt.mp_fps->mpfb2 & 0x80)
402 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
405 * Look for an Intel MP spec table (ie, SMP capable hardware).
413 POSTCODE(MP_PROBE_POST);
415 /* see if EBDA exists */
416 if (ebda_addr != 0) {
417 /* search first 1K of EBDA */
418 target = (u_int32_t)ebda_addr;
419 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
422 /* last 1K of base memory, effective 'top of base' passed in */
423 target = (u_int32_t)(base_memory - 0x400);
424 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
428 /* search the BIOS */
429 target = (u_int32_t)BIOS_BASE;
430 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
433 /* search the extended BIOS */
434 target = (u_int32_t)BIOS_BASE2;
435 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
443 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
445 int count, total_size;
446 const void *position;
448 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
449 total_size = cth->base_table_length - sizeof(struct MPCTH);
450 position = (const uint8_t *)cth + sizeof(struct MPCTH);
451 count = cth->entry_count;
456 KKASSERT(total_size >= 0);
457 if (total_size == 0) {
458 kprintf("invalid base MP table, "
459 "entry count and length mismatch\n");
463 type = *(const uint8_t *)position;
465 case 0: /* processor_entry */
466 case 1: /* bus_entry */
467 case 2: /* io_apic_entry */
468 case 3: /* int_entry */
469 case 4: /* int_entry */
472 kprintf("unknown base MP table entry type %d\n", type);
476 if (total_size < basetable_entry_types[type].length) {
477 kprintf("invalid base MP table length, "
478 "does not contain all entries\n");
481 total_size -= basetable_entry_types[type].length;
483 error = func(arg, position, type);
487 position = (const uint8_t *)position +
488 basetable_entry_types[type].length;
495 * Startup the SMP processors.
500 POSTCODE(MP_START_POST);
501 mp_enable(boot_address);
506 * Print various information about the SMP system hardware and setup.
513 POSTCODE(MP_ANNOUNCE_POST);
515 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
516 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
517 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
518 for (x = 1; x <= mp_naps; ++x) {
519 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
520 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
524 kprintf(" Warning: APIC I/O disabled\n");
528 * AP cpu's call this to sync up protected mode.
530 * WARNING! %gs is not set up on entry. This routine sets up %gs.
536 int x, myid = bootAP;
538 struct mdglobaldata *md;
539 struct privatespace *ps;
541 ps = &CPU_prvspace[myid];
543 gdt_segs[GPROC0_SEL].ssd_base =
544 (long) &ps->mdglobaldata.gd_common_tss;
545 ps->mdglobaldata.mi.gd_prvspace = ps;
547 /* We fill the 32-bit segment descriptors */
548 for (x = 0; x < NGDT; x++) {
549 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
550 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
552 /* And now a 64-bit one */
553 ssdtosyssd(&gdt_segs[GPROC0_SEL],
554 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
556 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
557 r_gdt.rd_base = (long) &gdt[myid * NGDT];
558 lgdt(&r_gdt); /* does magic intra-segment return */
560 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
561 wrmsr(MSR_FSBASE, 0); /* User value */
562 wrmsr(MSR_GSBASE, (u_int64_t)ps);
563 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
569 mdcpu->gd_currentldt = _default_ldt;
572 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
573 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
575 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
577 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
579 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
581 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
582 md->gd_common_tssd = *md->gd_tss_gdt;
584 /* double fault stack */
585 md->gd_common_tss.tss_ist1 =
586 (long)&md->mi.gd_prvspace->idlestack[
587 sizeof(md->mi.gd_prvspace->idlestack)];
592 * Set to a known state:
593 * Set by mpboot.s: CR0_PG, CR0_PE
594 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
597 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
600 /* Set up the fast syscall stuff */
601 msr = rdmsr(MSR_EFER) | EFER_SCE;
602 wrmsr(MSR_EFER, msr);
603 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
604 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
605 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
606 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
607 wrmsr(MSR_STAR, msr);
608 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
610 pmap_set_opt(); /* PSE/4MB pages, etc */
612 /* Initialize the PAT MSR. */
616 /* set up CPU registers and state */
619 /* set up SSE/NX registers */
622 /* set up FPU state on the AP */
623 npxinit(__INITIAL_NPXCW__);
625 /* disable the APIC, just to be SURE */
626 lapic->svr &= ~APIC_SVR_ENABLE;
628 /* data returned to BSP */
629 cpu_apic_versions[0] = lapic->version;
632 /*******************************************************************
633 * local functions and data
637 * start the SMP system
640 mp_enable(u_int boot_addr)
642 POSTCODE(MP_ENABLE_POST);
646 /* Initialize BSP's local APIC */
649 /* start each Application Processor */
650 start_all_aps(boot_addr);
656 MachIntrABI.finalize();
661 * look for the MP spec signature
664 /* string defined by the Intel MP Spec as identifying the MP table */
665 #define MP_SIG 0x5f504d5f /* _MP_ */
666 #define NEXT(X) ((X) += 4)
668 mptable_search_sig(u_int32_t target, int count)
674 KKASSERT(target != 0);
676 map_size = count * sizeof(u_int32_t);
677 addr = pmap_mapdev((vm_paddr_t)target, map_size);
680 for (x = 0; x < count; NEXT(x)) {
681 if (addr[x] == MP_SIG) {
682 /* make array index a byte index */
683 ret = target + (x * sizeof(u_int32_t));
688 pmap_unmapdev((vm_offset_t)addr, map_size);
693 typedef struct BUSDATA {
695 enum busTypes bus_type;
698 typedef struct INTDATA {
708 typedef struct BUSTYPENAME {
713 static int processor_entry (const struct PROCENTRY *entry, int cpu);
716 * Check if we should perform a hyperthreading "fix-up" to
717 * enumerate any logical CPU's that aren't already listed
720 * XXX: We assume that all of the physical CPUs in the
721 * system have the same number of logical CPUs.
723 * XXX: We assume that APIC ID's are allocated such that
724 * the APIC ID's for a physical processor are aligned
725 * with the number of logical CPU's in the processor.
728 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
730 int i, id, lcpus_max, logical_cpus;
732 if ((cpu_feature & CPUID_HTT) == 0)
735 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
739 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
741 * INSTRUCTION SET REFERENCE, A-M (#253666)
742 * Page 3-181, Table 3-20
743 * "The nearest power-of-2 integer that is not smaller
744 * than EBX[23:16] is the number of unique initial APIC
745 * IDs reserved for addressing different logical
746 * processors in a physical package."
749 if ((1 << i) >= lcpus_max) {
756 KKASSERT(cpu_count != 0);
757 if (cpu_count == lcpus_max) {
758 /* We have nothing to fix */
760 } else if (cpu_count == 1) {
761 /* XXX this may be incorrect */
762 logical_cpus = lcpus_max;
767 * Calculate the distances between two nearest
768 * APIC IDs. If all such distances are same,
769 * then it is the number of missing cpus that
770 * we are going to fill later.
772 dist = cur = prev = -1;
773 for (id = 0; id < MAXCPU; ++id) {
774 if ((id_mask & CPUMASK(id)) == 0)
779 int new_dist = cur - prev;
785 * Make sure that all distances
786 * between two nearest APIC IDs
789 if (dist != new_dist)
797 /* Must be power of 2 */
798 if (dist & (dist - 1))
801 /* Can't exceed CPU package capacity */
802 if (dist > lcpus_max)
803 logical_cpus = lcpus_max;
809 * For each APIC ID of a CPU that is set in the mask,
810 * scan the other candidate APIC ID's for this
811 * physical processor. If any of those ID's are
812 * already in the table, then kill the fixup.
814 for (id = 0; id < MAXCPU; id++) {
815 if ((id_mask & CPUMASK(id)) == 0)
817 /* First, make sure we are on a logical_cpus boundary. */
818 if (id % logical_cpus != 0)
820 for (i = id + 1; i < id + logical_cpus; i++)
821 if ((id_mask & CPUMASK(i)) != 0)
828 mptable_map(struct mptable_pos *mpt)
832 vm_size_t cth_mapsz = 0;
834 KKASSERT(mptable_fps_phyaddr != 0);
836 bzero(mpt, sizeof(*mpt));
838 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
841 * Map configuration table header to get
842 * the base table size
844 cth = pmap_mapdev(fps->pap, sizeof(*cth));
845 cth_mapsz = cth->base_table_length;
846 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
848 if (cth_mapsz < sizeof(*cth)) {
849 kprintf("invalid base MP table length %d\n",
851 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
858 cth = pmap_mapdev(fps->pap, cth_mapsz);
863 mpt->mp_cth_mapsz = cth_mapsz;
869 mptable_unmap(struct mptable_pos *mpt)
871 if (mpt->mp_cth != NULL) {
872 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
874 mpt->mp_cth_mapsz = 0;
876 if (mpt->mp_fps != NULL) {
877 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
883 mp_set_cpuids(int cpu_id, int apic_id)
885 CPU_TO_ID(cpu_id) = apic_id;
886 ID_TO_CPU(apic_id) = cpu_id;
888 if (apic_id > lapic_id_max)
889 lapic_id_max = apic_id;
893 processor_entry(const struct PROCENTRY *entry, int cpu)
897 /* check for usability */
898 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
901 /* check for BSP flag */
902 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
903 mp_set_cpuids(0, entry->apic_id);
904 return 0; /* its already been counted */
907 /* add another AP to list, if less than max number of CPUs */
908 else if (cpu < MAXCPU) {
909 mp_set_cpuids(cpu, entry->apic_id);
917 * Map a physical memory address representing I/O into KVA. The I/O
918 * block is assumed not to cross a page boundary.
921 ioapic_map(vm_paddr_t pa)
923 KKASSERT(pa < 0x100000000LL);
925 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
929 * start each AP in our list
932 start_all_aps(u_int boot_addr)
934 vm_offset_t va = boot_address + KERNBASE;
935 u_int64_t *pt4, *pt3, *pt2;
942 u_long mpbioswarmvec;
943 struct mdglobaldata *gd;
944 struct privatespace *ps;
946 POSTCODE(START_ALL_APS_POST);
948 /* install the AP 1st level boot code */
949 pmap_kenter(va, boot_address);
950 cpu_invlpg((void *)va); /* JG XXX */
951 bcopy(mptramp_start, (void *)va, bootMP_size);
953 /* Locate the page tables, they'll be below the trampoline */
954 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
955 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
956 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
958 /* Create the initial 1GB replicated page tables */
959 for (i = 0; i < 512; i++) {
960 /* Each slot of the level 4 pages points to the same level 3 page */
961 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
962 pt4[i] |= PG_V | PG_RW | PG_U;
964 /* Each slot of the level 3 pages points to the same level 2 page */
965 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
966 pt3[i] |= PG_V | PG_RW | PG_U;
968 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
969 pt2[i] = i * (2 * 1024 * 1024);
970 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
973 /* save the current value of the warm-start vector */
974 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
975 outb(CMOS_REG, BIOS_RESET);
976 mpbiosreason = inb(CMOS_DATA);
978 /* setup a vector to our boot code */
979 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
980 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
981 outb(CMOS_REG, BIOS_RESET);
982 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
985 * If we have a TSC we can figure out the SMI interrupt rate.
986 * The SMI does not necessarily use a constant rate. Spend
987 * up to 250ms trying to figure it out.
990 if (cpu_feature & CPUID_TSC) {
991 set_apic_timer(275000);
992 smilast = read_apic_timer();
993 for (x = 0; x < 20 && read_apic_timer(); ++x) {
994 smicount = smitest();
995 if (smibest == 0 || smilast - smicount < smibest)
996 smibest = smilast - smicount;
999 if (smibest > 250000)
1002 smibest = smibest * (int64_t)1000000 /
1003 get_apic_timer_frequency();
1007 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
1008 1000000 / smibest, smibest);
1011 for (x = 1; x <= mp_naps; ++x) {
1013 /* This is a bit verbose, it will go away soon. */
1015 /* first page of AP's private space */
1016 pg = x * x86_64_btop(sizeof(struct privatespace));
1018 /* allocate new private data page(s) */
1019 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
1020 MDGLOBALDATA_BASEALLOC_SIZE);
1022 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
1023 bzero(gd, sizeof(*gd));
1024 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
1026 /* prime data page for it to use */
1027 mi_gdinit(&gd->mi, x);
1029 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
1030 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
1032 /* setup a vector to our boot code */
1033 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
1034 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
1035 outb(CMOS_REG, BIOS_RESET);
1036 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
1039 * Setup the AP boot stack
1041 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
1044 /* attempt to start the Application Processor */
1045 CHECK_INIT(99); /* setup checkpoints */
1046 if (!start_ap(gd, boot_addr, smibest)) {
1047 kprintf("\nAP #%d (PHY# %d) failed!\n",
1049 CHECK_PRINT("trace"); /* show checkpoints */
1050 /* better panic as the AP may be running loose */
1051 kprintf("panic y/n? [y] ");
1052 if (cngetc() != 'n')
1055 CHECK_PRINT("trace"); /* show checkpoints */
1057 /* record its version info */
1058 cpu_apic_versions[x] = cpu_apic_versions[0];
1061 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
1064 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
1065 for (shift = 0; (1 << shift) <= ncpus; ++shift)
1068 ncpus2_shift = shift;
1069 ncpus2 = 1 << shift;
1070 ncpus2_mask = ncpus2 - 1;
1072 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
1073 if ((1 << shift) < ncpus)
1075 ncpus_fit = 1 << shift;
1076 ncpus_fit_mask = ncpus_fit - 1;
1078 /* build our map of 'other' CPUs */
1079 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1080 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1081 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1083 /* fill in our (BSP) APIC version */
1084 cpu_apic_versions[0] = lapic->version;
1086 /* restore the warmstart vector */
1087 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
1088 outb(CMOS_REG, BIOS_RESET);
1089 outb(CMOS_DATA, mpbiosreason);
1092 * NOTE! The idlestack for the BSP was setup by locore. Finish
1093 * up, clean out the P==V mapping we did earlier.
1098 * Wait all APs to finish initializing LAPIC
1100 mp_finish_lapic = 1;
1102 kprintf("SMP: Waiting APs LAPIC initialization\n");
1103 if (cpu_feature & CPUID_TSC)
1104 tsc0_offset = rdtsc();
1107 while (smp_lapic_mask != smp_startup_mask) {
1109 if (cpu_feature & CPUID_TSC)
1110 tsc0_offset = rdtsc();
1112 while (try_mplock() == 0)
1115 /* number of APs actually started */
1121 * load the 1st level AP boot code into base memory.
1124 /* targets for relocation */
1125 extern void bigJump(void);
1126 extern void bootCodeSeg(void);
1127 extern void bootDataSeg(void);
1128 extern void MPentry(void);
1129 extern u_int MP_GDT;
1130 extern u_int mp_gdtbase;
1135 install_ap_tramp(u_int boot_addr)
1138 int size = *(int *) ((u_long) & bootMP_size);
1139 u_char *src = (u_char *) ((u_long) bootMP);
1140 u_char *dst = (u_char *) boot_addr + KERNBASE;
1141 u_int boot_base = (u_int) bootMP;
1146 POSTCODE(INSTALL_AP_TRAMP_POST);
1148 for (x = 0; x < size; ++x)
1152 * modify addresses in code we just moved to basemem. unfortunately we
1153 * need fairly detailed info about mpboot.s for this to work. changes
1154 * to mpboot.s might require changes here.
1157 /* boot code is located in KERNEL space */
1158 dst = (u_char *) boot_addr + KERNBASE;
1160 /* modify the lgdt arg */
1161 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
1162 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
1164 /* modify the ljmp target for MPentry() */
1165 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
1166 *dst32 = ((u_int) MPentry - KERNBASE);
1168 /* modify the target for boot code segment */
1169 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
1170 dst8 = (u_int8_t *) (dst16 + 1);
1171 *dst16 = (u_int) boot_addr & 0xffff;
1172 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1174 /* modify the target for boot data segment */
1175 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
1176 dst8 = (u_int8_t *) (dst16 + 1);
1177 *dst16 = (u_int) boot_addr & 0xffff;
1178 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
1184 * This function starts the AP (application processor) identified
1185 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
1186 * to accomplish this. This is necessary because of the nuances
1187 * of the different hardware we might encounter. It ain't pretty,
1188 * but it seems to work.
1190 * NOTE: eventually an AP gets to ap_init(), which is called just
1191 * before the AP goes into the LWKT scheduler's idle loop.
1194 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
1198 u_long icr_lo, icr_hi;
1200 POSTCODE(START_AP_POST);
1202 /* get the PHYSICAL APIC ID# */
1203 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
1205 /* calculate the vector */
1206 vector = (boot_addr >> 12) & 0xff;
1208 /* We don't want anything interfering */
1211 /* Make sure the target cpu sees everything */
1215 * Try to detect when a SMI has occurred, wait up to 200ms.
1217 * If a SMI occurs during an AP reset but before we issue
1218 * the STARTUP command, the AP may brick. To work around
1219 * this problem we hold off doing the AP startup until
1220 * after we have detected the SMI. Hopefully another SMI
1221 * will not occur before we finish the AP startup.
1223 * Retries don't seem to help. SMIs have a window of opportunity
1224 * and if USB->legacy keyboard emulation is enabled in the BIOS
1225 * the interrupt rate can be quite high.
1227 * NOTE: Don't worry about the L1 cache load, it might bloat
1228 * ldelta a little but ndelta will be so huge when the SMI
1229 * occurs the detection logic will still work fine.
1232 set_apic_timer(200000);
1237 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
1238 * and running the target CPU. OR this INIT IPI might be latched (P5
1239 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
1242 * see apic/apicreg.h for icr bit definitions.
1244 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
1248 * Setup the address for the target AP. We can setup
1249 * icr_hi once and then just trigger operations with
1252 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
1253 icr_hi |= (physical_cpu << 24);
1254 icr_lo = lapic->icr_lo & 0xfff00000;
1255 lapic->icr_hi = icr_hi;
1258 * Do an INIT IPI: assert RESET
1260 * Use edge triggered mode to assert INIT
1262 lapic->icr_lo = icr_lo | 0x00004500;
1263 while (lapic->icr_lo & APIC_DELSTAT_MASK)
1267 * The spec calls for a 10ms delay but we may have to use a
1268 * MUCH lower delay to avoid bricking an AP due to a fast SMI
1269 * interrupt. We have other loops here too and dividing by 2
1270 * doesn't seem to be enough even after subtracting 350us,
1271 * so we divide by 4.
1273 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
1274 * interrupt was detected we use the full 10ms.
1278 else if (smibest < 150 * 4 + 350)
1280 else if ((smibest - 350) / 4 < 10000)
1281 u_sleep((smibest - 350) / 4);
1286 * Do an INIT IPI: deassert RESET
1288 * Use level triggered mode to deassert. It is unclear
1289 * why we need to do this.
1291 lapic->icr_lo = icr_lo | 0x00008500;
1292 while (lapic->icr_lo & APIC_DELSTAT_MASK)
1294 u_sleep(150); /* wait 150us */
1297 * Next we do a STARTUP IPI: the previous INIT IPI might still be
1298 * latched, (P5 bug) this 1st STARTUP would then terminate
1299 * immediately, and the previously started INIT IPI would continue. OR
1300 * the previous INIT IPI has already run. and this STARTUP IPI will
1301 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
1304 lapic->icr_lo = icr_lo | 0x00000600 | vector;
1305 while (lapic->icr_lo & APIC_DELSTAT_MASK)
1307 u_sleep(200); /* wait ~200uS */
1310 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
1311 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
1312 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
1313 * recognized after hardware RESET or INIT IPI.
1315 lapic->icr_lo = icr_lo | 0x00000600 | vector;
1316 while (lapic->icr_lo & APIC_DELSTAT_MASK)
1319 /* Resume normal operation */
1322 /* wait for it to start, see ap_init() */
1323 set_apic_timer(5000000);/* == 5 seconds */
1324 while (read_apic_timer()) {
1325 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
1326 return 1; /* return SUCCESS */
1329 return 0; /* return FAILURE */
1344 while (read_apic_timer()) {
1346 for (count = 0; count < 100; ++count)
1347 ntsc = rdtsc(); /* force loop to occur */
1349 ndelta = ntsc - ltsc;
1350 if (ldelta > ndelta)
1352 if (ndelta > ldelta * 2)
1355 ldelta = ntsc - ltsc;
1358 return(read_apic_timer());
1362 * Synchronously flush the TLB on all other CPU's. The current cpu's
1363 * TLB is not flushed. If the caller wishes to flush the current cpu's
1364 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
1366 * NOTE: If for some reason we were unable to start all cpus we cannot
1367 * safely use broadcast IPIs.
1370 static cpumask_t smp_invltlb_req;
1372 #define SMP_INVLTLB_DEBUG
1378 struct mdglobaldata *md = mdcpu;
1379 #ifdef SMP_INVLTLB_DEBUG
1384 crit_enter_gd(&md->mi);
1385 md->gd_invltlb_ret = 0;
1386 ++md->mi.gd_cnt.v_smpinvltlb;
1387 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1388 #ifdef SMP_INVLTLB_DEBUG
1391 if (smp_startup_mask == smp_active_mask) {
1392 all_but_self_ipi(XINVLTLB_OFFSET);
1394 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
1395 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
1398 #ifdef SMP_INVLTLB_DEBUG
1400 kprintf("smp_invltlb: ipi sent\n");
1402 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
1403 (smp_active_mask & ~md->mi.gd_cpumask)) {
1406 #ifdef SMP_INVLTLB_DEBUG
1408 if (++count == 400000000) {
1409 print_backtrace(-1);
1410 kprintf("smp_invltlb: endless loop %08lx %08lx, "
1411 "rflags %016jx retry",
1412 (long)md->gd_invltlb_ret,
1413 (long)smp_invltlb_req,
1414 (intmax_t)read_rflags());
1415 __asm __volatile ("sti");
1418 lwkt_process_ipiq();
1420 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
1421 ~md->mi.gd_cpumask &
1425 kprintf("bcpu %d\n", bcpu);
1426 xgd = globaldata_find(bcpu);
1427 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
1430 Debugger("giving up");
1436 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
1437 crit_exit_gd(&md->mi);
1444 * Called from Xinvltlb assembly with interrupts disabled. We didn't
1445 * bother to bump the critical section count or nested interrupt count
1446 * so only do very low level operations here.
1449 smp_invltlb_intr(void)
1451 struct mdglobaldata *md = mdcpu;
1452 struct mdglobaldata *omd;
1457 mask = smp_invltlb_req;
1460 cpu = BSFCPUMASK(mask);
1461 mask &= ~CPUMASK(cpu);
1462 omd = (struct mdglobaldata *)globaldata_find(cpu);
1463 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
1470 * When called the executing CPU will send an IPI to all other CPUs
1471 * requesting that they halt execution.
1473 * Usually (but not necessarily) called with 'other_cpus' as its arg.
1475 * - Signals all CPUs in map to stop.
1476 * - Waits for each to stop.
1483 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
1484 * from executing at same time.
1487 stop_cpus(cpumask_t map)
1489 map &= smp_active_mask;
1491 /* send the Xcpustop IPI to all CPUs in map */
1492 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
1494 while ((stopped_cpus & map) != map)
1502 * Called by a CPU to restart stopped CPUs.
1504 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
1506 * - Signals all CPUs in map to restart.
1507 * - Waits for each to restart.
1515 restart_cpus(cpumask_t map)
1517 /* signal other cpus to restart */
1518 started_cpus = map & smp_active_mask;
1520 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
1527 * This is called once the mpboot code has gotten us properly relocated
1528 * and the MMU turned on, etc. ap_init() is actually the idle thread,
1529 * and when it returns the scheduler will call the real cpu_idle() main
1530 * loop for the idlethread. Interrupts are disabled on entry and should
1531 * remain disabled at return.
1539 * Adjust smp_startup_mask to signal the BSP that we have started
1540 * up successfully. Note that we do not yet hold the BGL. The BSP
1541 * is waiting for our signal.
1543 * We can't set our bit in smp_active_mask yet because we are holding
1544 * interrupts physically disabled and remote cpus could deadlock
1545 * trying to send us an IPI.
1547 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
1551 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
1552 * non-zero, then get the MP lock.
1554 * Note: We are in a critical section.
1556 * Note: we are the idle thread, we can only spin.
1558 * Note: The load fence is memory volatile and prevents the compiler
1559 * from improperly caching mp_finish_lapic, and the cpu from improperly
1562 while (mp_finish_lapic == 0)
1564 while (try_mplock() == 0)
1567 if (cpu_feature & CPUID_TSC) {
1569 * The BSP is constantly updating tsc0_offset, figure out
1570 * the relative difference to synchronize ktrdump.
1572 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1575 /* BSP may have changed PTD while we're waiting for the lock */
1578 /* Build our map of 'other' CPUs. */
1579 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1581 /* A quick check from sanity claus */
1582 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
1583 if (mycpu->gd_cpuid != apic_id) {
1584 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
1585 kprintf("SMP: apic_id = %d lapicid %d\n",
1586 apic_id, (lapic->id & 0xff000000) >> 24);
1588 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1590 panic("cpuid mismatch! boom!!");
1593 /* Initialize AP's local APIC for irq's */
1596 /* LAPIC initialization is done */
1597 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1600 /* Let BSP move onto the next initialization stage */
1604 * Interlock for finalization. Wait until mp_finish is non-zero,
1605 * then get the MP lock.
1607 * Note: We are in a critical section.
1609 * Note: we are the idle thread, we can only spin.
1611 * Note: The load fence is memory volatile and prevents the compiler
1612 * from improperly caching mp_finish, and the cpu from improperly
1615 while (mp_finish == 0)
1617 while (try_mplock() == 0)
1620 /* BSP may have changed PTD while we're waiting for the lock */
1623 /* Set memory range attributes for this CPU to match the BSP */
1624 mem_range_AP_init();
1627 * Once we go active we must process any IPIQ messages that may
1628 * have been queued, because no actual IPI will occur until we
1629 * set our bit in the smp_active_mask. If we don't the IPI
1630 * message interlock could be left set which would also prevent
1633 * The idle loop doesn't expect the BGL to be held and while
1634 * lwkt_switch() normally cleans things up this is a special case
1635 * because we returning almost directly into the idle loop.
1637 * The idle thread is never placed on the runq, make sure
1638 * nothing we've done put it there.
1640 KKASSERT(get_mplock_count(curthread) == 1);
1641 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1644 * Enable interrupts here. idle_restore will also do it, but
1645 * doing it here lets us clean up any strays that got posted to
1646 * the CPU during the AP boot while we are still in a critical
1649 __asm __volatile("sti; pause; pause"::);
1650 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1652 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1653 lwkt_process_ipiq();
1656 * Releasing the mp lock lets the BSP finish up the SMP init
1659 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1663 * Get SMP fully working before we start initializing devices.
1671 kprintf("Finish MP startup\n");
1673 while (smp_active_mask != smp_startup_mask)
1675 while (try_mplock() == 0)
1678 kprintf("Active CPU Mask: %016jx\n",
1679 (uintmax_t)smp_active_mask);
1683 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1686 cpu_send_ipiq(int dcpu)
1688 if (CPUMASK(dcpu) & smp_active_mask)
1689 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1692 #if 0 /* single_apic_ipi_passive() not working yet */
1694 * Returns 0 on failure, 1 on success
1697 cpu_send_ipiq_passive(int dcpu)
1700 if (CPUMASK(dcpu) & smp_active_mask) {
1701 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1702 APIC_DELMODE_FIXED);
1709 mptable_bus_info_callback(void *xarg, const void *pos, int type)
1711 struct mptable_bus_info *bus_info = xarg;
1712 const struct BUSENTRY *ent;
1713 struct mptable_bus *bus;
1719 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
1720 if (bus->mb_id == ent->bus_id) {
1721 kprintf("mptable_bus_info_alloc: duplicated bus id "
1722 "(%d)\n", bus->mb_id);
1728 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
1729 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1730 bus->mb_type = MPTABLE_BUS_PCI;
1731 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
1732 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
1733 bus->mb_type = MPTABLE_BUS_ISA;
1737 bus->mb_id = ent->bus_id;
1738 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
1744 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
1748 bzero(bus_info, sizeof(*bus_info));
1749 TAILQ_INIT(&bus_info->mbi_list);
1751 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
1753 mptable_bus_info_free(bus_info);
1757 mptable_bus_info_free(struct mptable_bus_info *bus_info)
1759 struct mptable_bus *bus;
1761 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
1762 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
1767 struct mptable_lapic_cbarg1 {
1770 u_int ht_apicid_mask;
1774 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
1776 const struct PROCENTRY *ent;
1777 struct mptable_lapic_cbarg1 *arg = xarg;
1783 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1787 if (ent->apic_id < 32) {
1788 arg->ht_apicid_mask |= 1 << ent->apic_id;
1789 } else if (arg->ht_fixup) {
1790 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
1796 struct mptable_lapic_cbarg2 {
1803 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
1805 const struct PROCENTRY *ent;
1806 struct mptable_lapic_cbarg2 *arg = xarg;
1812 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1813 KKASSERT(!arg->found_bsp);
1817 if (processor_entry(ent, arg->cpu))
1820 if (arg->logical_cpus) {
1821 struct PROCENTRY proc;
1825 * Create fake mptable processor entries
1826 * and feed them to processor_entry() to
1827 * enumerate the logical CPUs.
1829 bzero(&proc, sizeof(proc));
1831 proc.cpu_flags = PROCENTRY_FLAG_EN;
1832 proc.apic_id = ent->apic_id;
1834 for (i = 1; i < arg->logical_cpus; i++) {
1836 processor_entry(&proc, arg->cpu);
1844 mptable_lapic_default(void)
1846 int ap_apicid, bsp_apicid;
1848 mp_naps = 1; /* exclude BSP */
1850 /* Map local apic before the id field is accessed */
1851 lapic_map(DEFAULT_APIC_BASE);
1853 bsp_apicid = APIC_ID(lapic->id);
1854 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
1857 mp_set_cpuids(0, bsp_apicid);
1858 /* one and only AP */
1859 mp_set_cpuids(1, ap_apicid);
1865 * ID_TO_CPU(N), APIC ID to logical CPU table
1866 * CPU_TO_ID(N), logical CPU to APIC ID table
1869 mptable_lapic_enumerate(struct lapic_enumerator *e)
1871 struct mptable_pos mpt;
1872 struct mptable_lapic_cbarg1 arg1;
1873 struct mptable_lapic_cbarg2 arg2;
1875 int error, logical_cpus = 0;
1876 vm_offset_t lapic_addr;
1878 if (mptable_use_default) {
1879 mptable_lapic_default();
1883 error = mptable_map(&mpt);
1885 panic("mptable_lapic_enumerate mptable_map failed\n");
1886 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1890 /* Save local apic address */
1891 lapic_addr = (vm_offset_t)cth->apic_address;
1892 KKASSERT(lapic_addr != 0);
1895 * Find out how many CPUs do we have
1897 bzero(&arg1, sizeof(arg1));
1898 arg1.ht_fixup = 1; /* Apply ht fixup by default */
1900 error = mptable_iterate_entries(cth,
1901 mptable_lapic_pass1_callback, &arg1);
1903 panic("mptable_iterate_entries(lapic_pass1) failed\n");
1904 KKASSERT(arg1.cpu_count != 0);
1906 /* See if we need to fixup HT logical CPUs. */
1907 if (arg1.ht_fixup) {
1908 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
1910 if (logical_cpus != 0)
1911 arg1.cpu_count *= logical_cpus;
1913 mp_naps = arg1.cpu_count;
1915 /* Qualify the numbers again, after possible HT fixup */
1916 if (mp_naps > MAXCPU) {
1917 kprintf("Warning: only using %d of %d available CPUs!\n",
1923 --mp_naps; /* subtract the BSP */
1926 * Link logical CPU id to local apic id
1928 bzero(&arg2, sizeof(arg2));
1930 arg2.logical_cpus = logical_cpus;
1932 error = mptable_iterate_entries(cth,
1933 mptable_lapic_pass2_callback, &arg2);
1935 panic("mptable_iterate_entries(lapic_pass2) failed\n");
1936 KKASSERT(arg2.found_bsp);
1938 /* Map local apic */
1939 lapic_map(lapic_addr);
1941 mptable_unmap(&mpt);
1944 struct mptable_lapic_probe_cbarg {
1950 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
1952 const struct PROCENTRY *ent;
1953 struct mptable_lapic_probe_cbarg *arg = xarg;
1959 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
1963 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
1964 if (arg->found_bsp) {
1965 kprintf("more than one BSP in base MP table\n");
1974 mptable_lapic_probe(struct lapic_enumerator *e)
1976 struct mptable_pos mpt;
1977 struct mptable_lapic_probe_cbarg arg;
1981 if (mptable_fps_phyaddr == 0)
1984 if (mptable_use_default)
1987 error = mptable_map(&mpt);
1990 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
1995 if (cth->apic_address == 0)
1998 bzero(&arg, sizeof(arg));
1999 error = mptable_iterate_entries(cth,
2000 mptable_lapic_probe_callback, &arg);
2002 if (arg.cpu_count == 0) {
2003 kprintf("MP table contains no processor entries\n");
2005 } else if (!arg.found_bsp) {
2006 kprintf("MP table does not contains BSP entry\n");
2011 mptable_unmap(&mpt);
2015 static struct lapic_enumerator mptable_lapic_enumerator = {
2016 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
2017 .lapic_probe = mptable_lapic_probe,
2018 .lapic_enumerate = mptable_lapic_enumerate
2022 mptable_lapic_enum_register(void)
2024 lapic_enumerator_register(&mptable_lapic_enumerator);
2026 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2027 mptable_lapic_enum_register, 0);
2030 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
2032 const struct IOAPICENTRY *ent;
2033 struct mptable_ioapic *nioapic, *ioapic;
2039 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
2042 if (ent->apic_address == 0) {
2043 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
2047 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2048 if (ioapic->mio_apic_id == ent->apic_id) {
2049 kprintf("mptable_ioapic_create_list: duplicated "
2050 "apic id %d\n", ioapic->mio_apic_id);
2053 if (ioapic->mio_addr == ent->apic_address) {
2054 kprintf("mptable_ioapic_create_list: overlapped "
2055 "IOAPIC addr 0x%08x", ioapic->mio_addr);
2060 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2061 nioapic->mio_apic_id = ent->apic_id;
2062 nioapic->mio_addr = ent->apic_address;
2065 * Create IOAPIC list in ascending order of APIC ID
2067 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
2068 mptable_ioapic_list, mio_link) {
2069 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
2070 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
2071 ioapic, nioapic, mio_link);
2076 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
2082 mptable_ioapic_create_list(void)
2084 struct mptable_ioapic *ioapic;
2085 struct mptable_pos mpt;
2088 if (mptable_fps_phyaddr == 0)
2091 if (mptable_use_default) {
2092 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
2093 ioapic->mio_idx = 0;
2094 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
2095 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
2097 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
2101 error = mptable_map(&mpt);
2103 panic("mptable_ioapic_create_list: mptable_map failed\n");
2104 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2106 error = mptable_iterate_entries(mpt.mp_cth,
2107 mptable_ioapic_list_callback, NULL);
2109 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
2110 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
2111 kfree(ioapic, M_DEVBUF);
2117 * Assign index number for each IOAPIC
2120 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2121 ioapic->mio_idx = idx;
2125 mptable_unmap(&mpt);
2127 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
2128 mptable_ioapic_create_list, 0);
2131 mptable_pci_int_callback(void *xarg, const void *pos, int type)
2133 const struct mptable_bus_info *bus_info = xarg;
2134 const struct mptable_ioapic *ioapic;
2135 const struct mptable_bus *bus;
2136 struct mptable_pci_int *pci_int;
2137 const struct INTENTRY *ent;
2138 int pci_pin, pci_dev;
2144 if (ent->int_type != 0)
2147 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2148 if (bus->mb_type == MPTABLE_BUS_PCI &&
2149 bus->mb_id == ent->src_bus_id)
2155 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2156 if (ioapic->mio_apic_id == ent->dst_apic_id)
2159 if (ioapic == NULL) {
2160 kprintf("MPTABLE: warning PCI int dst apic id %d "
2161 "does not exist\n", ent->dst_apic_id);
2165 pci_pin = ent->src_bus_irq & 0x3;
2166 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
2168 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2169 if (pci_int->mpci_bus == ent->src_bus_id &&
2170 pci_int->mpci_dev == pci_dev &&
2171 pci_int->mpci_pin == pci_pin) {
2172 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
2173 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
2174 kprintf("MPTABLE: warning duplicated "
2175 "PCI int entry for "
2176 "bus %d, dev %d, pin %d\n",
2182 kprintf("mptable_pci_int_register: "
2183 "conflict PCI int entry for "
2184 "bus %d, dev %d, pin %d, "
2185 "IOAPIC %d.%d -> %d.%d\n",
2189 pci_int->mpci_ioapic_idx,
2190 pci_int->mpci_ioapic_pin,
2198 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
2200 pci_int->mpci_bus = ent->src_bus_id;
2201 pci_int->mpci_dev = pci_dev;
2202 pci_int->mpci_pin = pci_pin;
2203 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
2204 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
2206 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
2212 mptable_pci_int_register(void)
2214 struct mptable_bus_info bus_info;
2215 const struct mptable_bus *bus;
2216 struct mptable_pci_int *pci_int;
2217 struct mptable_pos mpt;
2218 int error, force_pci0, npcibus;
2221 if (mptable_fps_phyaddr == 0)
2224 if (mptable_use_default)
2227 if (TAILQ_EMPTY(&mptable_ioapic_list))
2230 error = mptable_map(&mpt);
2232 panic("mptable_pci_int_register: mptable_map failed\n");
2233 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2237 mptable_bus_info_alloc(cth, &bus_info);
2238 if (TAILQ_EMPTY(&bus_info.mbi_list))
2243 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
2244 if (bus->mb_type == MPTABLE_BUS_PCI)
2248 mptable_bus_info_free(&bus_info);
2250 } else if (npcibus == 1) {
2254 error = mptable_iterate_entries(cth,
2255 mptable_pci_int_callback, &bus_info);
2257 mptable_bus_info_free(&bus_info);
2260 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
2261 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
2262 kfree(pci_int, M_DEVBUF);
2268 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
2269 pci_int->mpci_bus = 0;
2272 mptable_unmap(&mpt);
2274 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2275 mptable_pci_int_register, 0);
2277 struct mptable_ioapic_probe_cbarg {
2278 const struct mptable_bus_info *bus_info;
2282 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
2284 struct mptable_ioapic_probe_cbarg *arg = xarg;
2285 const struct mptable_ioapic *ioapic;
2286 const struct mptable_bus *bus;
2287 const struct INTENTRY *ent;
2293 if (ent->int_type != 0)
2296 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2297 if (bus->mb_type == MPTABLE_BUS_ISA &&
2298 bus->mb_id == ent->src_bus_id)
2304 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2305 if (ioapic->mio_apic_id == ent->dst_apic_id)
2308 if (ioapic == NULL) {
2309 kprintf("MPTABLE: warning ISA int dst apic id %d "
2310 "does not exist\n", ent->dst_apic_id);
2314 /* XXX magic number */
2315 if (ent->src_bus_irq >= 16) {
2316 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
2324 mptable_ioapic_probe(struct ioapic_enumerator *e)
2326 struct mptable_ioapic_probe_cbarg arg;
2327 struct mptable_bus_info bus_info;
2328 struct mptable_pos mpt;
2332 if (mptable_fps_phyaddr == 0)
2335 if (mptable_use_default)
2338 if (TAILQ_EMPTY(&mptable_ioapic_list))
2341 error = mptable_map(&mpt);
2343 panic("mptable_ioapic_probe: mptable_map failed\n");
2344 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2348 mptable_bus_info_alloc(cth, &bus_info);
2350 bzero(&arg, sizeof(arg));
2351 arg.bus_info = &bus_info;
2353 error = mptable_iterate_entries(cth,
2354 mptable_ioapic_probe_callback, &arg);
2356 mptable_bus_info_free(&bus_info);
2357 mptable_unmap(&mpt);
2362 struct mptable_ioapic_int_cbarg {
2363 const struct mptable_bus_info *bus_info;
2368 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
2370 struct mptable_ioapic_int_cbarg *arg = xarg;
2371 const struct mptable_ioapic *ioapic;
2372 const struct mptable_bus *bus;
2373 const struct INTENTRY *ent;
2382 if (ent->int_type != 0)
2385 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
2386 if (bus->mb_type == MPTABLE_BUS_ISA &&
2387 bus->mb_id == ent->src_bus_id)
2393 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2394 if (ioapic->mio_apic_id == ent->dst_apic_id)
2397 if (ioapic == NULL) {
2398 kprintf("MPTABLE: warning ISA int dst apic id %d "
2399 "does not exist\n", ent->dst_apic_id);
2403 if (ent->dst_apic_int >= ioapic->mio_npin) {
2404 panic("mptable_ioapic_enumerate: invalid I/O APIC "
2405 "pin %d, should be < %d",
2406 ent->dst_apic_int, ioapic->mio_npin);
2408 gsi = ioapic->mio_gsi_base + ent->dst_apic_int;
2410 if (ent->src_bus_irq != gsi) {
2412 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
2413 ent->src_bus_irq, gsi);
2415 ioapic_intsrc(ent->src_bus_irq, gsi,
2416 INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2422 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
2424 struct mptable_bus_info bus_info;
2425 struct mptable_ioapic *ioapic;
2426 struct mptable_pos mpt;
2430 KKASSERT(mptable_fps_phyaddr != 0);
2431 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
2433 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
2434 const struct mptable_ioapic *prev_ioapic;
2438 addr = ioapic_map(ioapic->mio_addr);
2440 ver = ioapic_read(addr, IOAPIC_VER);
2441 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
2442 >> MAXREDIRSHIFT) + 1;
2444 prev_ioapic = TAILQ_PREV(ioapic,
2445 mptable_ioapic_list, mio_link);
2446 if (prev_ioapic == NULL) {
2447 ioapic->mio_gsi_base = 0;
2449 ioapic->mio_gsi_base =
2450 prev_ioapic->mio_gsi_base +
2451 prev_ioapic->mio_npin;
2453 ioapic_add(addr, ioapic->mio_gsi_base, ioapic->mio_npin);
2456 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
2457 "apic id %d, idx %d, gsi base %d, npin %d\n",
2459 ioapic->mio_apic_id,
2461 ioapic->mio_gsi_base,
2466 if (mptable_use_default) {
2468 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
2469 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2473 error = mptable_map(&mpt);
2475 panic("mptable_ioapic_probe: mptable_map failed\n");
2476 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2480 mptable_bus_info_alloc(cth, &bus_info);
2482 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
2484 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
2485 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
2487 struct mptable_ioapic_int_cbarg arg;
2489 bzero(&arg, sizeof(arg));
2490 arg.bus_info = &bus_info;
2492 error = mptable_iterate_entries(cth,
2493 mptable_ioapic_int_callback, &arg);
2495 panic("mptable_ioapic_int failed\n");
2497 if (arg.ioapic_nint == 0) {
2499 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
2502 ioapic_intsrc(0, 2, INTR_TRIGGER_EDGE,
2503 INTR_POLARITY_HIGH);
2507 mptable_bus_info_free(&bus_info);
2509 mptable_unmap(&mpt);
2512 static struct ioapic_enumerator mptable_ioapic_enumerator = {
2513 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
2514 .ioapic_probe = mptable_ioapic_probe,
2515 .ioapic_enumerate = mptable_ioapic_enumerate
2519 mptable_ioapic_enum_register(void)
2521 ioapic_enumerator_register(&mptable_ioapic_enumerator);
2523 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
2524 mptable_ioapic_enum_register, 0);
2527 mptable_pci_int_dump(void)
2529 const struct mptable_pci_int *pci_int;
2531 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2532 kprintf("MPTABLE: %d:%d INT%c -> IOAPIC %d.%d\n",
2535 pci_int->mpci_pin + 'A',
2536 pci_int->mpci_ioapic_idx,
2537 pci_int->mpci_ioapic_pin);
2542 mptable_pci_int_route(int bus, int dev, int pin, int intline)
2544 const struct mptable_pci_int *pci_int;
2548 --pin; /* zero based */
2550 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
2551 if (pci_int->mpci_bus == bus &&
2552 pci_int->mpci_dev == dev &&
2553 pci_int->mpci_pin == pin)
2556 if (pci_int != NULL) {
2559 gsi = ioapic_gsi(pci_int->mpci_ioapic_idx,
2560 pci_int->mpci_ioapic_pin);
2562 irq = ioapic_abi_find_gsi(gsi,
2563 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2569 kprintf("MPTABLE: fixed interrupt routing "
2570 "for %d:%d INT%c\n", bus, dev, pin + 'A');
2573 irq = ioapic_abi_find_irq(intline,
2574 INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW);
2577 if (irq >= 0 && bootverbose) {
2578 kprintf("MPTABLE: %d:%d INT%c routed to irq %d\n",
2579 bus, dev, pin + 'A', irq);